* [PATCH 0/5] ARM: imx: Add Freescale LS1021A SoC and board support
@ 2014-07-02 9:02 ` Jingchang Lu
0 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-02 9:02 UTC (permalink / raw)
To: shawn.guo-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8
This series contain the support for Freescale LS1021A CPU and LS1021A-QDS
and LS1021A-TWR board.
The LS1021A SoC combines two ARM Cortex-A7 cores that have been optimized
for high reliability and pack the highest level of integration available
for sub-3 W embedded communications processors and with a comprehensive
enablement model focused on ease of programmability.
The LS1021A SoC shares IPs with i.MX family, Vybrid family and Freescale
PowerPC platform.
For the detail information about LS1021A SoC, please refer to the RM doc.
----------------------------------------------------------------
Jingchang Lu (5):
ARM: dts: Add SoC level device tree support for LS1021A
ARM: dts: Add initial LS1021A QDS board dts support
ARM: dts: Add initial LS1021A TWR board dts support
ARM: imx: Add initial support for Freescale LS1021A
ARM: imx: Add Freescale LS1021A SMP support
arch/arm/boot/dts/Makefile | 4 +-
arch/arm/boot/dts/ls1021a-qds.dts | 380 ++++++++++++++++++++++++++++
arch/arm/boot/dts/ls1021a-twr.dts | 236 +++++++++++++++++
arch/arm/boot/dts/ls1021a.dtsi | 852 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/Kconfig | 17 ++
arch/arm/mach-imx/Makefile | 2 +
arch/arm/mach-imx/common.h | 2 +
arch/arm/mach-imx/headsmp.S | 11 +
arch/arm/mach-imx/mach-ls1021a.c | 50 ++++
arch/arm/mach-imx/platsmp.c | 44 ++++
10 files changed, 1597 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts
create mode 100755 arch/arm/boot/dts/ls1021a-twr.dts
create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
create mode 100644 arch/arm/mach-imx/mach-ls1021a.c
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 0/5] ARM: imx: Add Freescale LS1021A SoC and board support
@ 2014-07-02 9:02 ` Jingchang Lu
0 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-02 9:02 UTC (permalink / raw)
To: linux-arm-kernel
This series contain the support for Freescale LS1021A CPU and LS1021A-QDS
and LS1021A-TWR board.
The LS1021A SoC combines two ARM Cortex-A7 cores that have been optimized
for high reliability and pack the highest level of integration available
for sub-3 W embedded communications processors and with a comprehensive
enablement model focused on ease of programmability.
The LS1021A SoC shares IPs with i.MX family, Vybrid family and Freescale
PowerPC platform.
For the detail information about LS1021A SoC, please refer to the RM doc.
----------------------------------------------------------------
Jingchang Lu (5):
ARM: dts: Add SoC level device tree support for LS1021A
ARM: dts: Add initial LS1021A QDS board dts support
ARM: dts: Add initial LS1021A TWR board dts support
ARM: imx: Add initial support for Freescale LS1021A
ARM: imx: Add Freescale LS1021A SMP support
arch/arm/boot/dts/Makefile | 4 +-
arch/arm/boot/dts/ls1021a-qds.dts | 380 ++++++++++++++++++++++++++++
arch/arm/boot/dts/ls1021a-twr.dts | 236 +++++++++++++++++
arch/arm/boot/dts/ls1021a.dtsi | 852 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/Kconfig | 17 ++
arch/arm/mach-imx/Makefile | 2 +
arch/arm/mach-imx/common.h | 2 +
arch/arm/mach-imx/headsmp.S | 11 +
arch/arm/mach-imx/mach-ls1021a.c | 50 ++++
arch/arm/mach-imx/platsmp.c | 44 ++++
10 files changed, 1597 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts
create mode 100755 arch/arm/boot/dts/ls1021a-twr.dts
create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
create mode 100644 arch/arm/mach-imx/mach-ls1021a.c
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 1/5] ARM: dts: Add SoC level device tree support for LS1021A
2014-07-02 9:02 ` Jingchang Lu
@ 2014-07-02 9:02 ` Jingchang Lu
-1 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-02 9:02 UTC (permalink / raw)
To: shawn.guo-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
Jingchang Lu, Nikhil Badola, Chenhui Zhao, Suresh Gupta,
Shaveta Leekha, Adrian Sendroiu, Ruchika Gupta, Bhupesh Sharma,
Chao Fu, Xiubo Li, Jingchang Lu
From: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Add Freescale LS1021A SoC device tree support
Signed-off-by: Nikhil Badola <nikhil.badola-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Chenhui Zhao <chenhui.zhao-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Suresh Gupta <suresh.gupta-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Shaveta Leekha <shaveta-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Adrian Sendroiu <adrian.sendroiu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Chao Fu <b44548-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Xiubo Li <Li.Xiubo-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Jingchang Lu <jingchang.lu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
arch/arm/boot/dts/ls1021a.dtsi | 852 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 852 insertions(+)
create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
new file mode 100644
index 0000000..b06b320
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -0,0 +1,852 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "skeleton64.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "fsl,ls1021a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
+ serial4 = &lpuart4;
+ serial5 = &lpuart5;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ };
+
+ memory {
+ reg = <0x0 0x80000000 0x0 0x20000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0xf00>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0xf01>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ gic: interrupt-controller@1400000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0x0 0x1000>,
+ <0x0 0x1402000 0x0 0x1000>,
+ <0x0 0x1404000 0x0 0x2000>,
+ <0x0 0x1406000 0x0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+
+ };
+
+ tzasc: tzasc@1500000 {
+ reg = <0x0 0x1500000 0x0 0x10000>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ifc: ifc@1530000 {
+ compatible = "fsl,ls1021a-ifc", "fsl,ifc", "simple-bus";
+ reg = <0x0 0x1530000 0x0 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dcfg: dcfg@1ee0000 {
+ compatible = "fsl,ls1021a-dcfg";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ };
+
+ qspi: quadspi@1550000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,vf610-qspi";
+ reg = <0x0 0x1550000 0x0 0x10000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "qspi_en", "qspi";
+ clocks = <&platform_clk 1>, <&platform_clk 1>;
+ big-endian;
+ amba-base = <0x40000000>;
+ status = "disabled";
+ };
+
+ esdhc: esdhc@1560000 {
+ compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x1560000 0x0 0x10000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ big-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ scfg: scfg@1570000 {
+ compatible = "fsl,ls1021a-scfg";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ };
+
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x1700000 0x0 0x100000>;
+ ranges = <0x0 0x0 0x1700000 0x100000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.3-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.3-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.3-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.3-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+
+ clockgen: clocking@1ee1000 {
+ compatible = "fsl,ls1021a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1ee1000 0x10000>;
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ cga_pll1: pll1@800 {
+ compatible = "fsl,qoriq-core-pll-2.0";
+ #clock-cells = <1>;
+ reg = <0x800 0x10>;
+ clocks = <&sysclk>;
+ clock-output-names = "cga-pll1", "cga-pll1-div2",
+ "cga-pll1-div3", "cga-pll1-div4";
+ };
+
+ cga_pll2: pll2@820 {
+ compatible = "fsl,qoriq-core-pll-2.0";
+ #clock-cells = <1>;
+ reg = <0x820 0x10>;
+ clocks = <&sysclk>;
+ clock-output-names = "cga-pll2", "cga-pll2-div2",
+ "cga-pll2-div3", "cga-pll2-div4";
+ };
+
+ platform_clk: pll@c00 {
+ compatible = "fsl,qoriq-core-pll-2.0";
+ #clock-cells = <1>;
+ reg = <0xc00 0x10>;
+ clocks = <&sysclk>;
+ clock-output-names = "platform-clk", "platform-clk-div2";
+ };
+
+
+ cluster1_clk: clk0c0@0 {
+ compatible = "fsl,qoriq-core-mux-2.0";
+ #clock-cells = <1>;
+ reg = <0x0 0x10>;
+ clock-names = "pll1cga", "pll1cga-div2";
+ clocks = <&cga_pll1 0>, <&cga_pll1 2>;
+ clock-output-names = "cluster1-clk";
+
+ };
+
+ };
+
+ rcpm: rcpm@1ee2000 {
+ compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1";
+ reg = <0x0 0x1ee2000 0x0 0x10000>;
+ };
+
+ dspi0: dspi@2100000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,vf610-dspi";
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&platform_clk 1>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ dspi1: dspi@2110000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,vf610-dspi";
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&platform_clk 1>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2180000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,vf610-i2c";
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&platform_clk 1>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2190000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,vf610-i2c";
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&platform_clk 1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@21a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,vf610-i2c";
+ reg = <0x0 0x21a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&platform_clk 1>;
+ status = "disabled";
+ };
+
+ duart0: serial@21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0500 0x0 0x100>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ fifo-size = <8>;
+ status = "disabled";
+ };
+
+ duart1: serial@21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0600 0x0 0x100>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ fifo-size = <8>;
+ status = "disabled";
+ };
+
+ duart2: serial@21d0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0500 0x0 0x100>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ fifo-size = <8>;
+ status = "disabled";
+ };
+
+ duart3: serial@21d0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0600 0x0 0x100>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ fifo-size = <8>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@2300000 {
+ compatible = "fsl,ls1021a-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2310000 {
+ compatible = "fsl,ls1021a-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2320000 {
+ compatible = "fsl,ls1021a-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@2330000 {
+ compatible = "fsl,ls1021a-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uqe: uqe@2400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe";
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+
+ qeic: qeic@80 {
+ compatible = "fsl,qe-ic";
+ reg = <0x80 0x80>;
+ #address-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ ucc@2000 {
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ };
+
+ ucc@2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ };
+
+ muram@10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x10000 0x6000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x6000>;
+ };
+ };
+ };
+
+ lpuart0: serial@2950000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2950000 0x0 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial@2960000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2960000 0x0 0x1000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial@2970000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2970000 0x0 0x1000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart3: serial@2980000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2980000 0x0 0x1000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial@2990000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2990000 0x0 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial@29a0000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x29a0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ ftm0_1: ftm0_1@29d0000 {
+ compatible = "fsl,ftm-timer";
+ reg = <0x0 0x29d0000 0x0 0x10000>,
+ <0x0 0x29e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ftm-evt", "ftm-src",
+ "ftm-evt-counter-en", "ftm-src-counter-en";
+ clocks = <&platform_clk 1>, <&platform_clk 1>,
+ <&platform_clk 1>, <&platform_clk 1>;
+ big-endian;
+ status = "disabled";
+ };
+
+ ftm2: ftm@29f0000 {
+ reg = <0x0 0x29f0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pwm3: ftm@2a00000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2a00000 0x0 0x10000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&platform_clk 1>, <&platform_clk 1>,
+ <&platform_clk 1>, <&platform_clk 1>;
+ big-endian;
+ status = "disabled";
+ };
+
+ ftm4: ftm@2a10000 {
+ reg = <0x0 0x2a10000 0x0 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ftm5: ftm@2a20000 {
+ reg = <0x0 0x2a20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pwm6: ftm@2a30000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2a30000 0x0 0x10000>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&platform_clk 1>, <&platform_clk 1>,
+ <&platform_clk 1>, <&platform_clk 1>;
+ big-endian;
+ status = "disabled";
+ };
+
+ pwm7: ftm@2a40000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2a40000 0x0 0x10000>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&platform_clk 1>, <&platform_clk 1>,
+ <&platform_clk 1>, <&platform_clk 1>;
+ big-endian;
+ status = "disabled";
+ };
+
+ wdog0: wdog@2ad0000 {
+ compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "wdog";
+ big-endian;
+ };
+
+ sai2: sai@2b60000 {
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0x2b60000 0x0 0x10000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "sai";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 45>,
+ <&edma0 1 44>;
+ big-endian-regs;
+ status = "disabled";
+ };
+
+ edma0: edma@2c00000 {
+ #dma-cells = <2>;
+ compatible = "fsl,vf610-edma";
+ reg = <0x0 0x2c00000 0x0 0x10000>,
+ <0x0 0x2c10000 0x0 0x10000>,
+ <0x0 0x2c20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ big-endian;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&platform_clk 1>,
+ <&platform_clk 1>;
+ };
+
+ dcu0: dcu@2ce0000 {
+ compatible = "fsl,vf610-dcu";
+ reg = <0x0 0x2ce000 0x0 0x10000>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "dcu";
+ big-endian;
+ status = "disabled";
+ };
+
+ mdio0: mdio@2d24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <0x0 0x2d24000 0x0 0x4000>;
+ tbi0: tbi-phy@8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet@2d10000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,dma-endian-le;
+ fsl,num_rx_queues = <0x1>;
+ fsl,num_tx_queues = <0x1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x2d10000 0x0 0x8000>;
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+
+ enet1: ethernet@2d50000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,dma-endian-le;
+ fsl,num_rx_queues = <0x1>;
+ fsl,num_tx_queues = <0x1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x2d50000 0x0 0x8000>;
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+
+ enet2: ethernet@2d90000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,dma-endian-le;
+ fsl,num_rx_queues = <0x1>;
+ fsl,num_tx_queues = <0x1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x2d90000 0x0 0x8000>;
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ usb@8600000 {
+ compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+ reg = <0x0 0x8600000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ phy_type = "ulpi";
+ };
+
+ usb@3100000 {
+ compatible = "fsl,fsl-dwc3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dwc3 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+ };
+ };
+
+ can0: can@2a70000 {
+ compatible = "fsl,ls1021a-flexcan";
+ reg = <0x0 0x2a70000 0x0 0x1000>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+
+ can1: can@2a80000 {
+ compatible = "fsl,ls1021a-flexcan";
+ reg = <0x0 0x2a80000 0x0 0x1000>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+
+ can2: can@2a90000 {
+ compatible = "fsl,ls1021a-flexcan";
+ reg = <0x0 0x2a90000 0x0 0x1000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+
+ can3: can@2aa0000 {
+ compatible = "fsl,ls1021a-flexcan";
+ reg = <0x0 0x2aa0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+ };
+
+ dcsr@20000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1021a-dcsr", "simple-bus";
+
+ ranges = <0x0 0x0 0x20000000 0x1000000>;
+
+ dcsr-epu@0 {
+ compatible = "fsl,ls1021a-dcsr-epu";
+ reg = <0x0 0x10000>;
+ };
+
+ dcsr-gdi@100000 {
+ compatible = "fsl,ls1021a-dcsr-gdi";
+ reg = <0x100000 0x10000>;
+ };
+
+ dcsr-dddi@120000 {
+ compatible = "fsl,ls1021a-dcsr-dddi";
+ reg = <0x120000 0x10000>;
+ };
+
+ dcsr-dcfg@220000 {
+ compatible = "fsl,ls1021a-dcsr-dcfg";
+ reg = <0x220000 0x1000>;
+ };
+
+ dcsr-clock@221000 {
+ compatible = "fsl,ls1021a-dcsr-clock";
+ reg = <0x221000 0x1000>;
+ };
+
+ dcsr-rcpm@222000 {
+ compatible = "fsl,ls1021a-dcsr-rcpm";
+ reg = <0x222000 0x1000 0x223000 0x1000>;
+ };
+
+ dcsr-ccp@225000 {
+ compatible = "fsl,ls1021a-dcsr-ccp";
+ reg = <0x225000 0x1000>;
+ };
+
+ dcsr-fusectrl@226000 {
+ compatible = "fsl,ls1021a-dcsr-fusectrl";
+ reg = <0x226000 0x1000>;
+ };
+
+ dcsr-dap@300000 {
+ compatible = "fsl,ls1021a-dcsr-dap";
+ reg = <0x300000 0x10000>;
+ };
+
+ dcsr-cstf@350000 {
+ compatible = "fsl,ls1021a-dcsr-cstf";
+ reg = <0x350000 0x1000 0x3a7000 0x1000>;
+ };
+
+ dcsr-a7rom@360000 {
+ compatible = "fsl,ls1021a-dcsr-a7rom";
+ reg = <0x360000 0x10000>;
+ };
+
+ dcsr-a7cpu@370000 {
+ compatible = "fsl,ls1021a-dcsr-a7cpu";
+ reg = <0x370000 0x8000>;
+ };
+
+ dcsr-a7cti@378000 {
+ compatible = "fsl,ls1021a-dcsr-a7cti";
+ reg = <0x378000 0x4000>;
+ };
+
+ dcsr-etm@37c000 {
+ compatible = "fsl,ls1021a-dcsr-etm";
+ reg = <0x37c000 0x1000 0x37d000 0x3000>;
+ };
+
+ dcsr-hugorom@3a0000 {
+ compatible = "fsl,ls1021a-dcsr-hugorom";
+ reg = <0x3a0000 0x1000>;
+ };
+
+ dcsr-etf@3a1000 {
+ compatible = "fsl,ls1021a-dcsr-etf";
+ reg = <0x3a1000 0x1000 0x3a2000 0x1000>;
+ };
+
+ dcsr-etr@3a3000 {
+ compatible = "fsl,ls1021a-dcsr-etr";
+ reg = <0x3a3000 0x1000>;
+ };
+
+ dcsr-cti@3a4000 {
+ compatible = "fsl,ls1021a-dcsr-cti";
+ reg = <0x3a4000 0x1000 0x3a5000 0x1000 0x3a6000 0x1000>;
+ };
+
+ dcsr-atbrepl@3a8000 {
+ compatible = "fsl,ls1021a-dcsr-atbrepl";
+ reg = <0x3a8000 0x1000>;
+ };
+
+ dcsr-tsgen-ctrl@3a9000 {
+ compatible = "fsl,ls1021a-dcsr-tsgen-ctrl";
+ reg = <0x3a9000 0x1000>;
+ };
+
+ dcsr-tsgen-read@3aa000 {
+ compatible = "fsl,ls1021a-dcsr-tsgen-read";
+ reg = <0x3aa000 0x1000>;
+ };
+ };
+};
--
1.8.0
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^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 1/5] ARM: dts: Add SoC level device tree support for LS1021A
@ 2014-07-02 9:02 ` Jingchang Lu
0 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-02 9:02 UTC (permalink / raw)
To: linux-arm-kernel
From: Jingchang Lu <b35083@freescale.com>
Add Freescale LS1021A SoC device tree support
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Adrian Sendroiu <adrian.sendroiu@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 852 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 852 insertions(+)
create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
new file mode 100644
index 0000000..b06b320
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -0,0 +1,852 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "skeleton64.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "fsl,ls1021a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
+ serial4 = &lpuart4;
+ serial5 = &lpuart5;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ };
+
+ memory {
+ reg = <0x0 0x80000000 0x0 0x20000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0xf00>;
+ };
+
+ cpu at 1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0xf01>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ gic: interrupt-controller at 1400000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0x0 0x1000>,
+ <0x0 0x1402000 0x0 0x1000>,
+ <0x0 0x1404000 0x0 0x2000>,
+ <0x0 0x1406000 0x0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+
+ };
+
+ tzasc: tzasc at 1500000 {
+ reg = <0x0 0x1500000 0x0 0x10000>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ifc: ifc at 1530000 {
+ compatible = "fsl,ls1021a-ifc", "fsl,ifc", "simple-bus";
+ reg = <0x0 0x1530000 0x0 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dcfg: dcfg at 1ee0000 {
+ compatible = "fsl,ls1021a-dcfg";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ };
+
+ qspi: quadspi at 1550000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,vf610-qspi";
+ reg = <0x0 0x1550000 0x0 0x10000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "qspi_en", "qspi";
+ clocks = <&platform_clk 1>, <&platform_clk 1>;
+ big-endian;
+ amba-base = <0x40000000>;
+ status = "disabled";
+ };
+
+ esdhc: esdhc at 1560000 {
+ compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x1560000 0x0 0x10000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ big-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ scfg: scfg at 1570000 {
+ compatible = "fsl,ls1021a-scfg";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ };
+
+ crypto: crypto at 1700000 {
+ compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x1700000 0x0 0x100000>;
+ ranges = <0x0 0x0 0x1700000 0x100000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+
+ sec_jr0: jr at 10000 {
+ compatible = "fsl,sec-v5.3-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr at 20000 {
+ compatible = "fsl,sec-v5.3-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr at 30000 {
+ compatible = "fsl,sec-v5.3-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr at 40000 {
+ compatible = "fsl,sec-v5.3-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+
+ clockgen: clocking at 1ee1000 {
+ compatible = "fsl,ls1021a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1ee1000 0x10000>;
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ cga_pll1: pll1 at 800 {
+ compatible = "fsl,qoriq-core-pll-2.0";
+ #clock-cells = <1>;
+ reg = <0x800 0x10>;
+ clocks = <&sysclk>;
+ clock-output-names = "cga-pll1", "cga-pll1-div2",
+ "cga-pll1-div3", "cga-pll1-div4";
+ };
+
+ cga_pll2: pll2 at 820 {
+ compatible = "fsl,qoriq-core-pll-2.0";
+ #clock-cells = <1>;
+ reg = <0x820 0x10>;
+ clocks = <&sysclk>;
+ clock-output-names = "cga-pll2", "cga-pll2-div2",
+ "cga-pll2-div3", "cga-pll2-div4";
+ };
+
+ platform_clk: pll at c00 {
+ compatible = "fsl,qoriq-core-pll-2.0";
+ #clock-cells = <1>;
+ reg = <0xc00 0x10>;
+ clocks = <&sysclk>;
+ clock-output-names = "platform-clk", "platform-clk-div2";
+ };
+
+
+ cluster1_clk: clk0c0 at 0 {
+ compatible = "fsl,qoriq-core-mux-2.0";
+ #clock-cells = <1>;
+ reg = <0x0 0x10>;
+ clock-names = "pll1cga", "pll1cga-div2";
+ clocks = <&cga_pll1 0>, <&cga_pll1 2>;
+ clock-output-names = "cluster1-clk";
+
+ };
+
+ };
+
+ rcpm: rcpm at 1ee2000 {
+ compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1";
+ reg = <0x0 0x1ee2000 0x0 0x10000>;
+ };
+
+ dspi0: dspi at 2100000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,vf610-dspi";
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&platform_clk 1>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ dspi1: dspi at 2110000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,vf610-dspi";
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&platform_clk 1>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ i2c0: i2c at 2180000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,vf610-i2c";
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&platform_clk 1>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 2190000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,vf610-i2c";
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&platform_clk 1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 21a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,vf610-i2c";
+ reg = <0x0 0x21a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&platform_clk 1>;
+ status = "disabled";
+ };
+
+ duart0: serial at 21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0500 0x0 0x100>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ fifo-size = <8>;
+ status = "disabled";
+ };
+
+ duart1: serial at 21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0600 0x0 0x100>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ fifo-size = <8>;
+ status = "disabled";
+ };
+
+ duart2: serial at 21d0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0500 0x0 0x100>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ fifo-size = <8>;
+ status = "disabled";
+ };
+
+ duart3: serial at 21d0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0600 0x0 0x100>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ fifo-size = <8>;
+ status = "disabled";
+ };
+
+ gpio1: gpio at 2300000 {
+ compatible = "fsl,ls1021a-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 2310000 {
+ compatible = "fsl,ls1021a-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio at 2320000 {
+ compatible = "fsl,ls1021a-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio at 2330000 {
+ compatible = "fsl,ls1021a-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uqe: uqe at 2400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe";
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+
+ qeic: qeic at 80 {
+ compatible = "fsl,qe-ic";
+ reg = <0x80 0x80>;
+ #address-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ ucc at 2000 {
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ };
+
+ ucc at 2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ };
+
+ muram at 10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x10000 0x6000>;
+
+ data-only at 0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x6000>;
+ };
+ };
+ };
+
+ lpuart0: serial at 2950000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2950000 0x0 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial at 2960000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2960000 0x0 0x1000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial at 2970000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2970000 0x0 0x1000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart3: serial at 2980000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2980000 0x0 0x1000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial at 2990000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2990000 0x0 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial at 29a0000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x29a0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ ftm0_1: ftm0_1 at 29d0000 {
+ compatible = "fsl,ftm-timer";
+ reg = <0x0 0x29d0000 0x0 0x10000>,
+ <0x0 0x29e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ftm-evt", "ftm-src",
+ "ftm-evt-counter-en", "ftm-src-counter-en";
+ clocks = <&platform_clk 1>, <&platform_clk 1>,
+ <&platform_clk 1>, <&platform_clk 1>;
+ big-endian;
+ status = "disabled";
+ };
+
+ ftm2: ftm at 29f0000 {
+ reg = <0x0 0x29f0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pwm3: ftm at 2a00000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2a00000 0x0 0x10000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&platform_clk 1>, <&platform_clk 1>,
+ <&platform_clk 1>, <&platform_clk 1>;
+ big-endian;
+ status = "disabled";
+ };
+
+ ftm4: ftm at 2a10000 {
+ reg = <0x0 0x2a10000 0x0 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ftm5: ftm at 2a20000 {
+ reg = <0x0 0x2a20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pwm6: ftm at 2a30000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2a30000 0x0 0x10000>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&platform_clk 1>, <&platform_clk 1>,
+ <&platform_clk 1>, <&platform_clk 1>;
+ big-endian;
+ status = "disabled";
+ };
+
+ pwm7: ftm at 2a40000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2a40000 0x0 0x10000>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&platform_clk 1>, <&platform_clk 1>,
+ <&platform_clk 1>, <&platform_clk 1>;
+ big-endian;
+ status = "disabled";
+ };
+
+ wdog0: wdog at 2ad0000 {
+ compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "wdog";
+ big-endian;
+ };
+
+ sai2: sai at 2b60000 {
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0x2b60000 0x0 0x10000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "sai";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 45>,
+ <&edma0 1 44>;
+ big-endian-regs;
+ status = "disabled";
+ };
+
+ edma0: edma at 2c00000 {
+ #dma-cells = <2>;
+ compatible = "fsl,vf610-edma";
+ reg = <0x0 0x2c00000 0x0 0x10000>,
+ <0x0 0x2c10000 0x0 0x10000>,
+ <0x0 0x2c20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ big-endian;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&platform_clk 1>,
+ <&platform_clk 1>;
+ };
+
+ dcu0: dcu at 2ce0000 {
+ compatible = "fsl,vf610-dcu";
+ reg = <0x0 0x2ce000 0x0 0x10000>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "dcu";
+ big-endian;
+ status = "disabled";
+ };
+
+ mdio0: mdio at 2d24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <0x0 0x2d24000 0x0 0x4000>;
+ tbi0: tbi-phy at 8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet at 2d10000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,dma-endian-le;
+ fsl,num_rx_queues = <0x1>;
+ fsl,num_tx_queues = <0x1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x2d10000 0x0 0x8000>;
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+
+ enet1: ethernet at 2d50000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,dma-endian-le;
+ fsl,num_rx_queues = <0x1>;
+ fsl,num_tx_queues = <0x1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x2d50000 0x0 0x8000>;
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+
+ enet2: ethernet at 2d90000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,dma-endian-le;
+ fsl,num_rx_queues = <0x1>;
+ fsl,num_tx_queues = <0x1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x2d90000 0x0 0x8000>;
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ usb at 8600000 {
+ compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+ reg = <0x0 0x8600000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ phy_type = "ulpi";
+ };
+
+ usb at 3100000 {
+ compatible = "fsl,fsl-dwc3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dwc3 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+ };
+ };
+
+ can0: can at 2a70000 {
+ compatible = "fsl,ls1021a-flexcan";
+ reg = <0x0 0x2a70000 0x0 0x1000>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+
+ can1: can at 2a80000 {
+ compatible = "fsl,ls1021a-flexcan";
+ reg = <0x0 0x2a80000 0x0 0x1000>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+
+ can2: can at 2a90000 {
+ compatible = "fsl,ls1021a-flexcan";
+ reg = <0x0 0x2a90000 0x0 0x1000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+
+ can3: can at 2aa0000 {
+ compatible = "fsl,ls1021a-flexcan";
+ reg = <0x0 0x2aa0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+ };
+
+ dcsr at 20000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1021a-dcsr", "simple-bus";
+
+ ranges = <0x0 0x0 0x20000000 0x1000000>;
+
+ dcsr-epu at 0 {
+ compatible = "fsl,ls1021a-dcsr-epu";
+ reg = <0x0 0x10000>;
+ };
+
+ dcsr-gdi at 100000 {
+ compatible = "fsl,ls1021a-dcsr-gdi";
+ reg = <0x100000 0x10000>;
+ };
+
+ dcsr-dddi at 120000 {
+ compatible = "fsl,ls1021a-dcsr-dddi";
+ reg = <0x120000 0x10000>;
+ };
+
+ dcsr-dcfg at 220000 {
+ compatible = "fsl,ls1021a-dcsr-dcfg";
+ reg = <0x220000 0x1000>;
+ };
+
+ dcsr-clock at 221000 {
+ compatible = "fsl,ls1021a-dcsr-clock";
+ reg = <0x221000 0x1000>;
+ };
+
+ dcsr-rcpm at 222000 {
+ compatible = "fsl,ls1021a-dcsr-rcpm";
+ reg = <0x222000 0x1000 0x223000 0x1000>;
+ };
+
+ dcsr-ccp at 225000 {
+ compatible = "fsl,ls1021a-dcsr-ccp";
+ reg = <0x225000 0x1000>;
+ };
+
+ dcsr-fusectrl at 226000 {
+ compatible = "fsl,ls1021a-dcsr-fusectrl";
+ reg = <0x226000 0x1000>;
+ };
+
+ dcsr-dap at 300000 {
+ compatible = "fsl,ls1021a-dcsr-dap";
+ reg = <0x300000 0x10000>;
+ };
+
+ dcsr-cstf at 350000 {
+ compatible = "fsl,ls1021a-dcsr-cstf";
+ reg = <0x350000 0x1000 0x3a7000 0x1000>;
+ };
+
+ dcsr-a7rom at 360000 {
+ compatible = "fsl,ls1021a-dcsr-a7rom";
+ reg = <0x360000 0x10000>;
+ };
+
+ dcsr-a7cpu at 370000 {
+ compatible = "fsl,ls1021a-dcsr-a7cpu";
+ reg = <0x370000 0x8000>;
+ };
+
+ dcsr-a7cti at 378000 {
+ compatible = "fsl,ls1021a-dcsr-a7cti";
+ reg = <0x378000 0x4000>;
+ };
+
+ dcsr-etm at 37c000 {
+ compatible = "fsl,ls1021a-dcsr-etm";
+ reg = <0x37c000 0x1000 0x37d000 0x3000>;
+ };
+
+ dcsr-hugorom at 3a0000 {
+ compatible = "fsl,ls1021a-dcsr-hugorom";
+ reg = <0x3a0000 0x1000>;
+ };
+
+ dcsr-etf at 3a1000 {
+ compatible = "fsl,ls1021a-dcsr-etf";
+ reg = <0x3a1000 0x1000 0x3a2000 0x1000>;
+ };
+
+ dcsr-etr at 3a3000 {
+ compatible = "fsl,ls1021a-dcsr-etr";
+ reg = <0x3a3000 0x1000>;
+ };
+
+ dcsr-cti at 3a4000 {
+ compatible = "fsl,ls1021a-dcsr-cti";
+ reg = <0x3a4000 0x1000 0x3a5000 0x1000 0x3a6000 0x1000>;
+ };
+
+ dcsr-atbrepl at 3a8000 {
+ compatible = "fsl,ls1021a-dcsr-atbrepl";
+ reg = <0x3a8000 0x1000>;
+ };
+
+ dcsr-tsgen-ctrl at 3a9000 {
+ compatible = "fsl,ls1021a-dcsr-tsgen-ctrl";
+ reg = <0x3a9000 0x1000>;
+ };
+
+ dcsr-tsgen-read at 3aa000 {
+ compatible = "fsl,ls1021a-dcsr-tsgen-read";
+ reg = <0x3aa000 0x1000>;
+ };
+ };
+};
--
1.8.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 2/5] ARM: dts: Add initial LS1021A QDS board dts support
2014-07-02 9:02 ` Jingchang Lu
@ 2014-07-02 9:02 ` Jingchang Lu
-1 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-02 9:02 UTC (permalink / raw)
To: shawn.guo-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
Jingchang Lu, Alison Wang, Chao Fu, Jason Jin, Xiubo Li,
Bhupesh Sharma, Jaiprakash Singh, Jingchang Lu
From: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Alison Wang <alison.wang-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Chao Fu <B44548-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Jason Jin <Jason.Jin-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Xiubo Li <Li.Xiubo-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Jaiprakash Singh <b44839-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Jingchang Lu <jingchang.lu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/ls1021a-qds.dts | 380 ++++++++++++++++++++++++++++++++++++++
2 files changed, 382 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9e7adc..0569312 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -235,7 +235,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6sx-sdb.dtb \
vf610-colibri.dtb \
vf610-cosmic.dtb \
- vf610-twr.dtb
+ vf610-twr.dtb \
+ ls1021a-qds.dtb
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx23-olinuxino.dtb \
imx23-stmp378x_devb.dtb \
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
new file mode 100644
index 0000000..586165c
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -0,0 +1,380 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+ model = "LS1021A QDS Board";
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_3p3v: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+
+ sound {
+ compatible = "fsl,vf610-sgtl5000";
+ simple-audio-card,name = "FSL-VF610-TWR-BOARD";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu = <&sai2>;
+
+ simple-audio-card,codec = <&codec>;
+ };
+
+ soc {
+ leds {
+ compatible = "pwm-leds";
+ led0 {
+ label = "led0";
+ pwms = <&pwm3 0 150000 0>;
+ max-brightness = <100>;
+ };
+ led1 {
+ label = "led1";
+ pwms = <&pwm3 1 150000 0>;
+ max-brightness = <100>;
+ };
+ led2 {
+ label = "led2";
+ pwms = <&pwm3 2 150000 0>;
+ max-brightness = <100>;
+ };
+ led3 {
+ label = "led3";
+ pwms = <&pwm3 3 150000 0>;
+ max-brightness = <100>;
+ };
+ led4 {
+ label = "led4";
+ pwms = <&pwm3 4 150000 0>;
+ max-brightness = <100>;
+ };
+ led5 {
+ label = "led5";
+ pwms = <&pwm3 5 150000 0>;
+ max-brightness = <100>;
+ };
+ led6 {
+ label = "led6";
+ pwms = <&pwm3 6 150000 0>;
+ max-brightness = <100>;
+ };
+ led7 {
+ label = "led7";
+ pwms = <&pwm3 7 150000 0>;
+ max-brightness = <100>;
+ };
+ };
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: at45db021d@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
+
+&enet0 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&physgmii1c>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&physgmii1d>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&phyrgmii3>;
+ phy-connection-type = "rgmii";
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ pca9547@77 {
+ compatible = "philips,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+
+ ina220@41 {
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ eeprom@56 {
+ compatible = "at24,24c512";
+ reg = <0x56>;
+ };
+
+ eeprom@57 {
+ compatible = "at24,24c512";
+ reg = <0x57>;
+ };
+
+ adt7461a@4c {
+ compatible = "adt7461a";
+ reg = <0x4c>;
+ };
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ clocks = <&platform_clk 1>;
+ };
+ };
+
+ };
+
+};
+
+&ifc {
+ status = "okay";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+ 0x2 0x0 0x0 0x7e800000 0x00010000
+ 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc-nand";
+ reg = <0x2 0x0 0x10000>;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = <0x0 0x00100000>;
+ label = "NAND U-Boot Image";
+ read-only;
+ };
+
+ partition@100000 {
+ /* 1MB for DTB Image */
+ reg = <0x00100000 0x00100000>;
+ label = "NAND DTB Image";
+ };
+
+ partition@200000 {
+ /* 10MB for Linux Kernel Image */
+ reg = <0x00200000 0x00a00000>;
+ label = "NAND Linux Kernel Image";
+ };
+
+ partition@c00000 {
+ /* 500MB for Root file System Image */
+ reg = <0x00c00000 0x1f400000>;
+ label = "NAND Compressed RFS Image";
+ };
+ };
+
+ fpga: board-control@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1021aqds-fpga", "fsl,fpga-qixis";
+ reg = <0x3 0x0 0x0000100>;
+ bank-width = <1>;
+ device-width = <1>;
+ ranges = <0 3 0 0x100>;
+
+ mdio-mux-emi1 {
+ compatible = "mdio-mux-mmioreg";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1[2:0] */
+
+ /* Onboard PHYs */
+ ls1021amdio0: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phyrgmii1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ };
+ ls1021amdio1: mdio@20 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phyrgmii2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+ ls1021amdio2: mdio@40 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phyrgmii3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+ };
+ ls1021amdio3: mdio@60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ physgmii1c: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+ ls1021amdio4: mdio@80 {
+ reg = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ physgmii1d: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+ };
+
+ };
+
+ };
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm7 {
+ status = "okay";
+};
+
+&qspi {
+ num-cs = <2>;
+ bus-num = <0>;
+ fsl,spi-num-chipselects = <2>;
+ fsl,spi-flash-chipselects = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl129p1";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ partition@0 {
+ label = "s25fl128s-0";
+ reg = <0x0 0x1000000>;
+ };
+ };
+
+ qflash1: s25fl128s@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl129p1";
+ spi-max-frequency = <20000000>;
+ reg = <1>;
+
+ partition@0x0 {
+ label = "s25fl128s-1";
+ reg = <0x0 0x1000000>;
+ };
+ };
+};
--
1.8.0
--
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^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 2/5] ARM: dts: Add initial LS1021A QDS board dts support
@ 2014-07-02 9:02 ` Jingchang Lu
0 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-02 9:02 UTC (permalink / raw)
To: linux-arm-kernel
From: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Chao Fu <B44548@freescale.com>
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/ls1021a-qds.dts | 380 ++++++++++++++++++++++++++++++++++++++
2 files changed, 382 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9e7adc..0569312 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -235,7 +235,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6sx-sdb.dtb \
vf610-colibri.dtb \
vf610-cosmic.dtb \
- vf610-twr.dtb
+ vf610-twr.dtb \
+ ls1021a-qds.dtb
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx23-olinuxino.dtb \
imx23-stmp378x_devb.dtb \
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
new file mode 100644
index 0000000..586165c
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -0,0 +1,380 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+ model = "LS1021A QDS Board";
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_3p3v: regulator at 0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+
+ sound {
+ compatible = "fsl,vf610-sgtl5000";
+ simple-audio-card,name = "FSL-VF610-TWR-BOARD";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu = <&sai2>;
+
+ simple-audio-card,codec = <&codec>;
+ };
+
+ soc {
+ leds {
+ compatible = "pwm-leds";
+ led0 {
+ label = "led0";
+ pwms = <&pwm3 0 150000 0>;
+ max-brightness = <100>;
+ };
+ led1 {
+ label = "led1";
+ pwms = <&pwm3 1 150000 0>;
+ max-brightness = <100>;
+ };
+ led2 {
+ label = "led2";
+ pwms = <&pwm3 2 150000 0>;
+ max-brightness = <100>;
+ };
+ led3 {
+ label = "led3";
+ pwms = <&pwm3 3 150000 0>;
+ max-brightness = <100>;
+ };
+ led4 {
+ label = "led4";
+ pwms = <&pwm3 4 150000 0>;
+ max-brightness = <100>;
+ };
+ led5 {
+ label = "led5";
+ pwms = <&pwm3 5 150000 0>;
+ max-brightness = <100>;
+ };
+ led6 {
+ label = "led6";
+ pwms = <&pwm3 6 150000 0>;
+ max-brightness = <100>;
+ };
+ led7 {
+ label = "led7";
+ pwms = <&pwm3 7 150000 0>;
+ max-brightness = <100>;
+ };
+ };
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: at45db021d at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
+
+&enet0 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&physgmii1c>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&physgmii1d>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&phyrgmii3>;
+ phy-connection-type = "rgmii";
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ pca9547 at 77 {
+ compatible = "philips,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ rtc at 68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ ina220 at 40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+
+ ina220 at 41 {
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ eeprom at 56 {
+ compatible = "at24,24c512";
+ reg = <0x56>;
+ };
+
+ eeprom at 57 {
+ compatible = "at24,24c512";
+ reg = <0x57>;
+ };
+
+ adt7461a at 4c {
+ compatible = "adt7461a";
+ reg = <0x4c>;
+ };
+ };
+
+ i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ codec: sgtl5000 at 0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ clocks = <&platform_clk 1>;
+ };
+ };
+
+ };
+
+};
+
+&ifc {
+ status = "okay";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+ 0x2 0x0 0x0 0x7e800000 0x00010000
+ 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc-nand";
+ reg = <0x2 0x0 0x10000>;
+
+ partition at 0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = <0x0 0x00100000>;
+ label = "NAND U-Boot Image";
+ read-only;
+ };
+
+ partition at 100000 {
+ /* 1MB for DTB Image */
+ reg = <0x00100000 0x00100000>;
+ label = "NAND DTB Image";
+ };
+
+ partition at 200000 {
+ /* 10MB for Linux Kernel Image */
+ reg = <0x00200000 0x00a00000>;
+ label = "NAND Linux Kernel Image";
+ };
+
+ partition at c00000 {
+ /* 500MB for Root file System Image */
+ reg = <0x00c00000 0x1f400000>;
+ label = "NAND Compressed RFS Image";
+ };
+ };
+
+ fpga: board-control at 3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1021aqds-fpga", "fsl,fpga-qixis";
+ reg = <0x3 0x0 0x0000100>;
+ bank-width = <1>;
+ device-width = <1>;
+ ranges = <0 3 0 0x100>;
+
+ mdio-mux-emi1 {
+ compatible = "mdio-mux-mmioreg";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1[2:0] */
+
+ /* Onboard PHYs */
+ ls1021amdio0: mdio at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phyrgmii1: ethernet-phy at 1 {
+ reg = <0x1>;
+ };
+ };
+ ls1021amdio1: mdio at 20 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phyrgmii2: ethernet-phy at 2 {
+ reg = <0x2>;
+ };
+ };
+ ls1021amdio2: mdio at 40 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phyrgmii3: ethernet-phy at 3 {
+ reg = <0x3>;
+ };
+ };
+ ls1021amdio3: mdio at 60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ physgmii1c: ethernet-phy at 1c {
+ reg = <0x1c>;
+ };
+ };
+ ls1021amdio4: mdio at 80 {
+ reg = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ physgmii1d: ethernet-phy at 1d {
+ reg = <0x1d>;
+ };
+ };
+
+ };
+
+ };
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm7 {
+ status = "okay";
+};
+
+&qspi {
+ num-cs = <2>;
+ bus-num = <0>;
+ fsl,spi-num-chipselects = <2>;
+ fsl,spi-flash-chipselects = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl129p1";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ partition at 0 {
+ label = "s25fl128s-0";
+ reg = <0x0 0x1000000>;
+ };
+ };
+
+ qflash1: s25fl128s at 1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl129p1";
+ spi-max-frequency = <20000000>;
+ reg = <1>;
+
+ partition at 0x0 {
+ label = "s25fl128s-1";
+ reg = <0x0 0x1000000>;
+ };
+ };
+};
--
1.8.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 3/5] ARM: dts: Add initial LS1021A TWR board dts support
2014-07-02 9:02 ` Jingchang Lu
@ 2014-07-02 9:02 ` Jingchang Lu
-1 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-02 9:02 UTC (permalink / raw)
To: shawn.guo
Cc: mark.rutland, devicetree, Chen Lu, Chao Fu, Jingchang Lu,
linux-arm-kernel
Signed-off-by: Chen Lu <B46807@freescale.com>
Signed-off-by: Chao Fu <B44548@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/ls1021a-twr.dts | 236 ++++++++++++++++++++++++++++++++++++++
2 files changed, 238 insertions(+), 1 deletion(-)
create mode 100755 arch/arm/boot/dts/ls1021a-twr.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0569312..4482cc5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -236,7 +236,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
vf610-colibri.dtb \
vf610-cosmic.dtb \
vf610-twr.dtb \
- ls1021a-qds.dtb
+ ls1021a-qds.dtb \
+ ls1021a-twr.dtb
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx23-olinuxino.dtb \
imx23-stmp378x_devb.dtb \
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
new file mode 100755
index 0000000..16e4d7a
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -0,0 +1,236 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+ model = "LS1021A TWR Board";
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_3p3v: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+
+ sound {
+ compatible = "fsl,vf610-sgtl5000";
+ simple-audio-card,name = "FSL-VF610-TWR-BOARD";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu = <&sai2>;
+
+ simple-audio-card,codec = <&codec>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dspi1 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: s25fl064k@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl064k";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
+
+&enet0 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy2>;
+ phy-connection-type = "sgmii";
+ status = "ok";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "sgmii";
+ status = "ok";
+};
+
+&enet2 {
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "ok";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ codec: sgtl5000@14 {
+ compatible = "fsl,sgtl5000";
+ reg = <0x14>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ clocks = <&platform_clk 1>;
+ };
+};
+
+&ifc {
+ status = "okay";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, and CPLD on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ /* 128KB for rcw */
+ reg = <0x00000000 0x0020000>;
+ label = "NOR bank0 RCW Image";
+ };
+
+ partition@20000 {
+ /* 1MB for DTB */
+ reg = <0x00020000 0x00100000>;
+ label = "NOR DTB Image";
+ };
+
+ partition@120000 {
+ /* 8 MB for Linux Kernel Image */
+ reg = <0x00120000 0x00800000>;
+ label = "NOR Linux Kernel Image";
+ };
+
+ partition@920000 {
+ /* 56MB for Ramdisk Root File System */
+ reg = <0x00920000 0x03600000>;
+ label = "NOR Ramdisk Root File System Image";
+ };
+
+ partition@3f80000 {
+ /* 512KB for bank4 u-boot Image */
+ reg = <0x03f80000 0x80000>;
+ label = "NOR bank4 u-boot Image";
+ };
+
+ partition@4000000 {
+ /* 128KB for bank4 RCW Image */
+ reg = <0x04000000 0x20000>;
+ label = "NOR bank4 RCW Image";
+ };
+
+ partition@4020000 {
+ /* 63MB JFFS2 ROOT File System Image */
+ reg = <0x04020000 0x3f00000>;
+ label = "NOR JFFS2 ROOT File System Image";
+ };
+
+ partition@7f80000 {
+ /* 512KB for bank0 u-boot Image */
+ reg = <0x07f80000 0x80000>;
+ label = "NOR bank0 u-boot Image";
+ };
+
+ };
+
+ fpga: board-control@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1021aqds-fpga", "fsl,fpga-qixis";
+ reg = <0x2 0x0 0x00000100>;
+ bank-width = <1>;
+ device-width = <1>;
+ ranges = <0 2 0 0x100>;
+ };
+
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&mdio0 {
+ phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ tbi1: tbi-phy@1f {
+ reg = <0x1f>;
+ device_type = "tbi-phy";
+ };
+};
+
+&pwm6 {
+ status = "okay";
+};
+
+&pwm7 {
+ status = "okay";
+};
+
+&qspi {
+ num-cs = <2>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl128s";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ partition@0 {
+ label = "s25fl128s-0";
+ reg = <0x0 0x1000000>;
+ };
+ };
+};
--
1.8.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 3/5] ARM: dts: Add initial LS1021A TWR board dts support
@ 2014-07-02 9:02 ` Jingchang Lu
0 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-02 9:02 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Chen Lu <B46807@freescale.com>
Signed-off-by: Chao Fu <B44548@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/ls1021a-twr.dts | 236 ++++++++++++++++++++++++++++++++++++++
2 files changed, 238 insertions(+), 1 deletion(-)
create mode 100755 arch/arm/boot/dts/ls1021a-twr.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0569312..4482cc5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -236,7 +236,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
vf610-colibri.dtb \
vf610-cosmic.dtb \
vf610-twr.dtb \
- ls1021a-qds.dtb
+ ls1021a-qds.dtb \
+ ls1021a-twr.dtb
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx23-olinuxino.dtb \
imx23-stmp378x_devb.dtb \
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
new file mode 100755
index 0000000..16e4d7a
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -0,0 +1,236 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+ model = "LS1021A TWR Board";
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_3p3v: regulator at 0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+
+ sound {
+ compatible = "fsl,vf610-sgtl5000";
+ simple-audio-card,name = "FSL-VF610-TWR-BOARD";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu = <&sai2>;
+
+ simple-audio-card,codec = <&codec>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dspi1 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: s25fl064k at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl064k";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
+
+&enet0 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy2>;
+ phy-connection-type = "sgmii";
+ status = "ok";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "sgmii";
+ status = "ok";
+};
+
+&enet2 {
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "ok";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ codec: sgtl5000 at 14 {
+ compatible = "fsl,sgtl5000";
+ reg = <0x14>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ clocks = <&platform_clk 1>;
+ };
+};
+
+&ifc {
+ status = "okay";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, and CPLD on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition at 0 {
+ /* 128KB for rcw */
+ reg = <0x00000000 0x0020000>;
+ label = "NOR bank0 RCW Image";
+ };
+
+ partition at 20000 {
+ /* 1MB for DTB */
+ reg = <0x00020000 0x00100000>;
+ label = "NOR DTB Image";
+ };
+
+ partition at 120000 {
+ /* 8 MB for Linux Kernel Image */
+ reg = <0x00120000 0x00800000>;
+ label = "NOR Linux Kernel Image";
+ };
+
+ partition at 920000 {
+ /* 56MB for Ramdisk Root File System */
+ reg = <0x00920000 0x03600000>;
+ label = "NOR Ramdisk Root File System Image";
+ };
+
+ partition at 3f80000 {
+ /* 512KB for bank4 u-boot Image */
+ reg = <0x03f80000 0x80000>;
+ label = "NOR bank4 u-boot Image";
+ };
+
+ partition at 4000000 {
+ /* 128KB for bank4 RCW Image */
+ reg = <0x04000000 0x20000>;
+ label = "NOR bank4 RCW Image";
+ };
+
+ partition at 4020000 {
+ /* 63MB JFFS2 ROOT File System Image */
+ reg = <0x04020000 0x3f00000>;
+ label = "NOR JFFS2 ROOT File System Image";
+ };
+
+ partition at 7f80000 {
+ /* 512KB for bank0 u-boot Image */
+ reg = <0x07f80000 0x80000>;
+ label = "NOR bank0 u-boot Image";
+ };
+
+ };
+
+ fpga: board-control at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1021aqds-fpga", "fsl,fpga-qixis";
+ reg = <0x2 0x0 0x00000100>;
+ bank-width = <1>;
+ device-width = <1>;
+ ranges = <0 2 0 0x100>;
+ };
+
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&mdio0 {
+ phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy at 1 {
+ reg = <0x1>;
+ };
+ phy2: ethernet-phy at 2 {
+ reg = <0x2>;
+ };
+ tbi1: tbi-phy at 1f {
+ reg = <0x1f>;
+ device_type = "tbi-phy";
+ };
+};
+
+&pwm6 {
+ status = "okay";
+};
+
+&pwm7 {
+ status = "okay";
+};
+
+&qspi {
+ num-cs = <2>;
+ status = "okay";
+
+ qflash0: s25fl128s at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl128s";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ partition at 0 {
+ label = "s25fl128s-0";
+ reg = <0x0 0x1000000>;
+ };
+ };
+};
--
1.8.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021A
2014-07-02 9:02 ` Jingchang Lu
@ 2014-07-02 9:02 ` Jingchang Lu
-1 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-02 9:02 UTC (permalink / raw)
To: shawn.guo-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
Jingchang Lu
From: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
The LS1021A SoC is a dual-core Cortex-A7 based processor,
this add the initial support for it.
Signed-off-by: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
arch/arm/mach-imx/Kconfig | 17 ++++++++++++++
arch/arm/mach-imx/Makefile | 2 ++
arch/arm/mach-imx/mach-ls1021a.c | 49 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 68 insertions(+)
create mode 100644 arch/arm/mach-imx/mach-ls1021a.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index bdfe276..7f24892 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -762,6 +762,23 @@ config SOC_VF610
help
This enable support for Freescale Vybrid VF610 processor.
+config FSL_SOC
+ bool
+
+config SOC_LS1021A
+ bool "Freescale LS1021A support"
+ select CPU_V7
+ select ARM_GIC
+ select CLKSRC_OF
+ select HAVE_ARM_ARCH_TIMER
+ select HAVE_SMP
+ select FSL_SOC
+ select MIGHT_HAVE_PCI
+ select PCI_DOMAINS if PCI
+
+ help
+ This enable support for Freescale LS1021A processor.
+
endif
source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index a364e20..f49cbdb 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -114,4 +114,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
+obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
+
obj-y += devices/
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
new file mode 100644
index 0000000..d1a9bb9
--- /dev/null
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static const struct of_device_id of_ls1021a_match_table[] = {
+ {
+ .compatible = "simple-bus",
+ },
+ {
+ .compatible = "fsl,ifc",
+ },
+ {
+ .compatible = "fsl,fpga-qixis",
+ },
+ {
+ .compatible = "fsl,qe",
+ },
+ {}
+};
+
+static void __init ls1021a_init_machine(void)
+{
+ mxc_arch_reset_init_dt();
+ of_platform_populate(NULL, of_ls1021a_match_table, NULL, NULL);
+}
+
+static const char *ls1021a_dt_compat[] __initdata = {
+ "fsl,ls1021a",
+ NULL,
+};
+
+DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+#ifdef CONFIG_ZONE_DMA
+ .dma_zone_size = SZ_128M,
+#endif
+ .init_machine = ls1021a_init_machine,
+ .dt_compat = ls1021a_dt_compat,
+ .restart = mxc_restart,
+MACHINE_END
--
1.8.0
--
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^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021A
@ 2014-07-02 9:02 ` Jingchang Lu
0 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-02 9:02 UTC (permalink / raw)
To: linux-arm-kernel
From: Jingchang Lu <b35083@freescale.com>
The LS1021A SoC is a dual-core Cortex-A7 based processor,
this add the initial support for it.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
---
arch/arm/mach-imx/Kconfig | 17 ++++++++++++++
arch/arm/mach-imx/Makefile | 2 ++
arch/arm/mach-imx/mach-ls1021a.c | 49 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 68 insertions(+)
create mode 100644 arch/arm/mach-imx/mach-ls1021a.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index bdfe276..7f24892 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -762,6 +762,23 @@ config SOC_VF610
help
This enable support for Freescale Vybrid VF610 processor.
+config FSL_SOC
+ bool
+
+config SOC_LS1021A
+ bool "Freescale LS1021A support"
+ select CPU_V7
+ select ARM_GIC
+ select CLKSRC_OF
+ select HAVE_ARM_ARCH_TIMER
+ select HAVE_SMP
+ select FSL_SOC
+ select MIGHT_HAVE_PCI
+ select PCI_DOMAINS if PCI
+
+ help
+ This enable support for Freescale LS1021A processor.
+
endif
source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index a364e20..f49cbdb 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -114,4 +114,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
+obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
+
obj-y += devices/
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
new file mode 100644
index 0000000..d1a9bb9
--- /dev/null
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static const struct of_device_id of_ls1021a_match_table[] = {
+ {
+ .compatible = "simple-bus",
+ },
+ {
+ .compatible = "fsl,ifc",
+ },
+ {
+ .compatible = "fsl,fpga-qixis",
+ },
+ {
+ .compatible = "fsl,qe",
+ },
+ {}
+};
+
+static void __init ls1021a_init_machine(void)
+{
+ mxc_arch_reset_init_dt();
+ of_platform_populate(NULL, of_ls1021a_match_table, NULL, NULL);
+}
+
+static const char *ls1021a_dt_compat[] __initdata = {
+ "fsl,ls1021a",
+ NULL,
+};
+
+DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+#ifdef CONFIG_ZONE_DMA
+ .dma_zone_size = SZ_128M,
+#endif
+ .init_machine = ls1021a_init_machine,
+ .dt_compat = ls1021a_dt_compat,
+ .restart = mxc_restart,
+MACHINE_END
--
1.8.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 5/5] ARM: imx: Add Freescale LS1021A SMP support
2014-07-02 9:02 ` Jingchang Lu
@ 2014-07-02 9:02 ` Jingchang Lu
-1 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-02 9:02 UTC (permalink / raw)
To: shawn.guo-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
Jingchang Lu
From: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Freescale LS1021A SoC deploys two cortex-A7 processors,
this adds bring-up support for the secondary core.
Signed-off-by: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
arch/arm/mach-imx/common.h | 2 ++
arch/arm/mach-imx/headsmp.S | 11 ++++++++++
arch/arm/mach-imx/mach-ls1021a.c | 1 +
arch/arm/mach-imx/platsmp.c | 44 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 58 insertions(+)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index e0632d1..8cdd498 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -98,6 +98,7 @@ void v7_secondary_startup(void);
void imx_scu_map_io(void);
void imx_smp_prepare(void);
void imx_scu_standby_enable(void);
+void ls1021a_secondary_startup(void);
#else
static inline void imx_scu_map_io(void) {}
static inline void imx_smp_prepare(void) {}
@@ -158,5 +159,6 @@ static inline void imx_init_l2cache(void) {}
#endif
extern struct smp_operations imx_smp_ops;
+extern struct smp_operations ls1021a_smp_ops;
#endif
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index de5047c..fdd93d9 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -29,3 +29,14 @@ ENTRY(v7_secondary_startup)
set_diag_reg
b secondary_startup
ENDPROC(v7_secondary_startup)
+
+ENTRY(ls1021a_secondary_startup)
+ /* set CNTFREQ of secondary core */
+ ldr r0, =12500000
+ mcr p15, 0, r0, c14, c0, 0
+ /* disable Physical and Virtural Timer */
+ mov r0, #0x0
+ mcr p15, 0, r0, c14, c2, 1
+ mcr p15, 0, r0, c14, c3, 1
+ b secondary_startup
+ENDPROC(ls1021a_secondary_startup)
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
index d1a9bb9..9931c5b 100644
--- a/arch/arm/mach-imx/mach-ls1021a.c
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -43,6 +43,7 @@ DT_MACHINE_START(LS1021A, "Freescale LS1021A")
#ifdef CONFIG_ZONE_DMA
.dma_zone_size = SZ_128M,
#endif
+ .smp = smp_ops(ls1021a_smp_ops),
.init_machine = ls1021a_init_machine,
.dt_compat = ls1021a_dt_compat,
.restart = mxc_restart,
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 5b57c17..8e1bcce 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -16,6 +16,8 @@
#include <asm/page.h>
#include <asm/smp_scu.h>
#include <asm/mach/map.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
#include "common.h"
#include "hardware.h"
@@ -104,3 +106,45 @@ struct smp_operations imx_smp_ops __initdata = {
.cpu_kill = imx_cpu_kill,
#endif
};
+
+static void __iomem *dcfg_base;
+#define DCFG_CCSR_BRR 0xE4
+#define DCFG_CCSR_SCRATCHRW1 0x200
+
+static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ unsigned long paddr;
+
+ paddr = virt_to_phys(ls1021a_secondary_startup);
+ writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
+ /* release core for booting */
+ writel_relaxed(cpu_to_be32(0x1 << cpu), dcfg_base + DCFG_CCSR_BRR);
+
+ return 0;
+}
+
+static void __init ls1021a_smp_init_cpus(void)
+{
+ int i, ncores;
+ /* get number of cores from CP15 L2 controller register(L2CTLR)*/
+ asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (ncores));
+
+ ncores = ((ncores >> 24) & 0x3) + 1;
+ for (i = ncores; i < NR_CPUS; i++)
+ set_cpu_possible(i, false);
+}
+
+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+ dcfg_base = of_iomap(np, 0);
+ WARN_ON(!dcfg_base);
+}
+
+struct smp_operations ls1021a_smp_ops __initdata = {
+ .smp_init_cpus = ls1021a_smp_init_cpus,
+ .smp_prepare_cpus = ls1021a_smp_prepare_cpus,
+ .smp_boot_secondary = ls1021a_boot_secondary,
+};
--
1.8.0
--
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^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 5/5] ARM: imx: Add Freescale LS1021A SMP support
@ 2014-07-02 9:02 ` Jingchang Lu
0 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-02 9:02 UTC (permalink / raw)
To: linux-arm-kernel
From: Jingchang Lu <b35083@freescale.com>
Freescale LS1021A SoC deploys two cortex-A7 processors,
this adds bring-up support for the secondary core.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
---
arch/arm/mach-imx/common.h | 2 ++
arch/arm/mach-imx/headsmp.S | 11 ++++++++++
arch/arm/mach-imx/mach-ls1021a.c | 1 +
arch/arm/mach-imx/platsmp.c | 44 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 58 insertions(+)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index e0632d1..8cdd498 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -98,6 +98,7 @@ void v7_secondary_startup(void);
void imx_scu_map_io(void);
void imx_smp_prepare(void);
void imx_scu_standby_enable(void);
+void ls1021a_secondary_startup(void);
#else
static inline void imx_scu_map_io(void) {}
static inline void imx_smp_prepare(void) {}
@@ -158,5 +159,6 @@ static inline void imx_init_l2cache(void) {}
#endif
extern struct smp_operations imx_smp_ops;
+extern struct smp_operations ls1021a_smp_ops;
#endif
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index de5047c..fdd93d9 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -29,3 +29,14 @@ ENTRY(v7_secondary_startup)
set_diag_reg
b secondary_startup
ENDPROC(v7_secondary_startup)
+
+ENTRY(ls1021a_secondary_startup)
+ /* set CNTFREQ of secondary core */
+ ldr r0, =12500000
+ mcr p15, 0, r0, c14, c0, 0
+ /* disable Physical and Virtural Timer */
+ mov r0, #0x0
+ mcr p15, 0, r0, c14, c2, 1
+ mcr p15, 0, r0, c14, c3, 1
+ b secondary_startup
+ENDPROC(ls1021a_secondary_startup)
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
index d1a9bb9..9931c5b 100644
--- a/arch/arm/mach-imx/mach-ls1021a.c
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -43,6 +43,7 @@ DT_MACHINE_START(LS1021A, "Freescale LS1021A")
#ifdef CONFIG_ZONE_DMA
.dma_zone_size = SZ_128M,
#endif
+ .smp = smp_ops(ls1021a_smp_ops),
.init_machine = ls1021a_init_machine,
.dt_compat = ls1021a_dt_compat,
.restart = mxc_restart,
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 5b57c17..8e1bcce 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -16,6 +16,8 @@
#include <asm/page.h>
#include <asm/smp_scu.h>
#include <asm/mach/map.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
#include "common.h"
#include "hardware.h"
@@ -104,3 +106,45 @@ struct smp_operations imx_smp_ops __initdata = {
.cpu_kill = imx_cpu_kill,
#endif
};
+
+static void __iomem *dcfg_base;
+#define DCFG_CCSR_BRR 0xE4
+#define DCFG_CCSR_SCRATCHRW1 0x200
+
+static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ unsigned long paddr;
+
+ paddr = virt_to_phys(ls1021a_secondary_startup);
+ writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
+ /* release core for booting */
+ writel_relaxed(cpu_to_be32(0x1 << cpu), dcfg_base + DCFG_CCSR_BRR);
+
+ return 0;
+}
+
+static void __init ls1021a_smp_init_cpus(void)
+{
+ int i, ncores;
+ /* get number of cores from CP15 L2 controller register(L2CTLR)*/
+ asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (ncores));
+
+ ncores = ((ncores >> 24) & 0x3) + 1;
+ for (i = ncores; i < NR_CPUS; i++)
+ set_cpu_possible(i, false);
+}
+
+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+ dcfg_base = of_iomap(np, 0);
+ WARN_ON(!dcfg_base);
+}
+
+struct smp_operations ls1021a_smp_ops __initdata = {
+ .smp_init_cpus = ls1021a_smp_init_cpus,
+ .smp_prepare_cpus = ls1021a_smp_prepare_cpus,
+ .smp_boot_secondary = ls1021a_boot_secondary,
+};
--
1.8.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] ARM: dts: Add SoC level device tree support for LS1021A
2014-07-02 9:02 ` Jingchang Lu
@ 2014-07-02 11:14 ` Mark Rutland
-1 siblings, 0 replies; 30+ messages in thread
From: Mark Rutland @ 2014-07-02 11:14 UTC (permalink / raw)
To: Jingchang Lu
Cc: shawn.guo-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Jingchang Lu, Nikhil Badola,
Chenhui Zhao, Suresh Gupta, Shaveta Leekha, Adrian Sendroiu,
Ruchika Gupta, Bhupesh Sharma, Chao Fu, Xiubo Li
Hi,
As a general note, there seem to be many nodes for which bindings and
drivers do not yet exist.
For those nodes which are unusable for reasons other than their status
being "disabled", I would prefer that they were removed. They're useless
now, and might not match the bindings that are eventually decided upon,
which will result in annoying churn and possible breakage.
On Wed, Jul 02, 2014 at 10:02:48AM +0100, Jingchang Lu wrote:
> From: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
>
> Add Freescale LS1021A SoC device tree support
>
> Signed-off-by: Nikhil Badola <nikhil.badola-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Chenhui Zhao <chenhui.zhao-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Suresh Gupta <suresh.gupta-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Shaveta Leekha <shaveta-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Adrian Sendroiu <adrian.sendroiu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Ruchika Gupta <ruchika.gupta-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Chao Fu <b44548-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Xiubo Li <Li.Xiubo-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Jingchang Lu <jingchang.lu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> ---
> arch/arm/boot/dts/ls1021a.dtsi | 852 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 852 insertions(+)
> create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
>
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> new file mode 100644
> index 0000000..b06b320
> --- /dev/null
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
[...]
> + memory {
> + reg = <0x0 0x80000000 0x0 0x20000000>;
> + };
Missing device_type = "memory";
For unit-address and reg consistency, this should be memory@0,80000000.
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0xf00>;
> + };
That reg doesn't match the unit-address, which should be cpu@f00.
Why is MPIDR.Aff1 == 0xf?
> +
> + cpu@1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0xf01>;
> + };
Likewise.
[...]
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
Please put the compatible first out of all properties, it makes it far
easier to read the DTS.
Please do that for other nodes too.
> + interrupt-parent = <&gic>;
> + ranges;
> +
> + gic: interrupt-controller@1400000 {
> + compatible = "arm,cortex-a15-gic";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x1401000 0x0 0x1000>,
> + <0x0 0x1402000 0x0 0x1000>,
> + <0x0 0x1404000 0x0 0x2000>,
> + <0x0 0x1406000 0x0 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> +
> + };
> +
> + tzasc: tzasc@1500000 {
> + reg = <0x0 0x1500000 0x0 0x10000>;
> + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
There's no compatible string and "tzasc" doesn't appear to be handled
magically anywhere, so this can't be probed even without the status
property being "disabled".
Why is this here?
> +
> + ifc: ifc@1530000 {
> + compatible = "fsl,ls1021a-ifc", "fsl,ifc", "simple-bus";
This doesn't seem to have any children, ranges, #address-cells, or
#size-cells. So why is "simple-bus" in the compatible list?
As far as I can see this is a flash controller, so "simple-bus" doesn't
make any sense whatsoever (and existing uses, including that in the
binding are a bug).
> + reg = <0x0 0x1530000 0x0 0x10000>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + dcfg: dcfg@1ee0000 {
> + compatible = "fsl,ls1021a-dcfg";
> + reg = <0x0 0x1ee0000 0x0 0x10000>;
> + };
Undocumented/unsupported binding.
What is this?
> + qspi: quadspi@1550000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,vf610-qspi";
Please put the compatible string first. It makes it easier to find.
> + reg = <0x0 0x1550000 0x0 0x10000>;
Missing the second reg entry? The binding didn't state it was optional.
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "qspi_en", "qspi";
> + clocks = <&platform_clk 1>, <&platform_clk 1>;
Normally we put $X before $X-names properties.
I note that these clock-names are poorly documented. It would be nice to
see that fixed up.
> + big-endian;
The binding doesn't mention this. Does the driver support it?
> + amba-base = <0x40000000>;
The string "amba-base" shows up nowhere in mainline. What is this, and
why is it here?
[...]
> + scfg: scfg@1570000 {
> + compatible = "fsl,ls1021a-scfg";
> + reg = <0x0 0x1570000 0x0 0x10000>;
> + };
Undocumented/unsupported binding.
What is this?
[...]
> + rcpm: rcpm@1ee2000 {
> + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1";
> + reg = <0x0 0x1ee2000 0x0 0x10000>;
> + };
Undocumented/unsupported binding (both compatible strings).
What is this?
[...]
> + gpio1: gpio@2300000 {
> + compatible = "fsl,ls1021a-gpio";
> + reg = <0x0 0x2300000 0x0 0x10000>;
> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
Undocumented/unsupported binding.
[...]
> + lpuart1: serial@2960000 {
> + compatible = "fsl,ls1021a-lpuart";
> + reg = <0x0 0x2960000 0x0 0x1000>;
> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&platform_clk 1>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
Undocumented/unsupported binding.
[...]
> + ftm2: ftm@29f0000 {
> + reg = <0x0 0x29f0000 0x0 0x10000>;
> + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
Missing compatible strings.
[...]
> + ftm5: ftm@2a20000 {
> + reg = <0x0 0x2a20000 0x0 0x10000>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
Missing compatible strings.
[...]
> + wdog0: wdog@2ad0000 {
> + compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt";
> + reg = <0x0 0x2ad0000 0x0 0x10000>;
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&platform_clk 1>;
> + clock-names = "wdog";
> + big-endian;
> + };
That clock name looks aribitrary, and "fsl,imx21-wdt" isn't documented
as taking a clock.
What is going on here?
[...]
> + can0: can@2a70000 {
> + compatible = "fsl,ls1021a-flexcan";
> + reg = <0x0 0x2a70000 0x0 0x1000>;
> + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&platform_clk 1>;
> + clock-names = "per";
> + status = "disabled";
> + };
Undocumented/unsupported binding.
Was this mean to have an existing compatible string in the list?
> +
> + can1: can@2a80000 {
> + compatible = "fsl,ls1021a-flexcan";
> + reg = <0x0 0x2a80000 0x0 0x1000>;
> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&platform_clk 1>;
> + clock-names = "per";
> + status = "disabled";
> + };
> +
> + can2: can@2a90000 {
> + compatible = "fsl,ls1021a-flexcan";
> + reg = <0x0 0x2a90000 0x0 0x1000>;
> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&platform_clk 1>;
> + clock-names = "per";
> + status = "disabled";
> + };
> +
> + can3: can@2aa0000 {
> + compatible = "fsl,ls1021a-flexcan";
> + reg = <0x0 0x2aa0000 0x0 0x1000>;
> + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&platform_clk 1>;
> + clock-names = "per";
> + status = "disabled";
> + };
> + };
> +
> + dcsr@20000000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,ls1021a-dcsr", "simple-bus";
Missing a reg entry? Or is the unit-address arbitrary?
The "fsl,ls1021a-dcsr" string is undocumented/unsupported, as with the
compatible strings of all the child nodes below.
Thanks,
Mark.
> +
> + ranges = <0x0 0x0 0x20000000 0x1000000>;
> +
> + dcsr-epu@0 {
> + compatible = "fsl,ls1021a-dcsr-epu";
> + reg = <0x0 0x10000>;
> + };
> +
> + dcsr-gdi@100000 {
> + compatible = "fsl,ls1021a-dcsr-gdi";
> + reg = <0x100000 0x10000>;
> + };
> +
> + dcsr-dddi@120000 {
> + compatible = "fsl,ls1021a-dcsr-dddi";
> + reg = <0x120000 0x10000>;
> + };
> +
> + dcsr-dcfg@220000 {
> + compatible = "fsl,ls1021a-dcsr-dcfg";
> + reg = <0x220000 0x1000>;
> + };
> +
> + dcsr-clock@221000 {
> + compatible = "fsl,ls1021a-dcsr-clock";
> + reg = <0x221000 0x1000>;
> + };
> +
> + dcsr-rcpm@222000 {
> + compatible = "fsl,ls1021a-dcsr-rcpm";
> + reg = <0x222000 0x1000 0x223000 0x1000>;
> + };
> +
> + dcsr-ccp@225000 {
> + compatible = "fsl,ls1021a-dcsr-ccp";
> + reg = <0x225000 0x1000>;
> + };
> +
> + dcsr-fusectrl@226000 {
> + compatible = "fsl,ls1021a-dcsr-fusectrl";
> + reg = <0x226000 0x1000>;
> + };
> +
> + dcsr-dap@300000 {
> + compatible = "fsl,ls1021a-dcsr-dap";
> + reg = <0x300000 0x10000>;
> + };
> +
> + dcsr-cstf@350000 {
> + compatible = "fsl,ls1021a-dcsr-cstf";
> + reg = <0x350000 0x1000 0x3a7000 0x1000>;
> + };
> +
> + dcsr-a7rom@360000 {
> + compatible = "fsl,ls1021a-dcsr-a7rom";
> + reg = <0x360000 0x10000>;
> + };
> +
> + dcsr-a7cpu@370000 {
> + compatible = "fsl,ls1021a-dcsr-a7cpu";
> + reg = <0x370000 0x8000>;
> + };
> +
> + dcsr-a7cti@378000 {
> + compatible = "fsl,ls1021a-dcsr-a7cti";
> + reg = <0x378000 0x4000>;
> + };
> +
> + dcsr-etm@37c000 {
> + compatible = "fsl,ls1021a-dcsr-etm";
> + reg = <0x37c000 0x1000 0x37d000 0x3000>;
> + };
> +
> + dcsr-hugorom@3a0000 {
> + compatible = "fsl,ls1021a-dcsr-hugorom";
> + reg = <0x3a0000 0x1000>;
> + };
> +
> + dcsr-etf@3a1000 {
> + compatible = "fsl,ls1021a-dcsr-etf";
> + reg = <0x3a1000 0x1000 0x3a2000 0x1000>;
> + };
> +
> + dcsr-etr@3a3000 {
> + compatible = "fsl,ls1021a-dcsr-etr";
> + reg = <0x3a3000 0x1000>;
> + };
> +
> + dcsr-cti@3a4000 {
> + compatible = "fsl,ls1021a-dcsr-cti";
> + reg = <0x3a4000 0x1000 0x3a5000 0x1000 0x3a6000 0x1000>;
> + };
> +
> + dcsr-atbrepl@3a8000 {
> + compatible = "fsl,ls1021a-dcsr-atbrepl";
> + reg = <0x3a8000 0x1000>;
> + };
> +
> + dcsr-tsgen-ctrl@3a9000 {
> + compatible = "fsl,ls1021a-dcsr-tsgen-ctrl";
> + reg = <0x3a9000 0x1000>;
> + };
> +
> + dcsr-tsgen-read@3aa000 {
> + compatible = "fsl,ls1021a-dcsr-tsgen-read";
> + reg = <0x3aa000 0x1000>;
> + };
> + };
> +};
> --
> 1.8.0
>
> --
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 1/5] ARM: dts: Add SoC level device tree support for LS1021A
@ 2014-07-02 11:14 ` Mark Rutland
0 siblings, 0 replies; 30+ messages in thread
From: Mark Rutland @ 2014-07-02 11:14 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
As a general note, there seem to be many nodes for which bindings and
drivers do not yet exist.
For those nodes which are unusable for reasons other than their status
being "disabled", I would prefer that they were removed. They're useless
now, and might not match the bindings that are eventually decided upon,
which will result in annoying churn and possible breakage.
On Wed, Jul 02, 2014 at 10:02:48AM +0100, Jingchang Lu wrote:
> From: Jingchang Lu <b35083@freescale.com>
>
> Add Freescale LS1021A SoC device tree support
>
> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Adrian Sendroiu <adrian.sendroiu@freescale.com>
> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> Signed-off-by: Chao Fu <b44548@freescale.com>
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
> ---
> arch/arm/boot/dts/ls1021a.dtsi | 852 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 852 insertions(+)
> create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
>
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> new file mode 100644
> index 0000000..b06b320
> --- /dev/null
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
[...]
> + memory {
> + reg = <0x0 0x80000000 0x0 0x20000000>;
> + };
Missing device_type = "memory";
For unit-address and reg consistency, this should be memory at 0,80000000.
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu at 0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0xf00>;
> + };
That reg doesn't match the unit-address, which should be cpu at f00.
Why is MPIDR.Aff1 == 0xf?
> +
> + cpu at 1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0xf01>;
> + };
Likewise.
[...]
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
Please put the compatible first out of all properties, it makes it far
easier to read the DTS.
Please do that for other nodes too.
> + interrupt-parent = <&gic>;
> + ranges;
> +
> + gic: interrupt-controller at 1400000 {
> + compatible = "arm,cortex-a15-gic";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x1401000 0x0 0x1000>,
> + <0x0 0x1402000 0x0 0x1000>,
> + <0x0 0x1404000 0x0 0x2000>,
> + <0x0 0x1406000 0x0 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> +
> + };
> +
> + tzasc: tzasc at 1500000 {
> + reg = <0x0 0x1500000 0x0 0x10000>;
> + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
There's no compatible string and "tzasc" doesn't appear to be handled
magically anywhere, so this can't be probed even without the status
property being "disabled".
Why is this here?
> +
> + ifc: ifc at 1530000 {
> + compatible = "fsl,ls1021a-ifc", "fsl,ifc", "simple-bus";
This doesn't seem to have any children, ranges, #address-cells, or
#size-cells. So why is "simple-bus" in the compatible list?
As far as I can see this is a flash controller, so "simple-bus" doesn't
make any sense whatsoever (and existing uses, including that in the
binding are a bug).
> + reg = <0x0 0x1530000 0x0 0x10000>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + dcfg: dcfg at 1ee0000 {
> + compatible = "fsl,ls1021a-dcfg";
> + reg = <0x0 0x1ee0000 0x0 0x10000>;
> + };
Undocumented/unsupported binding.
What is this?
> + qspi: quadspi at 1550000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,vf610-qspi";
Please put the compatible string first. It makes it easier to find.
> + reg = <0x0 0x1550000 0x0 0x10000>;
Missing the second reg entry? The binding didn't state it was optional.
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "qspi_en", "qspi";
> + clocks = <&platform_clk 1>, <&platform_clk 1>;
Normally we put $X before $X-names properties.
I note that these clock-names are poorly documented. It would be nice to
see that fixed up.
> + big-endian;
The binding doesn't mention this. Does the driver support it?
> + amba-base = <0x40000000>;
The string "amba-base" shows up nowhere in mainline. What is this, and
why is it here?
[...]
> + scfg: scfg at 1570000 {
> + compatible = "fsl,ls1021a-scfg";
> + reg = <0x0 0x1570000 0x0 0x10000>;
> + };
Undocumented/unsupported binding.
What is this?
[...]
> + rcpm: rcpm at 1ee2000 {
> + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1";
> + reg = <0x0 0x1ee2000 0x0 0x10000>;
> + };
Undocumented/unsupported binding (both compatible strings).
What is this?
[...]
> + gpio1: gpio at 2300000 {
> + compatible = "fsl,ls1021a-gpio";
> + reg = <0x0 0x2300000 0x0 0x10000>;
> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
Undocumented/unsupported binding.
[...]
> + lpuart1: serial at 2960000 {
> + compatible = "fsl,ls1021a-lpuart";
> + reg = <0x0 0x2960000 0x0 0x1000>;
> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&platform_clk 1>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
Undocumented/unsupported binding.
[...]
> + ftm2: ftm at 29f0000 {
> + reg = <0x0 0x29f0000 0x0 0x10000>;
> + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
Missing compatible strings.
[...]
> + ftm5: ftm at 2a20000 {
> + reg = <0x0 0x2a20000 0x0 0x10000>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
Missing compatible strings.
[...]
> + wdog0: wdog at 2ad0000 {
> + compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt";
> + reg = <0x0 0x2ad0000 0x0 0x10000>;
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&platform_clk 1>;
> + clock-names = "wdog";
> + big-endian;
> + };
That clock name looks aribitrary, and "fsl,imx21-wdt" isn't documented
as taking a clock.
What is going on here?
[...]
> + can0: can at 2a70000 {
> + compatible = "fsl,ls1021a-flexcan";
> + reg = <0x0 0x2a70000 0x0 0x1000>;
> + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&platform_clk 1>;
> + clock-names = "per";
> + status = "disabled";
> + };
Undocumented/unsupported binding.
Was this mean to have an existing compatible string in the list?
> +
> + can1: can at 2a80000 {
> + compatible = "fsl,ls1021a-flexcan";
> + reg = <0x0 0x2a80000 0x0 0x1000>;
> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&platform_clk 1>;
> + clock-names = "per";
> + status = "disabled";
> + };
> +
> + can2: can at 2a90000 {
> + compatible = "fsl,ls1021a-flexcan";
> + reg = <0x0 0x2a90000 0x0 0x1000>;
> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&platform_clk 1>;
> + clock-names = "per";
> + status = "disabled";
> + };
> +
> + can3: can at 2aa0000 {
> + compatible = "fsl,ls1021a-flexcan";
> + reg = <0x0 0x2aa0000 0x0 0x1000>;
> + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&platform_clk 1>;
> + clock-names = "per";
> + status = "disabled";
> + };
> + };
> +
> + dcsr at 20000000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,ls1021a-dcsr", "simple-bus";
Missing a reg entry? Or is the unit-address arbitrary?
The "fsl,ls1021a-dcsr" string is undocumented/unsupported, as with the
compatible strings of all the child nodes below.
Thanks,
Mark.
> +
> + ranges = <0x0 0x0 0x20000000 0x1000000>;
> +
> + dcsr-epu at 0 {
> + compatible = "fsl,ls1021a-dcsr-epu";
> + reg = <0x0 0x10000>;
> + };
> +
> + dcsr-gdi at 100000 {
> + compatible = "fsl,ls1021a-dcsr-gdi";
> + reg = <0x100000 0x10000>;
> + };
> +
> + dcsr-dddi at 120000 {
> + compatible = "fsl,ls1021a-dcsr-dddi";
> + reg = <0x120000 0x10000>;
> + };
> +
> + dcsr-dcfg at 220000 {
> + compatible = "fsl,ls1021a-dcsr-dcfg";
> + reg = <0x220000 0x1000>;
> + };
> +
> + dcsr-clock at 221000 {
> + compatible = "fsl,ls1021a-dcsr-clock";
> + reg = <0x221000 0x1000>;
> + };
> +
> + dcsr-rcpm at 222000 {
> + compatible = "fsl,ls1021a-dcsr-rcpm";
> + reg = <0x222000 0x1000 0x223000 0x1000>;
> + };
> +
> + dcsr-ccp at 225000 {
> + compatible = "fsl,ls1021a-dcsr-ccp";
> + reg = <0x225000 0x1000>;
> + };
> +
> + dcsr-fusectrl at 226000 {
> + compatible = "fsl,ls1021a-dcsr-fusectrl";
> + reg = <0x226000 0x1000>;
> + };
> +
> + dcsr-dap at 300000 {
> + compatible = "fsl,ls1021a-dcsr-dap";
> + reg = <0x300000 0x10000>;
> + };
> +
> + dcsr-cstf at 350000 {
> + compatible = "fsl,ls1021a-dcsr-cstf";
> + reg = <0x350000 0x1000 0x3a7000 0x1000>;
> + };
> +
> + dcsr-a7rom at 360000 {
> + compatible = "fsl,ls1021a-dcsr-a7rom";
> + reg = <0x360000 0x10000>;
> + };
> +
> + dcsr-a7cpu at 370000 {
> + compatible = "fsl,ls1021a-dcsr-a7cpu";
> + reg = <0x370000 0x8000>;
> + };
> +
> + dcsr-a7cti at 378000 {
> + compatible = "fsl,ls1021a-dcsr-a7cti";
> + reg = <0x378000 0x4000>;
> + };
> +
> + dcsr-etm at 37c000 {
> + compatible = "fsl,ls1021a-dcsr-etm";
> + reg = <0x37c000 0x1000 0x37d000 0x3000>;
> + };
> +
> + dcsr-hugorom at 3a0000 {
> + compatible = "fsl,ls1021a-dcsr-hugorom";
> + reg = <0x3a0000 0x1000>;
> + };
> +
> + dcsr-etf at 3a1000 {
> + compatible = "fsl,ls1021a-dcsr-etf";
> + reg = <0x3a1000 0x1000 0x3a2000 0x1000>;
> + };
> +
> + dcsr-etr at 3a3000 {
> + compatible = "fsl,ls1021a-dcsr-etr";
> + reg = <0x3a3000 0x1000>;
> + };
> +
> + dcsr-cti at 3a4000 {
> + compatible = "fsl,ls1021a-dcsr-cti";
> + reg = <0x3a4000 0x1000 0x3a5000 0x1000 0x3a6000 0x1000>;
> + };
> +
> + dcsr-atbrepl at 3a8000 {
> + compatible = "fsl,ls1021a-dcsr-atbrepl";
> + reg = <0x3a8000 0x1000>;
> + };
> +
> + dcsr-tsgen-ctrl at 3a9000 {
> + compatible = "fsl,ls1021a-dcsr-tsgen-ctrl";
> + reg = <0x3a9000 0x1000>;
> + };
> +
> + dcsr-tsgen-read at 3aa000 {
> + compatible = "fsl,ls1021a-dcsr-tsgen-read";
> + reg = <0x3aa000 0x1000>;
> + };
> + };
> +};
> --
> 1.8.0
>
> --
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> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021A
2014-07-02 9:02 ` Jingchang Lu
@ 2014-07-02 11:21 ` Mark Rutland
-1 siblings, 0 replies; 30+ messages in thread
From: Mark Rutland @ 2014-07-02 11:21 UTC (permalink / raw)
To: Jingchang Lu
Cc: shawn.guo-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Jingchang Lu
On Wed, Jul 02, 2014 at 10:02:51AM +0100, Jingchang Lu wrote:
> From: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
>
> The LS1021A SoC is a dual-core Cortex-A7 based processor,
> this add the initial support for it.
>
> Signed-off-by: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> ---
> arch/arm/mach-imx/Kconfig | 17 ++++++++++++++
> arch/arm/mach-imx/Makefile | 2 ++
> arch/arm/mach-imx/mach-ls1021a.c | 49 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 68 insertions(+)
> create mode 100644 arch/arm/mach-imx/mach-ls1021a.c
>
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index bdfe276..7f24892 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -762,6 +762,23 @@ config SOC_VF610
> help
> This enable support for Freescale Vybrid VF610 processor.
>
> +config FSL_SOC
> + bool
> +
> +config SOC_LS1021A
> + bool "Freescale LS1021A support"
> + select CPU_V7
> + select ARM_GIC
> + select CLKSRC_OF
> + select HAVE_ARM_ARCH_TIMER
> + select HAVE_SMP
> + select FSL_SOC
> + select MIGHT_HAVE_PCI
> + select PCI_DOMAINS if PCI
> +
> + help
> + This enable support for Freescale LS1021A processor.
> +
> endif
>
> source "arch/arm/mach-imx/devices/Kconfig"
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index a364e20..f49cbdb 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -114,4 +114,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
>
> obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
>
> +obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
> +
> obj-y += devices/
> diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
> new file mode 100644
> index 0000000..d1a9bb9
> --- /dev/null
> +++ b/arch/arm/mach-imx/mach-ls1021a.c
> @@ -0,0 +1,49 @@
> +/*
> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/of_platform.h>
> +#include <asm/mach/arch.h>
> +
> +#include "common.h"
> +
> +static const struct of_device_id of_ls1021a_match_table[] = {
> + {
> + .compatible = "simple-bus",
> + },
> + {
> + .compatible = "fsl,ifc",
> + },
> + {
> + .compatible = "fsl,fpga-qixis",
> + },
> + {
> + .compatible = "fsl,qe",
> + },
> + {}
> +};
Are any of thse not always-on (or default-on) MMIO busses?
Is there any reason for not giving them their own drivers?
> +
> +static void __init ls1021a_init_machine(void)
> +{
> + mxc_arch_reset_init_dt();
This looks to only be used to set up a watchdog timer. Is there any
reason this logic can't be moved to the watchdog timer driver?
> + of_platform_populate(NULL, of_ls1021a_match_table, NULL, NULL);
> +}
> +
> +static const char *ls1021a_dt_compat[] __initdata = {
> + "fsl,ls1021a",
> + NULL,
> +};
> +
> +DT_MACHINE_START(LS1021A, "Freescale LS1021A")
> +#ifdef CONFIG_ZONE_DMA
> + .dma_zone_size = SZ_128M,
> +#endif
> + .init_machine = ls1021a_init_machine,
> + .dt_compat = ls1021a_dt_compat,
> + .restart = mxc_restart,
AFAICT, that jsut uses the WDT for restart. Why can't the watchdog
driver register itself as a restart device?
That would bring us close to an empty machine descriptor, and enable
reuse of the WDT and those busses.
Thanks,
Mark.
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021A
@ 2014-07-02 11:21 ` Mark Rutland
0 siblings, 0 replies; 30+ messages in thread
From: Mark Rutland @ 2014-07-02 11:21 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 02, 2014 at 10:02:51AM +0100, Jingchang Lu wrote:
> From: Jingchang Lu <b35083@freescale.com>
>
> The LS1021A SoC is a dual-core Cortex-A7 based processor,
> this add the initial support for it.
>
> Signed-off-by: Jingchang Lu <b35083@freescale.com>
> ---
> arch/arm/mach-imx/Kconfig | 17 ++++++++++++++
> arch/arm/mach-imx/Makefile | 2 ++
> arch/arm/mach-imx/mach-ls1021a.c | 49 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 68 insertions(+)
> create mode 100644 arch/arm/mach-imx/mach-ls1021a.c
>
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index bdfe276..7f24892 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -762,6 +762,23 @@ config SOC_VF610
> help
> This enable support for Freescale Vybrid VF610 processor.
>
> +config FSL_SOC
> + bool
> +
> +config SOC_LS1021A
> + bool "Freescale LS1021A support"
> + select CPU_V7
> + select ARM_GIC
> + select CLKSRC_OF
> + select HAVE_ARM_ARCH_TIMER
> + select HAVE_SMP
> + select FSL_SOC
> + select MIGHT_HAVE_PCI
> + select PCI_DOMAINS if PCI
> +
> + help
> + This enable support for Freescale LS1021A processor.
> +
> endif
>
> source "arch/arm/mach-imx/devices/Kconfig"
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index a364e20..f49cbdb 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -114,4 +114,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
>
> obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
>
> +obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
> +
> obj-y += devices/
> diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
> new file mode 100644
> index 0000000..d1a9bb9
> --- /dev/null
> +++ b/arch/arm/mach-imx/mach-ls1021a.c
> @@ -0,0 +1,49 @@
> +/*
> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/of_platform.h>
> +#include <asm/mach/arch.h>
> +
> +#include "common.h"
> +
> +static const struct of_device_id of_ls1021a_match_table[] = {
> + {
> + .compatible = "simple-bus",
> + },
> + {
> + .compatible = "fsl,ifc",
> + },
> + {
> + .compatible = "fsl,fpga-qixis",
> + },
> + {
> + .compatible = "fsl,qe",
> + },
> + {}
> +};
Are any of thse not always-on (or default-on) MMIO busses?
Is there any reason for not giving them their own drivers?
> +
> +static void __init ls1021a_init_machine(void)
> +{
> + mxc_arch_reset_init_dt();
This looks to only be used to set up a watchdog timer. Is there any
reason this logic can't be moved to the watchdog timer driver?
> + of_platform_populate(NULL, of_ls1021a_match_table, NULL, NULL);
> +}
> +
> +static const char *ls1021a_dt_compat[] __initdata = {
> + "fsl,ls1021a",
> + NULL,
> +};
> +
> +DT_MACHINE_START(LS1021A, "Freescale LS1021A")
> +#ifdef CONFIG_ZONE_DMA
> + .dma_zone_size = SZ_128M,
> +#endif
> + .init_machine = ls1021a_init_machine,
> + .dt_compat = ls1021a_dt_compat,
> + .restart = mxc_restart,
AFAICT, that jsut uses the WDT for restart. Why can't the watchdog
driver register itself as a restart device?
That would bring us close to an empty machine descriptor, and enable
reuse of the WDT and those busses.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 5/5] ARM: imx: Add Freescale LS1021A SMP support
2014-07-02 9:02 ` Jingchang Lu
@ 2014-07-02 11:30 ` Mark Rutland
-1 siblings, 0 replies; 30+ messages in thread
From: Mark Rutland @ 2014-07-02 11:30 UTC (permalink / raw)
To: Jingchang Lu
Cc: shawn.guo-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Jingchang Lu
On Wed, Jul 02, 2014 at 10:02:52AM +0100, Jingchang Lu wrote:
> From: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
>
> Freescale LS1021A SoC deploys two cortex-A7 processors,
> this adds bring-up support for the secondary core.
>
> Signed-off-by: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> ---
> arch/arm/mach-imx/common.h | 2 ++
> arch/arm/mach-imx/headsmp.S | 11 ++++++++++
> arch/arm/mach-imx/mach-ls1021a.c | 1 +
> arch/arm/mach-imx/platsmp.c | 44 ++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 58 insertions(+)
[...]
> diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
> index de5047c..fdd93d9 100644
> --- a/arch/arm/mach-imx/headsmp.S
> +++ b/arch/arm/mach-imx/headsmp.S
> @@ -29,3 +29,14 @@ ENTRY(v7_secondary_startup)
> set_diag_reg
> b secondary_startup
> ENDPROC(v7_secondary_startup)
> +
> +ENTRY(ls1021a_secondary_startup)
> + /* set CNTFREQ of secondary core */
> + ldr r0, =12500000
> + mcr p15, 0, r0, c14, c0, 0
> + /* disable Physical and Virtural Timer */
> + mov r0, #0x0
> + mcr p15, 0, r0, c14, c2, 1
> + mcr p15, 0, r0, c14, c3, 1
> + b secondary_startup
Urrgh...
What about CNTVOFF? That's been a source of problems elsewhere.
Is the boot CPU set up correctly?
Is that frequency always going to be correct?
[...]
> +static void __init ls1021a_smp_init_cpus(void)
> +{
> + int i, ncores;
> + /* get number of cores from CP15 L2 controller register(L2CTLR)*/
> + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (ncores));
> +
> + ncores = ((ncores >> 24) & 0x3) + 1;
> + for (i = ncores; i < NR_CPUS; i++)
> + set_cpu_possible(i, false);
> +}
NAK.
This information is _already_ in the DT. This adds more code to do
redundant work, and it's broken.
The physical<->logical CPU ID mapping is arbitrary, so you set arbitrary
CPUs as being online despite this not necessarily being the case.
Get rid of this, and rely on the DT being correct. There;s no reason it
shouldn't be for a new platform.
Thanks,
Mark.
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 5/5] ARM: imx: Add Freescale LS1021A SMP support
@ 2014-07-02 11:30 ` Mark Rutland
0 siblings, 0 replies; 30+ messages in thread
From: Mark Rutland @ 2014-07-02 11:30 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 02, 2014 at 10:02:52AM +0100, Jingchang Lu wrote:
> From: Jingchang Lu <b35083@freescale.com>
>
> Freescale LS1021A SoC deploys two cortex-A7 processors,
> this adds bring-up support for the secondary core.
>
> Signed-off-by: Jingchang Lu <b35083@freescale.com>
> ---
> arch/arm/mach-imx/common.h | 2 ++
> arch/arm/mach-imx/headsmp.S | 11 ++++++++++
> arch/arm/mach-imx/mach-ls1021a.c | 1 +
> arch/arm/mach-imx/platsmp.c | 44 ++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 58 insertions(+)
[...]
> diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
> index de5047c..fdd93d9 100644
> --- a/arch/arm/mach-imx/headsmp.S
> +++ b/arch/arm/mach-imx/headsmp.S
> @@ -29,3 +29,14 @@ ENTRY(v7_secondary_startup)
> set_diag_reg
> b secondary_startup
> ENDPROC(v7_secondary_startup)
> +
> +ENTRY(ls1021a_secondary_startup)
> + /* set CNTFREQ of secondary core */
> + ldr r0, =12500000
> + mcr p15, 0, r0, c14, c0, 0
> + /* disable Physical and Virtural Timer */
> + mov r0, #0x0
> + mcr p15, 0, r0, c14, c2, 1
> + mcr p15, 0, r0, c14, c3, 1
> + b secondary_startup
Urrgh...
What about CNTVOFF? That's been a source of problems elsewhere.
Is the boot CPU set up correctly?
Is that frequency always going to be correct?
[...]
> +static void __init ls1021a_smp_init_cpus(void)
> +{
> + int i, ncores;
> + /* get number of cores from CP15 L2 controller register(L2CTLR)*/
> + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (ncores));
> +
> + ncores = ((ncores >> 24) & 0x3) + 1;
> + for (i = ncores; i < NR_CPUS; i++)
> + set_cpu_possible(i, false);
> +}
NAK.
This information is _already_ in the DT. This adds more code to do
redundant work, and it's broken.
The physical<->logical CPU ID mapping is arbitrary, so you set arbitrary
CPUs as being online despite this not necessarily being the case.
Get rid of this, and rely on the DT being correct. There;s no reason it
shouldn't be for a new platform.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH 1/5] ARM: dts: Add SoC level device tree support for LS1021A
2014-07-02 11:14 ` Mark Rutland
@ 2014-07-03 7:58 ` Jingchang Lu
-1 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-03 7:58 UTC (permalink / raw)
To: Mark Rutland
Cc: Shawn Guo, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
nikhil.badola-KZfg59tc24xl57MIdRCFDg,
chenhui.zhao-KZfg59tc24xl57MIdRCFDg,
suresh.gupta-KZfg59tc24xl57MIdRCFDg,
shaveta-KZfg59tc24xl57MIdRCFDg, Adrian Sendroiu, Ruchika Gupta,
bhupesh.sharma-KZfg59tc24xl57MIdRCFDg, Chao Fu,
Li.Xiubo-KZfg59tc24xl57MIdRCFDg
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 11906 bytes --]
>-----Original Message-----
>From: Mark Rutland [mailto:mark.rutland@arm.com]
>Sent: Wednesday, July 02, 2014 7:15 PM
>To: Lu Jingchang-B35083
>Cc: shawn.guo@linaro.org; linux-arm-kernel@lists.infradead.org;
>devicetree@vger.kernel.org; Lu Jingchang-B35083; Badola Nikhil-B46172;
>Zhao Chenhui-B35336; Gupta Suresh-B42813; Leekha Shaveta-B20052; Sendroiu
>Adrian-B46904; Gupta Ruchika-R66431; Sharma Bhupesh-B45370; Fu Chao-B44548;
>Xiubo Li-B47053
>Subject: Re: [PATCH 1/5] ARM: dts: Add SoC level device tree support for
>LS1021A
>
>Hi,
>
>As a general note, there seem to be many nodes for which bindings and
>drivers do not yet exist.
>
>For those nodes which are unusable for reasons other than their status
>being "disabled", I would prefer that they were removed. They're useless
>now, and might not match the bindings that are eventually decided upon,
>which will result in annoying churn and possible breakage.
>
Thanks for help review these patches, I will revise the node as your comment.
The LS1021A shares IP and driver with i.MX, Vybrid and PowerPC, some driver's
behavior minor different between them, so patches is needed to make them work
well between different platform and architecture. Thus some compatible include
undocumented string, could it be added along with the driver support after the
platform support is accepted? Thanks.
>On Wed, Jul 02, 2014 at 10:02:48AM +0100, Jingchang Lu wrote:
>> From: Jingchang Lu <b35083@freescale.com>
>>
>> Add Freescale LS1021A SoC device tree support
>>
>> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
>> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
>> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
>> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
>> Signed-off-by: Adrian Sendroiu <adrian.sendroiu@freescale.com>
>> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
>> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
>> Signed-off-by: Chao Fu <b44548@freescale.com>
>> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
>> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
>> ---
>> arch/arm/boot/dts/ls1021a.dtsi | 852
>> +++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 852 insertions(+)
>> create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
>>
>> diff --git a/arch/arm/boot/dts/ls1021a.dtsi
>> b/arch/arm/boot/dts/ls1021a.dtsi new file mode 100644 index
>> 0000000..b06b320
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/ls1021a.dtsi
>
>[...]
>
>> + memory {
>> + reg = <0x0 0x80000000 0x0 0x20000000>;
>> + };
>
>Missing device_type = "memory";
>
>For unit-address and reg consistency, this should be memory@0,80000000.
>
I will add this, thanks.
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0xf00>;
>> + };
>
>That reg doesn't match the unit-address, which should be cpu@f00.
>
>Why is MPIDR.Aff1 == 0xf?
The MPIDR value got from the SoC is 80000f00, so to match this the reg is set to x0f00.
Thanks.
>[...]
>> +
>> + tzasc: tzasc@1500000 {
>> + reg = <0x0 0x1500000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>
>There's no compatible string and "tzasc" doesn't appear to be handled
>magically anywhere, so this can't be probed even without the status
>property being "disabled".
I will remove this and all other unused node, it is not used currently. Thanks.
>
>
>> +
>> + ifc: ifc@1530000 {
>> + compatible = "fsl,ls1021a-ifc", "fsl,ifc",
>> + "simple-bus";
>
>This doesn't seem to have any children, ranges, #address-cells, or #size-
>cells. So why is "simple-bus" in the compatible list?
>
>As far as I can see this is a flash controller, so "simple-bus" doesn't
>make any sense whatsoever (and existing uses, including that in the
>binding are a bug).
Yes, it is a flash controller, the child nodes, ranges are in the <ls1021a-board>.dts.
Here only describe the SoC level device and resource.
I will remove the "simple-bus" string, Thanks.
>
>> + reg = <0x0 0x1530000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + dcfg: dcfg@1ee0000 {
>> + compatible = "fsl,ls1021a-dcfg";
>> + reg = <0x0 0x1ee0000 0x0 0x10000>;
>> + };
>
>Undocumented/unsupported binding.
>
>What is this?
It is the device configuration unit that provides general purpose configuration and status
for the device, there isn't a dedicate driver for it, device that has configuration and status
register located in this space could operate on it. Currently it is used to set the secondary
core start address and release the secondary core from holdoff and startup. Thanks.
>
>> + qspi: quadspi@1550000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "fsl,vf610-qspi";
>
>Please put the compatible string first. It makes it easier to find.
>
>> + reg = <0x0 0x1550000 0x0 0x10000>;
>
>Missing the second reg entry? The binding didn't state it was optional.
I will check this, thanks.
>
>> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-names = "qspi_en", "qspi";
>> + clocks = <&platform_clk 1>, <&platform_clk 1>;
>
>Normally we put $X before $X-names properties.
>
>I note that these clock-names are poorly documented. It would be nice to
>see that fixed up.
We will check this subsequently. Thanks.
>
>> + big-endian;
>
>The binding doesn't mention this. Does the driver support it?
>
>> + amba-base = <0x40000000>;
>
>The string "amba-base" shows up nowhere in mainline. What is this, and why
>is it here?
>
>[...]
>
>> + scfg: scfg@1570000 {
>> + compatible = "fsl,ls1021a-scfg";
>> + reg = <0x0 0x1570000 0x0 0x10000>;
>> + };
>
>Undocumented/unsupported binding.
>
>What is this?
It is the supplemental configuration unit, provides SoC specific configuration and status
registers for the device. Some device driver need this space to configure or get status.
If this is need document, which location is suitable for its document?
Thanks.
>
>[...]
>
>> + rcpm: rcpm@1ee2000 {
>> + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-
>rcpm-2.1";
>> + reg = <0x0 0x1ee2000 0x0 0x10000>;
>> + };
>
>Undocumented/unsupported binding (both compatible strings).
>
>What is this?
The Run Control and Power Management (RCPM) module performs all device-level tasks associated with
device run control and power management. It will be used by the PM driver currently. Thanks.
>
>[...]
>
>> + gpio1: gpio@2300000 {
>> + compatible = "fsl,ls1021a-gpio";
>> + reg = <0x0 0x2300000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>
>Undocumented/unsupported binding.
The bind document will be add along with the SoC platform support patch for it. Thanks.
>
>[...]
>
>> + lpuart1: serial@2960000 {
>> + compatible = "fsl,ls1021a-lpuart";
>> + reg = <0x0 0x2960000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&platform_clk 1>;
>> + clock-names = "ipg";
>> + status = "disabled";
>> + };
>
>Undocumented/unsupported binding.
I will add the bind document for this. Thanks.
>
>[...]
>
>[...]
>
>> + wdog0: wdog@2ad0000 {
>> + compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt";
>> + reg = <0x0 0x2ad0000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&platform_clk 1>;
>> + clock-names = "wdog";
>> + big-endian;
>> + };
>
>That clock name looks aribitrary, and "fsl,imx21-wdt" isn't documented as
>taking a clock.
>
>What is going on here?
The imx2_wdt driver need the clock, the clock name is not used, should it be removed?
and maybe the document is omitted, we'll check and add it subsequently. Thanks.
>
>[...]
>
>> + can0: can@2a70000 {
>> + compatible = "fsl,ls1021a-flexcan";
>> + reg = <0x0 0x2a70000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&platform_clk 1>;
>> + clock-names = "per";
>> + status = "disabled";
>> + };
>
>Undocumented/unsupported binding.
>
>Was this mean to have an existing compatible string in the list?
There will be fsl,ls1021a-flexcan support after the platform support is accepted,
It is list here just for the SoC level device resource.
>
>> +
>> + can1: can@2a80000 {
>> + compatible = "fsl,ls1021a-flexcan";
>> + reg = <0x0 0x2a80000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&platform_clk 1>;
>> + clock-names = "per";
>> + status = "disabled";
>> + };
>> +
>> + can2: can@2a90000 {
>> + compatible = "fsl,ls1021a-flexcan";
>> + reg = <0x0 0x2a90000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&platform_clk 1>;
>> + clock-names = "per";
>> + status = "disabled";
>> + };
>> +
>> + can3: can@2aa0000 {
>> + compatible = "fsl,ls1021a-flexcan";
>> + reg = <0x0 0x2aa0000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&platform_clk 1>;
>> + clock-names = "per";
>> + status = "disabled";
>> + };
>> + };
>> +
>> + dcsr@20000000 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "fsl,ls1021a-dcsr", "simple-bus";
>
>Missing a reg entry? Or is the unit-address arbitrary?
>
>The "fsl,ls1021a-dcsr" string is undocumented/unsupported, as with the
>compatible strings of all the child nodes below.
>
>Thanks,
>Mark.
It share the drive with PowerPC SoCs, the reg here is not used, only the child node's will
be used. Thanks.
Best Regards,
Jingchang
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 1/5] ARM: dts: Add SoC level device tree support for LS1021A
@ 2014-07-03 7:58 ` Jingchang Lu
0 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-03 7:58 UTC (permalink / raw)
To: linux-arm-kernel
>-----Original Message-----
>From: Mark Rutland [mailto:mark.rutland at arm.com]
>Sent: Wednesday, July 02, 2014 7:15 PM
>To: Lu Jingchang-B35083
>Cc: shawn.guo at linaro.org; linux-arm-kernel at lists.infradead.org;
>devicetree at vger.kernel.org; Lu Jingchang-B35083; Badola Nikhil-B46172;
>Zhao Chenhui-B35336; Gupta Suresh-B42813; Leekha Shaveta-B20052; Sendroiu
>Adrian-B46904; Gupta Ruchika-R66431; Sharma Bhupesh-B45370; Fu Chao-B44548;
>Xiubo Li-B47053
>Subject: Re: [PATCH 1/5] ARM: dts: Add SoC level device tree support for
>LS1021A
>
>Hi,
>
>As a general note, there seem to be many nodes for which bindings and
>drivers do not yet exist.
>
>For those nodes which are unusable for reasons other than their status
>being "disabled", I would prefer that they were removed. They're useless
>now, and might not match the bindings that are eventually decided upon,
>which will result in annoying churn and possible breakage.
>
Thanks for help review these patches, I will revise the node as your comment.
The LS1021A shares IP and driver with i.MX, Vybrid and PowerPC, some driver's
behavior minor different between them, so patches is needed to make them work
well between different platform and architecture. Thus some compatible include
undocumented string, could it be added along with the driver support after the
platform support is accepted? Thanks.
>On Wed, Jul 02, 2014 at 10:02:48AM +0100, Jingchang Lu wrote:
>> From: Jingchang Lu <b35083@freescale.com>
>>
>> Add Freescale LS1021A SoC device tree support
>>
>> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
>> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
>> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
>> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
>> Signed-off-by: Adrian Sendroiu <adrian.sendroiu@freescale.com>
>> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
>> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
>> Signed-off-by: Chao Fu <b44548@freescale.com>
>> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
>> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
>> ---
>> arch/arm/boot/dts/ls1021a.dtsi | 852
>> +++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 852 insertions(+)
>> create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
>>
>> diff --git a/arch/arm/boot/dts/ls1021a.dtsi
>> b/arch/arm/boot/dts/ls1021a.dtsi new file mode 100644 index
>> 0000000..b06b320
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/ls1021a.dtsi
>
>[...]
>
>> + memory {
>> + reg = <0x0 0x80000000 0x0 0x20000000>;
>> + };
>
>Missing device_type = "memory";
>
>For unit-address and reg consistency, this should be memory at 0,80000000.
>
I will add this, thanks.
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu at 0 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0xf00>;
>> + };
>
>That reg doesn't match the unit-address, which should be cpu at f00.
>
>Why is MPIDR.Aff1 == 0xf?
The MPIDR value got from the SoC is 80000f00, so to match this the reg is set to x0f00.
Thanks.
>[...]
>> +
>> + tzasc: tzasc at 1500000 {
>> + reg = <0x0 0x1500000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>
>There's no compatible string and "tzasc" doesn't appear to be handled
>magically anywhere, so this can't be probed even without the status
>property being "disabled".
I will remove this and all other unused node, it is not used currently. Thanks.
>
>
>> +
>> + ifc: ifc at 1530000 {
>> + compatible = "fsl,ls1021a-ifc", "fsl,ifc",
>> + "simple-bus";
>
>This doesn't seem to have any children, ranges, #address-cells, or #size-
>cells. So why is "simple-bus" in the compatible list?
>
>As far as I can see this is a flash controller, so "simple-bus" doesn't
>make any sense whatsoever (and existing uses, including that in the
>binding are a bug).
Yes, it is a flash controller, the child nodes, ranges are in the <ls1021a-board>.dts.
Here only describe the SoC level device and resource.
I will remove the "simple-bus" string, Thanks.
>
>> + reg = <0x0 0x1530000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + dcfg: dcfg at 1ee0000 {
>> + compatible = "fsl,ls1021a-dcfg";
>> + reg = <0x0 0x1ee0000 0x0 0x10000>;
>> + };
>
>Undocumented/unsupported binding.
>
>What is this?
It is the device configuration unit that provides general purpose configuration and status
for the device, there isn't a dedicate driver for it, device that has configuration and status
register located in this space could operate on it. Currently it is used to set the secondary
core start address and release the secondary core from holdoff and startup. Thanks.
>
>> + qspi: quadspi at 1550000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "fsl,vf610-qspi";
>
>Please put the compatible string first. It makes it easier to find.
>
>> + reg = <0x0 0x1550000 0x0 0x10000>;
>
>Missing the second reg entry? The binding didn't state it was optional.
I will check this, thanks.
>
>> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-names = "qspi_en", "qspi";
>> + clocks = <&platform_clk 1>, <&platform_clk 1>;
>
>Normally we put $X before $X-names properties.
>
>I note that these clock-names are poorly documented. It would be nice to
>see that fixed up.
We will check this subsequently. Thanks.
>
>> + big-endian;
>
>The binding doesn't mention this. Does the driver support it?
>
>> + amba-base = <0x40000000>;
>
>The string "amba-base" shows up nowhere in mainline. What is this, and why
>is it here?
>
>[...]
>
>> + scfg: scfg at 1570000 {
>> + compatible = "fsl,ls1021a-scfg";
>> + reg = <0x0 0x1570000 0x0 0x10000>;
>> + };
>
>Undocumented/unsupported binding.
>
>What is this?
It is the supplemental configuration unit, provides SoC specific configuration and status
registers for the device. Some device driver need this space to configure or get status.
If this is need document, which location is suitable for its document?
Thanks.
>
>[...]
>
>> + rcpm: rcpm at 1ee2000 {
>> + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-
>rcpm-2.1";
>> + reg = <0x0 0x1ee2000 0x0 0x10000>;
>> + };
>
>Undocumented/unsupported binding (both compatible strings).
>
>What is this?
The Run Control and Power Management (RCPM) module performs all device-level tasks associated with
device run control and power management. It will be used by the PM driver currently. Thanks.
>
>[...]
>
>> + gpio1: gpio at 2300000 {
>> + compatible = "fsl,ls1021a-gpio";
>> + reg = <0x0 0x2300000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>
>Undocumented/unsupported binding.
The bind document will be add along with the SoC platform support patch for it. Thanks.
>
>[...]
>
>> + lpuart1: serial at 2960000 {
>> + compatible = "fsl,ls1021a-lpuart";
>> + reg = <0x0 0x2960000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&platform_clk 1>;
>> + clock-names = "ipg";
>> + status = "disabled";
>> + };
>
>Undocumented/unsupported binding.
I will add the bind document for this. Thanks.
>
>[...]
>
>[...]
>
>> + wdog0: wdog at 2ad0000 {
>> + compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt";
>> + reg = <0x0 0x2ad0000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&platform_clk 1>;
>> + clock-names = "wdog";
>> + big-endian;
>> + };
>
>That clock name looks aribitrary, and "fsl,imx21-wdt" isn't documented as
>taking a clock.
>
>What is going on here?
The imx2_wdt driver need the clock, the clock name is not used, should it be removed?
and maybe the document is omitted, we'll check and add it subsequently. Thanks.
>
>[...]
>
>> + can0: can at 2a70000 {
>> + compatible = "fsl,ls1021a-flexcan";
>> + reg = <0x0 0x2a70000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&platform_clk 1>;
>> + clock-names = "per";
>> + status = "disabled";
>> + };
>
>Undocumented/unsupported binding.
>
>Was this mean to have an existing compatible string in the list?
There will be fsl,ls1021a-flexcan support after the platform support is accepted,
It is list here just for the SoC level device resource.
>
>> +
>> + can1: can at 2a80000 {
>> + compatible = "fsl,ls1021a-flexcan";
>> + reg = <0x0 0x2a80000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&platform_clk 1>;
>> + clock-names = "per";
>> + status = "disabled";
>> + };
>> +
>> + can2: can at 2a90000 {
>> + compatible = "fsl,ls1021a-flexcan";
>> + reg = <0x0 0x2a90000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&platform_clk 1>;
>> + clock-names = "per";
>> + status = "disabled";
>> + };
>> +
>> + can3: can at 2aa0000 {
>> + compatible = "fsl,ls1021a-flexcan";
>> + reg = <0x0 0x2aa0000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&platform_clk 1>;
>> + clock-names = "per";
>> + status = "disabled";
>> + };
>> + };
>> +
>> + dcsr at 20000000 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "fsl,ls1021a-dcsr", "simple-bus";
>
>Missing a reg entry? Or is the unit-address arbitrary?
>
>The "fsl,ls1021a-dcsr" string is undocumented/unsupported, as with the
>compatible strings of all the child nodes below.
>
>Thanks,
>Mark.
It share the drive with PowerPC SoCs, the reg here is not used, only the child node's will
be used. Thanks.
Best Regards,
Jingchang
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] ARM: dts: Add SoC level device tree support for LS1021A
2014-07-03 7:58 ` Jingchang Lu
@ 2014-07-03 10:10 ` Mark Rutland
-1 siblings, 0 replies; 30+ messages in thread
From: Mark Rutland @ 2014-07-03 10:10 UTC (permalink / raw)
To: Jingchang Lu
Cc: Shawn Guo, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
nikhil.badola-KZfg59tc24xl57MIdRCFDg,
chenhui.zhao-KZfg59tc24xl57MIdRCFDg,
suresh.gupta-KZfg59tc24xl57MIdRCFDg,
shaveta-KZfg59tc24xl57MIdRCFDg, Adrian Sendroiu, Ruchika Gupta,
bhupesh.sharma-KZfg59tc24xl57MIdRCFDg, Chao Fu,
Li.Xiubo-KZfg59tc24xl57MIdRCFDg
On Thu, Jul 03, 2014 at 08:58:04AM +0100, Jingchang Lu wrote:
> >-----Original Message-----
> >From: Mark Rutland [mailto:mark.rutland-5wv7dgnIgG8@public.gmane.org]
> >Sent: Wednesday, July 02, 2014 7:15 PM
> >To: Lu Jingchang-B35083
> >Cc: shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org;
> >devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Lu Jingchang-B35083; Badola Nikhil-B46172;
> >Zhao Chenhui-B35336; Gupta Suresh-B42813; Leekha Shaveta-B20052; Sendroiu
> >Adrian-B46904; Gupta Ruchika-R66431; Sharma Bhupesh-B45370; Fu Chao-B44548;
> >Xiubo Li-B47053
> >Subject: Re: [PATCH 1/5] ARM: dts: Add SoC level device tree support for
> >LS1021A
> >
> >Hi,
> >
> >As a general note, there seem to be many nodes for which bindings and
> >drivers do not yet exist.
> >
> >For those nodes which are unusable for reasons other than their status
> >being "disabled", I would prefer that they were removed. They're useless
> >now, and might not match the bindings that are eventually decided upon,
> >which will result in annoying churn and possible breakage.
> >
> Thanks for help review these patches, I will revise the node as your comment.
> The LS1021A shares IP and driver with i.MX, Vybrid and PowerPC, some driver's
> behavior minor different between them, so patches is needed to make them work
> well between different platform and architecture. Thus some compatible include
> undocumented string, could it be added along with the driver support after the
> platform support is accepted? Thanks.
Those nodes in the DT which are useless at the moment should be dropped.
There's no point having them there.
We can add them when driver support is added, along with documentation.
[...]
> >> +
> >> + cpus {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + cpu@0 {
> >> + compatible = "arm,cortex-a7";
> >> + device_type = "cpu";
> >> + reg = <0xf00>;
> >> + };
> >
> >That reg doesn't match the unit-address, which should be cpu@f00.
> >
> >Why is MPIDR.Aff1 == 0xf?
> The MPIDR value got from the SoC is 80000f00, so to match this the reg is set to x0f00.
> Thanks.
Ok. Please update the unit-address on the nodes to match.
> >[...]
> >> +
> >> + tzasc: tzasc@1500000 {
> >> + reg = <0x0 0x1500000 0x0 0x10000>;
> >> + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
> >> + status = "disabled";
> >> + };
> >
> >There's no compatible string and "tzasc" doesn't appear to be handled
> >magically anywhere, so this can't be probed even without the status
> >property being "disabled".
> I will remove this and all other unused node, it is not used currently. Thanks.
Thanks.
> >
> >
> >> +
> >> + ifc: ifc@1530000 {
> >> + compatible = "fsl,ls1021a-ifc", "fsl,ifc",
> >> + "simple-bus";
> >
> >This doesn't seem to have any children, ranges, #address-cells, or #size-
> >cells. So why is "simple-bus" in the compatible list?
> >
> >As far as I can see this is a flash controller, so "simple-bus" doesn't
> >make any sense whatsoever (and existing uses, including that in the
> >binding are a bug).
> Yes, it is a flash controller, the child nodes, ranges are in the <ls1021a-board>.dts.
> Here only describe the SoC level device and resource.
> I will remove the "simple-bus" string, Thanks.
Ok.
> >
> >> + reg = <0x0 0x1530000 0x0 0x10000>;
> >> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> >> + };
> >> +
> >> + dcfg: dcfg@1ee0000 {
> >> + compatible = "fsl,ls1021a-dcfg";
> >> + reg = <0x0 0x1ee0000 0x0 0x10000>;
> >> + };
> >
> >Undocumented/unsupported binding.
> >
> >What is this?
> It is the device configuration unit that provides general purpose configuration and status
> for the device, there isn't a dedicate driver for it, device that has configuration and status
> register located in this space could operate on it. Currently it is used to set the secondary
> core start address and release the secondary core from holdoff and startup. Thanks.
Then we should document it.
[...]
> >
> >> + big-endian;
> >
> >The binding doesn't mention this. Does the driver support it?
> >
> >> + amba-base = <0x40000000>;
> >
> >The string "amba-base" shows up nowhere in mainline. What is this, and why
> >is it here?
> >
> >[...]
> >
> >> + scfg: scfg@1570000 {
> >> + compatible = "fsl,ls1021a-scfg";
> >> + reg = <0x0 0x1570000 0x0 0x10000>;
> >> + };
> >
> >Undocumented/unsupported binding.
> >
> >What is this?
> It is the supplemental configuration unit, provides SoC specific configuration and status
> registers for the device. Some device driver need this space to configure or get status.
> If this is need document, which location is suitable for its document?
> Thanks.
Documentation/devicetree/bindings/soc/ ?
> >
> >[...]
> >
> >> + rcpm: rcpm@1ee2000 {
> >> + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-
> >rcpm-2.1";
> >> + reg = <0x0 0x1ee2000 0x0 0x10000>;
> >> + };
> >
> >Undocumented/unsupported binding (both compatible strings).
> >
> >What is this?
> The Run Control and Power Management (RCPM) module performs all device-level tasks associated with
> device run control and power management. It will be used by the PM driver currently. Thanks.
As far as I can see this is _not_ used currently; both strings appear
nowhere in mainline.
Drop the node for now. It can be added alongside the driver and binding.
> >
> >[...]
> >
> >> + gpio1: gpio@2300000 {
> >> + compatible = "fsl,ls1021a-gpio";
> >> + reg = <0x0 0x2300000 0x0 0x10000>;
> >> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >
> >Undocumented/unsupported binding.
> The bind document will be add along with the SoC platform support patch for it. Thanks.
Drop the node for now.
> >
> >[...]
> >
> >> + lpuart1: serial@2960000 {
> >> + compatible = "fsl,ls1021a-lpuart";
> >> + reg = <0x0 0x2960000 0x0 0x1000>;
> >> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&platform_clk 1>;
> >> + clock-names = "ipg";
> >> + status = "disabled";
> >> + };
> >
> >Undocumented/unsupported binding.
> I will add the bind document for this. Thanks.
Ok.
> >
> >[...]
> >
> >[...]
> >
> >> + wdog0: wdog@2ad0000 {
> >> + compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt";
> >> + reg = <0x0 0x2ad0000 0x0 0x10000>;
> >> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&platform_clk 1>;
> >> + clock-names = "wdog";
> >> + big-endian;
> >> + };
> >
> >That clock name looks aribitrary, and "fsl,imx21-wdt" isn't documented as
> >taking a clock.
> >
> >What is going on here?
> The imx2_wdt driver need the clock, the clock name is not used, should it be removed?
> and maybe the document is omitted, we'll check and add it subsequently. Thanks.
Either document the clock name and make sure it's used consistently, or
drop it. The latter seems like the easiest approach.
> >
> >[...]
> >
> >> + can0: can@2a70000 {
> >> + compatible = "fsl,ls1021a-flexcan";
> >> + reg = <0x0 0x2a70000 0x0 0x1000>;
> >> + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&platform_clk 1>;
> >> + clock-names = "per";
> >> + status = "disabled";
> >> + };
> >
> >Undocumented/unsupported binding.
> >
> >Was this mean to have an existing compatible string in the list?
> There will be fsl,ls1021a-flexcan support after the platform support is accepted,
> It is list here just for the SoC level device resource.
Add the node when you add support. Drop it for now.
> >
> >> +
> >> + can1: can@2a80000 {
> >> + compatible = "fsl,ls1021a-flexcan";
> >> + reg = <0x0 0x2a80000 0x0 0x1000>;
> >> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&platform_clk 1>;
> >> + clock-names = "per";
> >> + status = "disabled";
> >> + };
> >> +
> >> + can2: can@2a90000 {
> >> + compatible = "fsl,ls1021a-flexcan";
> >> + reg = <0x0 0x2a90000 0x0 0x1000>;
> >> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&platform_clk 1>;
> >> + clock-names = "per";
> >> + status = "disabled";
> >> + };
> >> +
> >> + can3: can@2aa0000 {
> >> + compatible = "fsl,ls1021a-flexcan";
> >> + reg = <0x0 0x2aa0000 0x0 0x1000>;
> >> + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&platform_clk 1>;
> >> + clock-names = "per";
> >> + status = "disabled";
> >> + };
> >> + };
> >> +
> >> + dcsr@20000000 {
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + compatible = "fsl,ls1021a-dcsr", "simple-bus";
> >
> >Missing a reg entry? Or is the unit-address arbitrary?
> >
> >The "fsl,ls1021a-dcsr" string is undocumented/unsupported, as with the
> >compatible strings of all the child nodes below.
> >
> >Thanks,
> >Mark.
> It share the drive with PowerPC SoCs, the reg here is not used, only the child node's will
> be used. Thanks.
Ok. So drop the unit-address.
Thanks,
Mark.
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 1/5] ARM: dts: Add SoC level device tree support for LS1021A
@ 2014-07-03 10:10 ` Mark Rutland
0 siblings, 0 replies; 30+ messages in thread
From: Mark Rutland @ 2014-07-03 10:10 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 03, 2014 at 08:58:04AM +0100, Jingchang Lu wrote:
> >-----Original Message-----
> >From: Mark Rutland [mailto:mark.rutland at arm.com]
> >Sent: Wednesday, July 02, 2014 7:15 PM
> >To: Lu Jingchang-B35083
> >Cc: shawn.guo at linaro.org; linux-arm-kernel at lists.infradead.org;
> >devicetree at vger.kernel.org; Lu Jingchang-B35083; Badola Nikhil-B46172;
> >Zhao Chenhui-B35336; Gupta Suresh-B42813; Leekha Shaveta-B20052; Sendroiu
> >Adrian-B46904; Gupta Ruchika-R66431; Sharma Bhupesh-B45370; Fu Chao-B44548;
> >Xiubo Li-B47053
> >Subject: Re: [PATCH 1/5] ARM: dts: Add SoC level device tree support for
> >LS1021A
> >
> >Hi,
> >
> >As a general note, there seem to be many nodes for which bindings and
> >drivers do not yet exist.
> >
> >For those nodes which are unusable for reasons other than their status
> >being "disabled", I would prefer that they were removed. They're useless
> >now, and might not match the bindings that are eventually decided upon,
> >which will result in annoying churn and possible breakage.
> >
> Thanks for help review these patches, I will revise the node as your comment.
> The LS1021A shares IP and driver with i.MX, Vybrid and PowerPC, some driver's
> behavior minor different between them, so patches is needed to make them work
> well between different platform and architecture. Thus some compatible include
> undocumented string, could it be added along with the driver support after the
> platform support is accepted? Thanks.
Those nodes in the DT which are useless at the moment should be dropped.
There's no point having them there.
We can add them when driver support is added, along with documentation.
[...]
> >> +
> >> + cpus {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + cpu at 0 {
> >> + compatible = "arm,cortex-a7";
> >> + device_type = "cpu";
> >> + reg = <0xf00>;
> >> + };
> >
> >That reg doesn't match the unit-address, which should be cpu at f00.
> >
> >Why is MPIDR.Aff1 == 0xf?
> The MPIDR value got from the SoC is 80000f00, so to match this the reg is set to x0f00.
> Thanks.
Ok. Please update the unit-address on the nodes to match.
> >[...]
> >> +
> >> + tzasc: tzasc at 1500000 {
> >> + reg = <0x0 0x1500000 0x0 0x10000>;
> >> + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
> >> + status = "disabled";
> >> + };
> >
> >There's no compatible string and "tzasc" doesn't appear to be handled
> >magically anywhere, so this can't be probed even without the status
> >property being "disabled".
> I will remove this and all other unused node, it is not used currently. Thanks.
Thanks.
> >
> >
> >> +
> >> + ifc: ifc at 1530000 {
> >> + compatible = "fsl,ls1021a-ifc", "fsl,ifc",
> >> + "simple-bus";
> >
> >This doesn't seem to have any children, ranges, #address-cells, or #size-
> >cells. So why is "simple-bus" in the compatible list?
> >
> >As far as I can see this is a flash controller, so "simple-bus" doesn't
> >make any sense whatsoever (and existing uses, including that in the
> >binding are a bug).
> Yes, it is a flash controller, the child nodes, ranges are in the <ls1021a-board>.dts.
> Here only describe the SoC level device and resource.
> I will remove the "simple-bus" string, Thanks.
Ok.
> >
> >> + reg = <0x0 0x1530000 0x0 0x10000>;
> >> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> >> + };
> >> +
> >> + dcfg: dcfg at 1ee0000 {
> >> + compatible = "fsl,ls1021a-dcfg";
> >> + reg = <0x0 0x1ee0000 0x0 0x10000>;
> >> + };
> >
> >Undocumented/unsupported binding.
> >
> >What is this?
> It is the device configuration unit that provides general purpose configuration and status
> for the device, there isn't a dedicate driver for it, device that has configuration and status
> register located in this space could operate on it. Currently it is used to set the secondary
> core start address and release the secondary core from holdoff and startup. Thanks.
Then we should document it.
[...]
> >
> >> + big-endian;
> >
> >The binding doesn't mention this. Does the driver support it?
> >
> >> + amba-base = <0x40000000>;
> >
> >The string "amba-base" shows up nowhere in mainline. What is this, and why
> >is it here?
> >
> >[...]
> >
> >> + scfg: scfg at 1570000 {
> >> + compatible = "fsl,ls1021a-scfg";
> >> + reg = <0x0 0x1570000 0x0 0x10000>;
> >> + };
> >
> >Undocumented/unsupported binding.
> >
> >What is this?
> It is the supplemental configuration unit, provides SoC specific configuration and status
> registers for the device. Some device driver need this space to configure or get status.
> If this is need document, which location is suitable for its document?
> Thanks.
Documentation/devicetree/bindings/soc/ ?
> >
> >[...]
> >
> >> + rcpm: rcpm at 1ee2000 {
> >> + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-
> >rcpm-2.1";
> >> + reg = <0x0 0x1ee2000 0x0 0x10000>;
> >> + };
> >
> >Undocumented/unsupported binding (both compatible strings).
> >
> >What is this?
> The Run Control and Power Management (RCPM) module performs all device-level tasks associated with
> device run control and power management. It will be used by the PM driver currently. Thanks.
As far as I can see this is _not_ used currently; both strings appear
nowhere in mainline.
Drop the node for now. It can be added alongside the driver and binding.
> >
> >[...]
> >
> >> + gpio1: gpio at 2300000 {
> >> + compatible = "fsl,ls1021a-gpio";
> >> + reg = <0x0 0x2300000 0x0 0x10000>;
> >> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >
> >Undocumented/unsupported binding.
> The bind document will be add along with the SoC platform support patch for it. Thanks.
Drop the node for now.
> >
> >[...]
> >
> >> + lpuart1: serial at 2960000 {
> >> + compatible = "fsl,ls1021a-lpuart";
> >> + reg = <0x0 0x2960000 0x0 0x1000>;
> >> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&platform_clk 1>;
> >> + clock-names = "ipg";
> >> + status = "disabled";
> >> + };
> >
> >Undocumented/unsupported binding.
> I will add the bind document for this. Thanks.
Ok.
> >
> >[...]
> >
> >[...]
> >
> >> + wdog0: wdog at 2ad0000 {
> >> + compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt";
> >> + reg = <0x0 0x2ad0000 0x0 0x10000>;
> >> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&platform_clk 1>;
> >> + clock-names = "wdog";
> >> + big-endian;
> >> + };
> >
> >That clock name looks aribitrary, and "fsl,imx21-wdt" isn't documented as
> >taking a clock.
> >
> >What is going on here?
> The imx2_wdt driver need the clock, the clock name is not used, should it be removed?
> and maybe the document is omitted, we'll check and add it subsequently. Thanks.
Either document the clock name and make sure it's used consistently, or
drop it. The latter seems like the easiest approach.
> >
> >[...]
> >
> >> + can0: can at 2a70000 {
> >> + compatible = "fsl,ls1021a-flexcan";
> >> + reg = <0x0 0x2a70000 0x0 0x1000>;
> >> + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&platform_clk 1>;
> >> + clock-names = "per";
> >> + status = "disabled";
> >> + };
> >
> >Undocumented/unsupported binding.
> >
> >Was this mean to have an existing compatible string in the list?
> There will be fsl,ls1021a-flexcan support after the platform support is accepted,
> It is list here just for the SoC level device resource.
Add the node when you add support. Drop it for now.
> >
> >> +
> >> + can1: can at 2a80000 {
> >> + compatible = "fsl,ls1021a-flexcan";
> >> + reg = <0x0 0x2a80000 0x0 0x1000>;
> >> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&platform_clk 1>;
> >> + clock-names = "per";
> >> + status = "disabled";
> >> + };
> >> +
> >> + can2: can at 2a90000 {
> >> + compatible = "fsl,ls1021a-flexcan";
> >> + reg = <0x0 0x2a90000 0x0 0x1000>;
> >> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&platform_clk 1>;
> >> + clock-names = "per";
> >> + status = "disabled";
> >> + };
> >> +
> >> + can3: can at 2aa0000 {
> >> + compatible = "fsl,ls1021a-flexcan";
> >> + reg = <0x0 0x2aa0000 0x0 0x1000>;
> >> + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&platform_clk 1>;
> >> + clock-names = "per";
> >> + status = "disabled";
> >> + };
> >> + };
> >> +
> >> + dcsr at 20000000 {
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + compatible = "fsl,ls1021a-dcsr", "simple-bus";
> >
> >Missing a reg entry? Or is the unit-address arbitrary?
> >
> >The "fsl,ls1021a-dcsr" string is undocumented/unsupported, as with the
> >compatible strings of all the child nodes below.
> >
> >Thanks,
> >Mark.
> It share the drive with PowerPC SoCs, the reg here is not used, only the child node's will
> be used. Thanks.
Ok. So drop the unit-address.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021A
2014-07-02 11:21 ` Mark Rutland
@ 2014-07-03 10:17 ` Jingchang Lu
-1 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-03 10:17 UTC (permalink / raw)
To: Mark Rutland
Cc: Shawn Guo, shawn.guo-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
>-----Original Message-----
>From: Mark Rutland [mailto:mark.rutland@arm.com]
>Sent: Wednesday, July 02, 2014 7:21 PM
>To: Lu Jingchang-B35083
>Cc: shawn.guo@linaro.org; linux-arm-kernel@lists.infradead.org;
>devicetree@vger.kernel.org; Lu Jingchang-B35083
>Subject: Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale
>LS1021A
>
>On Wed, Jul 02, 2014 at 10:02:51AM +0100, Jingchang Lu wrote:
>> From: Jingchang Lu <b35083@freescale.com>
>>
>> diff --git a/arch/arm/mach-imx/mach-ls1021a.c
>> b/arch/arm/mach-imx/mach-ls1021a.c
>> new file mode 100644
>> index 0000000..d1a9bb9
>> --- /dev/null
>> +++ b/arch/arm/mach-imx/mach-ls1021a.c
>> @@ -0,0 +1,49 @@
>> +/*
>> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> +modify
>> + * it under the terms of the GNU General Public License as published
>> +by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + */
>> +
>> +#include <linux/of_platform.h>
>> +#include <asm/mach/arch.h>
>> +
>> +#include "common.h"
>> +
>> +static const struct of_device_id of_ls1021a_match_table[] = {
>> + {
>> + .compatible = "simple-bus",
>> + },
>> + {
>> + .compatible = "fsl,ifc",
>> + },
>> + {
>> + .compatible = "fsl,fpga-qixis",
>> + },
>> + {
>> + .compatible = "fsl,qe",
>> + },
>> + {}
>> +};
>
>Are any of thse not always-on (or default-on) MMIO busses?
>
>Is there any reason for not giving them their own drivers?
>
Normally these are always-on. The child nodes are handled by different drivers,
so to make the devices being added by the of system, they are claimed here.
Thanks.
>> +
>> +static void __init ls1021a_init_machine(void) {
>> + mxc_arch_reset_init_dt();
>
>This looks to only be used to set up a watchdog timer. Is there any reason
>this logic can't be moved to the watchdog timer driver?
>
>> +
>> +DT_MACHINE_START(LS1021A, "Freescale LS1021A") #ifdef CONFIG_ZONE_DMA
>> + .dma_zone_size = SZ_128M,
>> +#endif
>> + .init_machine = ls1021a_init_machine,
>> + .dt_compat = ls1021a_dt_compat,
>> + .restart = mxc_restart,
>
>AFAICT, that jsut uses the WDT for restart. Why can't the watchdog driver
>register itself as a restart device?
>
>That would bring us close to an empty machine descriptor, and enable reuse
>of the WDT and those busses.
>
>Thanks,
>Mark.
Yes, we use the watchdog timer for restart, just as i.MX and Vybrid, the WDT as a
common driver it is still work for watchdog. Thanks.
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021A
@ 2014-07-03 10:17 ` Jingchang Lu
0 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-03 10:17 UTC (permalink / raw)
To: linux-arm-kernel
>-----Original Message-----
>From: Mark Rutland [mailto:mark.rutland at arm.com]
>Sent: Wednesday, July 02, 2014 7:21 PM
>To: Lu Jingchang-B35083
>Cc: shawn.guo at linaro.org; linux-arm-kernel at lists.infradead.org;
>devicetree at vger.kernel.org; Lu Jingchang-B35083
>Subject: Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale
>LS1021A
>
>On Wed, Jul 02, 2014 at 10:02:51AM +0100, Jingchang Lu wrote:
>> From: Jingchang Lu <b35083@freescale.com>
>>
>> diff --git a/arch/arm/mach-imx/mach-ls1021a.c
>> b/arch/arm/mach-imx/mach-ls1021a.c
>> new file mode 100644
>> index 0000000..d1a9bb9
>> --- /dev/null
>> +++ b/arch/arm/mach-imx/mach-ls1021a.c
>> @@ -0,0 +1,49 @@
>> +/*
>> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> +modify
>> + * it under the terms of the GNU General Public License as published
>> +by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + */
>> +
>> +#include <linux/of_platform.h>
>> +#include <asm/mach/arch.h>
>> +
>> +#include "common.h"
>> +
>> +static const struct of_device_id of_ls1021a_match_table[] = {
>> + {
>> + .compatible = "simple-bus",
>> + },
>> + {
>> + .compatible = "fsl,ifc",
>> + },
>> + {
>> + .compatible = "fsl,fpga-qixis",
>> + },
>> + {
>> + .compatible = "fsl,qe",
>> + },
>> + {}
>> +};
>
>Are any of thse not always-on (or default-on) MMIO busses?
>
>Is there any reason for not giving them their own drivers?
>
Normally these are always-on. The child nodes are handled by different drivers,
so to make the devices being added by the of system, they are claimed here.
Thanks.
>> +
>> +static void __init ls1021a_init_machine(void) {
>> + mxc_arch_reset_init_dt();
>
>This looks to only be used to set up a watchdog timer. Is there any reason
>this logic can't be moved to the watchdog timer driver?
>
>> +
>> +DT_MACHINE_START(LS1021A, "Freescale LS1021A") #ifdef CONFIG_ZONE_DMA
>> + .dma_zone_size = SZ_128M,
>> +#endif
>> + .init_machine = ls1021a_init_machine,
>> + .dt_compat = ls1021a_dt_compat,
>> + .restart = mxc_restart,
>
>AFAICT, that jsut uses the WDT for restart. Why can't the watchdog driver
>register itself as a restart device?
>
>That would bring us close to an empty machine descriptor, and enable reuse
>of the WDT and those busses.
>
>Thanks,
>Mark.
Yes, we use the watchdog timer for restart, just as i.MX and Vybrid, the WDT as a
common driver it is still work for watchdog. Thanks.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021A
2014-07-03 10:17 ` Jingchang Lu
@ 2014-07-03 15:12 ` Mark Rutland
-1 siblings, 0 replies; 30+ messages in thread
From: Mark Rutland @ 2014-07-03 15:12 UTC (permalink / raw)
To: Jingchang Lu
Cc: Shawn Guo, shawn.guo-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
On Thu, Jul 03, 2014 at 11:17:12AM +0100, Jingchang Lu wrote:
> >-----Original Message-----
> >From: Mark Rutland [mailto:mark.rutland-5wv7dgnIgG8@public.gmane.org]
> >Sent: Wednesday, July 02, 2014 7:21 PM
> >To: Lu Jingchang-B35083
> >Cc: shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org;
> >devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Lu Jingchang-B35083
> >Subject: Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale
> >LS1021A
> >
> >On Wed, Jul 02, 2014 at 10:02:51AM +0100, Jingchang Lu wrote:
> >> From: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> >>
> >> diff --git a/arch/arm/mach-imx/mach-ls1021a.c
> >> b/arch/arm/mach-imx/mach-ls1021a.c
> >> new file mode 100644
> >> index 0000000..d1a9bb9
> >> --- /dev/null
> >> +++ b/arch/arm/mach-imx/mach-ls1021a.c
> >> @@ -0,0 +1,49 @@
> >> +/*
> >> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
> >> + *
> >> + * This program is free software; you can redistribute it and/or
> >> +modify
> >> + * it under the terms of the GNU General Public License as published
> >> +by
> >> + * the Free Software Foundation; either version 2 of the License, or
> >> + * (at your option) any later version.
> >> + */
> >> +
> >> +#include <linux/of_platform.h>
> >> +#include <asm/mach/arch.h>
> >> +
> >> +#include "common.h"
> >> +
> >> +static const struct of_device_id of_ls1021a_match_table[] = {
> >> + {
> >> + .compatible = "simple-bus",
> >> + },
> >> + {
> >> + .compatible = "fsl,ifc",
> >> + },
> >> + {
> >> + .compatible = "fsl,fpga-qixis",
> >> + },
> >> + {
> >> + .compatible = "fsl,qe",
> >> + },
> >> + {}
> >> +};
> >
> >Are any of thse not always-on (or default-on) MMIO busses?
> >
> >Is there any reason for not giving them their own drivers?
> >
> Normally these are always-on. The child nodes are handled by different drivers,
> so to make the devices being added by the of system, they are claimed here.
> Thanks.
If these are always-on MMIO busses, is there any reason these can't have
"simple-bus" as a fallback in their compatible lists in the DT? They
would seemd to be compatible with it given they are in the table
above...
That way we don't need the table at all, and we can always add drivers
for them later if we need them...
> >> +
> >> +static void __init ls1021a_init_machine(void) {
> >> + mxc_arch_reset_init_dt();
> >
> >This looks to only be used to set up a watchdog timer. Is there any reason
> >this logic can't be moved to the watchdog timer driver?
> >
> >> +
> >> +DT_MACHINE_START(LS1021A, "Freescale LS1021A") #ifdef CONFIG_ZONE_DMA
> >> + .dma_zone_size = SZ_128M,
> >> +#endif
> >> + .init_machine = ls1021a_init_machine,
> >> + .dt_compat = ls1021a_dt_compat,
> >> + .restart = mxc_restart,
> >
> >AFAICT, that jsut uses the WDT for restart. Why can't the watchdog driver
> >register itself as a restart device?
> >
> >That would bring us close to an empty machine descriptor, and enable reuse
> >of the WDT and those busses.
> >
> >Thanks,
> >Mark.
> Yes, we use the watchdog timer for restart, just as i.MX and Vybrid, the WDT as a
> common driver it is still work for watchdog. Thanks.
That doesn't answer the question of why the restart code (and
registration thereof) can't live in the WDT driver.
Thanks,
Mark.
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021A
@ 2014-07-03 15:12 ` Mark Rutland
0 siblings, 0 replies; 30+ messages in thread
From: Mark Rutland @ 2014-07-03 15:12 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 03, 2014 at 11:17:12AM +0100, Jingchang Lu wrote:
> >-----Original Message-----
> >From: Mark Rutland [mailto:mark.rutland at arm.com]
> >Sent: Wednesday, July 02, 2014 7:21 PM
> >To: Lu Jingchang-B35083
> >Cc: shawn.guo at linaro.org; linux-arm-kernel at lists.infradead.org;
> >devicetree at vger.kernel.org; Lu Jingchang-B35083
> >Subject: Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale
> >LS1021A
> >
> >On Wed, Jul 02, 2014 at 10:02:51AM +0100, Jingchang Lu wrote:
> >> From: Jingchang Lu <b35083@freescale.com>
> >>
> >> diff --git a/arch/arm/mach-imx/mach-ls1021a.c
> >> b/arch/arm/mach-imx/mach-ls1021a.c
> >> new file mode 100644
> >> index 0000000..d1a9bb9
> >> --- /dev/null
> >> +++ b/arch/arm/mach-imx/mach-ls1021a.c
> >> @@ -0,0 +1,49 @@
> >> +/*
> >> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
> >> + *
> >> + * This program is free software; you can redistribute it and/or
> >> +modify
> >> + * it under the terms of the GNU General Public License as published
> >> +by
> >> + * the Free Software Foundation; either version 2 of the License, or
> >> + * (at your option) any later version.
> >> + */
> >> +
> >> +#include <linux/of_platform.h>
> >> +#include <asm/mach/arch.h>
> >> +
> >> +#include "common.h"
> >> +
> >> +static const struct of_device_id of_ls1021a_match_table[] = {
> >> + {
> >> + .compatible = "simple-bus",
> >> + },
> >> + {
> >> + .compatible = "fsl,ifc",
> >> + },
> >> + {
> >> + .compatible = "fsl,fpga-qixis",
> >> + },
> >> + {
> >> + .compatible = "fsl,qe",
> >> + },
> >> + {}
> >> +};
> >
> >Are any of thse not always-on (or default-on) MMIO busses?
> >
> >Is there any reason for not giving them their own drivers?
> >
> Normally these are always-on. The child nodes are handled by different drivers,
> so to make the devices being added by the of system, they are claimed here.
> Thanks.
If these are always-on MMIO busses, is there any reason these can't have
"simple-bus" as a fallback in their compatible lists in the DT? They
would seemd to be compatible with it given they are in the table
above...
That way we don't need the table at all, and we can always add drivers
for them later if we need them...
> >> +
> >> +static void __init ls1021a_init_machine(void) {
> >> + mxc_arch_reset_init_dt();
> >
> >This looks to only be used to set up a watchdog timer. Is there any reason
> >this logic can't be moved to the watchdog timer driver?
> >
> >> +
> >> +DT_MACHINE_START(LS1021A, "Freescale LS1021A") #ifdef CONFIG_ZONE_DMA
> >> + .dma_zone_size = SZ_128M,
> >> +#endif
> >> + .init_machine = ls1021a_init_machine,
> >> + .dt_compat = ls1021a_dt_compat,
> >> + .restart = mxc_restart,
> >
> >AFAICT, that jsut uses the WDT for restart. Why can't the watchdog driver
> >register itself as a restart device?
> >
> >That would bring us close to an empty machine descriptor, and enable reuse
> >of the WDT and those busses.
> >
> >Thanks,
> >Mark.
> Yes, we use the watchdog timer for restart, just as i.MX and Vybrid, the WDT as a
> common driver it is still work for watchdog. Thanks.
That doesn't answer the question of why the restart code (and
registration thereof) can't live in the WDT driver.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021A
2014-07-03 15:12 ` Mark Rutland
@ 2014-07-04 6:21 ` Jingchang Lu
-1 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-04 6:21 UTC (permalink / raw)
To: Mark Rutland
Cc: Shawn Guo, shawn.guo-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
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[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 4412 bytes --]
>-----Original Message-----
>From: Mark Rutland [mailto:mark.rutland@arm.com]
>Sent: Thursday, July 03, 2014 11:12 PM
>To: Lu Jingchang-B35083
>Cc: Guo Shawn-R65073; shawn.guo@linaro.org; linux-arm-
>kernel@lists.infradead.org; devicetree@vger.kernel.org
>Subject: Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale
>LS1021A
>
>On Thu, Jul 03, 2014 at 11:17:12AM +0100, Jingchang Lu wrote:
>> >-----Original Message-----
>> >From: Mark Rutland [mailto:mark.rutland@arm.com]
>> >Sent: Wednesday, July 02, 2014 7:21 PM
>> >To: Lu Jingchang-B35083
>> >Cc: shawn.guo@linaro.org; linux-arm-kernel@lists.infradead.org;
>> >devicetree@vger.kernel.org; Lu Jingchang-B35083
>> >Subject: Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale
>> >LS1021A
>> >
>> >On Wed, Jul 02, 2014 at 10:02:51AM +0100, Jingchang Lu wrote:
>> >> From: Jingchang Lu <b35083@freescale.com>
>> >>
>> >> diff --git a/arch/arm/mach-imx/mach-ls1021a.c
>> >> b/arch/arm/mach-imx/mach-ls1021a.c
>> >> new file mode 100644
>> >> index 0000000..d1a9bb9
>> >> --- /dev/null
>> >> +++ b/arch/arm/mach-imx/mach-ls1021a.c
>> >> @@ -0,0 +1,49 @@
>> >> +/*
>> >> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or
>> >> +modify
>> >> + * it under the terms of the GNU General Public License as
>> >> +published by
>> >> + * the Free Software Foundation; either version 2 of the License,
>> >> +or
>> >> + * (at your option) any later version.
>> >> + */
>> >> +
>> >> +#include <linux/of_platform.h>
>> >> +#include <asm/mach/arch.h>
>> >> +
>> >> +#include "common.h"
>> >> +
>> >> +static const struct of_device_id of_ls1021a_match_table[] = {
>> >> + {
>> >> + .compatible = "simple-bus",
>> >> + },
>> >> + {
>> >> + .compatible = "fsl,ifc",
>> >> + },
>> >> + {
>> >> + .compatible = "fsl,fpga-qixis",
>> >> + },
>> >> + {
>> >> + .compatible = "fsl,qe",
>> >> + },
>> >> + {}
>> >> +};
>> >
>> >Are any of thse not always-on (or default-on) MMIO busses?
>> >
>> >Is there any reason for not giving them their own drivers?
>> >
>> Normally these are always-on. The child nodes are handled by different
>> drivers, so to make the devices being added by the of system, they are
>claimed here.
>> Thanks.
>
>If these are always-on MMIO busses, is there any reason these can't have
>"simple-bus" as a fallback in their compatible lists in the DT? They would
>seemd to be compatible with it given they are in the table above...
>
>That way we don't need the table at all, and we can always add drivers for
>them later if we need them...
Yes, if they can work well with the default "simple-bus", I will change to it,
I will try this. Thanks.
>
>> >> +
>> >> +static void __init ls1021a_init_machine(void) {
>> >> + mxc_arch_reset_init_dt();
>> >
>> >This looks to only be used to set up a watchdog timer. Is there any
>> >reason this logic can't be moved to the watchdog timer driver?
>> >
>> >> +
>> >> +DT_MACHINE_START(LS1021A, "Freescale LS1021A") #ifdef
>CONFIG_ZONE_DMA
>> >> + .dma_zone_size = SZ_128M,
>> >> +#endif
>> >> + .init_machine = ls1021a_init_machine,
>> >> + .dt_compat = ls1021a_dt_compat,
>> >> + .restart = mxc_restart,
>> >
>> >AFAICT, that jsut uses the WDT for restart. Why can't the watchdog
>> >driver register itself as a restart device?
>> >
>> >That would bring us close to an empty machine descriptor, and enable
>> >reuse of the WDT and those busses.
>> >
>> >Thanks,
>> >Mark.
>> Yes, we use the watchdog timer for restart, just as i.MX and Vybrid,
>> the WDT as a common driver it is still work for watchdog. Thanks.
>
>That doesn't answer the question of why the restart code (and registration
>thereof) can't live in the WDT driver.
>
>Thanks,
>Mark.
Several i.MX SoCs have used this mxc_restart currently, and the watchdog driver is
shared between them, if here move it to the driver layer, all others needs changes
accordingly. So I think if that is preferred, we can move it together some times later.
And BTW, what's the preferred restart register manner in the driver, just assign to
the arm_pm_restart? Thanks.
Best Regards,
Jingchang
N‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·zøœzÚÞz)í…æèw*\x1fjg¬±¨\x1e¶‰šŽŠÝ¢j.ïÛ°\½½MŽúgjÌæa×\x02››–' ™©Þ¢¸\f¢·¦j:+v‰¨ŠwèjØm¶Ÿÿ¾\a«‘êçzZ+ƒùšŽŠÝ¢j"ú!¶i
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021A
@ 2014-07-04 6:21 ` Jingchang Lu
0 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-04 6:21 UTC (permalink / raw)
To: linux-arm-kernel
>-----Original Message-----
>From: Mark Rutland [mailto:mark.rutland at arm.com]
>Sent: Thursday, July 03, 2014 11:12 PM
>To: Lu Jingchang-B35083
>Cc: Guo Shawn-R65073; shawn.guo at linaro.org; linux-arm-
>kernel at lists.infradead.org; devicetree at vger.kernel.org
>Subject: Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale
>LS1021A
>
>On Thu, Jul 03, 2014 at 11:17:12AM +0100, Jingchang Lu wrote:
>> >-----Original Message-----
>> >From: Mark Rutland [mailto:mark.rutland at arm.com]
>> >Sent: Wednesday, July 02, 2014 7:21 PM
>> >To: Lu Jingchang-B35083
>> >Cc: shawn.guo at linaro.org; linux-arm-kernel at lists.infradead.org;
>> >devicetree at vger.kernel.org; Lu Jingchang-B35083
>> >Subject: Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale
>> >LS1021A
>> >
>> >On Wed, Jul 02, 2014 at 10:02:51AM +0100, Jingchang Lu wrote:
>> >> From: Jingchang Lu <b35083@freescale.com>
>> >>
>> >> diff --git a/arch/arm/mach-imx/mach-ls1021a.c
>> >> b/arch/arm/mach-imx/mach-ls1021a.c
>> >> new file mode 100644
>> >> index 0000000..d1a9bb9
>> >> --- /dev/null
>> >> +++ b/arch/arm/mach-imx/mach-ls1021a.c
>> >> @@ -0,0 +1,49 @@
>> >> +/*
>> >> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or
>> >> +modify
>> >> + * it under the terms of the GNU General Public License as
>> >> +published by
>> >> + * the Free Software Foundation; either version 2 of the License,
>> >> +or
>> >> + * (at your option) any later version.
>> >> + */
>> >> +
>> >> +#include <linux/of_platform.h>
>> >> +#include <asm/mach/arch.h>
>> >> +
>> >> +#include "common.h"
>> >> +
>> >> +static const struct of_device_id of_ls1021a_match_table[] = {
>> >> + {
>> >> + .compatible = "simple-bus",
>> >> + },
>> >> + {
>> >> + .compatible = "fsl,ifc",
>> >> + },
>> >> + {
>> >> + .compatible = "fsl,fpga-qixis",
>> >> + },
>> >> + {
>> >> + .compatible = "fsl,qe",
>> >> + },
>> >> + {}
>> >> +};
>> >
>> >Are any of thse not always-on (or default-on) MMIO busses?
>> >
>> >Is there any reason for not giving them their own drivers?
>> >
>> Normally these are always-on. The child nodes are handled by different
>> drivers, so to make the devices being added by the of system, they are
>claimed here.
>> Thanks.
>
>If these are always-on MMIO busses, is there any reason these can't have
>"simple-bus" as a fallback in their compatible lists in the DT? They would
>seemd to be compatible with it given they are in the table above...
>
>That way we don't need the table at all, and we can always add drivers for
>them later if we need them...
Yes, if they can work well with the default "simple-bus", I will change to it,
I will try this. Thanks.
>
>> >> +
>> >> +static void __init ls1021a_init_machine(void) {
>> >> + mxc_arch_reset_init_dt();
>> >
>> >This looks to only be used to set up a watchdog timer. Is there any
>> >reason this logic can't be moved to the watchdog timer driver?
>> >
>> >> +
>> >> +DT_MACHINE_START(LS1021A, "Freescale LS1021A") #ifdef
>CONFIG_ZONE_DMA
>> >> + .dma_zone_size = SZ_128M,
>> >> +#endif
>> >> + .init_machine = ls1021a_init_machine,
>> >> + .dt_compat = ls1021a_dt_compat,
>> >> + .restart = mxc_restart,
>> >
>> >AFAICT, that jsut uses the WDT for restart. Why can't the watchdog
>> >driver register itself as a restart device?
>> >
>> >That would bring us close to an empty machine descriptor, and enable
>> >reuse of the WDT and those busses.
>> >
>> >Thanks,
>> >Mark.
>> Yes, we use the watchdog timer for restart, just as i.MX and Vybrid,
>> the WDT as a common driver it is still work for watchdog. Thanks.
>
>That doesn't answer the question of why the restart code (and registration
>thereof) can't live in the WDT driver.
>
>Thanks,
>Mark.
Several i.MX SoCs have used this mxc_restart currently, and the watchdog driver is
shared between them, if here move it to the driver layer, all others needs changes
accordingly. So I think if that is preferred, we can move it together some times later.
And BTW, what's the preferred restart register manner in the driver, just assign to
the arm_pm_restart? Thanks.
Best Regards,
Jingchang
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH 5/5] ARM: imx: Add Freescale LS1021A SMP support
2014-07-02 11:30 ` Mark Rutland
@ 2014-07-04 10:16 ` Jingchang Lu
-1 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-04 10:16 UTC (permalink / raw)
To: Mark Rutland
Cc: shawn.guo-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
>-----Original Message-----
>From: Mark Rutland [mailto:mark.rutland@arm.com]
>Sent: Wednesday, July 02, 2014 7:31 PM
>To: Lu Jingchang-B35083
>Cc: shawn.guo@linaro.org; linux-arm-kernel@lists.infradead.org;
>devicetree@vger.kernel.org; Lu Jingchang-B35083
>Subject: Re: [PATCH 5/5] ARM: imx: Add Freescale LS1021A SMP support
>
>On Wed, Jul 02, 2014 at 10:02:52AM +0100, Jingchang Lu wrote:
>> From: Jingchang Lu <b35083@freescale.com>
>>
>> Freescale LS1021A SoC deploys two cortex-A7 processors, this adds
>> bring-up support for the secondary core.
>>
>> Signed-off-by: Jingchang Lu <b35083@freescale.com>
>> ---
>> arch/arm/mach-imx/common.h | 2 ++
>> arch/arm/mach-imx/headsmp.S | 11 ++++++++++
>> arch/arm/mach-imx/mach-ls1021a.c | 1 +
>> arch/arm/mach-imx/platsmp.c | 44
>++++++++++++++++++++++++++++++++++++++++
>> 4 files changed, 58 insertions(+)
>
>[...]
>
>> diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
>> index de5047c..fdd93d9 100644
>> --- a/arch/arm/mach-imx/headsmp.S
>> +++ b/arch/arm/mach-imx/headsmp.S
>> @@ -29,3 +29,14 @@ ENTRY(v7_secondary_startup)
>> set_diag_reg
>> b secondary_startup
>> ENDPROC(v7_secondary_startup)
>> +
>> +ENTRY(ls1021a_secondary_startup)
>> + /* set CNTFREQ of secondary core */
>> + ldr r0, =12500000
>> + mcr p15, 0, r0, c14, c0, 0
>> + /* disable Physical and Virtural Timer */
>> + mov r0, #0x0
>> + mcr p15, 0, r0, c14, c2, 1
>> + mcr p15, 0, r0, c14, c3, 1
>> + b secondary_startup
>
>Urrgh...
>
>What about CNTVOFF? That's been a source of problems elsewhere.
>
>Is the boot CPU set up correctly?
>
>Is that frequency always going to be correct?
>
We use 12.5Mhz as the counter clock, and We have found the virtual counter offset issue.
We currently use the physical counter as a workaround for this, we are also working on
to clear the CNTVOFF in u-boot, when it is finished, the virtual counter would be sync
and work well.
Thanks.
>[...]
>
>> +static void __init ls1021a_smp_init_cpus(void) {
>> + int i, ncores;
>> + /* get number of cores from CP15 L2 controller register(L2CTLR)*/
>> + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (ncores));
>> +
>> + ncores = ((ncores >> 24) & 0x3) + 1;
>> + for (i = ncores; i < NR_CPUS; i++)
>> + set_cpu_possible(i, false);
>> +}
>
>NAK.
>
>This information is _already_ in the DT. This adds more code to do
>redundant work, and it's broken.
>
>The physical<->logical CPU ID mapping is arbitrary, so you set arbitrary
>CPUs as being online despite this not necessarily being the case.
>
>Get rid of this, and rely on the DT being correct. There;s no reason it
>shouldn't be for a new platform.
>
>Thanks,
>Mark.
I will remove this. Thanks.
Best Regards,
Jingchang
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 5/5] ARM: imx: Add Freescale LS1021A SMP support
@ 2014-07-04 10:16 ` Jingchang Lu
0 siblings, 0 replies; 30+ messages in thread
From: Jingchang Lu @ 2014-07-04 10:16 UTC (permalink / raw)
To: linux-arm-kernel
>-----Original Message-----
>From: Mark Rutland [mailto:mark.rutland at arm.com]
>Sent: Wednesday, July 02, 2014 7:31 PM
>To: Lu Jingchang-B35083
>Cc: shawn.guo at linaro.org; linux-arm-kernel at lists.infradead.org;
>devicetree at vger.kernel.org; Lu Jingchang-B35083
>Subject: Re: [PATCH 5/5] ARM: imx: Add Freescale LS1021A SMP support
>
>On Wed, Jul 02, 2014 at 10:02:52AM +0100, Jingchang Lu wrote:
>> From: Jingchang Lu <b35083@freescale.com>
>>
>> Freescale LS1021A SoC deploys two cortex-A7 processors, this adds
>> bring-up support for the secondary core.
>>
>> Signed-off-by: Jingchang Lu <b35083@freescale.com>
>> ---
>> arch/arm/mach-imx/common.h | 2 ++
>> arch/arm/mach-imx/headsmp.S | 11 ++++++++++
>> arch/arm/mach-imx/mach-ls1021a.c | 1 +
>> arch/arm/mach-imx/platsmp.c | 44
>++++++++++++++++++++++++++++++++++++++++
>> 4 files changed, 58 insertions(+)
>
>[...]
>
>> diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
>> index de5047c..fdd93d9 100644
>> --- a/arch/arm/mach-imx/headsmp.S
>> +++ b/arch/arm/mach-imx/headsmp.S
>> @@ -29,3 +29,14 @@ ENTRY(v7_secondary_startup)
>> set_diag_reg
>> b secondary_startup
>> ENDPROC(v7_secondary_startup)
>> +
>> +ENTRY(ls1021a_secondary_startup)
>> + /* set CNTFREQ of secondary core */
>> + ldr r0, =12500000
>> + mcr p15, 0, r0, c14, c0, 0
>> + /* disable Physical and Virtural Timer */
>> + mov r0, #0x0
>> + mcr p15, 0, r0, c14, c2, 1
>> + mcr p15, 0, r0, c14, c3, 1
>> + b secondary_startup
>
>Urrgh...
>
>What about CNTVOFF? That's been a source of problems elsewhere.
>
>Is the boot CPU set up correctly?
>
>Is that frequency always going to be correct?
>
We use 12.5Mhz as the counter clock, and We have found the virtual counter offset issue.
We currently use the physical counter as a workaround for this, we are also working on
to clear the CNTVOFF in u-boot, when it is finished, the virtual counter would be sync
and work well.
Thanks.
>[...]
>
>> +static void __init ls1021a_smp_init_cpus(void) {
>> + int i, ncores;
>> + /* get number of cores from CP15 L2 controller register(L2CTLR)*/
>> + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (ncores));
>> +
>> + ncores = ((ncores >> 24) & 0x3) + 1;
>> + for (i = ncores; i < NR_CPUS; i++)
>> + set_cpu_possible(i, false);
>> +}
>
>NAK.
>
>This information is _already_ in the DT. This adds more code to do
>redundant work, and it's broken.
>
>The physical<->logical CPU ID mapping is arbitrary, so you set arbitrary
>CPUs as being online despite this not necessarily being the case.
>
>Get rid of this, and rely on the DT being correct. There;s no reason it
>shouldn't be for a new platform.
>
>Thanks,
>Mark.
I will remove this. Thanks.
Best Regards,
Jingchang
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2014-07-04 10:16 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-07-02 9:02 [PATCH 0/5] ARM: imx: Add Freescale LS1021A SoC and board support Jingchang Lu
2014-07-02 9:02 ` Jingchang Lu
2014-07-02 9:02 ` [PATCH 3/5] ARM: dts: Add initial LS1021A TWR board dts support Jingchang Lu
2014-07-02 9:02 ` Jingchang Lu
[not found] ` <1404291772-2644-1-git-send-email-jingchang.lu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-07-02 9:02 ` [PATCH 1/5] ARM: dts: Add SoC level device tree support for LS1021A Jingchang Lu
2014-07-02 9:02 ` Jingchang Lu
[not found] ` <1404291772-2644-2-git-send-email-jingchang.lu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-07-02 11:14 ` Mark Rutland
2014-07-02 11:14 ` Mark Rutland
2014-07-03 7:58 ` Jingchang Lu
2014-07-03 7:58 ` Jingchang Lu
[not found] ` <c0f6813bc62a41b19790158d761d6652-AZ66ij2kwab4MB1ZSnT4iOO6mTEJWrR4XA4E9RH9d+qIuWR1G4zioA@public.gmane.org>
2014-07-03 10:10 ` Mark Rutland
2014-07-03 10:10 ` Mark Rutland
2014-07-02 9:02 ` [PATCH 2/5] ARM: dts: Add initial LS1021A QDS board dts support Jingchang Lu
2014-07-02 9:02 ` Jingchang Lu
2014-07-02 9:02 ` [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021A Jingchang Lu
2014-07-02 9:02 ` Jingchang Lu
[not found] ` <1404291772-2644-5-git-send-email-jingchang.lu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-07-02 11:21 ` Mark Rutland
2014-07-02 11:21 ` Mark Rutland
2014-07-03 10:17 ` Jingchang Lu
2014-07-03 10:17 ` Jingchang Lu
[not found] ` <cb01fef2c4d44711b04a321fddae33d4-AZ66ij2kwab4MB1ZSnT4iOO6mTEJWrR4XA4E9RH9d+qIuWR1G4zioA@public.gmane.org>
2014-07-03 15:12 ` Mark Rutland
2014-07-03 15:12 ` Mark Rutland
2014-07-04 6:21 ` Jingchang Lu
2014-07-04 6:21 ` Jingchang Lu
2014-07-02 9:02 ` [PATCH 5/5] ARM: imx: Add Freescale LS1021A SMP support Jingchang Lu
2014-07-02 9:02 ` Jingchang Lu
[not found] ` <1404291772-2644-6-git-send-email-jingchang.lu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-07-02 11:30 ` Mark Rutland
2014-07-02 11:30 ` Mark Rutland
2014-07-04 10:16 ` Jingchang Lu
2014-07-04 10:16 ` Jingchang Lu
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