* [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support
@ 2014-07-04 19:05 Pekon Gupta
2014-07-04 19:05 ` [U-Boot] [PATCH v1 1/7] TI: armv7: move board specific NAND configs out from ti_armv7_common.h and ti_am335x_common.h Pekon Gupta
` (7 more replies)
0 siblings, 8 replies; 20+ messages in thread
From: Pekon Gupta @ 2014-07-04 19:05 UTC (permalink / raw)
To: u-boot
This patch series adds support for parallel NAND devices support connected via
GPMC chip-select on various boards belonging to AM33xx and OMAPx platforms.
This series also moves some board specific CONFIG_NAND_xx from generic files
to individual files.
Tested using: ./MAKEALL -s am33xx -s omap3 -s oamp4 -s omap5
works fine except for am335x_boneblack_vboot
build breaks for am335x_boneblack_vboot for un-related reasons
u-boot/scripts/dtc-version.sh: line 17: dtc: command not found
Pekon Gupta (7):
TI: armv7: move board specific NAND configs out from ti_armv7_common.h
and ti_am335x_common.h
board/ti/am335x: add support for beaglebone NAND cape
arm: lib: continue board_init_r even if valid flash device is not
detected
board/ti/am335x: add support for beaglebone NOR Cape
board/ti/am335x: update configs for parallel NAND
board/ti/am43xx: add support for parallel NAND
board/ti/dra7xx: add support for parallel NAND
arch/arm/lib/board.c | 7 +-
board/ti/am335x/mux.c | 149 ++++++++++++++++++-------------------
board/ti/am43xx/board.c | 1 +
board/ti/am43xx/mux.c | 42 +++++++++++
board/ti/dra7xx/mux_data.h | 30 ++++++++
boards.cfg | 4 +-
doc/README.nand | 12 +++
include/configs/am335x_evm.h | 64 +++++++++-------
include/configs/am43xx_evm.h | 70 +++++++++++++++++
include/configs/cm_t335.h | 10 +++
include/configs/dra7xx_evm.h | 58 ++++++++++++++-
include/configs/omap3_beagle.h | 6 ++
include/configs/omap3_igep00x0.h | 9 +++
include/configs/omap3_overo.h | 8 ++
include/configs/omap3_zoom1.h | 7 ++
include/configs/pengwyn.h | 7 ++
include/configs/ti_am335x_common.h | 4 -
include/configs/ti_armv7_common.h | 9 ---
18 files changed, 369 insertions(+), 128 deletions(-)
--
1.8.5.1.163.gd7aced9
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH v1 1/7] TI: armv7: move board specific NAND configs out from ti_armv7_common.h and ti_am335x_common.h
2014-07-04 19:05 [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Pekon Gupta
@ 2014-07-04 19:05 ` Pekon Gupta
2014-07-14 21:30 ` Tom Rini
2014-07-04 19:05 ` [U-Boot] [PATCH v1 2/7] board/ti/am335x: add support for beaglebone NAND cape Pekon Gupta
` (6 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Pekon Gupta @ 2014-07-04 19:05 UTC (permalink / raw)
To: u-boot
This patch moves some board specific NAND configs:
- FROM: generic config files like 'ti_armv7_common.h' and 'ti_am335x_common.h'
- TO: individual board config files using these configs.
So that each board can independently set the value as per its design.
Following configs are affected in this patch:
CONFIG_NAND_OMAP_GPMC: <refer doc/README.nand>
CONFIG_NAND_OMAP_ELM: <refer doc/README.nand>
CONFIG_SPL_NAND_AM33XX_BCH: <refer doc/README.nand>
CONFIG_SYS_NAND_U_BOOT_OFFS: <refer doc/README.nand>
CONFIG_CMD_SPL_NAND_OFS: <refer doc/README.falcon>
CONFIG_SYS_NAND_SPL_KERNEL_OFFS: <refer doc/README.falcon>
CONFIG_CMD_SPL_WRITE_SIZE: <refer doc/README.falcon>
This patch also updates documentation for few of above NAND configs.
Signed-off-by: Pekon Gupta <pekon@ti.com>
---
doc/README.nand | 12 ++++++++++++
include/configs/am335x_evm.h | 7 +++++++
include/configs/cm_t335.h | 10 ++++++++++
include/configs/omap3_beagle.h | 6 ++++++
include/configs/omap3_igep00x0.h | 9 +++++++++
include/configs/omap3_overo.h | 8 ++++++++
include/configs/omap3_zoom1.h | 7 +++++++
include/configs/pengwyn.h | 7 +++++++
include/configs/ti_am335x_common.h | 4 ----
include/configs/ti_armv7_common.h | 9 ---------
10 files changed, 66 insertions(+), 13 deletions(-)
diff --git a/doc/README.nand b/doc/README.nand
index 70cf768..e29188f 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -89,6 +89,10 @@ Commands:
Configuration Options:
+ CONFIG_SYS_NAND_U_BOOT_OFFS
+ NAND Offset from where SPL will read u-boot image. This is the starting
+ address of u-boot MTD partition in NAND.
+
CONFIG_CMD_NAND
Enables NAND support and commmands.
@@ -226,6 +230,14 @@ Platform specific options
detection. However ECC calculation on such plaforms would still be
done by GPMC controller.
+ CONFIG_SPL_NAND_AM33XX_BCH
+ Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
+ hardware ECC correction. This is useful for platforms which have ELM
+ hardware engine and use NAND boot mode.
+ Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
+ so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
+ SPL-NAND driver with software ECC correction support.
+
CONFIG_NAND_OMAP_ECCSCHEME
On OMAP platforms, this CONFIG specifies NAND ECC scheme.
It can take following values:
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index a48b386..57a6cab 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -233,6 +233,8 @@
#ifdef CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SPL_NAND_AM33XX_BCH
+/* NAND: device related configs */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
@@ -254,6 +256,11 @@
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+#ifdef CONFIG_SPL_OS_BOOT
+ #define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */
+ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
+ #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
#endif
#endif
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index 4d1dd28..70b6e90 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -150,6 +150,16 @@
#define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* NAND: driver related configs */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SPL_NAND_AM33XX_BCH /* SPL-NAND driver with ELM support */
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+ #define CONFIG_CMD_SPL_NAND_OFS 0x400000 /* un-assigned: (using dtb) */
+ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000
+ #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
/* GPIO pin + bank to pin ID mapping */
#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin)
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index c023483..7878765 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -126,6 +126,12 @@
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 79daabd..7daaef5 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -187,6 +187,15 @@
/* NAND boot config */
#ifdef CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+ #define CONFIG_CMD_SPL_NAND_OFS 0x240000
+ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+ #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/* NAND: device related configs */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index f7483a0..a879d72 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -206,6 +206,14 @@
#define CONFIG_SYS_CACHELINE_SIZE 64
/* NAND boot config */
+#define CONFIG_NAND_OMAP_GPMC
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+ #define CONFIG_CMD_SPL_NAND_OFS 0x240000
+ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+ #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
+/* NAND: device related configs */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 3efe4cf..409be31 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -69,6 +69,13 @@
"1920k(u-boot),128k(u-boot-env),"\
"4m(kernel),-(fs)"
+#define CONFIG_NAND_OMAP_GPMC
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+ #define CONFIG_CMD_SPL_NAND_OFS 0x240000
+ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+ #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
#if defined(CONFIG_CMD_NAND)
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
#endif
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 8510405..f758cf9 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -127,6 +127,7 @@
#define CONFIG_CMD_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SPL_NAND_AM33XX_BCH
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
@@ -159,6 +160,12 @@
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+ #define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* un-assigned */
+ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+ #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
/*
* USB configuration. We enable MUSB support, both for host and for
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 80976e7..12fceb7 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -84,10 +84,6 @@
#define CONFIG_BOARD_EARLY_INIT_F
#endif
-#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
-#endif
-
/* Now bring in the rest of the common code. */
#include <configs/ti_armv7_common.h>
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 6e0bf09..c901522 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -110,7 +110,6 @@
* access CS0 at is 0x8000000.
*/
#ifdef CONFIG_NAND
-#define CONFIG_NAND_OMAP_GPMC
#ifndef CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_BASE 0x8000000
#endif
@@ -243,13 +242,6 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
-/* NAND */
-#ifdef CONFIG_NAND
-#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
-#endif
-
/* spl export command */
#define CONFIG_CMD_SPL
#endif
@@ -275,7 +267,6 @@
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_MTD_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif
#endif /* !CONFIG_NOR_BOOT */
--
1.8.5.1.163.gd7aced9
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH v1 2/7] board/ti/am335x: add support for beaglebone NAND cape
2014-07-04 19:05 [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Pekon Gupta
2014-07-04 19:05 ` [U-Boot] [PATCH v1 1/7] TI: armv7: move board specific NAND configs out from ti_armv7_common.h and ti_am335x_common.h Pekon Gupta
@ 2014-07-04 19:05 ` Pekon Gupta
2014-07-16 20:02 ` Tom Rini
2014-07-04 19:05 ` [U-Boot] [PATCH v1 3/7] arm: lib: continue board_init_r even if valid flash device is not detected Pekon Gupta
` (5 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Pekon Gupta @ 2014-07-04 19:05 UTC (permalink / raw)
To: u-boot
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]
* How to boot from NAND using Memory Expander + NAND Cape ? *
- Important: As BOOTSEL values are sampled only at POR, so after changing any
setting on SW2 (DIP switch), disconnect and reconnect all board power supply
(including mini-USB console port) to POR the beaglebone.
- Selection of ECC scheme
for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
for NAND cape(b), ROM code expects BCH16_HW ecc-scheme
- Selction of boot modes can be controlled via DIP switch(SW2) present on
Memory Expander cape.
SW2[SWITCH_BOOT] == OFF follow default boot order MMC-> SPI -> UART -> USB
SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2)
So to flash NAND, first boot via MMC or other sources and then switch to
SW2[SWITCH_BOOT]=ON to boot from NAND Cape.
- For NAND boot following switch settings need to be followed
SW2[ 1] = OFF (SYSBOOT[ 0]==1: NAND boot mode selected )
SW2[ 2] = OFF (SYSBOOT[ 1]==1: -- do -- )
SW2[ 3] = ON (SYSBOOT[ 2]==0: -- do -- )
SW2[ 4] = ON (SYSBOOT[ 3]==0: -- do -- )
SW2[ 5] = OFF (SYSBOOT[ 4]==1: -- do -- )
SW2[ 6] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
SW2[ 7] = ON (SYSBOOT[ 9]==0: ECC done by ROM )
SW2[ 8] = ON (SYSBOOT[10]==0: Non Muxed device )
SW2[ 9] = ON (SYSBOOT[11]==0: -- do -- )
[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2] http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
Signed-off-by: Pekon Gupta <pekon@ti.com>
---
board/ti/am335x/mux.c | 58 +++++++++++++++++++++++++++++++++------------------
1 file changed, 38 insertions(+), 20 deletions(-)
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index b2bfda5..439da4b 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -171,25 +171,36 @@ static struct module_pin_mux mii1_pin_mux[] = {
{-1},
};
+#ifdef CONFIG_NAND
static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
+ {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
+ {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
+ {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
+ {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
+ {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
+ {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
+ {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
+#endif
+ {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
{-1},
};
-
+#endif
#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
static struct module_pin_mux bone_norcape_pin_mux[] = {
{OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
@@ -336,11 +347,12 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
-#ifndef CONFIG_NOR
- configure_module_pin_mux(mmc1_pin_mux);
-#endif
-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+#if defined(CONFIG_NAND)
+ configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
configure_module_pin_mux(bone_norcape_pin_mux);
+#else
+ configure_module_pin_mux(mmc1_pin_mux);
#endif
} else if (board_is_gp_evm(header)) {
/* General Purpose EVM */
@@ -351,8 +363,10 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
if (profile & ~PROFILE_2)
configure_module_pin_mux(i2c1_pin_mux);
/* Profiles 2 & 3 don't have NAND */
+#ifdef CONFIG_NAND
if (profile & ~(PROFILE_2 | PROFILE_3))
configure_module_pin_mux(nand_pin_mux);
+#endif
else if (profile == PROFILE_2) {
configure_module_pin_mux(mmc1_pin_mux);
configure_module_pin_mux(spi0_pin_mux);
@@ -377,7 +391,11 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
+#if defined(CONFIG_NAND)
+ configure_module_pin_mux(nand_pin_mux);
+#else
configure_module_pin_mux(mmc1_pin_mux);
+#endif
} else {
puts("Unknown board, cannot configure pinmux.");
hang();
--
1.8.5.1.163.gd7aced9
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH v1 3/7] arm: lib: continue board_init_r even if valid flash device is not detected
2014-07-04 19:05 [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Pekon Gupta
2014-07-04 19:05 ` [U-Boot] [PATCH v1 1/7] TI: armv7: move board specific NAND configs out from ti_armv7_common.h and ti_am335x_common.h Pekon Gupta
2014-07-04 19:05 ` [U-Boot] [PATCH v1 2/7] board/ti/am335x: add support for beaglebone NAND cape Pekon Gupta
@ 2014-07-04 19:05 ` Pekon Gupta
2014-07-16 20:07 ` Tom Rini
2014-07-04 19:05 ` [U-Boot] [PATCH v1 4/7] board/ti/am335x: add support for beaglebone NOR Cape Pekon Gupta
` (4 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Pekon Gupta @ 2014-07-04 19:05 UTC (permalink / raw)
To: u-boot
Most platforms have fall-back boot sources, if their primary boot fails.
This patch allows board_init to continue scanning through other secondary boot
sources like NAND, MMC, etc if valid FLASH device is not detected.
Signed-off-by: Pekon Gupta <pekon@ti.com>
---
arch/arm/lib/board.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 76adaf3..413ee60 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -460,10 +460,6 @@ void board_init_f(ulong bootflag)
memcpy(id, (void *)gd, sizeof(gd_t));
}
-#if !defined(CONFIG_SYS_NO_FLASH)
-static char *failed = "*** failed ***\n";
-#endif
-
/*
* Tell if it's OK to load the environment early in boot.
*
@@ -574,8 +570,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
print_size(flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
- puts(failed);
- hang();
+ puts("unable to detect valid flash device\n");
}
#endif
--
1.8.5.1.163.gd7aced9
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH v1 4/7] board/ti/am335x: add support for beaglebone NOR Cape
2014-07-04 19:05 [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Pekon Gupta
` (2 preceding siblings ...)
2014-07-04 19:05 ` [U-Boot] [PATCH v1 3/7] arm: lib: continue board_init_r even if valid flash device is not detected Pekon Gupta
@ 2014-07-04 19:05 ` Pekon Gupta
2014-07-16 20:06 ` Tom Rini
2014-07-04 19:05 ` [U-Boot] [PATCH v1 5/7] board/ti/am335x: update configs for parallel NAND Pekon Gupta
` (3 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Pekon Gupta @ 2014-07-04 19:05 UTC (permalink / raw)
To: u-boot
This patch updates pin-mux for beaglebone NOR cape [1]
This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.
On Beaglebone, GPMC chip-select-0 is shared by both NAND and NOR capes,
so only one of them can be enabled at a time from board profile configs.
[1] http://elinux.org/Beagleboardtoys:BeagleBone_128Mb_16-Bit_NOR_Module
Signed-off-by: Pekon Gupta <pekon@ti.com>
---
board/ti/am335x/mux.c | 95 +++++++++++++++++++--------------------------------
1 file changed, 35 insertions(+), 60 deletions(-)
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 439da4b..f6a9b29 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -200,73 +200,46 @@ static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
{-1},
};
-#endif
-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+#elif defined(CONFIG_NOR)
static struct module_pin_mux bone_norcape_pin_mux[] = {
- {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
- {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */
- {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */
- {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */
- {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */
- {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */
- {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */
- {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */
- {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */
- {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */
- {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */
- {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
- {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */
- {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */
- {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */
- {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */
- {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */
- {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */
- {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */
- {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */
- {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */
- {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */
- {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */
- {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */
- {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */
- {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */
- {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */
- {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */
- {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */
- {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */
- {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */
- {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */
- {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */
- {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */
- {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */
- {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */
-
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
+ {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD0 */
+ {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD1 */
+ {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD2 */
+ {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD3 */
+ {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD4 */
+ {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD5 */
+ {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD6 */
+ {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD7 */
+ {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD8 */
+ {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD9 */
+ {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD10 */
+ {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD11 */
+ {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD12 */
+ {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD13 */
+ {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD14 */
+ {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD15 */
+ {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* A0 */
+ {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* A1 */
+ {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* A2 */
+ {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* A3 */
+ {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* A4 */
+ {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* A5 */
+ {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* A6 */
+ {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* A7 */
+ {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
+ {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
+ {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
+ {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
+ {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
+ {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
{-1},
};
#endif
#if defined(CONFIG_NOR_BOOT)
-static struct module_pin_mux norboot_pin_mux[] = {
- {OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
- {-1},
-};
-
void enable_norboot_pin_mux(void)
{
- configure_module_pin_mux(norboot_pin_mux);
+ configure_module_pin_mux(bone_norcape_pin_mux);
}
#endif
@@ -349,7 +322,7 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
configure_module_pin_mux(mmc0_pin_mux);
#if defined(CONFIG_NAND)
configure_module_pin_mux(nand_pin_mux);
-#elif defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+#elif defined(CONFIG_NOR)
configure_module_pin_mux(bone_norcape_pin_mux);
#else
configure_module_pin_mux(mmc1_pin_mux);
@@ -393,6 +366,8 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
configure_module_pin_mux(mmc0_pin_mux);
#if defined(CONFIG_NAND)
configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_NOR)
+ configure_module_pin_mux(bone_norcape_pin_mux);
#else
configure_module_pin_mux(mmc1_pin_mux);
#endif
--
1.8.5.1.163.gd7aced9
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH v1 5/7] board/ti/am335x: update configs for parallel NAND
2014-07-04 19:05 [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Pekon Gupta
` (3 preceding siblings ...)
2014-07-04 19:05 ` [U-Boot] [PATCH v1 4/7] board/ti/am335x: add support for beaglebone NOR Cape Pekon Gupta
@ 2014-07-04 19:05 ` Pekon Gupta
2014-07-04 19:05 ` [U-Boot] [PATCH v1 6/7] board/ti/am43xx: add support " Pekon Gupta
` (2 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Pekon Gupta @ 2014-07-04 19:05 UTC (permalink / raw)
To: u-boot
This patch
- consolidate CONFIG_SYS_NAND_xx and CONFIG_SPL_NAND_xx from various
configuration files into single file.
- update MTD Partition table to match AM335x_EVM DT in linux-kernel
- segregate CONFIGs based on different boot modes (like SPL and U-Boot)
Signed-off-by: Pekon Gupta <pekon@ti.com>
---
include/configs/am335x_evm.h | 61 ++++++++++++++++++++++----------------------
1 file changed, 31 insertions(+), 30 deletions(-)
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 57a6cab..4f8ed2f 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -61,7 +61,7 @@
"${optargs} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
- "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \
"nandrootfstype=ubifs rootwait=1\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
@@ -229,18 +229,23 @@
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#endif
+/* NAND support */
#ifdef CONFIG_NAND
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_NAND_OMAP_ELM
-#define CONFIG_SPL_NAND_AM33XX_BCH
/* NAND: device related configs */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/* NAND: driver related configs */
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
@@ -252,17 +257,30 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+#define MTDIDS_DEFAULT "nand0=nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
+ "128k(NAND.SPL)," \
+ "128k(NAND.SPL.backup1)," \
+ "128k(NAND.SPL.backup2)," \
+ "128k(NAND.SPL.backup3)," \
+ "256k(NAND.u-boot-spl-os)," \
+ "1m(NAND.u-boot)," \
+ "128k(NAND.u-boot-env)," \
+ "128k(NAND.u-boot-env.backup1)," \
+ "8m(NAND.kernel)," \
+ "-(NAND.rootfs)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
+#define CONFIG_ENV_OFFSET 0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
#endif
-#endif
-#endif
+#endif /* !CONFIG_NAND */
/*
* For NOR boot, we must set this to the start of where NOR is mapped
@@ -419,23 +437,6 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
-/* NAND support */
-#ifdef CONFIG_NAND
-#define CONFIG_CMD_NAND
-#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
-#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
- "128k(SPL.backup1)," \
- "128k(SPL.backup2)," \
- "128k(SPL.backup3),1792k(u-boot)," \
- "128k(u-boot-spl-os)," \
- "128k(u-boot-env),5m(kernel),-(rootfs)"
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#endif
-#endif
-
/*
* NOR Size = 16 MiB
* Number of Sectors/Blocks = 128
--
1.8.5.1.163.gd7aced9
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH v1 6/7] board/ti/am43xx: add support for parallel NAND
2014-07-04 19:05 [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Pekon Gupta
` (4 preceding siblings ...)
2014-07-04 19:05 ` [U-Boot] [PATCH v1 5/7] board/ti/am335x: update configs for parallel NAND Pekon Gupta
@ 2014-07-04 19:05 ` Pekon Gupta
2014-07-16 20:14 ` Tom Rini
2014-07-04 19:05 ` [U-Boot] [PATCH v1 7/7] board/ti/dra7xx: " Pekon Gupta
2014-07-06 7:35 ` [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Igor Grinberg
7 siblings, 1 reply; 20+ messages in thread
From: Pekon Gupta @ 2014-07-04 19:05 UTC (permalink / raw)
To: u-boot
This patch adds support for NAND device connected to GPMC chip-select on
following AM43xx EVM boards.
am437x-gp-evm: On this board, NAND Flash signals are muxed with eMMC, thus at a
time either eMMC or NAND can be enabled. Selection between eMMC and NAND is
controlled by:
(a) Statically using Jumper on connecter (J89) present on board.
(a) If Jumper on J89 is NOT used, then selection can be dynamically controlled
by driving SPI2_CS0[MUX_MODE=GPIO] pin via software:
SPI2_CS0 == 0: NAND (default)
SPI2_CS0 == 1: eMMC
am43x-epos-evm: On this board, NAND Flash control lines are muxed with QSPI,
Thus only one of the two can be used at a time. Selection is controlled by:
(a) Dynamically driving following GPIO pin from software
GPMC_A0(GPIO) == 0 NAND is selected (default)
NAND device (MT29F4G08AB) on these boards has:
- data-width=8bits
- blocksize=256KB
- pagesize=4KB
- oobsize=224 bytes
For above NAND device, ROM code expects the boot-loader to be flashed in BCH16
ECC scheme for NAND boot, So by default BCH16 ECC is enabled for AM43xx EVMs.
Signed-off-by: Pekon Gupta <pekon@ti.com>
---
board/ti/am43xx/board.c | 1 +
board/ti/am43xx/mux.c | 42 ++++++++++++++++++++++++++
boards.cfg | 2 +-
include/configs/am43xx_evm.h | 70 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 114 insertions(+), 1 deletion(-)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 054a452..2c3a290 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -487,6 +487,7 @@ void sdram_init(void)
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gpmc_init();
return 0;
}
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 50967e1..172adcd 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -73,6 +73,36 @@ static struct module_pin_mux gpio5_7_pin_mux[] = {
{-1},
};
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
+ {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
+ {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
+ {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
+ {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
+ {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
+ {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
+ {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
+#endif
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */
+ {-1},
+};
+#else
static struct module_pin_mux qspi_pin_mux[] = {
{OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
{OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
@@ -82,6 +112,7 @@ static struct module_pin_mux qspi_pin_mux[] = {
{OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
{-1},
};
+#endif
void enable_uart0_pin_mux(void)
{
@@ -97,12 +128,23 @@ void enable_board_pin_mux(void)
if (board_is_gpevm()) {
configure_module_pin_mux(gpio5_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_NAND)
+ configure_module_pin_mux(nand_pin_mux);
+#endif
} else if (board_is_sk()) {
configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_NAND)
+ pr_err("NAND flash is not present on this board\n");
+#else
configure_module_pin_mux(qspi_pin_mux);
+#endif
} else if (board_is_eposevm()) {
configure_module_pin_mux(rmii1_pin_mux);
+#if defined(CONFIG_NAND)
+ configure_module_pin_mux(nand_pin_mux);
+#else
configure_module_pin_mux(qspi_pin_mux);
+#endif
}
}
diff --git a/boards.cfg b/boards.cfg
index 8e2db82..52aeb7f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -274,7 +274,7 @@ Active arm armv7 am33xx ti am335x
Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=5,NAND Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
+Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1,NAND Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 am33xx ti am43xx am43xx_evm_qspiboot am43xx_evm:SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org>
Active arm armv7 am33xx ti ti816x ti816x_evm - -
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 974ce98..22c9019 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -263,4 +263,74 @@
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SYS_RX_ETH_BUFFER 64
+/* NAND support */
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_PAGE_SIZE 4096
+#define CONFIG_SYS_NAND_OOBSIZE 224
+#define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/* NAND: driver related configs */
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
+ 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
+ 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
+ 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+ 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
+ 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
+ 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+ 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
+ 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
+ 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
+ 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
+ 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
+ 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
+ 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
+ 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
+ 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
+ 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
+ }
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 26
+#define MTDIDS_DEFAULT "nand0=nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
+ "256k(NAND.SPL)," \
+ "256k(NAND.SPL.backup1)," \
+ "256k(NAND.SPL.backup2)," \
+ "256k(NAND.SPL.backup3)," \
+ "512k(NAND.u-boot-spl-os)," \
+ "1m(NAND.u-boot)," \
+ "256k(NAND.u-boot-env)," \
+ "256k(NAND.u-boot-env.backup1)," \
+ "7m(NAND.kernel)," \
+ "-(NAND.rootfs)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000
+#define CONFIG_ENV_OFFSET 0x00280000
+#define CONFIG_ENV_OFFSET_REDUND 0x002c0000
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+/* NAND: SPL related configs */
+#if defined(CONFIG_SPL_NAND_SUPPORT)
+ /* NAND: SPL falcon mode configs */
+ #ifdef CONFIG_SPL_OS_BOOT
+ #undef CONFIG_SPL_OS_BOOT
+ #define CONFIG_CMD_SPL_NAND_OFS 0x00100000 /* os parameters */
+ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */
+ #define CONFIG_CMD_SPL_WRITE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+ #endif
+#endif
+#endif /* !CONFIG_NAND */
+
#endif /* __CONFIG_AM43XX_EVM_H */
--
1.8.5.1.163.gd7aced9
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH v1 7/7] board/ti/dra7xx: add support for parallel NAND
2014-07-04 19:05 [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Pekon Gupta
` (5 preceding siblings ...)
2014-07-04 19:05 ` [U-Boot] [PATCH v1 6/7] board/ti/am43xx: add support " Pekon Gupta
@ 2014-07-04 19:05 ` Pekon Gupta
2014-07-16 20:20 ` Tom Rini
2014-07-06 7:35 ` [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Igor Grinberg
7 siblings, 1 reply; 20+ messages in thread
From: Pekon Gupta @ 2014-07-04 19:05 UTC (permalink / raw)
To: u-boot
This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
chip-select present on DRA7xx EVM.
On this board, GPMC_WPN and NAND_BOOTn are controlled by DIP switch,
So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH
Signed-off-by: Pekon Gupta <pekon@ti.com>
---
board/ti/dra7xx/mux_data.h | 30 +++++++++++++++++++++++
boards.cfg | 2 +-
include/configs/dra7xx_evm.h | 58 +++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 38de9d5..697e9e4 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -51,6 +51,35 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{RGMII0_RXD2, (IEN | M0) },
{RGMII0_RXD1, (IEN | M0) },
{RGMII0_RXD0, (IEN | M0) },
+#ifdef CONFIG_NAND
+ /* NAND / NOR pin-mux */
+ {GPMC_AD0 , M0 | IEN | PDIS}, /* AD0 */
+ {GPMC_AD1 , M0 | IEN | PDIS}, /* AD1 */
+ {GPMC_AD2 , M0 | IEN | PDIS}, /* AD2 */
+ {GPMC_AD3 , M0 | IEN | PDIS}, /* AD3 */
+ {GPMC_AD4 , M0 | IEN | PDIS}, /* AD4 */
+ {GPMC_AD5 , M0 | IEN | PDIS}, /* AD5 */
+ {GPMC_AD6 , M0 | IEN | PDIS}, /* AD6 */
+ {GPMC_AD7 , M0 | IEN | PDIS}, /* AD7 */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ {GPMC_AD8 , M0 | IEN | PDIS}, /* AD8 */
+ {GPMC_AD9 , M0 | IEN | PDIS}, /* AD9 */
+ {GPMC_AD10, M0 | IEN | PDIS}, /* AD10 */
+ {GPMC_AD11, M0 | IEN | PDIS}, /* AD11 */
+ {GPMC_AD12, M0 | IEN | PDIS}, /* AD12 */
+ {GPMC_AD13, M0 | IEN | PDIS}, /* AD13 */
+ {GPMC_AD14, M0 | IEN | PDIS}, /* AD14 */
+ {GPMC_AD15, M0 | IEN | PDIS}, /* AD15 */
+#endif
+ {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* chip-select */
+ {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* Addr latch */
+ {GPMC_OEN_REN, M0 | IDIS | PEN | PTD}, /* Read enable */
+ {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* Write enable_n */
+ {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* Byte/Column En */
+ {GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* Wait/Ready */
+ /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
+#else
+ /* QSPI pin-mux */
{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
@@ -61,6 +90,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
{GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
{GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
+#endif /* CONFIG_NAND */
{USB2_DRVVBUS, (M0 | IEN | FSC) },
};
#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/boards.cfg b/boards.cfg
index 52aeb7f..1cc0e94 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -361,7 +361,7 @@ Active arm armv7 omap4 gumstix duovero
Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com>
Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com>
Active arm armv7 omap5 compulab cm_t54 cm_t54 - Dmitry Lifshitz <lifshitz@compulab.co.il>
-Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
+Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1,NAND Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 omap5 ti dra7xx dra7xx_evm_qspiboot dra7xx_evm:CONS_INDEX=1,QSPI_BOOT Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 8d0a0eb..9e6a565 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -14,7 +14,7 @@
#define CONFIG_DRA7XX
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_NAND)
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
@@ -143,4 +143,60 @@
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
+/* NAND support */
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/* NAND: driver related configs */
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+#define MTDIDS_DEFAULT "nand0=nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
+ "128k(NAND.SPL)," \
+ "128k(NAND.SPL.backup1)," \
+ "128k(NAND.SPL.backup2)," \
+ "128k(NAND.SPL.backup3)," \
+ "256k(NAND.u-boot-spl-os)," \
+ "1m(NAND.u-boot)," \
+ "128k(NAND.u-boot-env)," \
+ "128k(NAND.u-boot-env.backup1)," \
+ "8m(NAND.kernel)," \
+ "-(NAND.rootfs)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
+#define CONFIG_ENV_OFFSET 0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_SIZE (128 * 1024)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+/* NAND: SPL related configs */
+#if defined(CONFIG_SPL_NAND_SUPPORT)
+ /* NAND: SPL falcon mode configs */
+ #ifdef CONFIG_SPL_OS_BOOT
+ #define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os-boot params*/
+ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
+ #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+ #endif
+#endif
+#endif /* !CONFIG_NAND */
+
#endif /* __CONFIG_DRA7XX_EVM_H */
--
1.8.5.1.163.gd7aced9
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support
2014-07-04 19:05 [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Pekon Gupta
` (6 preceding siblings ...)
2014-07-04 19:05 ` [U-Boot] [PATCH v1 7/7] board/ti/dra7xx: " Pekon Gupta
@ 2014-07-06 7:35 ` Igor Grinberg
2014-07-07 6:35 ` Gupta, Pekon
7 siblings, 1 reply; 20+ messages in thread
From: Igor Grinberg @ 2014-07-06 7:35 UTC (permalink / raw)
To: u-boot
Hi Pekon,
On 07/04/14 22:05, Pekon Gupta wrote:
> This patch series adds support for parallel NAND devices support connected via
> GPMC chip-select on various boards belonging to AM33xx and OMAPx platforms.
> This series also moves some board specific CONFIG_NAND_xx from generic files
> to individual files.
>
> Tested using: ./MAKEALL -s am33xx -s omap3 -s oamp4 -s omap5
> works fine except for am335x_boneblack_vboot
> build breaks for am335x_boneblack_vboot for un-related reasons
> u-boot/scripts/dtc-version.sh: line 17: dtc: command not found
This is obvious, apparently beagle bone black wants to use the DT for U-Boot
and you don't have dtc installed or it is not in your PATH.
>
>
> Pekon Gupta (7):
> TI: armv7: move board specific NAND configs out from ti_armv7_common.h
> and ti_am335x_common.h
> board/ti/am335x: add support for beaglebone NAND cape
> arm: lib: continue board_init_r even if valid flash device is not
> detected
> board/ti/am335x: add support for beaglebone NOR Cape
> board/ti/am335x: update configs for parallel NAND
> board/ti/am43xx: add support for parallel NAND
> board/ti/dra7xx: add support for parallel NAND
>
> arch/arm/lib/board.c | 7 +-
> board/ti/am335x/mux.c | 149 ++++++++++++++++++-------------------
> board/ti/am43xx/board.c | 1 +
> board/ti/am43xx/mux.c | 42 +++++++++++
> board/ti/dra7xx/mux_data.h | 30 ++++++++
> boards.cfg | 4 +-
> doc/README.nand | 12 +++
> include/configs/am335x_evm.h | 64 +++++++++-------
> include/configs/am43xx_evm.h | 70 +++++++++++++++++
> include/configs/cm_t335.h | 10 +++
> include/configs/dra7xx_evm.h | 58 ++++++++++++++-
> include/configs/omap3_beagle.h | 6 ++
> include/configs/omap3_igep00x0.h | 9 +++
> include/configs/omap3_overo.h | 8 ++
> include/configs/omap3_zoom1.h | 7 ++
> include/configs/pengwyn.h | 7 ++
> include/configs/ti_am335x_common.h | 4 -
> include/configs/ti_armv7_common.h | 9 ---
> 18 files changed, 369 insertions(+), 128 deletions(-)
>
--
Regards,
Igor.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support
2014-07-06 7:35 ` [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Igor Grinberg
@ 2014-07-07 6:35 ` Gupta, Pekon
0 siblings, 0 replies; 20+ messages in thread
From: Gupta, Pekon @ 2014-07-07 6:35 UTC (permalink / raw)
To: u-boot
>From: Igor Grinberg [mailto:grinberg at compulab.co.il]
>Hi Pekon,
>
>On 07/04/14 22:05, Pekon Gupta wrote:
>> This patch series adds support for parallel NAND devices support connected via
>> GPMC chip-select on various boards belonging to AM33xx and OMAPx platforms.
>> This series also moves some board specific CONFIG_NAND_xx from generic files
>> to individual files.
>>
>> Tested using: ./MAKEALL -s am33xx -s omap3 -s oamp4 -s omap5
>> works fine except for am335x_boneblack_vboot
>> build breaks for am335x_boneblack_vboot for un-related reasons
>> u-boot/scripts/dtc-version.sh: line 17: dtc: command not found
>
>This is obvious, apparently beagle bone black wants to use the DT for U-Boot
>and you don't have dtc installed or it is not in your PATH.
>
Yes, my bad. I was expecting dtc to be part of $UBOOT/scripts/... as in linux.
' am335x_boneblack_vboot' builds cleanly after I fix my $PATH to point to linux kernel dtc.
------------------
Configuring for am335x_boneblack_vboot - Board: am335x_evm, Options: SERIAL1,CONS_INDEX=1,EMMC_BOOT,ENABLE_VBOOT
text data bss dec hex filename
367622 12722 8693820 9074164 8a75f4 ./u-boot
72795 3084 198024 273903 42def ./spl/u-boot-spl
------------------
One request, as [PATCH 1/7] touches some non-TI board configs,
So some tested-by would help here to confirm that this patch isn't breaking anything.
with regards, pekon
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH v1 1/7] TI: armv7: move board specific NAND configs out from ti_armv7_common.h and ti_am335x_common.h
2014-07-04 19:05 ` [U-Boot] [PATCH v1 1/7] TI: armv7: move board specific NAND configs out from ti_armv7_common.h and ti_am335x_common.h Pekon Gupta
@ 2014-07-14 21:30 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2014-07-14 21:30 UTC (permalink / raw)
To: u-boot
On Sat, Jul 05, 2014 at 12:35:11AM +0530, Pekon Gupta wrote:
> This patch moves some board specific NAND configs:
> - FROM: generic config files like 'ti_armv7_common.h' and 'ti_am335x_common.h'
> - TO: individual board config files using these configs.
> So that each board can independently set the value as per its design.
I don't know. I intentionally merged these as they were all the same
based on the reference layout. Maybe it should be in the
ti_soc_common.h file rather than ti_armv7_common.h
> @@ -254,6 +256,11 @@
> #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
> #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
> #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
> +#ifdef CONFIG_SPL_OS_BOOT
> + #define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */
> + #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
> + #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
> +#endif
No leading spaces please.
> diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
> index 80976e7..12fceb7 100644
> --- a/include/configs/ti_am335x_common.h
> +++ b/include/configs/ti_am335x_common.h
> @@ -84,10 +84,6 @@
> #define CONFIG_BOARD_EARLY_INIT_F
> #endif
>
> -#ifdef CONFIG_NAND
> -#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
> -#endif
This highlights a problem, this _is_ a SoC feature not a board feature.
> diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
> index 6e0bf09..c901522 100644
> --- a/include/configs/ti_armv7_common.h
> +++ b/include/configs/ti_armv7_common.h
> @@ -110,7 +110,6 @@
> * access CS0 at is 0x8000000.
> */
> #ifdef CONFIG_NAND
> -#define CONFIG_NAND_OMAP_GPMC
> #ifndef CONFIG_SYS_NAND_BASE
> #define CONFIG_SYS_NAND_BASE 0x8000000
> #endif
And given keystone this should move to ti_{am335x,omap*}_common.h again
as a SoC feature.
--
Tom
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* [U-Boot] [PATCH v1 2/7] board/ti/am335x: add support for beaglebone NAND cape
2014-07-04 19:05 ` [U-Boot] [PATCH v1 2/7] board/ti/am335x: add support for beaglebone NAND cape Pekon Gupta
@ 2014-07-16 20:02 ` Tom Rini
2014-07-21 6:12 ` Gupta, Pekon
0 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2014-07-16 20:02 UTC (permalink / raw)
To: u-boot
On Sat, Jul 05, 2014 at 12:35:12AM +0530, Pekon Gupta wrote:
> Beaglebone Board can be connected to expansion boards to add devices to them.
> These expansion boards are called 'capes'. This patch adds support for
> following versions of Beaglebone(AM335x) NAND capes
> (a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
> (b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
> Further information and datasheets can be found at [1] and [2]
[snip]
> @@ -377,7 +391,11 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
> configure_module_pin_mux(i2c1_pin_mux);
> configure_module_pin_mux(mii1_pin_mux);
> configure_module_pin_mux(mmc0_pin_mux);
> +#if defined(CONFIG_NAND)
> + configure_module_pin_mux(nand_pin_mux);
> +#else
> configure_module_pin_mux(mmc1_pin_mux);
> +#endif
The above is the case for Beaglebone Black. Did you test the capes
there as well? AFAIK the eMMC makes it a bit more tricky (or
impossible?) to use some of the memory capes.
--
Tom
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* [U-Boot] [PATCH v1 4/7] board/ti/am335x: add support for beaglebone NOR Cape
2014-07-04 19:05 ` [U-Boot] [PATCH v1 4/7] board/ti/am335x: add support for beaglebone NOR Cape Pekon Gupta
@ 2014-07-16 20:06 ` Tom Rini
2014-07-21 10:27 ` Gupta, Pekon
0 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2014-07-16 20:06 UTC (permalink / raw)
To: u-boot
On Sat, Jul 05, 2014 at 12:35:14AM +0530, Pekon Gupta wrote:
> This patch updates pin-mux for beaglebone NOR cape [1]
> This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.
>
> On Beaglebone, GPMC chip-select-0 is shared by both NAND and NOR capes,
> so only one of them can be enabled at a time from board profile configs.
>
> [1] http://elinux.org/Beagleboardtoys:BeagleBone_128Mb_16-Bit_NOR_Module
[snip]
> @@ -200,73 +200,46 @@ static struct module_pin_mux nand_pin_mux[] = {
> {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
> {-1},
> };
> -#endif
> -#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
> +#elif defined(CONFIG_NOR)
> static struct module_pin_mux bone_norcape_pin_mux[] = {
> - {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
It _looks_ like this is jsut whitespace only. Since that doesn't match
the rest of the file, please don't do that.
[snip]
> #endif
>
> #if defined(CONFIG_NOR_BOOT)
> -static struct module_pin_mux norboot_pin_mux[] = {
> - {OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
> - {OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
> - {OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
> - {OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
> - {OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
> - {OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
> - {OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
> - {OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
> - {OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
> - {-1},
> -};
> -
> void enable_norboot_pin_mux(void)
> {
> - configure_module_pin_mux(norboot_pin_mux);
> + configure_module_pin_mux(bone_norcape_pin_mux);
Did you boot test this? The system requirements here are a bit strict
and I don't know if we can just do what you're doing here...
--
Tom
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* [U-Boot] [PATCH v1 3/7] arm: lib: continue board_init_r even if valid flash device is not detected
2014-07-04 19:05 ` [U-Boot] [PATCH v1 3/7] arm: lib: continue board_init_r even if valid flash device is not detected Pekon Gupta
@ 2014-07-16 20:07 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2014-07-16 20:07 UTC (permalink / raw)
To: u-boot
On Sat, Jul 05, 2014 at 12:35:13AM +0530, Pekon Gupta wrote:
> Most platforms have fall-back boot sources, if their primary boot fails.
> This patch allows board_init to continue scanning through other secondary boot
> sources like NAND, MMC, etc if valid FLASH device is not detected.
>
> Signed-off-by: Pekon Gupta <pekon@ti.com>
> ---
> arch/arm/lib/board.c | 7 +------
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
> index 76adaf3..413ee60 100644
> --- a/arch/arm/lib/board.c
> +++ b/arch/arm/lib/board.c
> @@ -460,10 +460,6 @@ void board_init_f(ulong bootflag)
> memcpy(id, (void *)gd, sizeof(gd_t));
> }
>
> -#if !defined(CONFIG_SYS_NO_FLASH)
> -static char *failed = "*** failed ***\n";
> -#endif
> -
> /*
> * Tell if it's OK to load the environment early in boot.
> *
> @@ -574,8 +570,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
> print_size(flash_size, "\n");
> # endif /* CONFIG_SYS_FLASH_CHECKSUM */
> } else {
> - puts(failed);
> - hang();
> + puts("unable to detect valid flash device\n");
> }
> #endif
Albert?
--
Tom
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* [U-Boot] [PATCH v1 6/7] board/ti/am43xx: add support for parallel NAND
2014-07-04 19:05 ` [U-Boot] [PATCH v1 6/7] board/ti/am43xx: add support " Pekon Gupta
@ 2014-07-16 20:14 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2014-07-16 20:14 UTC (permalink / raw)
To: u-boot
On Sat, Jul 05, 2014 at 12:35:16AM +0530, Pekon Gupta wrote:
> This patch adds support for NAND device connected to GPMC chip-select on
> following AM43xx EVM boards.
[snip]
> diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
> index 50967e1..172adcd 100644
> --- a/board/ti/am43xx/mux.c
> +++ b/board/ti/am43xx/mux.c
[snip]
> @@ -97,12 +128,23 @@ void enable_board_pin_mux(void)
> if (board_is_gpevm()) {
> configure_module_pin_mux(gpio5_7_pin_mux);
> configure_module_pin_mux(rgmii1_pin_mux);
> +#if defined(CONFIG_NAND)
> + configure_module_pin_mux(nand_pin_mux);
> +#endif
> } else if (board_is_sk()) {
> configure_module_pin_mux(rgmii1_pin_mux);
> +#if defined(CONFIG_NAND)
> + pr_err("NAND flash is not present on this board\n");
> +#else
> configure_module_pin_mux(qspi_pin_mux);
> +#endif
No, this breaks EVM-SK booting now in the normal case.
> diff --git a/boards.cfg b/boards.cfg
> index 8e2db82..52aeb7f 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -274,7 +274,7 @@ Active arm armv7 am33xx ti am335x
> Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=5,NAND Tom Rini <trini@ti.com>
> Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini <trini@ti.com>
> Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com>
> -Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
> +Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1,NAND Lokesh Vutla <lokeshvutla@ti.com>
> Active arm armv7 am33xx ti am43xx am43xx_evm_qspiboot am43xx_evm:SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT Lokesh Vutla <lokeshvutla@ti.com>
> Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org>
> Active arm armv7 am33xx ti ti816x ti816x_evm - -
I don't like this. We're making the normal build only work on boards
with NAND, and defaulting to NAND being there, which is not the most
common case.
> diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
> index 974ce98..22c9019 100644
> --- a/include/configs/am43xx_evm.h
> +++ b/include/configs/am43xx_evm.h
[snip]
> +#undef CONFIG_ENV_IS_NOWHERE
> +#define CONFIG_ENV_IS_IN_NAND
NAK. I'd like to see us default to environment being a file in the FAT
filesystem on SD card and specific boot builds going elsewhere
(_qspiboot in QSPI, adding in a _nand build that assumes / requires
NAND, puts env there).
> +/* NAND: SPL related configs */
> +#if defined(CONFIG_SPL_NAND_SUPPORT)
> + /* NAND: SPL falcon mode configs */
> + #ifdef CONFIG_SPL_OS_BOOT
> + #undef CONFIG_SPL_OS_BOOT
> + #define CONFIG_CMD_SPL_NAND_OFS 0x00100000 /* os parameters */
> + #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */
> + #define CONFIG_CMD_SPL_WRITE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
> + #endif
> +#endif
> +#endif /* !CONFIG_NAND */
No extra spacing, thanks.
--
Tom
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* [U-Boot] [PATCH v1 7/7] board/ti/dra7xx: add support for parallel NAND
2014-07-04 19:05 ` [U-Boot] [PATCH v1 7/7] board/ti/dra7xx: " Pekon Gupta
@ 2014-07-16 20:20 ` Tom Rini
2014-07-17 10:59 ` Gupta, Pekon
0 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2014-07-16 20:20 UTC (permalink / raw)
To: u-boot
On Sat, Jul 05, 2014 at 12:35:17AM +0530, Pekon Gupta wrote:
> This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
> chip-select present on DRA7xx EVM.
> On this board, GPMC_WPN and NAND_BOOTn are controlled by DIP switch,
> So following board settings are required for NAND device detection:
> SW5.9 (GPMC_WPN) = LOW
> SW5.1 (NAND_BOOTn) = HIGH
First, again, I don't like moving towards NAND being the default assumed
present storage and making QSPI harder to use. Second, I forgot about
this earlier but for the record and per later emails, we should just use
CONFIG_CMD_NAND rather than CONFIG_NAND.
> index 8d0a0eb..9e6a565 100644
> --- a/include/configs/dra7xx_evm.h
> +++ b/include/configs/dra7xx_evm.h
> @@ -14,7 +14,7 @@
>
> #define CONFIG_DRA7XX
>
> -#ifndef CONFIG_QSPI_BOOT
> +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_NAND)
> /* MMC ENV related defines */
> #define CONFIG_ENV_IS_IN_MMC
We want to keep the default env location to be on the eMMC.
> +/* NAND: SPL related configs */
> +#if defined(CONFIG_SPL_NAND_SUPPORT)
> + /* NAND: SPL falcon mode configs */
> + #ifdef CONFIG_SPL_OS_BOOT
> + #define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os-boot params*/
> + #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
> + #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
> + #endif
> +#endif
No leading spaces.
Thanks.
--
Tom
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* [U-Boot] [PATCH v1 7/7] board/ti/dra7xx: add support for parallel NAND
2014-07-16 20:20 ` Tom Rini
@ 2014-07-17 10:59 ` Gupta, Pekon
2014-07-17 12:57 ` Tom Rini
0 siblings, 1 reply; 20+ messages in thread
From: Gupta, Pekon @ 2014-07-17 10:59 UTC (permalink / raw)
To: u-boot
>From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Rini, Tom
>>On Sat, Jul 05, 2014 at 12:35:17AM +0530, Pekon Gupta wrote:
>
>> This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
>> chip-select present on DRA7xx EVM.
>> On this board, GPMC_WPN and NAND_BOOTn are controlled by DIP switch,
>> So following board settings are required for NAND device detection:
>> SW5.9 (GPMC_WPN) = LOW
>> SW5.1 (NAND_BOOTn) = HIGH
>
>First, again, I don't like moving towards NAND being the default assumed
>present storage and making QSPI harder to use. Second, I forgot about
>this earlier but for the record and per later emails, we should just use
>CONFIG_CMD_NAND rather than CONFIG_NAND.
>
All your feedbacks taken, except below one which is bit trivial ..
Converting CONFIG_NAND to CONFIG_CMD_NAND need review because:
(1) CONFIG_NAND has spread to so many files, and is also part of
include/configs/ti_armv7_common.h
arch/arm/cpu/armv7/omap-common/mem.c
And many more places..
(2) CONFIG_CMD_NAND is not synonymous with other CONFIG_xx which
used for enabling complete subsystem like CONFIG_NOR, CONFIG_MMC.
So, for now I'll continue using CONFIG_NAND, and may be later if
CONFIG_NAND needs to be deprecated, then it can come as separate
patch series. Hope that is fine?
with regards, pekon
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH v1 7/7] board/ti/dra7xx: add support for parallel NAND
2014-07-17 10:59 ` Gupta, Pekon
@ 2014-07-17 12:57 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2014-07-17 12:57 UTC (permalink / raw)
To: u-boot
On Thu, Jul 17, 2014 at 10:59:58AM +0000, Gupta, Pekon wrote:
> >From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Rini, Tom
> >>On Sat, Jul 05, 2014 at 12:35:17AM +0530, Pekon Gupta wrote:
> >
> >> This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
> >> chip-select present on DRA7xx EVM.
> >> On this board, GPMC_WPN and NAND_BOOTn are controlled by DIP switch,
> >> So following board settings are required for NAND device detection:
> >> SW5.9 (GPMC_WPN) = LOW
> >> SW5.1 (NAND_BOOTn) = HIGH
> >
> >First, again, I don't like moving towards NAND being the default assumed
> >present storage and making QSPI harder to use. Second, I forgot about
> >this earlier but for the record and per later emails, we should just use
> >CONFIG_CMD_NAND rather than CONFIG_NAND.
> >
> All your feedbacks taken, except below one which is bit trivial ..
>
> Converting CONFIG_NAND to CONFIG_CMD_NAND need review because:
> (1) CONFIG_NAND has spread to so many files, and is also part of
> include/configs/ti_armv7_common.h
> arch/arm/cpu/armv7/omap-common/mem.c
> And many more places..
>
> (2) CONFIG_CMD_NAND is not synonymous with other CONFIG_xx which
> used for enabling complete subsystem like CONFIG_NOR, CONFIG_MMC.
>
> So, for now I'll continue using CONFIG_NAND, and may be later if
> CONFIG_NAND needs to be deprecated, then it can come as separate
> patch series. Hope that is fine?
OK, I can live with that for now, thanks.
--
Tom
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* [U-Boot] [PATCH v1 2/7] board/ti/am335x: add support for beaglebone NAND cape
2014-07-16 20:02 ` Tom Rini
@ 2014-07-21 6:12 ` Gupta, Pekon
0 siblings, 0 replies; 20+ messages in thread
From: Gupta, Pekon @ 2014-07-21 6:12 UTC (permalink / raw)
To: u-boot
>From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Rini, Tom
>>On Sat, Jul 05, 2014 at 12:35:12AM +0530, Pekon Gupta wrote:
>> Beaglebone Board can be connected to expansion boards to add devices to them.
>> These expansion boards are called 'capes'. This patch adds support for
>> following versions of Beaglebone(AM335x) NAND capes
>> (a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
>> (b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
>> Further information and datasheets can be found at [1] and [2]
>[snip]
>> @@ -377,7 +391,11 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
>> configure_module_pin_mux(i2c1_pin_mux);
>> configure_module_pin_mux(mii1_pin_mux);
>> configure_module_pin_mux(mmc0_pin_mux);
>> +#if defined(CONFIG_NAND)
>> + configure_module_pin_mux(nand_pin_mux);
>> +#else
>> configure_module_pin_mux(mmc1_pin_mux);
>> +#endif
>
>The above is the case for Beaglebone Black. Did you test the capes
>there as well? AFAIK the eMMC makes it a bit more tricky (or
>impossible?) to use some of the memory capes.
>
Yes, slightly tricky, but not impossible :-)
On Beaglebone all storage devices (NAND, NOR and eMMC) share GPMC pins.
So this patch gives priority based on configs enabled in board-profile:
#ifdef CONFIG_NAND
/* define NAND pin-mux */
#elseif CONFIG_NOR
/* configure NOR pin-mux */
#else
/* config eMMC pin-mux (default, if no NAND | NOR cape is present) */
#endif
Please refer to following log from beaglebone Black booting from NAND.
U-boot was flashed on NAND using following commands:
/* Flash MLO to NAND */
fatload mmc 0 0x82000000 mlo
nand write 0x82000000 0x0 0x20000
/* Flash u-boot.img to NAND */
fatload mmc 0 0x82000000 u-boot.img
nand write 0x82000000 0xc0000 0x80000
-----------------
U-Boot 2014.07-00013-g838a657-dirty (Jul 21 2014 - 10:27:34)
I2C: ready
DRAM: 512 MiB
NAND: 512 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Warning - bad CRC, using default environment
Net: <ethaddr> not set. Validating first E-fuse MAC
cpsw, usb_ether
Hit any key to stop autoboot: 1 \b\b\b 0
U-Boot#
------------------
*IMPORTANT NOTE*
As Beaglebone board shares the same config as AM335x EVM, so following
changes are required in addition to this patch for Beaglebone NAND cape.
Therefore above image has a 'dirty commit'.
(1) Enable NAND in am335x_beaglebone board profile
(2) Add CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config because:
- AM335x EVM has NAND device with datawidth=8, whereas
- Beaglebone NAND cape has NAND device with data-width=16
diff --git a/boards.cfg b/boards.cfg
-Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL
+Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
with regards, pekon
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH v1 4/7] board/ti/am335x: add support for beaglebone NOR Cape
2014-07-16 20:06 ` Tom Rini
@ 2014-07-21 10:27 ` Gupta, Pekon
0 siblings, 0 replies; 20+ messages in thread
From: Gupta, Pekon @ 2014-07-21 10:27 UTC (permalink / raw)
To: u-boot
>From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Rini, Tom
>>On Sat, Jul 05, 2014 at 12:35:14AM +0530, Pekon Gupta wrote:
>
>> This patch updates pin-mux for beaglebone NOR cape [1]
>> This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.
>>
>> On Beaglebone, GPMC chip-select-0 is shared by both NAND and NOR capes,
>> so only one of them can be enabled at a time from board profile configs.
>>
>> [1] http://elinux.org/Beagleboardtoys:BeagleBone_128Mb_16-Bit_NOR_Module
>[snip]
>> @@ -200,73 +200,46 @@ static struct module_pin_mux nand_pin_mux[] = {
>> {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
>> {-1},
>> };
>> -#endif
>> -#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
>> +#elif defined(CONFIG_NOR)
>> static struct module_pin_mux bone_norcape_pin_mux[] = {
>> - {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
>
>It _looks_ like this is jsut whitespace only. Since that doesn't match
>the rest of the file, please don't do that.
>
Will be fixed in next version of this patch.
>[snip]
>> #endif
>>
>> #if defined(CONFIG_NOR_BOOT)
>> -static struct module_pin_mux norboot_pin_mux[] = {
>> - {OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
>> - {OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
>> - {OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
>> - {OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
>> - {OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
>> - {OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
>> - {OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
>> - {OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
>> - {OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
>> - {-1},
>> -};
>> -
>> void enable_norboot_pin_mux(void)
>> {
>> - configure_module_pin_mux(norboot_pin_mux);
>> + configure_module_pin_mux(bone_norcape_pin_mux);
>
>Did you boot test this? The system requirements here are a bit strict
>and I don't know if we can just do what you're doing here...
>
Yes, this one is also tested on Beaglebone-Black with following change in
boards.cfg to enable NOR on Beaglebone-Black
diff --git a/boards.cfg b/boards.cfg
-Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CO
+Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CO
---------------------
U-Boot SPL 2014.07-00012-g0e5512a-dirty (Jul 21 2014 - 15:38:26)
reading u-boot.img
reading u-boot.img
U-Boot 2014.07-00012-g0e5512a-dirty (Jul 21 2014 - 15:38:26)
I2C: ready
DRAM: 512 MiB
Flash: 16 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Using default environment
Net: <ethaddr> not set. Validating first E-fuse MAC
cpsw, usb_ether
Hit any key to stop autoboot: 1 \b\b\b 0
U-Boot#
U-Boot# flinfo
Bank # 1: CFI conformant flash (16 x 16) Size: 16 MB in 128 Sectors
AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x227E2100
Advanced Sector Protection (PPB) enabled
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 1 ms, buffer size: 64 bytes
Sector Start Addresses:
08000000 RO 08020000 RO 08040000 RO 08060000 RO 08080000 RO
080A0000 RO 080C0000 RO 080E0000 RO 08100000 RO 08120000 RO
...
08E60000 RO 08E80000 RO 08EA0000 RO 08EC0000 RO 08EE0000 RO
08F00000 RO 08F20000 RO 08F40000 RO 08F60000 RO 08F80000 RO
08FA0000 RO 08FC0000 RO 08FE0000 RO
U-Boot#
---------------------
with regards, pekon
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2014-07-21 10:27 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-07-04 19:05 [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Pekon Gupta
2014-07-04 19:05 ` [U-Boot] [PATCH v1 1/7] TI: armv7: move board specific NAND configs out from ti_armv7_common.h and ti_am335x_common.h Pekon Gupta
2014-07-14 21:30 ` Tom Rini
2014-07-04 19:05 ` [U-Boot] [PATCH v1 2/7] board/ti/am335x: add support for beaglebone NAND cape Pekon Gupta
2014-07-16 20:02 ` Tom Rini
2014-07-21 6:12 ` Gupta, Pekon
2014-07-04 19:05 ` [U-Boot] [PATCH v1 3/7] arm: lib: continue board_init_r even if valid flash device is not detected Pekon Gupta
2014-07-16 20:07 ` Tom Rini
2014-07-04 19:05 ` [U-Boot] [PATCH v1 4/7] board/ti/am335x: add support for beaglebone NOR Cape Pekon Gupta
2014-07-16 20:06 ` Tom Rini
2014-07-21 10:27 ` Gupta, Pekon
2014-07-04 19:05 ` [U-Boot] [PATCH v1 5/7] board/ti/am335x: update configs for parallel NAND Pekon Gupta
2014-07-04 19:05 ` [U-Boot] [PATCH v1 6/7] board/ti/am43xx: add support " Pekon Gupta
2014-07-16 20:14 ` Tom Rini
2014-07-04 19:05 ` [U-Boot] [PATCH v1 7/7] board/ti/dra7xx: " Pekon Gupta
2014-07-16 20:20 ` Tom Rini
2014-07-17 10:59 ` Gupta, Pekon
2014-07-17 12:57 ` Tom Rini
2014-07-06 7:35 ` [U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support Igor Grinberg
2014-07-07 6:35 ` Gupta, Pekon
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