From: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> To: Ben Skeggs <bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>, David Airlie <airlied-cv59FeDIM0c@public.gmane.org>, David Herrmann <dh.herrmann-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Lucas Stach <dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>, Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Maarten Lankhorst <maarten.lankhorst-Z7WLFzj8eWMS+FvcfC7Uqw@public.gmane.org> Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: [PATCH v4 3/6] drm/nouveau: introduce nv_device_is_cpu_coherent() Date: Tue, 8 Jul 2014 17:25:58 +0900 [thread overview] Message-ID: <1404807961-30530-4-git-send-email-acourbot@nvidia.com> (raw) In-Reply-To: <1404807961-30530-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Add a function allowing us to know whether a device is CPU-coherent, i.e. accesses performed by the CPU on GPU-mapped buffers will be immediately visible on the GPU side and vice-versa. For now, a device is considered to be coherent if it uses the PCI bus on a non-ARM architecture. Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- drivers/gpu/drm/nouveau/core/engine/device/base.c | 6 ++++++ drivers/gpu/drm/nouveau/core/include/core/device.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c index e4e9e64988fe..23c7061aac3c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c @@ -520,6 +520,12 @@ nv_device_get_irq(struct nouveau_device *device, bool stall) } } +bool +nv_device_is_cpu_coherent(struct nouveau_device *device) +{ + return (!IS_ENABLED(CONFIG_ARM) && nv_device_is_pci(device)); +} + static struct nouveau_oclass nouveau_device_oclass = { .handle = NV_ENGINE(DEVICE, 0x00), diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/core/include/core/device.h index a8a9a9cf16cb..1f9d5d87cf06 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/device.h +++ b/drivers/gpu/drm/nouveau/core/include/core/device.h @@ -171,4 +171,7 @@ nv_device_unmap_page(struct nouveau_device *device, dma_addr_t addr); int nv_device_get_irq(struct nouveau_device *device, bool stall); +bool +nv_device_is_cpu_coherent(struct nouveau_device *device); + #endif -- 2.0.0
WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Courbot <acourbot@nvidia.com> To: Ben Skeggs <bskeggs@redhat.com>, David Airlie <airlied@linux.ie>, David Herrmann <dh.herrmann@gmail.com>, Lucas Stach <dev@lynxeye.de>, Thierry Reding <thierry.reding@gmail.com>, Maarten Lankhorst <maarten.lankhorst@canonical.com> Cc: <nouveau@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <gnurou@gmail.com>, Alexandre Courbot <acourbot@nvidia.com> Subject: [PATCH v4 3/6] drm/nouveau: introduce nv_device_is_cpu_coherent() Date: Tue, 8 Jul 2014 17:25:58 +0900 [thread overview] Message-ID: <1404807961-30530-4-git-send-email-acourbot@nvidia.com> (raw) In-Reply-To: <1404807961-30530-1-git-send-email-acourbot@nvidia.com> Add a function allowing us to know whether a device is CPU-coherent, i.e. accesses performed by the CPU on GPU-mapped buffers will be immediately visible on the GPU side and vice-versa. For now, a device is considered to be coherent if it uses the PCI bus on a non-ARM architecture. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> --- drivers/gpu/drm/nouveau/core/engine/device/base.c | 6 ++++++ drivers/gpu/drm/nouveau/core/include/core/device.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c index e4e9e64988fe..23c7061aac3c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c @@ -520,6 +520,12 @@ nv_device_get_irq(struct nouveau_device *device, bool stall) } } +bool +nv_device_is_cpu_coherent(struct nouveau_device *device) +{ + return (!IS_ENABLED(CONFIG_ARM) && nv_device_is_pci(device)); +} + static struct nouveau_oclass nouveau_device_oclass = { .handle = NV_ENGINE(DEVICE, 0x00), diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/core/include/core/device.h index a8a9a9cf16cb..1f9d5d87cf06 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/device.h +++ b/drivers/gpu/drm/nouveau/core/include/core/device.h @@ -171,4 +171,7 @@ nv_device_unmap_page(struct nouveau_device *device, dma_addr_t addr); int nv_device_get_irq(struct nouveau_device *device, bool stall); +bool +nv_device_is_cpu_coherent(struct nouveau_device *device); + #endif -- 2.0.0
next prev parent reply other threads:[~2014-07-08 8:25 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-07-08 8:25 [PATCH v4 0/6] drm: nouveau: memory coherency on ARM Alexandre Courbot 2014-07-08 8:25 ` Alexandre Courbot [not found] ` <1404807961-30530-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2014-07-08 8:25 ` [PATCH v4 1/6] drm/ttm: expose CPU address of DMA-allocated pages Alexandre Courbot 2014-07-08 8:25 ` Alexandre Courbot 2014-07-08 8:25 ` [PATCH v4 2/6] drm/nouveau: map pages using DMA API on platform devices Alexandre Courbot 2014-07-08 8:25 ` Alexandre Courbot [not found] ` <1404807961-30530-3-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2014-07-10 12:58 ` Daniel Vetter 2014-07-10 12:58 ` [Nouveau] " Daniel Vetter [not found] ` <20140710125849.GF17271-dv86pmgwkMBes7Z6vYuT8azUEOm+Xw19@public.gmane.org> 2014-07-11 2:35 ` Alexandre Courbot 2014-07-11 2:35 ` Alexandre Courbot [not found] ` <53BF4D6B.70904-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2014-07-11 2:50 ` Ben Skeggs 2014-07-11 2:50 ` [Nouveau] " Ben Skeggs [not found] ` <CACAvsv7eER4VmbR81Ym=YE7fQZ9cNuJsb5372SAuSX+PQfYyrQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2014-07-11 2:57 ` Alexandre Courbot 2014-07-11 2:57 ` Alexandre Courbot 2014-07-11 9:53 ` Lucas Stach 2014-07-11 9:53 ` Lucas Stach 2014-07-11 7:38 ` Daniel Vetter 2014-07-11 7:38 ` Daniel Vetter 2014-07-08 8:25 ` Alexandre Courbot [this message] 2014-07-08 8:25 ` [PATCH v4 3/6] drm/nouveau: introduce nv_device_is_cpu_coherent() Alexandre Courbot 2014-07-08 8:25 ` [PATCH v4 4/6] drm/nouveau: synchronize BOs when required Alexandre Courbot 2014-07-08 8:25 ` Alexandre Courbot 2014-07-10 13:04 ` [Nouveau] " Daniel Vetter 2014-07-10 13:04 ` Daniel Vetter [not found] ` <20140710130449.GG17271-dv86pmgwkMBes7Z6vYuT8azUEOm+Xw19@public.gmane.org> 2014-07-11 2:40 ` Alexandre Courbot 2014-07-11 2:40 ` Alexandre Courbot [not found] ` <53BF4E9B.7090606-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2014-07-11 7:41 ` Daniel Vetter 2014-07-11 7:41 ` [Nouveau] " Daniel Vetter [not found] ` <20140711074138.GW17271-dv86pmgwkMBes7Z6vYuT8azUEOm+Xw19@public.gmane.org> 2014-07-11 9:35 ` Alexandre Courbot 2014-07-11 9:35 ` [Nouveau] " Alexandre Courbot 2014-07-08 8:26 ` [PATCH v4 5/6] drm/nouveau: implement explicitly coherent BOs Alexandre Courbot 2014-07-08 8:26 ` Alexandre Courbot 2014-07-08 8:26 ` [PATCH v4 6/6] drm/nouveau: allocate GPFIFOs and fences coherently Alexandre Courbot 2014-07-08 8:26 ` Alexandre Courbot
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