[PATCH 0/4] Add pgprot_writecombine function for MIPS

[PATCH 0/4] Add pgprot_writecombine function for MIPS

[Markos Chandras]

Hi,

This patchset implements the pgprot_writecombine function for MIPS

Markos Chandras (4):
  MIPS: pgtable-bits: Move the CCA bits out of the core's ifdef blocks
  MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores
  MIPS: cpu-probe: Set the write-combine CCA value on per core basis
  MIPS: pgtable.h: Implement the pgprot_writecombine function for MIPS

 arch/mips/include/asm/cpu-info.h     |  5 ++++
 arch/mips/include/asm/pgtable-bits.h | 44 ++++++++++++++++++++++++------------
 arch/mips/include/asm/pgtable.h      | 10 ++++++++
 arch/mips/kernel/cpu-probe.c         | 21 +++++++++++++++++
 4 files changed, 65 insertions(+), 15 deletions(-)

-- 
2.0.0

[PATCH 0/4] Add pgprot_writecombine function for MIPS

[Markos Chandras]

Hi,

This patchset implements the pgprot_writecombine function for MIPS

Markos Chandras (4):
  MIPS: pgtable-bits: Move the CCA bits out of the core's ifdef blocks
  MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores
  MIPS: cpu-probe: Set the write-combine CCA value on per core basis
  MIPS: pgtable.h: Implement the pgprot_writecombine function for MIPS

 arch/mips/include/asm/cpu-info.h     |  5 ++++
 arch/mips/include/asm/pgtable-bits.h | 44 ++++++++++++++++++++++++------------
 arch/mips/include/asm/pgtable.h      | 10 ++++++++
 arch/mips/kernel/cpu-probe.c         | 21 +++++++++++++++++
 4 files changed, 65 insertions(+), 15 deletions(-)

-- 
2.0.0

[PATCH 1/4] MIPS: pgtable-bits: Move the CCA bits out of the core's ifdef blocks

[Markos Chandras]

Define all the CCA bits outside the ifdef blocks for specific cores
but also allow cores to override them if necessary.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/include/asm/pgtable-bits.h | 41 ++++++++++++++++++++++--------------
 1 file changed, 25 insertions(+), 16 deletions(-)

diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index e592f3687d6f..011b0dcf306e 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -224,38 +224,47 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 
 #define _CACHE_CACHABLE_NONCOHERENT 0
+#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
 
 #elif defined(CONFIG_CPU_SB1)
 
 /* No penalty for being coherent on the SB1, so just
    use it for "noncoherent" spaces, too.  Shouldn't hurt. */
 
-#define _CACHE_UNCACHED		    (2<<_CACHE_SHIFT)
-#define _CACHE_CACHABLE_COW	    (5<<_CACHE_SHIFT)
 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
-#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
 
 #elif defined(CONFIG_CPU_LOONGSON3)
 
 /* Using COHERENT flag for NONCOHERENT doesn't hurt. */
 
-#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)  /* LOONGSON       */
 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
 #define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */
-#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* LOONGSON       */
 
-#else
-
-#define _CACHE_CACHABLE_NO_WA	    (0<<_CACHE_SHIFT)  /* R4600 only	  */
-#define _CACHE_CACHABLE_WA	    (1<<_CACHE_SHIFT)  /* R4600 only	  */
-#define _CACHE_UNCACHED		    (2<<_CACHE_SHIFT)  /* R4[0246]00	  */
-#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* R4[0246]00	  */
-#define _CACHE_CACHABLE_CE	    (4<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_CACHABLE_COW	    (5<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_CACHABLE_COHERENT    (5<<_CACHE_SHIFT)  /* MIPS32R2 CMP	  */
-#define _CACHE_CACHABLE_CUW	    (6<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* R10000 only	  */
+#endif
 
+#ifndef _CACHE_CACHABLE_NO_WA
+#define _CACHE_CACHABLE_NO_WA		(0<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_WA
+#define _CACHE_CACHABLE_WA		(1<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED
+#define _CACHE_UNCACHED			(2<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_NONCOHERENT
+#define _CACHE_CACHABLE_NONCOHERENT	(3<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CE
+#define _CACHE_CACHABLE_CE		(4<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_COW
+#define _CACHE_CACHABLE_COW		(5<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CUW
+#define _CACHE_CACHABLE_CUW		(6<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED_ACCELERATED
+#define _CACHE_UNCACHED_ACCELERATED	(7<<_CACHE_SHIFT)
 #endif
 
 #define __READABLE	(_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
-- 
2.0.0

[PATCH 1/4] MIPS: pgtable-bits: Move the CCA bits out of the core's ifdef blocks

[Markos Chandras]

Define all the CCA bits outside the ifdef blocks for specific cores
but also allow cores to override them if necessary.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/include/asm/pgtable-bits.h | 41 ++++++++++++++++++++++--------------
 1 file changed, 25 insertions(+), 16 deletions(-)

diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index e592f3687d6f..011b0dcf306e 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -224,38 +224,47 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 
 #define _CACHE_CACHABLE_NONCOHERENT 0
+#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
 
 #elif defined(CONFIG_CPU_SB1)
 
 /* No penalty for being coherent on the SB1, so just
    use it for "noncoherent" spaces, too.  Shouldn't hurt. */
 
-#define _CACHE_UNCACHED		    (2<<_CACHE_SHIFT)
-#define _CACHE_CACHABLE_COW	    (5<<_CACHE_SHIFT)
 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
-#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
 
 #elif defined(CONFIG_CPU_LOONGSON3)
 
 /* Using COHERENT flag for NONCOHERENT doesn't hurt. */
 
-#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)  /* LOONGSON       */
 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
 #define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */
-#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* LOONGSON       */
 
-#else
-
-#define _CACHE_CACHABLE_NO_WA	    (0<<_CACHE_SHIFT)  /* R4600 only	  */
-#define _CACHE_CACHABLE_WA	    (1<<_CACHE_SHIFT)  /* R4600 only	  */
-#define _CACHE_UNCACHED		    (2<<_CACHE_SHIFT)  /* R4[0246]00	  */
-#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* R4[0246]00	  */
-#define _CACHE_CACHABLE_CE	    (4<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_CACHABLE_COW	    (5<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_CACHABLE_COHERENT    (5<<_CACHE_SHIFT)  /* MIPS32R2 CMP	  */
-#define _CACHE_CACHABLE_CUW	    (6<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* R10000 only	  */
+#endif
 
+#ifndef _CACHE_CACHABLE_NO_WA
+#define _CACHE_CACHABLE_NO_WA		(0<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_WA
+#define _CACHE_CACHABLE_WA		(1<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED
+#define _CACHE_UNCACHED			(2<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_NONCOHERENT
+#define _CACHE_CACHABLE_NONCOHERENT	(3<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CE
+#define _CACHE_CACHABLE_CE		(4<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_COW
+#define _CACHE_CACHABLE_COW		(5<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CUW
+#define _CACHE_CACHABLE_CUW		(6<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED_ACCELERATED
+#define _CACHE_UNCACHED_ACCELERATED	(7<<_CACHE_SHIFT)
 #endif
 
 #define __READABLE	(_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
-- 
2.0.0

[PATCH 2/4] MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores

[Markos Chandras]

Ingenic uses the CCA:1 bit to achieve write-combine memory writes.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
As found in the following git repository
https://github.com/IngenicSemiconductor/KERNEL-WARRIOR/blob/master/arch/mips/include/asm/pgtable.h#L342
---
 arch/mips/include/asm/pgtable-bits.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 011b0dcf306e..e747bfa0be7e 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -240,6 +240,11 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
 #define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */
 
+#elif defined(CONFIG_MACH_JZ4740)
+
+/* Ingenic uses the WA bit to achieve write-combine memory writes */
+#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
+
 #endif
 
 #ifndef _CACHE_CACHABLE_NO_WA
-- 
2.0.0

[PATCH 2/4] MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores

[Markos Chandras]

Ingenic uses the CCA:1 bit to achieve write-combine memory writes.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
As found in the following git repository
https://github.com/IngenicSemiconductor/KERNEL-WARRIOR/blob/master/arch/mips/include/asm/pgtable.h#L342
---
 arch/mips/include/asm/pgtable-bits.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 011b0dcf306e..e747bfa0be7e 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -240,6 +240,11 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
 #define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */
 
+#elif defined(CONFIG_MACH_JZ4740)
+
+/* Ingenic uses the WA bit to achieve write-combine memory writes */
+#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
+
 #endif
 
 #ifndef _CACHE_CACHABLE_NO_WA
-- 
2.0.0

[PATCH 3/4] MIPS: cpu-probe: Set the write-combine CCA value on per core basis

[Markos Chandras]

Different cores use different CCA values to achieve write-combine
memory writes. For cores that do not support write-combine we
set the default value to CCA:2 (uncached, non-coherent) which is the
default value as set by the kernel.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/include/asm/cpu-info.h |  5 +++++
 arch/mips/kernel/cpu-probe.c     | 21 +++++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 47d5967ce7ef..7747bc7eafaa 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -78,6 +78,11 @@ struct cpuinfo_mips {
 #define NUM_WATCH_REGS 4
 	u16			watch_reg_masks[NUM_WATCH_REGS];
 	unsigned int		kscratch_mask; /* Usable KScratch mask. */
+	/*
+	 * Cache Coherency attribute for write-combine memory writes.
+	 * (shifted by _CACHE_SHIFT)
+	 */
+	unsigned int		writecombine;
 } __attribute__((aligned(SMP_CACHE_BYTES)));
 
 extern struct cpuinfo_mips cpu_data[];
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index d74f957c561e..f85c2c6670f5 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -27,6 +27,7 @@
 #include <asm/msa.h>
 #include <asm/watch.h>
 #include <asm/elf.h>
+#include <asm/pgtable-bits.h>
 #include <asm/spram.h>
 #include <asm/uaccess.h>
 
@@ -737,6 +738,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 			break;
 		case PRID_REV_LOONGSON3A:
 			c->cputype = CPU_LOONGSON3;
+			c->writecombine = _CACHE_UNCACHED_ACCELERATED;
 			__cpu_name[cpu] = "ICT Loongson-3";
 			set_elf_platform(cpu, "loongson3a");
 			break;
@@ -765,67 +767,83 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 
 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 {
+	c->writecombine = _CACHE_UNCACHED_ACCELERATED;
 	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_4KC:
 		c->cputype = CPU_4KC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 4Kc";
 		break;
 	case PRID_IMP_4KEC:
 	case PRID_IMP_4KECR2:
 		c->cputype = CPU_4KEC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 4KEc";
 		break;
 	case PRID_IMP_4KSC:
 	case PRID_IMP_4KSD:
 		c->cputype = CPU_4KSC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 4KSc";
 		break;
 	case PRID_IMP_5KC:
 		c->cputype = CPU_5KC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 5Kc";
 		break;
 	case PRID_IMP_5KE:
 		c->cputype = CPU_5KE;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 5KE";
 		break;
 	case PRID_IMP_20KC:
 		c->cputype = CPU_20KC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 20Kc";
 		break;
 	case PRID_IMP_24K:
 		c->cputype = CPU_24K;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 24Kc";
 		break;
 	case PRID_IMP_24KE:
 		c->cputype = CPU_24K;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 24KEc";
 		break;
 	case PRID_IMP_25KF:
 		c->cputype = CPU_25KF;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 25Kc";
 		break;
 	case PRID_IMP_34K:
 		c->cputype = CPU_34K;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 34Kc";
 		break;
 	case PRID_IMP_74K:
 		c->cputype = CPU_74K;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 74Kc";
 		break;
 	case PRID_IMP_M14KC:
 		c->cputype = CPU_M14KC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS M14Kc";
 		break;
 	case PRID_IMP_M14KEC:
 		c->cputype = CPU_M14KEC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS M14KEc";
 		break;
 	case PRID_IMP_1004K:
 		c->cputype = CPU_1004K;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 1004Kc";
 		break;
 	case PRID_IMP_1074K:
 		c->cputype = CPU_1074K;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 1074Kc";
 		break;
 	case PRID_IMP_INTERAPTIV_UP:
@@ -899,6 +917,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);
 
+	c->writecombine = _CACHE_UNCACHED_ACCELERATED;
 	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_SB1:
 		c->cputype = CPU_SB1;
@@ -1030,6 +1049,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_JZRISC:
 		c->cputype = CPU_JZRISC;
+		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
 		__cpu_name[cpu] = "Ingenic JZRISC";
 		break;
 	default:
@@ -1136,6 +1156,7 @@ void cpu_probe(void)
 	c->processor_id = PRID_IMP_UNKNOWN;
 	c->fpu_id	= FPIR_IMP_NONE;
 	c->cputype	= CPU_UNKNOWN;
+	c->writecombine = _CACHE_UNCACHED;
 
 	c->processor_id = read_c0_prid();
 	switch (c->processor_id & PRID_COMP_MASK) {
-- 
2.0.0

[PATCH 3/4] MIPS: cpu-probe: Set the write-combine CCA value on per core basis

[Markos Chandras]

Different cores use different CCA values to achieve write-combine
memory writes. For cores that do not support write-combine we
set the default value to CCA:2 (uncached, non-coherent) which is the
default value as set by the kernel.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/include/asm/cpu-info.h |  5 +++++
 arch/mips/kernel/cpu-probe.c     | 21 +++++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 47d5967ce7ef..7747bc7eafaa 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -78,6 +78,11 @@ struct cpuinfo_mips {
 #define NUM_WATCH_REGS 4
 	u16			watch_reg_masks[NUM_WATCH_REGS];
 	unsigned int		kscratch_mask; /* Usable KScratch mask. */
+	/*
+	 * Cache Coherency attribute for write-combine memory writes.
+	 * (shifted by _CACHE_SHIFT)
+	 */
+	unsigned int		writecombine;
 } __attribute__((aligned(SMP_CACHE_BYTES)));
 
 extern struct cpuinfo_mips cpu_data[];
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index d74f957c561e..f85c2c6670f5 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -27,6 +27,7 @@
 #include <asm/msa.h>
 #include <asm/watch.h>
 #include <asm/elf.h>
+#include <asm/pgtable-bits.h>
 #include <asm/spram.h>
 #include <asm/uaccess.h>
 
@@ -737,6 +738,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 			break;
 		case PRID_REV_LOONGSON3A:
 			c->cputype = CPU_LOONGSON3;
+			c->writecombine = _CACHE_UNCACHED_ACCELERATED;
 			__cpu_name[cpu] = "ICT Loongson-3";
 			set_elf_platform(cpu, "loongson3a");
 			break;
@@ -765,67 +767,83 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 
 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 {
+	c->writecombine = _CACHE_UNCACHED_ACCELERATED;
 	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_4KC:
 		c->cputype = CPU_4KC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 4Kc";
 		break;
 	case PRID_IMP_4KEC:
 	case PRID_IMP_4KECR2:
 		c->cputype = CPU_4KEC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 4KEc";
 		break;
 	case PRID_IMP_4KSC:
 	case PRID_IMP_4KSD:
 		c->cputype = CPU_4KSC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 4KSc";
 		break;
 	case PRID_IMP_5KC:
 		c->cputype = CPU_5KC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 5Kc";
 		break;
 	case PRID_IMP_5KE:
 		c->cputype = CPU_5KE;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 5KE";
 		break;
 	case PRID_IMP_20KC:
 		c->cputype = CPU_20KC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 20Kc";
 		break;
 	case PRID_IMP_24K:
 		c->cputype = CPU_24K;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 24Kc";
 		break;
 	case PRID_IMP_24KE:
 		c->cputype = CPU_24K;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 24KEc";
 		break;
 	case PRID_IMP_25KF:
 		c->cputype = CPU_25KF;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 25Kc";
 		break;
 	case PRID_IMP_34K:
 		c->cputype = CPU_34K;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 34Kc";
 		break;
 	case PRID_IMP_74K:
 		c->cputype = CPU_74K;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 74Kc";
 		break;
 	case PRID_IMP_M14KC:
 		c->cputype = CPU_M14KC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS M14Kc";
 		break;
 	case PRID_IMP_M14KEC:
 		c->cputype = CPU_M14KEC;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS M14KEc";
 		break;
 	case PRID_IMP_1004K:
 		c->cputype = CPU_1004K;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 1004Kc";
 		break;
 	case PRID_IMP_1074K:
 		c->cputype = CPU_1074K;
+		c->writecombine = _CACHE_UNCACHED;
 		__cpu_name[cpu] = "MIPS 1074Kc";
 		break;
 	case PRID_IMP_INTERAPTIV_UP:
@@ -899,6 +917,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);
 
+	c->writecombine = _CACHE_UNCACHED_ACCELERATED;
 	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_SB1:
 		c->cputype = CPU_SB1;
@@ -1030,6 +1049,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_JZRISC:
 		c->cputype = CPU_JZRISC;
+		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
 		__cpu_name[cpu] = "Ingenic JZRISC";
 		break;
 	default:
@@ -1136,6 +1156,7 @@ void cpu_probe(void)
 	c->processor_id = PRID_IMP_UNKNOWN;
 	c->fpu_id	= FPIR_IMP_NONE;
 	c->cputype	= CPU_UNKNOWN;
+	c->writecombine = _CACHE_UNCACHED;
 
 	c->processor_id = read_c0_prid();
 	switch (c->processor_id & PRID_COMP_MASK) {
-- 
2.0.0

[PATCH 4/4] MIPS: pgtable.h: Implement the pgprot_writecombine function for MIPS

[Markos Chandras]

Previously, the pgprot_writecombine function was simply defined
as pgprot_uncached in include/asm-generic/pgtable.h. This is not
optimal for cores that can actually do write-combine memory writes
so define this function to take into account the core's cache coherency
attribute to achieve such behavior.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/include/asm/pgtable.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 539ddd148bbb..08f82e99ea8f 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -338,6 +338,16 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
 	return __pgprot(prot);
 }
 
+static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
+{
+	unsigned long prot = pgprot_val(_prot);
+
+	/* cpu_data[0].writecombine is already shifted by _CACHE_SHIFT */
+	prot = (prot & ~_CACHE_MASK) | cpu_data[0].writecombine;
+
+	return __pgprot(prot);
+}
+
 /*
  * Conversion functions: convert a page and protection to a page entry,
  * and a page entry and page directory to the page they refer to.
-- 
2.0.0

[PATCH 4/4] MIPS: pgtable.h: Implement the pgprot_writecombine function for MIPS

[Markos Chandras]

Previously, the pgprot_writecombine function was simply defined
as pgprot_uncached in include/asm-generic/pgtable.h. This is not
optimal for cores that can actually do write-combine memory writes
so define this function to take into account the core's cache coherency
attribute to achieve such behavior.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/include/asm/pgtable.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 539ddd148bbb..08f82e99ea8f 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -338,6 +338,16 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
 	return __pgprot(prot);
 }
 
+static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
+{
+	unsigned long prot = pgprot_val(_prot);
+
+	/* cpu_data[0].writecombine is already shifted by _CACHE_SHIFT */
+	prot = (prot & ~_CACHE_MASK) | cpu_data[0].writecombine;
+
+	return __pgprot(prot);
+}
+
 /*
  * Conversion functions: convert a page and protection to a page entry,
  * and a page entry and page directory to the page they refer to.
-- 
2.0.0

Re: [PATCH 3/4] MIPS: cpu-probe: Set the write-combine CCA value on per core basis

[Florian Fainelli]

Hi Markos,

On 07/18/2014 02:51 AM, Markos Chandras wrote:
> Different cores use different CCA values to achieve write-combine
> memory writes. For cores that do not support write-combine we
> set the default value to CCA:2 (uncached, non-coherent) which is the
> default value as set by the kernel.
> 
> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> ---
[snip]
			break;
> @@ -765,67 +767,83 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
>  
>  static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
>  {
> +	c->writecombine = _CACHE_UNCACHED_ACCELERATED;

Why do we set this writecombine setting by default, when later we are
going to override writecombine on a per-cpu basic.

In the end, we have the following:

cpu_probe()
	c->writecombine = _CACHE_UNCACHED;

	cpu_probe_mips()
		c->writecombine = _CACHE_UNCACHED_ACCELERATED:
		... per-cpu case ...
		c->writecombine = _CACHE_UNCACHED;

Can't we just eliminate the various assignments in cpu_probe_mips() and
only override c->writecombine if _CACHE_UNCACHED is not suitable?


>  	switch (c->processor_id & PRID_IMP_MASK) {
>  	case PRID_IMP_4KC:
>  		c->cputype = CPU_4KC;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 4Kc";
>  		break;
>  	case PRID_IMP_4KEC:
>  	case PRID_IMP_4KECR2:
>  		c->cputype = CPU_4KEC;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 4KEc";
>  		break;
>  	case PRID_IMP_4KSC:
>  	case PRID_IMP_4KSD:
>  		c->cputype = CPU_4KSC;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 4KSc";
>  		break;
>  	case PRID_IMP_5KC:
>  		c->cputype = CPU_5KC;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 5Kc";
>  		break;
>  	case PRID_IMP_5KE:
>  		c->cputype = CPU_5KE;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 5KE";
>  		break;
>  	case PRID_IMP_20KC:
>  		c->cputype = CPU_20KC;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 20Kc";
>  		break;
>  	case PRID_IMP_24K:
>  		c->cputype = CPU_24K;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 24Kc";
>  		break;
>  	case PRID_IMP_24KE:
>  		c->cputype = CPU_24K;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 24KEc";
>  		break;
>  	case PRID_IMP_25KF:
>  		c->cputype = CPU_25KF;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 25Kc";
>  		break;
>  	case PRID_IMP_34K:
>  		c->cputype = CPU_34K;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 34Kc";
>  		break;
>  	case PRID_IMP_74K:
>  		c->cputype = CPU_74K;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 74Kc";
>  		break;
>  	case PRID_IMP_M14KC:
>  		c->cputype = CPU_M14KC;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS M14Kc";
>  		break;
>  	case PRID_IMP_M14KEC:
>  		c->cputype = CPU_M14KEC;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS M14KEc";
>  		break;
>  	case PRID_IMP_1004K:
>  		c->cputype = CPU_1004K;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 1004Kc";
>  		break;
>  	case PRID_IMP_1074K:
>  		c->cputype = CPU_1074K;
> +		c->writecombine = _CACHE_UNCACHED;
>  		__cpu_name[cpu] = "MIPS 1074Kc";
>  		break;
>  	case PRID_IMP_INTERAPTIV_UP:
> @@ -899,6 +917,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
>  {
>  	decode_configs(c);
>  
> +	c->writecombine = _CACHE_UNCACHED_ACCELERATED;
>  	switch (c->processor_id & PRID_IMP_MASK) {
>  	case PRID_IMP_SB1:
>  		c->cputype = CPU_SB1;
> @@ -1030,6 +1049,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
>  	switch (c->processor_id & PRID_IMP_MASK) {
>  	case PRID_IMP_JZRISC:
>  		c->cputype = CPU_JZRISC;
> +		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
>  		__cpu_name[cpu] = "Ingenic JZRISC";
>  		break;
>  	default:
> @@ -1136,6 +1156,7 @@ void cpu_probe(void)
>  	c->processor_id = PRID_IMP_UNKNOWN;
>  	c->fpu_id	= FPIR_IMP_NONE;
>  	c->cputype	= CPU_UNKNOWN;
> +	c->writecombine = _CACHE_UNCACHED;



>  
>  	c->processor_id = read_c0_prid();
>  	switch (c->processor_id & PRID_COMP_MASK) {
> 

Re: [PATCH 3/4] MIPS: cpu-probe: Set the write-combine CCA value on per core basis

[Markos Chandras]

Hi Florian,

On Mon, Aug 04, 2014 at 03:54:49PM -0700, Florian Fainelli wrote:
> Hi Markos,
> 
> On 07/18/2014 02:51 AM, Markos Chandras wrote:
> > Different cores use different CCA values to achieve write-combine
> > memory writes. For cores that do not support write-combine we
> > set the default value to CCA:2 (uncached, non-coherent) which is the
> > default value as set by the kernel.
> > 
> > Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> > ---
> [snip]
> 			break;
> > @@ -765,67 +767,83 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
> >  
> >  static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
> >  {
> > +	c->writecombine = _CACHE_UNCACHED_ACCELERATED;
> 
> Why do we set this writecombine setting by default, when later we are
> going to override writecombine on a per-cpu basic.
> 
> In the end, we have the following:
> 
> cpu_probe()
> 	c->writecombine = _CACHE_UNCACHED;
> 
> 	cpu_probe_mips()
> 		c->writecombine = _CACHE_UNCACHED_ACCELERATED:
> 		... per-cpu case ...
> 		c->writecombine = _CACHE_UNCACHED;
> 
> Can't we just eliminate the various assignments in cpu_probe_mips() and
> only override c->writecombine if _CACHE_UNCACHED is not suitable?
> 
The reason I did it like this, is that new cores (eg *Aptiv family) will use
_CACHE_UNCACHED_ACCELERATED and that's why it's the 'default' option for
the MIPS cores. _CACHE_UNCACHED is only suitable for old cores.
The way it is right now, allows us to not have to set this option whenever we
add support for a new core since it will inherit the default option.

-- 
markos

Re: [PATCH 3/4] MIPS: cpu-probe: Set the write-combine CCA value on per core basis

[Markos Chandras]

Hi Florian,

On Mon, Aug 04, 2014 at 03:54:49PM -0700, Florian Fainelli wrote:
> Hi Markos,
> 
> On 07/18/2014 02:51 AM, Markos Chandras wrote:
> > Different cores use different CCA values to achieve write-combine
> > memory writes. For cores that do not support write-combine we
> > set the default value to CCA:2 (uncached, non-coherent) which is the
> > default value as set by the kernel.
> > 
> > Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> > ---
> [snip]
> 			break;
> > @@ -765,67 +767,83 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
> >  
> >  static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
> >  {
> > +	c->writecombine = _CACHE_UNCACHED_ACCELERATED;
> 
> Why do we set this writecombine setting by default, when later we are
> going to override writecombine on a per-cpu basic.
> 
> In the end, we have the following:
> 
> cpu_probe()
> 	c->writecombine = _CACHE_UNCACHED;
> 
> 	cpu_probe_mips()
> 		c->writecombine = _CACHE_UNCACHED_ACCELERATED:
> 		... per-cpu case ...
> 		c->writecombine = _CACHE_UNCACHED;
> 
> Can't we just eliminate the various assignments in cpu_probe_mips() and
> only override c->writecombine if _CACHE_UNCACHED is not suitable?
> 
The reason I did it like this, is that new cores (eg *Aptiv family) will use
_CACHE_UNCACHED_ACCELERATED and that's why it's the 'default' option for
the MIPS cores. _CACHE_UNCACHED is only suitable for old cores.
The way it is right now, allows us to not have to set this option whenever we
add support for a new core since it will inherit the default option.

-- 
markos

Re: [PATCH 3/4] MIPS: cpu-probe: Set the write-combine CCA value on per core basis

[Florian Fainelli]

Hi Markos,

2014-08-12 0:23 GMT-07:00 Markos Chandras <markos.chandras@imgtec.com>:
> Hi Florian,
>
> On Mon, Aug 04, 2014 at 03:54:49PM -0700, Florian Fainelli wrote:
>> Hi Markos,
>>
>> On 07/18/2014 02:51 AM, Markos Chandras wrote:
>> > Different cores use different CCA values to achieve write-combine
>> > memory writes. For cores that do not support write-combine we
>> > set the default value to CCA:2 (uncached, non-coherent) which is the
>> > default value as set by the kernel.
>> >
>> > Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>> > ---
>> [snip]
>>                       break;
>> > @@ -765,67 +767,83 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
>> >
>> >  static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
>> >  {
>> > +   c->writecombine = _CACHE_UNCACHED_ACCELERATED;
>>
>> Why do we set this writecombine setting by default, when later we are
>> going to override writecombine on a per-cpu basic.
>>
>> In the end, we have the following:
>>
>> cpu_probe()
>>       c->writecombine = _CACHE_UNCACHED;
>>
>>       cpu_probe_mips()
>>               c->writecombine = _CACHE_UNCACHED_ACCELERATED:
>>               ... per-cpu case ...
>>               c->writecombine = _CACHE_UNCACHED;
>>
>> Can't we just eliminate the various assignments in cpu_probe_mips() and
>> only override c->writecombine if _CACHE_UNCACHED is not suitable?
>>
> The reason I did it like this, is that new cores (eg *Aptiv family) will use
> _CACHE_UNCACHED_ACCELERATED and that's why it's the 'default' option for
> the MIPS cores. _CACHE_UNCACHED is only suitable for old cores.
> The way it is right now, allows us to not have to set this option whenever we
> add support for a new core since it will inherit the default option.

Ok, that makes sense, although we currently have more _CACHE_UNCACHED
platforms supported than _CACHE_UNCACHED_ACCELERATED, so maybe once
you reach a critical number of Aptiv cores or with similar caching
settings, we can reverse the tendency by then? This is not a strong
objection, I was just looking at a way to minimize the changes.
-- 
Florian

Re: [PATCH 0/4] Add pgprot_writecombine function for MIPS

[Ralf Baechle]

On Fri, Jul 18, 2014 at 10:51:29AM +0100, Markos Chandras wrote:

> This patchset implements the pgprot_writecombine function for MIPS
> 
> Markos Chandras (4):
>   MIPS: pgtable-bits: Move the CCA bits out of the core's ifdef blocks
>   MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores
>   MIPS: cpu-probe: Set the write-combine CCA value on per core basis
>   MIPS: pgtable.h: Implement the pgprot_writecombine function for MIPS

A good thing - but I'd really like to see the entire long-winded #ifdefed
list of cache modes in <asm/pgtable-bits.h> to be removed but I guess
that's left for a future patch.

  Ralf