From: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
To: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org
Cc: Stephen Warren <swarren@wwwdotorg.org>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Paul Walmsley <pwalmsley@nvidia.com>,
devicetree@vger.kernel.org,
Tuomas Tynkkynen <ttynkkynen@nvidia.com>,
broonie@kernel.org
Subject: [PATCH v2 00/16] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq
Date: Mon, 21 Jul 2014 18:38:46 +0300 [thread overview]
Message-ID: <1405957142-19416-1-git-send-email-ttynkkynen@nvidia.com> (raw)
v2 changes:
- Add new helpers to the regulator framework to obtain the voltage
register address etc., as suggested by Mark. Added in patches 1 & 2.
They get used in patch 5.
- Use cpufreq-cpu0 in the cpufreq driver
- Fixed one bug in patch 8, where deferred probing would attempt to
fill the OPP table multiple times and cause a bunch of warnings
Original cover letter:
This series implements the DFLL/CL-DVFS clock source for the fast CPU
cluster on Tegra124, and a cpufreq driver that uses the DFLL for
clocking the CPU. Most of this is based on Paul Walmsley's public patch
set from December 2013, which is available at
http://comments.gmane.org/gmane.linux.ports.tegra/15273
The DFLL clock hardware is a voltage-controlled oscillator plus
control logic that compares the generated output clock with a
51 MHz reference clock, and can make decisions to either lower
or raise the DFLL voltage to keep the output rate close to the
software-requested rate. The voltage changes are done by
communicating with an off-chip PMIC via either I2C or PWM.
As the DFLL oscillator is powered via the CPU rail, using
the DFLL as the CPU clocksource also gives us dynamic CPU
voltage scaling.
This series has been tested on the Jetson TK1 (Rev C). Porting this to
the Venice2 should be simple, though do note that it does not have
active cooling.
Thanks,
Tuomas
Paul Walmsley (1):
clk: tegra: Add DFLL DVCO reset control for Tegra124
Tuomas Tynkkynen (15):
regmap: Add regmap_get_device
regulator: Add helpers for low-level register access
clk: tegra: Add binding for the Tegra124 DFLL clocksource
clk: tegra: Add library for the DFLL clock source (open-loop mode)
clk: tegra: Add closed loop support for the DFLL
clk: tegra: Add functions for parsing CVB tables
clk: tegra: Add Tegra124 DFLL clocksource platform driver
clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend
clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
ARM: tegra: Add the DFLL to Tegra124 device tree
ARM: tegra: Enable the DFLL on the Jetson TK1
cpufreq: tegra124: Add device tree bindings
cpufreq: Add cpufreq driver for Tegra124
ARM: tegra: Add entries for cpufreq on Tegra124
ARM: tegra: Update defconfig for tegra124-cpufreq
.../bindings/clock/nvidia,tegra124-dfll.txt | 69 +
.../bindings/cpufreq/tegra124-cpufreq.txt | 42 +
Documentation/power/regulator/consumer.txt | 35 +
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 8 +-
arch/arm/boot/dts/tegra124.dtsi | 31 +
arch/arm/configs/tegra_defconfig | 1 +
arch/arm/mach-tegra/Kconfig | 1 +
drivers/base/regmap/regmap.c | 12 +
drivers/clk/tegra/Makefile | 3 +
drivers/clk/tegra/clk-dfll.c | 1735 ++++++++++++++++++++
drivers/clk/tegra/clk-dfll.h | 55 +
drivers/clk/tegra/clk-tegra-super-gen4.c | 4 +-
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 165 ++
drivers/clk/tegra/clk-tegra124.c | 61 +
drivers/clk/tegra/clk.h | 3 +
drivers/clk/tegra/cvb.c | 133 ++
drivers/clk/tegra/cvb.h | 67 +
drivers/cpufreq/Kconfig.arm | 1 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/tegra124-cpufreq.c | 169 ++
drivers/regulator/core.c | 71 +
include/linux/regmap.h | 7 +
include/linux/regulator/consumer.h | 26 +
23 files changed, 2698 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
create mode 100644 Documentation/devicetree/bindings/cpufreq/tegra124-cpufreq.txt
create mode 100644 drivers/clk/tegra/clk-dfll.c
create mode 100644 drivers/clk/tegra/clk-dfll.h
create mode 100644 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
create mode 100644 drivers/clk/tegra/cvb.c
create mode 100644 drivers/clk/tegra/cvb.h
create mode 100644 drivers/cpufreq/tegra124-cpufreq.c
--
1.8.1.5
WARNING: multiple messages have this Message-ID (diff)
From: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
To: <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-pm@vger.kernel.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Paul Walmsley <pwalmsley@nvidia.com>,
<devicetree@vger.kernel.org>,
Tuomas Tynkkynen <ttynkkynen@nvidia.com>, <broonie@kernel.org>
Subject: [PATCH v2 00/16] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq
Date: Mon, 21 Jul 2014 18:38:46 +0300 [thread overview]
Message-ID: <1405957142-19416-1-git-send-email-ttynkkynen@nvidia.com> (raw)
v2 changes:
- Add new helpers to the regulator framework to obtain the voltage
register address etc., as suggested by Mark. Added in patches 1 & 2.
They get used in patch 5.
- Use cpufreq-cpu0 in the cpufreq driver
- Fixed one bug in patch 8, where deferred probing would attempt to
fill the OPP table multiple times and cause a bunch of warnings
Original cover letter:
This series implements the DFLL/CL-DVFS clock source for the fast CPU
cluster on Tegra124, and a cpufreq driver that uses the DFLL for
clocking the CPU. Most of this is based on Paul Walmsley's public patch
set from December 2013, which is available at
http://comments.gmane.org/gmane.linux.ports.tegra/15273
The DFLL clock hardware is a voltage-controlled oscillator plus
control logic that compares the generated output clock with a
51 MHz reference clock, and can make decisions to either lower
or raise the DFLL voltage to keep the output rate close to the
software-requested rate. The voltage changes are done by
communicating with an off-chip PMIC via either I2C or PWM.
As the DFLL oscillator is powered via the CPU rail, using
the DFLL as the CPU clocksource also gives us dynamic CPU
voltage scaling.
This series has been tested on the Jetson TK1 (Rev C). Porting this to
the Venice2 should be simple, though do note that it does not have
active cooling.
Thanks,
Tuomas
Paul Walmsley (1):
clk: tegra: Add DFLL DVCO reset control for Tegra124
Tuomas Tynkkynen (15):
regmap: Add regmap_get_device
regulator: Add helpers for low-level register access
clk: tegra: Add binding for the Tegra124 DFLL clocksource
clk: tegra: Add library for the DFLL clock source (open-loop mode)
clk: tegra: Add closed loop support for the DFLL
clk: tegra: Add functions for parsing CVB tables
clk: tegra: Add Tegra124 DFLL clocksource platform driver
clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend
clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
ARM: tegra: Add the DFLL to Tegra124 device tree
ARM: tegra: Enable the DFLL on the Jetson TK1
cpufreq: tegra124: Add device tree bindings
cpufreq: Add cpufreq driver for Tegra124
ARM: tegra: Add entries for cpufreq on Tegra124
ARM: tegra: Update defconfig for tegra124-cpufreq
.../bindings/clock/nvidia,tegra124-dfll.txt | 69 +
.../bindings/cpufreq/tegra124-cpufreq.txt | 42 +
Documentation/power/regulator/consumer.txt | 35 +
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 8 +-
arch/arm/boot/dts/tegra124.dtsi | 31 +
arch/arm/configs/tegra_defconfig | 1 +
arch/arm/mach-tegra/Kconfig | 1 +
drivers/base/regmap/regmap.c | 12 +
drivers/clk/tegra/Makefile | 3 +
drivers/clk/tegra/clk-dfll.c | 1735 ++++++++++++++++++++
drivers/clk/tegra/clk-dfll.h | 55 +
drivers/clk/tegra/clk-tegra-super-gen4.c | 4 +-
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 165 ++
drivers/clk/tegra/clk-tegra124.c | 61 +
drivers/clk/tegra/clk.h | 3 +
drivers/clk/tegra/cvb.c | 133 ++
drivers/clk/tegra/cvb.h | 67 +
drivers/cpufreq/Kconfig.arm | 1 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/tegra124-cpufreq.c | 169 ++
drivers/regulator/core.c | 71 +
include/linux/regmap.h | 7 +
include/linux/regulator/consumer.h | 26 +
23 files changed, 2698 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
create mode 100644 Documentation/devicetree/bindings/cpufreq/tegra124-cpufreq.txt
create mode 100644 drivers/clk/tegra/clk-dfll.c
create mode 100644 drivers/clk/tegra/clk-dfll.h
create mode 100644 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
create mode 100644 drivers/clk/tegra/cvb.c
create mode 100644 drivers/clk/tegra/cvb.h
create mode 100644 drivers/cpufreq/tegra124-cpufreq.c
--
1.8.1.5
WARNING: multiple messages have this Message-ID (diff)
From: ttynkkynen@nvidia.com (Tuomas Tynkkynen)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 00/16] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq
Date: Mon, 21 Jul 2014 18:38:46 +0300 [thread overview]
Message-ID: <1405957142-19416-1-git-send-email-ttynkkynen@nvidia.com> (raw)
v2 changes:
- Add new helpers to the regulator framework to obtain the voltage
register address etc., as suggested by Mark. Added in patches 1 & 2.
They get used in patch 5.
- Use cpufreq-cpu0 in the cpufreq driver
- Fixed one bug in patch 8, where deferred probing would attempt to
fill the OPP table multiple times and cause a bunch of warnings
Original cover letter:
This series implements the DFLL/CL-DVFS clock source for the fast CPU
cluster on Tegra124, and a cpufreq driver that uses the DFLL for
clocking the CPU. Most of this is based on Paul Walmsley's public patch
set from December 2013, which is available at
http://comments.gmane.org/gmane.linux.ports.tegra/15273
The DFLL clock hardware is a voltage-controlled oscillator plus
control logic that compares the generated output clock with a
51 MHz reference clock, and can make decisions to either lower
or raise the DFLL voltage to keep the output rate close to the
software-requested rate. The voltage changes are done by
communicating with an off-chip PMIC via either I2C or PWM.
As the DFLL oscillator is powered via the CPU rail, using
the DFLL as the CPU clocksource also gives us dynamic CPU
voltage scaling.
This series has been tested on the Jetson TK1 (Rev C). Porting this to
the Venice2 should be simple, though do note that it does not have
active cooling.
Thanks,
Tuomas
Paul Walmsley (1):
clk: tegra: Add DFLL DVCO reset control for Tegra124
Tuomas Tynkkynen (15):
regmap: Add regmap_get_device
regulator: Add helpers for low-level register access
clk: tegra: Add binding for the Tegra124 DFLL clocksource
clk: tegra: Add library for the DFLL clock source (open-loop mode)
clk: tegra: Add closed loop support for the DFLL
clk: tegra: Add functions for parsing CVB tables
clk: tegra: Add Tegra124 DFLL clocksource platform driver
clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend
clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
ARM: tegra: Add the DFLL to Tegra124 device tree
ARM: tegra: Enable the DFLL on the Jetson TK1
cpufreq: tegra124: Add device tree bindings
cpufreq: Add cpufreq driver for Tegra124
ARM: tegra: Add entries for cpufreq on Tegra124
ARM: tegra: Update defconfig for tegra124-cpufreq
.../bindings/clock/nvidia,tegra124-dfll.txt | 69 +
.../bindings/cpufreq/tegra124-cpufreq.txt | 42 +
Documentation/power/regulator/consumer.txt | 35 +
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 8 +-
arch/arm/boot/dts/tegra124.dtsi | 31 +
arch/arm/configs/tegra_defconfig | 1 +
arch/arm/mach-tegra/Kconfig | 1 +
drivers/base/regmap/regmap.c | 12 +
drivers/clk/tegra/Makefile | 3 +
drivers/clk/tegra/clk-dfll.c | 1735 ++++++++++++++++++++
drivers/clk/tegra/clk-dfll.h | 55 +
drivers/clk/tegra/clk-tegra-super-gen4.c | 4 +-
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 165 ++
drivers/clk/tegra/clk-tegra124.c | 61 +
drivers/clk/tegra/clk.h | 3 +
drivers/clk/tegra/cvb.c | 133 ++
drivers/clk/tegra/cvb.h | 67 +
drivers/cpufreq/Kconfig.arm | 1 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/tegra124-cpufreq.c | 169 ++
drivers/regulator/core.c | 71 +
include/linux/regmap.h | 7 +
include/linux/regulator/consumer.h | 26 +
23 files changed, 2698 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
create mode 100644 Documentation/devicetree/bindings/cpufreq/tegra124-cpufreq.txt
create mode 100644 drivers/clk/tegra/clk-dfll.c
create mode 100644 drivers/clk/tegra/clk-dfll.h
create mode 100644 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
create mode 100644 drivers/clk/tegra/cvb.c
create mode 100644 drivers/clk/tegra/cvb.h
create mode 100644 drivers/cpufreq/tegra124-cpufreq.c
--
1.8.1.5
next reply other threads:[~2014-07-21 15:38 UTC|newest]
Thread overview: 115+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-21 15:38 Tuomas Tynkkynen [this message]
2014-07-21 15:38 ` [PATCH v2 00/16] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 01/16] regmap: Add regmap_get_device Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-25 17:34 ` Mark Brown
2014-07-25 17:34 ` Mark Brown
[not found] ` <1405957142-19416-2-git-send-email-ttynkkynen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-07-25 17:43 ` Mark Brown
2014-07-25 17:43 ` Mark Brown
2014-07-25 17:43 ` Mark Brown
2014-07-21 15:38 ` [PATCH v2 02/16] regulator: Add helpers for low-level register access Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
[not found] ` <1405957142-19416-3-git-send-email-ttynkkynen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-07-25 17:48 ` Mark Brown
2014-07-25 17:48 ` Mark Brown
2014-07-25 17:48 ` Mark Brown
2014-07-21 15:38 ` [PATCH v2 03/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 04/16] clk: tegra: Add library for the DFLL clock source (open-loop mode) Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
[not found] ` <1405957142-19416-5-git-send-email-ttynkkynen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-08-18 6:05 ` Vince Hsu
2014-08-18 6:05 ` Vince Hsu
2014-08-18 6:05 ` Vince Hsu
2014-07-21 15:38 ` [PATCH v2 05/16] clk: tegra: Add closed loop support for the DFLL Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
[not found] ` <1405957142-19416-6-git-send-email-ttynkkynen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-08-18 6:08 ` Vince Hsu
2014-08-18 6:08 ` Vince Hsu
2014-08-18 6:08 ` Vince Hsu
2014-07-21 15:38 ` [PATCH v2 06/16] clk: tegra: Add functions for parsing CVB tables Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 07/16] clk: tegra: Add DFLL DVCO reset control for Tegra124 Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 08/16] clk: tegra: Add Tegra124 DFLL clocksource platform driver Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-08-12 10:37 ` Vince Hsu
2014-08-12 10:37 ` Vince Hsu
2014-08-12 10:37 ` Vince Hsu
2014-07-21 15:38 ` [PATCH v2 09/16] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 10/16] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 11/16] ARM: tegra: Add the DFLL to Tegra124 device tree Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 12/16] ARM: tegra: Enable the DFLL on the Jetson TK1 Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` [PATCH v2 13/16] cpufreq: tegra124: Add device tree bindings Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
2014-07-21 15:38 ` Tuomas Tynkkynen
[not found] ` <1405957142-19416-1-git-send-email-ttynkkynen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-07-21 15:39 ` [PATCH v2 14/16] cpufreq: Add cpufreq driver for Tegra124 Tuomas Tynkkynen
2014-07-21 15:39 ` Tuomas Tynkkynen
2014-07-21 15:39 ` Tuomas Tynkkynen
2014-07-22 0:49 ` Rafael J. Wysocki
2014-07-22 0:49 ` Rafael J. Wysocki
2014-07-22 0:49 ` Rafael J. Wysocki
2014-07-23 4:44 ` Viresh Kumar
2014-07-23 4:44 ` Viresh Kumar
2014-07-23 4:44 ` Viresh Kumar
2014-07-23 6:54 ` Thierry Reding
2014-07-23 6:54 ` Thierry Reding
2014-07-23 6:54 ` Thierry Reding
[not found] ` <20140723065412.GA15759-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2014-07-23 6:58 ` Viresh Kumar
2014-07-23 6:58 ` Viresh Kumar
2014-07-23 6:58 ` Viresh Kumar
2014-07-23 7:24 ` Thierry Reding
2014-07-23 7:24 ` Thierry Reding
2014-07-23 7:24 ` Thierry Reding
2014-07-23 8:25 ` Viresh Kumar
2014-07-23 8:25 ` Viresh Kumar
2014-07-23 8:25 ` Viresh Kumar
[not found] ` <CAKohponfKzuK+TnQvWcvaT8hRX8XZJWXWGMQw138DCwP=qcx+A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-07-23 13:51 ` Thierry Reding
2014-07-23 13:51 ` Thierry Reding
2014-07-23 13:51 ` Thierry Reding
[not found] ` <CAKohpomQthJ_XE-HhzW07Q4aVtxQVy97iaL0Vy6Q4Lhw22A=VA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-07-23 11:57 ` Tuomas Tynkkynen
2014-07-23 11:57 ` Tuomas Tynkkynen
2014-07-23 11:57 ` Tuomas Tynkkynen
2014-07-23 16:50 ` Viresh Kumar
2014-07-23 16:50 ` Viresh Kumar
2014-07-23 16:50 ` Viresh Kumar
2014-07-23 19:17 ` Tuomas Tynkkynen
2014-07-23 19:17 ` Tuomas Tynkkynen
2014-07-23 19:17 ` Tuomas Tynkkynen
[not found] ` <53D00A47.7050203-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-07-24 0:13 ` Viresh Kumar
2014-07-24 0:13 ` Viresh Kumar
2014-07-24 0:13 ` Viresh Kumar
2014-07-24 9:10 ` Thierry Reding
2014-07-24 9:10 ` Thierry Reding
2014-07-24 9:10 ` Thierry Reding
2014-07-23 7:09 ` Thierry Reding
2014-07-23 7:09 ` Thierry Reding
2014-07-23 12:35 ` Tuomas Tynkkynen
2014-07-23 12:35 ` Tuomas Tynkkynen
2014-07-23 12:35 ` Tuomas Tynkkynen
2014-07-23 13:59 ` Thierry Reding
2014-07-23 13:59 ` Thierry Reding
2014-07-23 13:59 ` Thierry Reding
2014-07-23 7:21 ` pramod gurav
2014-07-23 7:21 ` pramod gurav
2014-07-23 7:21 ` pramod gurav
2014-07-21 15:39 ` [PATCH v2 15/16] ARM: tegra: Add entries for cpufreq on Tegra124 Tuomas Tynkkynen
2014-07-21 15:39 ` Tuomas Tynkkynen
2014-07-21 15:39 ` Tuomas Tynkkynen
2014-07-21 15:39 ` [PATCH v2 16/16] ARM: tegra: Update defconfig for tegra124-cpufreq Tuomas Tynkkynen
2014-07-21 15:39 ` Tuomas Tynkkynen
2014-07-21 15:39 ` Tuomas Tynkkynen
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