* [cbootimage-configs PATCH] Update colibri_t30 BCT to use all SDRAM entries
@ 2014-08-06 7:46 Stefan Agner
[not found] ` <1407311217-1742-1-git-send-email-stefan-XLVq0VzYD2Y@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: Stefan Agner @ 2014-08-06 7:46 UTC (permalink / raw)
To: twarren-DDmLM1+adcrQT0dZR+AlfA
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
marcel-mitwqZ+T+m9Wk0Htik3J/w, dev-8ppwABl0HbeELgA04lAiVw,
stefan-XLVq0VzYD2Y
Use all SDRAM entries to make sure in any case a valid configuration
is selected.
Signed-off-by: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org>
---
...12MHz_1GB_NT5CC256M16CP-DI_400MHz-shmoo.bct.cfg | 579 +++++++++++++++++++++
1 file changed, 579 insertions(+)
diff --git a/tegra30/toradex/colibri_t30/colibri_t30_12MHz_1GB_NT5CC256M16CP-DI_400MHz-shmoo.bct.cfg b/tegra30/toradex/colibri_t30/colibri_t30_12MHz_1GB_NT5CC256M16CP-DI_400MHz-shmoo.bct.cfg
index b77bf35..89c5ce2 100755
--- a/tegra30/toradex/colibri_t30/colibri_t30_12MHz_1GB_NT5CC256M16CP-DI_400MHz-shmoo.bct.cfg
+++ b/tegra30/toradex/colibri_t30/colibri_t30_12MHz_1GB_NT5CC256M16CP-DI_400MHz-shmoo.bct.cfg
@@ -238,3 +238,582 @@ SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
SDRAM[0].McEmemArbOverride = 0x00000080;
SDRAM[0].McEmemArbRsv = 0xff00ff00;
SDRAM[0].McClkenOverride = 0x00000000;
+
+SDRAM[1].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[1].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[1].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[1].PllMInputDivider = 0x0000000c;
+SDRAM[1].PllMFeedbackDivider = 0x00000320;
+SDRAM[1].PllMPostDivider = 0x00000000;
+SDRAM[1].PllMStableTime = 0x0000012c;
+SDRAM[1].EmcClockDivider = 0x00000002;
+SDRAM[1].EmcClockSource = 0x00000000;
+SDRAM[1].EmcClockUsePllMUD = 0x00000000;
+SDRAM[1].EmcAutoCalInterval = 0x001fffff;
+SDRAM[1].EmcAutoCalConfig = 0xa0f10000;
+SDRAM[1].EmcAutoCalWait = 0x00000064;
+SDRAM[1].EmcAdrCfg = 0x00000000;
+SDRAM[1].EmcPinProgramWait = 0x00000001;
+SDRAM[1].EmcPinExtraWait = 0x00000000;
+SDRAM[1].EmcTimingControlWait = 0x00000000;
+SDRAM[1].EmcRc = 0x00000012;
+SDRAM[1].EmcRfc = 0x0000008a;
+SDRAM[1].EmcRas = 0x0000000c;
+SDRAM[1].EmcRp = 0x00000004;
+SDRAM[1].EmcR2w = 0x00000003;
+SDRAM[1].EmcW2r = 0x00000008;
+SDRAM[1].EmcR2p = 0x00000002;
+SDRAM[1].EmcW2p = 0x0000000a;
+SDRAM[1].EmcRdRcd = 0x00000004;
+SDRAM[1].EmcWrRcd = 0x00000004;
+SDRAM[1].EmcRrd = 0x00000002;
+SDRAM[1].EmcRext = 0x00000001;
+SDRAM[1].EmcWext = 0x00000000;
+SDRAM[1].EmcWdv = 0x00000004;
+SDRAM[1].EmcQUse = 0x00000006;
+SDRAM[1].EmcQRst = 0x00000004;
+SDRAM[1].EmcQSafe = 0x00000009;
+SDRAM[1].EmcRdv = 0x0000000c;
+SDRAM[1].EmcCtt = 0x00000000;
+SDRAM[1].EmcCttDuration = 0x00000000;
+SDRAM[1].EmcRefresh = 0x00000bf5;
+SDRAM[1].EmcBurstRefreshNum = 0x00000000;
+SDRAM[1].EmcPreRefreshReqCnt = 0x000002fd;
+SDRAM[1].EmcPdEx2Wr = 0x00000001;
+SDRAM[1].EmcPdEx2Rd = 0x00000008;
+SDRAM[1].EmcPChg2Pden = 0x00000001;
+SDRAM[1].EmcAct2Pden = 0x00000000;
+SDRAM[1].EmcAr2Pden = 0x00000008;
+SDRAM[1].EmcRw2Pden = 0x0000000f;
+SDRAM[1].EmcTxsr = 0x00000090;
+SDRAM[1].EmcTxsrDll = 0x00000200;
+SDRAM[1].EmcTcke = 0x00000004;
+SDRAM[1].EmcTfaw = 0x00000010;
+SDRAM[1].EmcTrpab = 0x00000000;
+SDRAM[1].EmcTClkStable = 0x00000004;
+SDRAM[1].EmcTClkStop = 0x00000005;
+SDRAM[1].EmcTRefBw = 0x00000c35;
+SDRAM[1].EmcQUseExtra = 0x00000000;
+SDRAM[1].EmcFbioCfg5 = 0x00007088;
+SDRAM[1].EmcFbioCfg6 = 0x00000004;
+SDRAM[1].EmcFbioSpare = 0xe8000000;
+SDRAM[1].EmcCfgRsv = 0xff00ff88;
+SDRAM[1].EmcMrs = 0x80000521;
+SDRAM[1].EmcEmrs = 0x80100002;
+SDRAM[1].EmcMrw1 = 0x00000000;
+SDRAM[1].EmcMrw2 = 0x00000000;
+SDRAM[1].EmcMrw3 = 0x00000000;
+SDRAM[1].EmcMrwExtra = 0x00000000;
+SDRAM[1].EmcWarmBootMrw1 = 0x00000000;
+SDRAM[1].EmcWarmBootMrw2 = 0x00000000;
+SDRAM[1].EmcWarmBootMrw3 = 0x00000000;
+SDRAM[1].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[1].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[1].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[1].EmcMrwResetCommand = 0x00000000;
+SDRAM[1].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[1].EmcMrsWaitCnt = 0x0134000c;
+SDRAM[1].EmcCfg = 0x23c00000;
+SDRAM[1].EmcCfg2 = 0x000c0099;
+SDRAM[1].EmcDbg = 0x01000400;
+SDRAM[1].EmcCmdQ = 0x10004408;
+SDRAM[1].EmcMc2EmcQ = 0x06000404;
+SDRAM[1].EmcDynSelfRefControl = 0x800018d1;
+SDRAM[1].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[1].EmcCfgDigDll = 0x00360084;
+SDRAM[1].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[1].EmcDevSelect = 0x00000002;
+SDRAM[1].EmcSelDpdCtrl = 0x0004032c;
+SDRAM[1].EmcDllXformDqs0 = 0x0000c002;
+SDRAM[1].EmcDllXformDqs1 = 0x00014002;
+SDRAM[1].EmcDllXformDqs2 = 0x0000c002;
+SDRAM[1].EmcDllXformDqs3 = 0x00014002;
+SDRAM[1].EmcDllXformDqs4 = 0x00014000;
+SDRAM[1].EmcDllXformDqs5 = 0x00014000;
+SDRAM[1].EmcDllXformDqs6 = 0x00014000;
+SDRAM[1].EmcDllXformDqs7 = 0x00014000;
+SDRAM[1].EmcDllXformQUse0 = 0x00000000;
+SDRAM[1].EmcDllXformQUse1 = 0x00000000;
+SDRAM[1].EmcDllXformQUse2 = 0x00000000;
+SDRAM[1].EmcDllXformQUse3 = 0x00000000;
+SDRAM[1].EmcDllXformQUse4 = 0x00000000;
+SDRAM[1].EmcDllXformQUse5 = 0x00000000;
+SDRAM[1].EmcDllXformQUse6 = 0x00000000;
+SDRAM[1].EmcDllXformQUse7 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[1].EmcDllXformDq0 = 0x00018000;
+SDRAM[1].EmcDllXformDq1 = 0x00018000;
+SDRAM[1].EmcDllXformDq2 = 0x00018000;
+SDRAM[1].EmcDllXformDq3 = 0x00018000;
+SDRAM[1].WarmBootWait = 0x00000002;
+SDRAM[1].EmcCttTermCtrl = 0x00000802;
+SDRAM[1].EmcOdtWrite = 0x00000000;
+SDRAM[1].EmcOdtRead = 0x00000000;
+SDRAM[1].EmcZcalInterval = 0x00020000;
+SDRAM[1].EmcZcalWaitCnt = 0x00000040;
+SDRAM[1].EmcZcalMrwCmd = 0x80000000;
+SDRAM[1].EmcMrsResetDll = 0x00000000;
+SDRAM[1].EmcZcalInitDev0 = 0x80000011;
+SDRAM[1].EmcZcalInitDev1 = 0x00000000;
+SDRAM[1].EmcZcalInitWait = 0x00000002;
+SDRAM[1].EmcZcalColdBootEnable = 0x00000001;
+SDRAM[1].EmcZcalWarmBootEnable = 0x00000001;
+SDRAM[1].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab;
+SDRAM[1].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[1].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[1].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[1].EmcMrsResetDllWait = 0x00000000;
+SDRAM[1].EmcEmrsEmr2 = 0x80200000;
+SDRAM[1].EmcEmrsEmr3 = 0x80300000;
+SDRAM[1].EmcMrsExtra = 0x80000521;
+SDRAM[1].EmcWarmBootMrs = 0x80100002;
+SDRAM[1].EmcWarmBootEmrs = 0x80000521;
+SDRAM[1].EmcWarmBootEmr2 = 0x80200000;
+SDRAM[1].EmcWarmBootEmr3 = 0x80300000;
+SDRAM[1].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[1].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[1].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[1].EmcDdr2Wait = 0x00000000;
+SDRAM[1].EmcClkenOverride = 0x00000000;
+SDRAM[1].EmcExtraRefreshNum = 0x00000002;
+SDRAM[1].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[1].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[1].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[1].PmcVddpSel = 0x00000002;
+SDRAM[1].PmcDdrPwr = 0x00000003;
+SDRAM[1].PmcDdrCfg = 0x00000002;
+SDRAM[1].PmcIoDpdReq = 0x80800000;
+SDRAM[1].PmcENoVttGen = 0x00000000;
+SDRAM[1].PmcNoIoPower = 0x00000000;
+SDRAM[1].EmcXm2CmdPadCtrl = 0x000002a0;
+SDRAM[1].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[1].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[1].EmcXm2DqsPadCtrl2 = 0x0a00013d;
+SDRAM[1].EmcXm2DqsPadCtrl3 = 0x08000021;
+SDRAM[1].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[1].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[1].EmcXm2ClkPadCtrl = 0x77fff884;
+SDRAM[1].EmcXm2CompPadCtrl = 0x01f1f508;
+SDRAM[1].EmcXm2VttGenPadCtrl = 0x05057404;
+SDRAM[1].EmcXm2VttGenPadCtrl2 = 0x54000007;
+SDRAM[1].EmcXm2QUsePadCtrl = 0x080001e8;
+SDRAM[1].McEmemAdrCfg = 0x00000000;
+SDRAM[1].McEmemAdrCfgDev0 = 0x00080303;
+SDRAM[1].McEmemAdrCfgDev1 = 0x00080303;
+SDRAM[1].McEmemCfg = 0x00000400;
+SDRAM[1].McEmemArbCfg = 0x00000006;
+SDRAM[1].McEmemArbOutstandingReq = 0x80000048;
+SDRAM[1].McEmemArbTimingRcd = 0x00000001;
+SDRAM[1].McEmemArbTimingRp = 0x00000002;
+SDRAM[1].McEmemArbTimingRc = 0x00000009;
+SDRAM[1].McEmemArbTimingRas = 0x00000005;
+SDRAM[1].McEmemArbTimingFaw = 0x00000007;
+SDRAM[1].McEmemArbTimingRrd = 0x00000001;
+SDRAM[1].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[1].McEmemArbTimingWap2Pre = 0x00000008;
+SDRAM[1].McEmemArbTimingR2R = 0x00000002;
+SDRAM[1].McEmemArbTimingW2W = 0x00000002;
+SDRAM[1].McEmemArbTimingR2W = 0x00000003;
+SDRAM[1].McEmemArbTimingW2R = 0x00000006;
+SDRAM[1].McEmemArbDaTurns = 0x06030202;
+SDRAM[1].McEmemArbDaCovers = 0x000d0709;
+SDRAM[1].McEmemArbMisc0 = 0x7086120a;
+SDRAM[1].McEmemArbMisc1 = 0x78000000;
+SDRAM[1].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[1].McEmemArbOverride = 0x00000080;
+SDRAM[1].McEmemArbRsv = 0xff00ff00;
+SDRAM[1].McClkenOverride = 0x00000000;
+
+SDRAM[2].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[2].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[2].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[2].PllMInputDivider = 0x0000000c;
+SDRAM[2].PllMFeedbackDivider = 0x00000320;
+SDRAM[2].PllMPostDivider = 0x00000000;
+SDRAM[2].PllMStableTime = 0x0000012c;
+SDRAM[2].EmcClockDivider = 0x00000002;
+SDRAM[2].EmcClockSource = 0x00000000;
+SDRAM[2].EmcClockUsePllMUD = 0x00000000;
+SDRAM[2].EmcAutoCalInterval = 0x001fffff;
+SDRAM[2].EmcAutoCalConfig = 0xa0f10000;
+SDRAM[2].EmcAutoCalWait = 0x00000064;
+SDRAM[2].EmcAdrCfg = 0x00000000;
+SDRAM[2].EmcPinProgramWait = 0x00000001;
+SDRAM[2].EmcPinExtraWait = 0x00000000;
+SDRAM[2].EmcTimingControlWait = 0x00000000;
+SDRAM[2].EmcRc = 0x00000012;
+SDRAM[2].EmcRfc = 0x0000008a;
+SDRAM[2].EmcRas = 0x0000000c;
+SDRAM[2].EmcRp = 0x00000004;
+SDRAM[2].EmcR2w = 0x00000003;
+SDRAM[2].EmcW2r = 0x00000008;
+SDRAM[2].EmcR2p = 0x00000002;
+SDRAM[2].EmcW2p = 0x0000000a;
+SDRAM[2].EmcRdRcd = 0x00000004;
+SDRAM[2].EmcWrRcd = 0x00000004;
+SDRAM[2].EmcRrd = 0x00000002;
+SDRAM[2].EmcRext = 0x00000001;
+SDRAM[2].EmcWext = 0x00000000;
+SDRAM[2].EmcWdv = 0x00000004;
+SDRAM[2].EmcQUse = 0x00000006;
+SDRAM[2].EmcQRst = 0x00000004;
+SDRAM[2].EmcQSafe = 0x00000009;
+SDRAM[2].EmcRdv = 0x0000000c;
+SDRAM[2].EmcCtt = 0x00000000;
+SDRAM[2].EmcCttDuration = 0x00000000;
+SDRAM[2].EmcRefresh = 0x00000bf5;
+SDRAM[2].EmcBurstRefreshNum = 0x00000000;
+SDRAM[2].EmcPreRefreshReqCnt = 0x000002fd;
+SDRAM[2].EmcPdEx2Wr = 0x00000001;
+SDRAM[2].EmcPdEx2Rd = 0x00000008;
+SDRAM[2].EmcPChg2Pden = 0x00000001;
+SDRAM[2].EmcAct2Pden = 0x00000000;
+SDRAM[2].EmcAr2Pden = 0x00000008;
+SDRAM[2].EmcRw2Pden = 0x0000000f;
+SDRAM[2].EmcTxsr = 0x00000090;
+SDRAM[2].EmcTxsrDll = 0x00000200;
+SDRAM[2].EmcTcke = 0x00000004;
+SDRAM[2].EmcTfaw = 0x00000010;
+SDRAM[2].EmcTrpab = 0x00000000;
+SDRAM[2].EmcTClkStable = 0x00000004;
+SDRAM[2].EmcTClkStop = 0x00000005;
+SDRAM[2].EmcTRefBw = 0x00000c35;
+SDRAM[2].EmcQUseExtra = 0x00000000;
+SDRAM[2].EmcFbioCfg5 = 0x00007088;
+SDRAM[2].EmcFbioCfg6 = 0x00000004;
+SDRAM[2].EmcFbioSpare = 0xe8000000;
+SDRAM[2].EmcCfgRsv = 0xff00ff88;
+SDRAM[2].EmcMrs = 0x80000521;
+SDRAM[2].EmcEmrs = 0x80100002;
+SDRAM[2].EmcMrw1 = 0x00000000;
+SDRAM[2].EmcMrw2 = 0x00000000;
+SDRAM[2].EmcMrw3 = 0x00000000;
+SDRAM[2].EmcMrwExtra = 0x00000000;
+SDRAM[2].EmcWarmBootMrw1 = 0x00000000;
+SDRAM[2].EmcWarmBootMrw2 = 0x00000000;
+SDRAM[2].EmcWarmBootMrw3 = 0x00000000;
+SDRAM[2].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[2].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[2].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[2].EmcMrwResetCommand = 0x00000000;
+SDRAM[2].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[2].EmcMrsWaitCnt = 0x0134000c;
+SDRAM[2].EmcCfg = 0x23c00000;
+SDRAM[2].EmcCfg2 = 0x000c0099;
+SDRAM[2].EmcDbg = 0x01000400;
+SDRAM[2].EmcCmdQ = 0x10004408;
+SDRAM[2].EmcMc2EmcQ = 0x06000404;
+SDRAM[2].EmcDynSelfRefControl = 0x800018d1;
+SDRAM[2].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[2].EmcCfgDigDll = 0x00360084;
+SDRAM[2].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[2].EmcDevSelect = 0x00000002;
+SDRAM[2].EmcSelDpdCtrl = 0x0004032c;
+SDRAM[2].EmcDllXformDqs0 = 0x0000c002;
+SDRAM[2].EmcDllXformDqs1 = 0x00014002;
+SDRAM[2].EmcDllXformDqs2 = 0x0000c002;
+SDRAM[2].EmcDllXformDqs3 = 0x00014002;
+SDRAM[2].EmcDllXformDqs4 = 0x00014000;
+SDRAM[2].EmcDllXformDqs5 = 0x00014000;
+SDRAM[2].EmcDllXformDqs6 = 0x00014000;
+SDRAM[2].EmcDllXformDqs7 = 0x00014000;
+SDRAM[2].EmcDllXformQUse0 = 0x00000000;
+SDRAM[2].EmcDllXformQUse1 = 0x00000000;
+SDRAM[2].EmcDllXformQUse2 = 0x00000000;
+SDRAM[2].EmcDllXformQUse3 = 0x00000000;
+SDRAM[2].EmcDllXformQUse4 = 0x00000000;
+SDRAM[2].EmcDllXformQUse5 = 0x00000000;
+SDRAM[2].EmcDllXformQUse6 = 0x00000000;
+SDRAM[2].EmcDllXformQUse7 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[2].EmcDllXformDq0 = 0x00018000;
+SDRAM[2].EmcDllXformDq1 = 0x00018000;
+SDRAM[2].EmcDllXformDq2 = 0x00018000;
+SDRAM[2].EmcDllXformDq3 = 0x00018000;
+SDRAM[2].WarmBootWait = 0x00000002;
+SDRAM[2].EmcCttTermCtrl = 0x00000802;
+SDRAM[2].EmcOdtWrite = 0x00000000;
+SDRAM[2].EmcOdtRead = 0x00000000;
+SDRAM[2].EmcZcalInterval = 0x00020000;
+SDRAM[2].EmcZcalWaitCnt = 0x00000040;
+SDRAM[2].EmcZcalMrwCmd = 0x80000000;
+SDRAM[2].EmcMrsResetDll = 0x00000000;
+SDRAM[2].EmcZcalInitDev0 = 0x80000011;
+SDRAM[2].EmcZcalInitDev1 = 0x00000000;
+SDRAM[2].EmcZcalInitWait = 0x00000002;
+SDRAM[2].EmcZcalColdBootEnable = 0x00000001;
+SDRAM[2].EmcZcalWarmBootEnable = 0x00000001;
+SDRAM[2].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab;
+SDRAM[2].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[2].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[2].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[2].EmcMrsResetDllWait = 0x00000000;
+SDRAM[2].EmcEmrsEmr2 = 0x80200000;
+SDRAM[2].EmcEmrsEmr3 = 0x80300000;
+SDRAM[2].EmcMrsExtra = 0x80000521;
+SDRAM[2].EmcWarmBootMrs = 0x80100002;
+SDRAM[2].EmcWarmBootEmrs = 0x80000521;
+SDRAM[2].EmcWarmBootEmr2 = 0x80200000;
+SDRAM[2].EmcWarmBootEmr3 = 0x80300000;
+SDRAM[2].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[2].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[2].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[2].EmcDdr2Wait = 0x00000000;
+SDRAM[2].EmcClkenOverride = 0x00000000;
+SDRAM[2].EmcExtraRefreshNum = 0x00000002;
+SDRAM[2].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[2].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[2].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[2].PmcVddpSel = 0x00000002;
+SDRAM[2].PmcDdrPwr = 0x00000003;
+SDRAM[2].PmcDdrCfg = 0x00000002;
+SDRAM[2].PmcIoDpdReq = 0x80800000;
+SDRAM[2].PmcENoVttGen = 0x00000000;
+SDRAM[2].PmcNoIoPower = 0x00000000;
+SDRAM[2].EmcXm2CmdPadCtrl = 0x000002a0;
+SDRAM[2].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[2].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[2].EmcXm2DqsPadCtrl2 = 0x0a00013d;
+SDRAM[2].EmcXm2DqsPadCtrl3 = 0x08000021;
+SDRAM[2].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[2].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[2].EmcXm2ClkPadCtrl = 0x77fff884;
+SDRAM[2].EmcXm2CompPadCtrl = 0x01f1f508;
+SDRAM[2].EmcXm2VttGenPadCtrl = 0x05057404;
+SDRAM[2].EmcXm2VttGenPadCtrl2 = 0x54000007;
+SDRAM[2].EmcXm2QUsePadCtrl = 0x080001e8;
+SDRAM[2].McEmemAdrCfg = 0x00000000;
+SDRAM[2].McEmemAdrCfgDev0 = 0x00080303;
+SDRAM[2].McEmemAdrCfgDev1 = 0x00080303;
+SDRAM[2].McEmemCfg = 0x00000400;
+SDRAM[2].McEmemArbCfg = 0x00000006;
+SDRAM[2].McEmemArbOutstandingReq = 0x80000048;
+SDRAM[2].McEmemArbTimingRcd = 0x00000001;
+SDRAM[2].McEmemArbTimingRp = 0x00000002;
+SDRAM[2].McEmemArbTimingRc = 0x00000009;
+SDRAM[2].McEmemArbTimingRas = 0x00000005;
+SDRAM[2].McEmemArbTimingFaw = 0x00000007;
+SDRAM[2].McEmemArbTimingRrd = 0x00000001;
+SDRAM[2].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[2].McEmemArbTimingWap2Pre = 0x00000008;
+SDRAM[2].McEmemArbTimingR2R = 0x00000002;
+SDRAM[2].McEmemArbTimingW2W = 0x00000002;
+SDRAM[2].McEmemArbTimingR2W = 0x00000003;
+SDRAM[2].McEmemArbTimingW2R = 0x00000006;
+SDRAM[2].McEmemArbDaTurns = 0x06030202;
+SDRAM[2].McEmemArbDaCovers = 0x000d0709;
+SDRAM[2].McEmemArbMisc0 = 0x7086120a;
+SDRAM[2].McEmemArbMisc1 = 0x78000000;
+SDRAM[2].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[2].McEmemArbOverride = 0x00000080;
+SDRAM[2].McEmemArbRsv = 0xff00ff00;
+SDRAM[2].McClkenOverride = 0x00000000;
+
+SDRAM[3].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[3].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[3].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[3].PllMInputDivider = 0x0000000c;
+SDRAM[3].PllMFeedbackDivider = 0x00000320;
+SDRAM[3].PllMPostDivider = 0x00000000;
+SDRAM[3].PllMStableTime = 0x0000012c;
+SDRAM[3].EmcClockDivider = 0x00000002;
+SDRAM[3].EmcClockSource = 0x00000000;
+SDRAM[3].EmcClockUsePllMUD = 0x00000000;
+SDRAM[3].EmcAutoCalInterval = 0x001fffff;
+SDRAM[3].EmcAutoCalConfig = 0xa0f10000;
+SDRAM[3].EmcAutoCalWait = 0x00000064;
+SDRAM[3].EmcAdrCfg = 0x00000000;
+SDRAM[3].EmcPinProgramWait = 0x00000001;
+SDRAM[3].EmcPinExtraWait = 0x00000000;
+SDRAM[3].EmcTimingControlWait = 0x00000000;
+SDRAM[3].EmcRc = 0x00000012;
+SDRAM[3].EmcRfc = 0x0000008a;
+SDRAM[3].EmcRas = 0x0000000c;
+SDRAM[3].EmcRp = 0x00000004;
+SDRAM[3].EmcR2w = 0x00000003;
+SDRAM[3].EmcW2r = 0x00000008;
+SDRAM[3].EmcR2p = 0x00000002;
+SDRAM[3].EmcW2p = 0x0000000a;
+SDRAM[3].EmcRdRcd = 0x00000004;
+SDRAM[3].EmcWrRcd = 0x00000004;
+SDRAM[3].EmcRrd = 0x00000002;
+SDRAM[3].EmcRext = 0x00000001;
+SDRAM[3].EmcWext = 0x00000000;
+SDRAM[3].EmcWdv = 0x00000004;
+SDRAM[3].EmcQUse = 0x00000006;
+SDRAM[3].EmcQRst = 0x00000004;
+SDRAM[3].EmcQSafe = 0x00000009;
+SDRAM[3].EmcRdv = 0x0000000c;
+SDRAM[3].EmcCtt = 0x00000000;
+SDRAM[3].EmcCttDuration = 0x00000000;
+SDRAM[3].EmcRefresh = 0x00000bf5;
+SDRAM[3].EmcBurstRefreshNum = 0x00000000;
+SDRAM[3].EmcPreRefreshReqCnt = 0x000002fd;
+SDRAM[3].EmcPdEx2Wr = 0x00000001;
+SDRAM[3].EmcPdEx2Rd = 0x00000008;
+SDRAM[3].EmcPChg2Pden = 0x00000001;
+SDRAM[3].EmcAct2Pden = 0x00000000;
+SDRAM[3].EmcAr2Pden = 0x00000008;
+SDRAM[3].EmcRw2Pden = 0x0000000f;
+SDRAM[3].EmcTxsr = 0x00000090;
+SDRAM[3].EmcTxsrDll = 0x00000200;
+SDRAM[3].EmcTcke = 0x00000004;
+SDRAM[3].EmcTfaw = 0x00000010;
+SDRAM[3].EmcTrpab = 0x00000000;
+SDRAM[3].EmcTClkStable = 0x00000004;
+SDRAM[3].EmcTClkStop = 0x00000005;
+SDRAM[3].EmcTRefBw = 0x00000c35;
+SDRAM[3].EmcQUseExtra = 0x00000000;
+SDRAM[3].EmcFbioCfg5 = 0x00007088;
+SDRAM[3].EmcFbioCfg6 = 0x00000004;
+SDRAM[3].EmcFbioSpare = 0xe8000000;
+SDRAM[3].EmcCfgRsv = 0xff00ff88;
+SDRAM[3].EmcMrs = 0x80000521;
+SDRAM[3].EmcEmrs = 0x80100002;
+SDRAM[3].EmcMrw1 = 0x00000000;
+SDRAM[3].EmcMrw2 = 0x00000000;
+SDRAM[3].EmcMrw3 = 0x00000000;
+SDRAM[3].EmcMrwExtra = 0x00000000;
+SDRAM[3].EmcWarmBootMrw1 = 0x00000000;
+SDRAM[3].EmcWarmBootMrw2 = 0x00000000;
+SDRAM[3].EmcWarmBootMrw3 = 0x00000000;
+SDRAM[3].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[3].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[3].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[3].EmcMrwResetCommand = 0x00000000;
+SDRAM[3].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[3].EmcMrsWaitCnt = 0x0134000c;
+SDRAM[3].EmcCfg = 0x23c00000;
+SDRAM[3].EmcCfg2 = 0x000c0099;
+SDRAM[3].EmcDbg = 0x01000400;
+SDRAM[3].EmcCmdQ = 0x10004408;
+SDRAM[3].EmcMc2EmcQ = 0x06000404;
+SDRAM[3].EmcDynSelfRefControl = 0x800018d1;
+SDRAM[3].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[3].EmcCfgDigDll = 0x00360084;
+SDRAM[3].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[3].EmcDevSelect = 0x00000002;
+SDRAM[3].EmcSelDpdCtrl = 0x0004032c;
+SDRAM[3].EmcDllXformDqs0 = 0x0000c002;
+SDRAM[3].EmcDllXformDqs1 = 0x00014002;
+SDRAM[3].EmcDllXformDqs2 = 0x0000c002;
+SDRAM[3].EmcDllXformDqs3 = 0x00014002;
+SDRAM[3].EmcDllXformDqs4 = 0x00014000;
+SDRAM[3].EmcDllXformDqs5 = 0x00014000;
+SDRAM[3].EmcDllXformDqs6 = 0x00014000;
+SDRAM[3].EmcDllXformDqs7 = 0x00014000;
+SDRAM[3].EmcDllXformQUse0 = 0x00000000;
+SDRAM[3].EmcDllXformQUse1 = 0x00000000;
+SDRAM[3].EmcDllXformQUse2 = 0x00000000;
+SDRAM[3].EmcDllXformQUse3 = 0x00000000;
+SDRAM[3].EmcDllXformQUse4 = 0x00000000;
+SDRAM[3].EmcDllXformQUse5 = 0x00000000;
+SDRAM[3].EmcDllXformQUse6 = 0x00000000;
+SDRAM[3].EmcDllXformQUse7 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[3].EmcDllXformDq0 = 0x00018000;
+SDRAM[3].EmcDllXformDq1 = 0x00018000;
+SDRAM[3].EmcDllXformDq2 = 0x00018000;
+SDRAM[3].EmcDllXformDq3 = 0x00018000;
+SDRAM[3].WarmBootWait = 0x00000002;
+SDRAM[3].EmcCttTermCtrl = 0x00000802;
+SDRAM[3].EmcOdtWrite = 0x00000000;
+SDRAM[3].EmcOdtRead = 0x00000000;
+SDRAM[3].EmcZcalInterval = 0x00020000;
+SDRAM[3].EmcZcalWaitCnt = 0x00000040;
+SDRAM[3].EmcZcalMrwCmd = 0x80000000;
+SDRAM[3].EmcMrsResetDll = 0x00000000;
+SDRAM[3].EmcZcalInitDev0 = 0x80000011;
+SDRAM[3].EmcZcalInitDev1 = 0x00000000;
+SDRAM[3].EmcZcalInitWait = 0x00000002;
+SDRAM[3].EmcZcalColdBootEnable = 0x00000001;
+SDRAM[3].EmcZcalWarmBootEnable = 0x00000001;
+SDRAM[3].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab;
+SDRAM[3].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[3].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[3].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[3].EmcMrsResetDllWait = 0x00000000;
+SDRAM[3].EmcEmrsEmr2 = 0x80200000;
+SDRAM[3].EmcEmrsEmr3 = 0x80300000;
+SDRAM[3].EmcMrsExtra = 0x80000521;
+SDRAM[3].EmcWarmBootMrs = 0x80100002;
+SDRAM[3].EmcWarmBootEmrs = 0x80000521;
+SDRAM[3].EmcWarmBootEmr2 = 0x80200000;
+SDRAM[3].EmcWarmBootEmr3 = 0x80300000;
+SDRAM[3].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[3].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[3].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[3].EmcDdr2Wait = 0x00000000;
+SDRAM[3].EmcClkenOverride = 0x00000000;
+SDRAM[3].EmcExtraRefreshNum = 0x00000002;
+SDRAM[3].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[3].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[3].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[3].PmcVddpSel = 0x00000002;
+SDRAM[3].PmcDdrPwr = 0x00000003;
+SDRAM[3].PmcDdrCfg = 0x00000002;
+SDRAM[3].PmcIoDpdReq = 0x80800000;
+SDRAM[3].PmcENoVttGen = 0x00000000;
+SDRAM[3].PmcNoIoPower = 0x00000000;
+SDRAM[3].EmcXm2CmdPadCtrl = 0x000002a0;
+SDRAM[3].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[3].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[3].EmcXm2DqsPadCtrl2 = 0x0a00013d;
+SDRAM[3].EmcXm2DqsPadCtrl3 = 0x08000021;
+SDRAM[3].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[3].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[3].EmcXm2ClkPadCtrl = 0x77fff884;
+SDRAM[3].EmcXm2CompPadCtrl = 0x01f1f508;
+SDRAM[3].EmcXm2VttGenPadCtrl = 0x05057404;
+SDRAM[3].EmcXm2VttGenPadCtrl2 = 0x54000007;
+SDRAM[3].EmcXm2QUsePadCtrl = 0x080001e8;
+SDRAM[3].McEmemAdrCfg = 0x00000000;
+SDRAM[3].McEmemAdrCfgDev0 = 0x00080303;
+SDRAM[3].McEmemAdrCfgDev1 = 0x00080303;
+SDRAM[3].McEmemCfg = 0x00000400;
+SDRAM[3].McEmemArbCfg = 0x00000006;
+SDRAM[3].McEmemArbOutstandingReq = 0x80000048;
+SDRAM[3].McEmemArbTimingRcd = 0x00000001;
+SDRAM[3].McEmemArbTimingRp = 0x00000002;
+SDRAM[3].McEmemArbTimingRc = 0x00000009;
+SDRAM[3].McEmemArbTimingRas = 0x00000005;
+SDRAM[3].McEmemArbTimingFaw = 0x00000007;
+SDRAM[3].McEmemArbTimingRrd = 0x00000001;
+SDRAM[3].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[3].McEmemArbTimingWap2Pre = 0x00000008;
+SDRAM[3].McEmemArbTimingR2R = 0x00000002;
+SDRAM[3].McEmemArbTimingW2W = 0x00000002;
+SDRAM[3].McEmemArbTimingR2W = 0x00000003;
+SDRAM[3].McEmemArbTimingW2R = 0x00000006;
+SDRAM[3].McEmemArbDaTurns = 0x06030202;
+SDRAM[3].McEmemArbDaCovers = 0x000d0709;
+SDRAM[3].McEmemArbMisc0 = 0x7086120a;
+SDRAM[3].McEmemArbMisc1 = 0x78000000;
+SDRAM[3].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[3].McEmemArbOverride = 0x00000080;
+SDRAM[3].McEmemArbRsv = 0xff00ff00;
+SDRAM[3].McClkenOverride = 0x00000000;
--
2.0.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [cbootimage-configs PATCH] Update colibri_t30 BCT to use all SDRAM entries
[not found] ` <1407311217-1742-1-git-send-email-stefan-XLVq0VzYD2Y@public.gmane.org>
@ 2014-08-06 16:12 ` Stephen Warren
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Warren @ 2014-08-06 16:12 UTC (permalink / raw)
To: Stefan Agner, twarren-DDmLM1+adcrQT0dZR+AlfA
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
marcel-mitwqZ+T+m9Wk0Htik3J/w, dev-8ppwABl0HbeELgA04lAiVw
On 08/06/2014 01:46 AM, Stefan Agner wrote:
> Use all SDRAM entries to make sure in any case a valid configuration
> is selected.
I've applied this.
I would have expected the COM itself to define the SDRAM straps, and
hence only SDRAM configuration 0 would ever be used. Still, this patch
is fine either way.
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2014-08-06 16:12 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-08-06 7:46 [cbootimage-configs PATCH] Update colibri_t30 BCT to use all SDRAM entries Stefan Agner
[not found] ` <1407311217-1742-1-git-send-email-stefan-XLVq0VzYD2Y@public.gmane.org>
2014-08-06 16:12 ` Stephen Warren
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