All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] drm/i915: Continuation of future readiness series
@ 2014-08-08 11:39 sonika.jindal
  2014-08-08 11:55 ` Ville Syrjälä
  0 siblings, 1 reply; 5+ messages in thread
From: sonika.jindal @ 2014-08-08 11:39 UTC (permalink / raw)
  To: intel-gfx

From: Sonika Jindal <sonika.jindal@intel.com>

Removing the check for HAS_PCH_SPLIT, it looks redundant here. Anyways all the
platforms are checked separately.

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   40 ++++++++++++++++------------------
 1 file changed, 19 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 89e0ac5..5a3e239 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12421,27 +12421,25 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.get_display_clock_speed =
 			i830_get_display_clock_speed;
 
-	if (HAS_PCH_SPLIT(dev)) {
-		if (IS_GEN5(dev)) {
-			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
-			dev_priv->display.write_eld = ironlake_write_eld;
-		} else if (IS_GEN6(dev)) {
-			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
-			dev_priv->display.write_eld = ironlake_write_eld;
-			dev_priv->display.modeset_global_resources =
-				snb_modeset_global_resources;
-		} else if (IS_IVYBRIDGE(dev)) {
-			/* FIXME: detect B0+ stepping and use auto training */
-			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
-			dev_priv->display.write_eld = ironlake_write_eld;
-			dev_priv->display.modeset_global_resources =
-				ivb_modeset_global_resources;
-		} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
-			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
-			dev_priv->display.write_eld = haswell_write_eld;
-			dev_priv->display.modeset_global_resources =
-				haswell_modeset_global_resources;
-		}
+	if (IS_GEN5(dev)) {
+		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
+		dev_priv->display.write_eld = ironlake_write_eld;
+	} else if (IS_GEN6(dev)) {
+		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+		dev_priv->display.write_eld = ironlake_write_eld;
+		dev_priv->display.modeset_global_resources =
+			snb_modeset_global_resources;
+	} else if (IS_IVYBRIDGE(dev)) {
+		/* FIXME: detect B0+ stepping and use auto training */
+		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+		dev_priv->display.write_eld = ironlake_write_eld;
+		dev_priv->display.modeset_global_resources =
+			ivb_modeset_global_resources;
+	} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
+		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
+		dev_priv->display.write_eld = haswell_write_eld;
+		dev_priv->display.modeset_global_resources =
+			haswell_modeset_global_resources;
 	} else if (IS_G4X(dev)) {
 		dev_priv->display.write_eld = g4x_write_eld;
 	} else if (IS_VALLEYVIEW(dev)) {
-- 
1.7.10.4

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Continuation of future readiness series
  2014-08-08 11:39 [PATCH] drm/i915: Continuation of future readiness series sonika.jindal
@ 2014-08-08 11:55 ` Ville Syrjälä
  2014-08-08 14:15   ` Daniel Vetter
  0 siblings, 1 reply; 5+ messages in thread
From: Ville Syrjälä @ 2014-08-08 11:55 UTC (permalink / raw)
  To: sonika.jindal; +Cc: intel-gfx

On Fri, Aug 08, 2014 at 05:09:14PM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
> 
> Removing the check for HAS_PCH_SPLIT, it looks redundant here. Anyways all the
> platforms are checked separately.
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   40 ++++++++++++++++------------------
>  1 file changed, 19 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 89e0ac5..5a3e239 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12421,27 +12421,25 @@ static void intel_init_display(struct drm_device *dev)
>  		dev_priv->display.get_display_clock_speed =
>  			i830_get_display_clock_speed;
>  
> -	if (HAS_PCH_SPLIT(dev)) {
> -		if (IS_GEN5(dev)) {
> -			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
> -			dev_priv->display.write_eld = ironlake_write_eld;
> -		} else if (IS_GEN6(dev)) {
> -			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> -			dev_priv->display.write_eld = ironlake_write_eld;
> -			dev_priv->display.modeset_global_resources =
> -				snb_modeset_global_resources;
> -		} else if (IS_IVYBRIDGE(dev)) {
> -			/* FIXME: detect B0+ stepping and use auto training */
> -			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> -			dev_priv->display.write_eld = ironlake_write_eld;
> -			dev_priv->display.modeset_global_resources =
> -				ivb_modeset_global_resources;
> -		} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
> -			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> -			dev_priv->display.write_eld = haswell_write_eld;
> -			dev_priv->display.modeset_global_resources =
> -				haswell_modeset_global_resources;
> -		}
> +	if (IS_GEN5(dev)) {
> +		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
> +		dev_priv->display.write_eld = ironlake_write_eld;
> +	} else if (IS_GEN6(dev)) {
> +		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> +		dev_priv->display.write_eld = ironlake_write_eld;
> +		dev_priv->display.modeset_global_resources =
> +			snb_modeset_global_resources;
> +	} else if (IS_IVYBRIDGE(dev)) {
> +		/* FIXME: detect B0+ stepping and use auto training */
> +		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> +		dev_priv->display.write_eld = ironlake_write_eld;
> +		dev_priv->display.modeset_global_resources =
> +			ivb_modeset_global_resources;
> +	} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
> +		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> +		dev_priv->display.write_eld = haswell_write_eld;
> +		dev_priv->display.modeset_global_resources =
> +			haswell_modeset_global_resources;

Maybe shuffle these around a bit while you're at it so that the checks
would be roughly in gen order.

>  	} else if (IS_G4X(dev)) {
>  		dev_priv->display.write_eld = g4x_write_eld;
>  	} else if (IS_VALLEYVIEW(dev)) {
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Continuation of future readiness series
  2014-08-08 11:55 ` Ville Syrjälä
@ 2014-08-08 14:15   ` Daniel Vetter
  2014-08-11  3:36     ` [PATCH v2] " sonika.jindal
  0 siblings, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2014-08-08 14:15 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Fri, Aug 08, 2014 at 02:55:10PM +0300, Ville Syrjälä wrote:
> On Fri, Aug 08, 2014 at 05:09:14PM +0530, sonika.jindal@intel.com wrote:
> > From: Sonika Jindal <sonika.jindal@intel.com>
> > 
> > Removing the check for HAS_PCH_SPLIT, it looks redundant here. Anyways all the
> > platforms are checked separately.
> > 
> > Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |   40 ++++++++++++++++------------------
> >  1 file changed, 19 insertions(+), 21 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 89e0ac5..5a3e239 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -12421,27 +12421,25 @@ static void intel_init_display(struct drm_device *dev)
> >  		dev_priv->display.get_display_clock_speed =
> >  			i830_get_display_clock_speed;
> >  
> > -	if (HAS_PCH_SPLIT(dev)) {
> > -		if (IS_GEN5(dev)) {
> > -			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
> > -			dev_priv->display.write_eld = ironlake_write_eld;
> > -		} else if (IS_GEN6(dev)) {
> > -			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> > -			dev_priv->display.write_eld = ironlake_write_eld;
> > -			dev_priv->display.modeset_global_resources =
> > -				snb_modeset_global_resources;
> > -		} else if (IS_IVYBRIDGE(dev)) {
> > -			/* FIXME: detect B0+ stepping and use auto training */
> > -			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> > -			dev_priv->display.write_eld = ironlake_write_eld;
> > -			dev_priv->display.modeset_global_resources =
> > -				ivb_modeset_global_resources;
> > -		} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
> > -			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> > -			dev_priv->display.write_eld = haswell_write_eld;
> > -			dev_priv->display.modeset_global_resources =
> > -				haswell_modeset_global_resources;
> > -		}
> > +	if (IS_GEN5(dev)) {
> > +		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
> > +		dev_priv->display.write_eld = ironlake_write_eld;
> > +	} else if (IS_GEN6(dev)) {
> > +		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> > +		dev_priv->display.write_eld = ironlake_write_eld;
> > +		dev_priv->display.modeset_global_resources =
> > +			snb_modeset_global_resources;
> > +	} else if (IS_IVYBRIDGE(dev)) {
> > +		/* FIXME: detect B0+ stepping and use auto training */
> > +		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> > +		dev_priv->display.write_eld = ironlake_write_eld;
> > +		dev_priv->display.modeset_global_resources =
> > +			ivb_modeset_global_resources;
> > +	} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
> > +		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> > +		dev_priv->display.write_eld = haswell_write_eld;
> > +		dev_priv->display.modeset_global_resources =
> > +			haswell_modeset_global_resources;
> 
> Maybe shuffle these around a bit while you're at it so that the checks
> would be roughly in gen order.

Agreed, that might be useful while we touch the code. There's no
preference over newer-first or older-first ordering, so you can pick what
you like. G4X = gen4.5, so oldest platform that supports DP.
-Daniel

> 
> >  	} else if (IS_G4X(dev)) {
> >  		dev_priv->display.write_eld = g4x_write_eld;
> >  	} else if (IS_VALLEYVIEW(dev)) {
> > -- 
> > 1.7.10.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH v2] drm/i915: Continuation of future readiness series
  2014-08-08 14:15   ` Daniel Vetter
@ 2014-08-11  3:36     ` sonika.jindal
  2014-08-11  9:27       ` Daniel Vetter
  0 siblings, 1 reply; 5+ messages in thread
From: sonika.jindal @ 2014-08-11  3:36 UTC (permalink / raw)
  To: intel-gfx

From: Sonika Jindal <sonika.jindal@intel.com>

Removing the check for HAS_PCH_SPLIT, it looks redundant here. Anyways all the
platforms are checked separately.

v2: Reordering as per the gen (Ville)

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   42 ++++++++++++++++------------------
 1 file changed, 20 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 89e0ac5..7e0b68a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12421,29 +12421,27 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.get_display_clock_speed =
 			i830_get_display_clock_speed;
 
-	if (HAS_PCH_SPLIT(dev)) {
-		if (IS_GEN5(dev)) {
-			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
-			dev_priv->display.write_eld = ironlake_write_eld;
-		} else if (IS_GEN6(dev)) {
-			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
-			dev_priv->display.write_eld = ironlake_write_eld;
-			dev_priv->display.modeset_global_resources =
-				snb_modeset_global_resources;
-		} else if (IS_IVYBRIDGE(dev)) {
-			/* FIXME: detect B0+ stepping and use auto training */
-			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
-			dev_priv->display.write_eld = ironlake_write_eld;
-			dev_priv->display.modeset_global_resources =
-				ivb_modeset_global_resources;
-		} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
-			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
-			dev_priv->display.write_eld = haswell_write_eld;
-			dev_priv->display.modeset_global_resources =
-				haswell_modeset_global_resources;
-		}
-	} else if (IS_G4X(dev)) {
+	if (IS_G4X(dev)) {
 		dev_priv->display.write_eld = g4x_write_eld;
+	} else if (IS_GEN5(dev)) {
+		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
+		dev_priv->display.write_eld = ironlake_write_eld;
+	} else if (IS_GEN6(dev)) {
+		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+		dev_priv->display.write_eld = ironlake_write_eld;
+		dev_priv->display.modeset_global_resources =
+			snb_modeset_global_resources;
+	} else if (IS_IVYBRIDGE(dev)) {
+		/* FIXME: detect B0+ stepping and use auto training */
+		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+		dev_priv->display.write_eld = ironlake_write_eld;
+		dev_priv->display.modeset_global_resources =
+			ivb_modeset_global_resources;
+	} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
+		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
+		dev_priv->display.write_eld = haswell_write_eld;
+		dev_priv->display.modeset_global_resources =
+			haswell_modeset_global_resources;
 	} else if (IS_VALLEYVIEW(dev)) {
 		dev_priv->display.modeset_global_resources =
 			valleyview_modeset_global_resources;
-- 
1.7.10.4

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/i915: Continuation of future readiness series
  2014-08-11  3:36     ` [PATCH v2] " sonika.jindal
@ 2014-08-11  9:27       ` Daniel Vetter
  0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2014-08-11  9:27 UTC (permalink / raw)
  To: sonika.jindal; +Cc: intel-gfx

On Mon, Aug 11, 2014 at 09:06:39AM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
> 
> Removing the check for HAS_PCH_SPLIT, it looks redundant here. Anyways all the
> platforms are checked separately.
> 
> v2: Reordering as per the gen (Ville)
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>

Queued for -next, thanks for the patch.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c |   42 ++++++++++++++++------------------
>  1 file changed, 20 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 89e0ac5..7e0b68a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12421,29 +12421,27 @@ static void intel_init_display(struct drm_device *dev)
>  		dev_priv->display.get_display_clock_speed =
>  			i830_get_display_clock_speed;
>  
> -	if (HAS_PCH_SPLIT(dev)) {
> -		if (IS_GEN5(dev)) {
> -			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
> -			dev_priv->display.write_eld = ironlake_write_eld;
> -		} else if (IS_GEN6(dev)) {
> -			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> -			dev_priv->display.write_eld = ironlake_write_eld;
> -			dev_priv->display.modeset_global_resources =
> -				snb_modeset_global_resources;
> -		} else if (IS_IVYBRIDGE(dev)) {
> -			/* FIXME: detect B0+ stepping and use auto training */
> -			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> -			dev_priv->display.write_eld = ironlake_write_eld;
> -			dev_priv->display.modeset_global_resources =
> -				ivb_modeset_global_resources;
> -		} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
> -			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> -			dev_priv->display.write_eld = haswell_write_eld;
> -			dev_priv->display.modeset_global_resources =
> -				haswell_modeset_global_resources;
> -		}
> -	} else if (IS_G4X(dev)) {
> +	if (IS_G4X(dev)) {
>  		dev_priv->display.write_eld = g4x_write_eld;
> +	} else if (IS_GEN5(dev)) {
> +		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
> +		dev_priv->display.write_eld = ironlake_write_eld;
> +	} else if (IS_GEN6(dev)) {
> +		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> +		dev_priv->display.write_eld = ironlake_write_eld;
> +		dev_priv->display.modeset_global_resources =
> +			snb_modeset_global_resources;
> +	} else if (IS_IVYBRIDGE(dev)) {
> +		/* FIXME: detect B0+ stepping and use auto training */
> +		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> +		dev_priv->display.write_eld = ironlake_write_eld;
> +		dev_priv->display.modeset_global_resources =
> +			ivb_modeset_global_resources;
> +	} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
> +		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> +		dev_priv->display.write_eld = haswell_write_eld;
> +		dev_priv->display.modeset_global_resources =
> +			haswell_modeset_global_resources;
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		dev_priv->display.modeset_global_resources =
>  			valleyview_modeset_global_resources;
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2014-08-11  9:27 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-08-08 11:39 [PATCH] drm/i915: Continuation of future readiness series sonika.jindal
2014-08-08 11:55 ` Ville Syrjälä
2014-08-08 14:15   ` Daniel Vetter
2014-08-11  3:36     ` [PATCH v2] " sonika.jindal
2014-08-11  9:27       ` Daniel Vetter

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.