[U-Boot] [PATCH V4 00/19] Introduce cm-fx6 board

[U-Boot] [PATCH V4 00/19] Introduce cm-fx6 board

[Nikita Kiryanov]

This patch series introduces the mx6 based cm-fx6 board.
cm-fx6 comes with either single, dual, or quad core mx6 soc, and various dram
configurations.

First 12 patches are preparatory steps which include:
	- Cleanups and bug fixes for the mx6 dram config code
	- New functions and macros for enabling clocks, i2c setup, querying
	  the status of sata port, and more
	- Support for M25PE16 and M25PX16 spi flashes
	- sf probe command fix when using mxc_spi driver

NOTE: the correctness of this series depends on https://patchwork.ozlabs.org/patch/376095/

Changes in V4:
	- Rebase whole series over latest code (commit e49f14af1349eef94e41b636320bbfcace7403b5)
	- Patch "arm: mx6: add get_cpu_type()" is new to the series.
	- Adapt to use Kconfig
	- Initialize all ddr related structs statically
	- Don't #define CONFIG_SYS_L2CACHE_OFF for cm_fx6
	- Use load instead of fatload in environment scripts
	- Refactoring across board support patches (introduce some functions
	  in later patches, move/remove variables, coding style, etc. etc.);
	  Details in the patches

Changes in V3:
	- Remove CONFIG_SYS_TEXT_BASE from config file to not clash with the
	  one supplied by imx6_spl.h
	- Use (clr|set)bits_le32() where possible

Changes in V2:
	- Patch "spl: improve spi configuration" is replaced with "spl: replace
	  CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*", which kills CONFIG_SPL_SPI_*
	  defines in favor of using CONFIG_SF_DEFAULT_*.
	- Updated commit message of "sf: fix sf probe", renaming it in the process
	  to "spi: mxc: fix sf probe when using mxc_spi".
	- Return value handling.
	- Update commit message of "arm: mx6: ddr: configure MMDC for slow_pd"
	- Remove unnecessary line removal from arch/arm/cpu/armv7/mx6/ddr.c
	- Move probe_mmdc_config() code straight to dram_init()
	- Use imx6_spl.h
	- Use imx_ddr_size()

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>

Nikita Kiryanov (19):
  spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*
  mx6: add clock enabling functions
  spi: mxc: fix sf probe when using mxc_spi
  mtd: spi: add support for M25PE16 and M25PX16
  compulab: eeprom: add support for defining eeprom i2c bus
  sata: dwc_ahsata: implement sata_port_status
  i2c: imx: add macros to setup pads for multiple SoC types
  arm: mx6: ddr: cleanup
  arm: mx6: ddr: do not write into reserved bit
  arm: mx6: ddr: configure MMDC for slow_pd
  arm: mx6: ddr: fix cs0_end calculation
  arm: mx6: add get_cpu_type()
  arm: mx6: add support for Compulab cm-fx6 CoM
  arm: mx6: cm_fx6: add nand support
  arm: mx6: cm_fx6: add ethernet support
  arm: mx6: cm_fx6: add usb support
  arm: mx6: cm_fx6: add i2c support
  arm: mx6: cm_fx6: use eeprom
  arm: mx6: cm_fx6: add sata support

 arch/arm/Kconfig                              |   4 +
 arch/arm/cpu/armv7/mx6/clock.c                |  90 +++++
 arch/arm/cpu/armv7/mx6/ddr.c                  | 271 +++++++--------
 arch/arm/include/asm/arch-mx6/clock.h         |   5 +
 arch/arm/include/asm/arch-mx6/sys_proto.h     |   5 +-
 arch/arm/include/asm/imx-common/mxc_i2c.h     |  33 ++
 board/boundary/nitrogen6x/nitrogen6x.c        |   5 +
 board/compulab/cm_fx6/Kconfig                 |  23 ++
 board/compulab/cm_fx6/MAINTAINERS             |   6 +
 board/compulab/cm_fx6/Makefile                |  12 +
 board/compulab/cm_fx6/cm_fx6.c                | 483 ++++++++++++++++++++++++++
 board/compulab/cm_fx6/common.c                |  84 +++++
 board/compulab/cm_fx6/common.h                |  37 ++
 board/compulab/cm_fx6/imximage.cfg            |   8 +
 board/compulab/cm_fx6/spl.c                   | 366 +++++++++++++++++++
 board/compulab/common/eeprom.c                |  13 +-
 board/embest/mx6boards/mx6boards.c            |   5 +
 board/freescale/mx6qsabreauto/mx6qsabreauto.c |   7 +
 board/freescale/mx6sabresd/mx6sabresd.c       |   7 +
 board/freescale/mx6slevk/mx6slevk.c           |   5 +
 board/gateworks/gw_ventana/gw_ventana.c       |   7 +-
 board/genesi/mx51_efikamx/efikamx.c           |   5 +
 board/ttcontrol/vision2/vision2.c             |   5 +
 common/cmd_sf.c                               |  13 -
 configs/cm_fx6_defconfig                      |   4 +
 drivers/block/dwc_ahsata.c                    |  17 +
 drivers/mtd/spi/sf_params.c                   |   2 +
 drivers/mtd/spi/spi_spl_load.c                |   6 +-
 drivers/spi/mxc_spi.c                         |  48 +--
 include/configs/am335x_evm.h                  |   2 -
 include/configs/cm_fx6.h                      | 290 ++++++++++++++++
 include/configs/cm_t335.h                     |   1 +
 include/configs/cm_t35.h                      |   1 +
 include/configs/cm_t54.h                      |   1 +
 include/configs/da850evm.h                    |   4 -
 include/configs/dra7xx_evm.h                  |   2 -
 include/configs/embestmx6boards.h             |   2 +-
 include/configs/gw_ventana.h                  |   2 +-
 include/configs/ks2_evm.h                     |   2 -
 include/configs/mx51_efikamx.h                |   4 +-
 include/configs/mx6sabre_common.h             |   2 +-
 include/configs/mx6slevk.h                    |   2 +-
 include/configs/nitrogen6x.h                  |   2 +-
 include/configs/pcm051.h                      |   2 -
 include/configs/sama5d3xek.h                  |   2 -
 include/configs/siemens-am33x-common.h        |   2 -
 include/configs/tseries.h                     |   2 -
 include/configs/vision2.h                     |   4 +-
 include/configs/zynq-common.h                 |   2 -
 include/sata.h                                |   1 +
 include/spi_flash.h                           |  13 +
 51 files changed, 1712 insertions(+), 209 deletions(-)
 create mode 100644 board/compulab/cm_fx6/Kconfig
 create mode 100644 board/compulab/cm_fx6/MAINTAINERS
 create mode 100644 board/compulab/cm_fx6/Makefile
 create mode 100644 board/compulab/cm_fx6/cm_fx6.c
 create mode 100644 board/compulab/cm_fx6/common.c
 create mode 100644 board/compulab/cm_fx6/common.h
 create mode 100644 board/compulab/cm_fx6/imximage.cfg
 create mode 100644 board/compulab/cm_fx6/spl.c
 create mode 100644 configs/cm_fx6_defconfig
 create mode 100644 include/configs/cm_fx6.h

-- 
1.9.1

[U-Boot] [PATCH V4 01/19] spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*

[Nikita Kiryanov]

Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
SPL. These #defines do not allow the user to select SPI mode for the SPI flash
(there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
spi_spl_load.c), and duplicate information already provided by
CONFIG_SF_DEFAULT_* #defines.

Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.

Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Hannes Petermaier <hannes.petermaier@br-automation.com>
Cc: Michal Simek <monstr@monstr.eu>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes

Changes in V3:
	- No changes

Changes in V2:
	- New patch replacing "spl: improve spi configuration".

 common/cmd_sf.c                        | 13 -------------
 drivers/mtd/spi/spi_spl_load.c         |  6 ++++--
 include/configs/am335x_evm.h           |  2 --
 include/configs/da850evm.h             |  4 ----
 include/configs/dra7xx_evm.h           |  2 --
 include/configs/ks2_evm.h              |  2 --
 include/configs/pcm051.h               |  2 --
 include/configs/sama5d3xek.h           |  2 --
 include/configs/siemens-am33x-common.h |  2 --
 include/configs/tseries.h              |  2 --
 include/configs/zynq-common.h          |  2 --
 include/spi_flash.h                    | 13 +++++++++++++
 12 files changed, 17 insertions(+), 35 deletions(-)

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index b4ceb71..c60e8d1 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -13,19 +13,6 @@
 
 #include <asm/io.h>
 
-#ifndef CONFIG_SF_DEFAULT_SPEED
-# define CONFIG_SF_DEFAULT_SPEED	1000000
-#endif
-#ifndef CONFIG_SF_DEFAULT_MODE
-# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
-#endif
-#ifndef CONFIG_SF_DEFAULT_CS
-# define CONFIG_SF_DEFAULT_CS		0
-#endif
-#ifndef CONFIG_SF_DEFAULT_BUS
-# define CONFIG_SF_DEFAULT_BUS		0
-#endif
-
 static struct spi_flash *flash;
 
 
diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
index 1954b7e..59cca0f 100644
--- a/drivers/mtd/spi/spi_spl_load.c
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -56,8 +56,10 @@ void spl_spi_load_image(void)
 	 * Load U-Boot image from SPI flash into RAM
 	 */
 
-	flash = spi_flash_probe(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS,
-				CONFIG_SF_DEFAULT_SPEED, SPI_MODE_3);
+	flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
+				CONFIG_SF_DEFAULT_CS,
+				CONFIG_SF_DEFAULT_SPEED,
+				CONFIG_SF_DEFAULT_MODE);
 	if (!flash) {
 		puts("SPI probe failed.\n");
 		hang();
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 35ae0e6..750aedd 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -381,8 +381,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 
 #define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 1252d7a..5f85755 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -157,8 +157,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
 #define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
 #endif
@@ -376,8 +374,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 8d0a0eb..0f91ef8 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -115,8 +115,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_BUS             0
-#define CONFIG_SPL_SPI_CS              0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000
 
 #define CONFIG_SUPPORT_EMMC_BOOT
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index 43db581..51926f7 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -58,8 +58,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
 #define CONFIG_SPL_FRAMEWORK
 
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index dcf5537..19ce121 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -232,8 +232,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 #define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index 56c2454..da545c4 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -287,8 +287,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8400
 
 #endif
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index b8fb77e..bf9752f 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -167,8 +167,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index 1fd6e32..2497a1e 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -222,8 +222,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 #undef CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index d57e9d5..b49de25 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -304,9 +304,7 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_BUS	0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x100000
-#define CONFIG_SPL_SPI_CS	0
 #endif
 
 /* for booting directly linux */
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 2db53c7..43f7f2c 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -19,6 +19,19 @@
 #include <linux/types.h>
 #include <linux/compiler.h>
 
+#ifndef CONFIG_SF_DEFAULT_SPEED
+	#define CONFIG_SF_DEFAULT_SPEED		1000000
+#endif
+#ifndef CONFIG_SF_DEFAULT_MODE
+	#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+#endif
+#ifndef CONFIG_SF_DEFAULT_CS
+	#define CONFIG_SF_DEFAULT_CS		0
+#endif
+#ifndef CONFIG_SF_DEFAULT_BUS
+	#define CONFIG_SF_DEFAULT_BUS		0
+#endif
+
 /* sf param flags */
 #define SECT_4K		1 << 1
 #define SECT_32K	1 << 2
-- 
1.9.1

[U-Boot] [PATCH V4 02/19] mx6: add clock enabling functions

[Nikita Kiryanov]

Add functions to enable/disable clocks for UART, SPI, ENET, and MMC.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes.

Changes in V3:
	- Use (clr|set)bits_le32() where possible

Changes in V2:
	- No changes.

 arch/arm/cpu/armv7/mx6/clock.c        | 90 +++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/clock.h |  5 ++
 2 files changed, 95 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 7dd83ec..034a005 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -36,6 +36,35 @@ void enable_ocotp_clk(unsigned char enable)
 }
 #endif
 
+#ifdef CONFIG_NAND_MXS
+void setup_gpmi_io_clk(u32 cfg)
+{
+	/* Disable clocks per ERR007177 from MX6 errata */
+	clrbits_le32(&imx_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+	clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+	clrsetbits_le32(&imx_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+			cfg);
+
+	setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+	setbits_le32(&imx_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+}
+#endif
+
 void enable_usboh3_clk(unsigned char enable)
 {
 	u32 reg;
@@ -49,6 +78,67 @@ void enable_usboh3_clk(unsigned char enable)
 
 }
 
+#ifdef CONFIG_FEC_MXC
+void enable_enet_clk(unsigned char enable)
+{
+	u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
+
+	if (enable)
+		setbits_le32(&imx_ccm->CCGR1, mask);
+	else
+		clrbits_le32(&imx_ccm->CCGR1, mask);
+}
+#endif
+
+#ifdef CONFIG_MXC_UART
+void enable_uart_clk(unsigned char enable)
+{
+	u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
+
+	if (enable)
+		setbits_le32(&imx_ccm->CCGR5, mask);
+	else
+		clrbits_le32(&imx_ccm->CCGR5, mask);
+}
+#endif
+
+#ifdef CONFIG_SPI
+/* spi_num can be from 0 - 4 */
+int enable_cspi_clock(unsigned char enable, unsigned spi_num)
+{
+	u32 mask;
+
+	if (spi_num > 4)
+		return -EINVAL;
+
+	mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
+	if (enable)
+		setbits_le32(&imx_ccm->CCGR1, mask);
+	else
+		clrbits_le32(&imx_ccm->CCGR1, mask);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MMC
+int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
+{
+	u32 mask;
+
+	if (bus_num > 3)
+		return -EINVAL;
+
+	mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
+	if (enable)
+		setbits_le32(&imx_ccm->CCGR6, mask);
+	else
+		clrbits_le32(&imx_ccm->CCGR6, mask);
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_SYS_I2C_MXC
 /* i2c_num can be from 0 - 2 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 1b4ded7..f0b728b 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -52,11 +52,16 @@ enum enet_freq {
 u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
+void setup_gpmi_io_clk(u32 cfg);
 void enable_ocotp_clk(unsigned char enable);
 void enable_usboh3_clk(unsigned char enable);
+void enable_uart_clk(unsigned char enable);
+int enable_cspi_clock(unsigned char enable, unsigned spi_num);
+int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
 int enable_sata_clock(void);
 int enable_pcie_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
+void enable_enet_clk(unsigned char enable);
 #endif /* __ASM_ARCH_CLOCK_H */
-- 
1.9.1

[U-Boot] [PATCH V4 03/19] spi: mxc: fix sf probe when using mxc_spi

[Nikita Kiryanov]

MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:

cs = (cs | gpio << 8)

This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".

This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.

Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.

Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes.

Changes in V3:
	- No changes.

Changes in V2:
	- Rewrote commit message, renaming the patch in the process (originally
	  "sf: fix sf probe").

 board/boundary/nitrogen6x/nitrogen6x.c        |  5 +++
 board/embest/mx6boards/mx6boards.c            |  5 +++
 board/freescale/mx6qsabreauto/mx6qsabreauto.c |  7 ++++
 board/freescale/mx6sabresd/mx6sabresd.c       |  7 ++++
 board/freescale/mx6slevk/mx6slevk.c           |  5 +++
 board/gateworks/gw_ventana/gw_ventana.c       |  7 +++-
 board/genesi/mx51_efikamx/efikamx.c           |  5 +++
 board/ttcontrol/vision2/vision2.c             |  5 +++
 drivers/spi/mxc_spi.c                         | 48 ++++++++++++++-------------
 include/configs/embestmx6boards.h             |  2 +-
 include/configs/gw_ventana.h                  |  2 +-
 include/configs/mx51_efikamx.h                |  4 +--
 include/configs/mx6sabre_common.h             |  2 +-
 include/configs/mx6slevk.h                    |  2 +-
 include/configs/nitrogen6x.h                  |  2 +-
 include/configs/vision2.h                     |  4 +--
 16 files changed, 79 insertions(+), 33 deletions(-)

diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 84294db..aadddb9 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -328,6 +328,11 @@ int board_mmc_init(bd_t *bis)
 #endif
 
 #ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
+}
+
 iomux_v3_cfg_t const ecspi1_pads[] = {
 	/* SS1 */
 	MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(NO_PAD_CTRL),
diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
index d06b57d..e8a11c2 100644
--- a/board/embest/mx6boards/mx6boards.c
+++ b/board/embest/mx6boards/mx6boards.c
@@ -284,6 +284,11 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
 	MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
+}
+
 static void setup_spi(void)
 {
 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 928dadf..836d722 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -259,6 +259,13 @@ int board_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index d7c4b4f..c5f10f7 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -513,6 +513,13 @@ static int pfuze_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index d2b64cc..ec63d9e 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -82,6 +82,11 @@ static iomux_v3_cfg_t ecspi1_pads[] = {
 	MX6_PAD_ECSPI1_SS0__GPIO4_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
+}
+
 static void setup_spi(void)
 {
 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 9d2651f..054f904 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -353,9 +353,14 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
 	IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 };
 
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
+}
+
 static void setup_spi(void)
 {
-	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
+	gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 	SETUP_IOMUX_PADS(ecspi1_pads);
 }
 #endif
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
index 16769e5..137e4ed 100644
--- a/board/genesi/mx51_efikamx/efikamx.c
+++ b/board/genesi/mx51_efikamx/efikamx.c
@@ -152,6 +152,11 @@ static iomux_v3_cfg_t const efikamx_spi_pads[] = {
  * PMIC configuration
  */
 #ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 1) ? 121 : -1;
+}
+
 static void power_init(void)
 {
 	unsigned int val;
diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
index b4d3994..b5249e7 100644
--- a/board/ttcontrol/vision2/vision2.c
+++ b/board/ttcontrol/vision2/vision2.c
@@ -144,6 +144,11 @@ static void setup_uart(void)
 }
 
 #ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 1) ? 121 : -1;
+}
+
 void spi_io_init(void)
 {
 	static const iomux_v3_cfg_t spi_pads[] = {
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 2d5f385..026f680 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -25,6 +25,11 @@ static unsigned long spi_bases[] = {
 	MXC_SPI_BASE_ADDRESSES
 };
 
+__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return -1;
+}
+
 #define OUT	MXC_GPIO_DIRECTION_OUT
 
 #define reg_read readl
@@ -371,31 +376,30 @@ void spi_init(void)
 {
 }
 
-static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
+/*
+ * Some SPI devices require active chip-select over multiple
+ * transactions, we achieve this using a GPIO. Still, the SPI
+ * controller has to be configured to use one of its own chipselects.
+ * To use this feature you have to implement board_spi_cs_gpio() to assign
+ * a gpio value for each cs (-1 if cs doesn't need to use gpio).
+ * You must use some unused on this SPI controller cs between 0 and 3.
+ */
+static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
+			 unsigned int bus, unsigned int cs)
 {
 	int ret;
 
-	/*
-	 * Some SPI devices require active chip-select over multiple
-	 * transactions, we achieve this using a GPIO. Still, the SPI
-	 * controller has to be configured to use one of its own chipselects.
-	 * To use this feature you have to call spi_setup_slave() with
-	 * cs = internal_cs | (gpio << 8), and you have to use some unused
-	 * on this SPI controller cs between 0 and 3.
-	 */
-	if (cs > 3) {
-		mxcs->gpio = cs >> 8;
-		cs &= 3;
-		ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
-		if (ret) {
-			printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
-			return -EINVAL;
-		}
-	} else {
-		mxcs->gpio = -1;
+	mxcs->gpio = board_spi_cs_gpio(bus, cs);
+	if (mxcs->gpio == -1)
+		return 0;
+
+	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
+	if (ret) {
+		printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
+		return -EINVAL;
 	}
 
-	return cs;
+	return 0;
 }
 
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
@@ -415,14 +419,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 
 	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
 
-	ret = decode_cs(mxcs, cs);
+	ret = setup_cs_gpio(mxcs, bus, cs);
 	if (ret < 0) {
 		free(mxcs);
 		return NULL;
 	}
 
-	cs = ret;
-
 	mxcs->base = spi_bases[bus];
 
 	ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index f1000f3..bcd5ea4 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -100,7 +100,7 @@
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
-#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(2, 30) << 8))
+#define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED		20000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 8197a72..97398a8 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -61,7 +61,7 @@
   #define CONFIG_SPI_FLASH_BAR
   #define CONFIG_SPI_FLASH_WINBOND
   #define CONFIG_SF_DEFAULT_BUS              0
-  #define CONFIG_SF_DEFAULT_CS               (0|(IMX_GPIO_NR(3, 19)<<8))
+  #define CONFIG_SF_DEFAULT_CS               0
 					     /* GPIO 3-19 (21248) */
   #define CONFIG_SF_DEFAULT_SPEED            30000000
   #define CONFIG_SF_DEFAULT_MODE             (SPI_MODE_0)
diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h
index 0f2a4ef..fce7ead 100644
--- a/include/configs/mx51_efikamx.h
+++ b/include/configs/mx51_efikamx.h
@@ -96,11 +96,11 @@
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_SST
-#define CONFIG_SF_DEFAULT_CS		(1 | 121 << 8)
+#define CONFIG_SF_DEFAULT_CS		1
 #define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
 #define CONFIG_SF_DEFAULT_SPEED		25000000
 
-#define CONFIG_ENV_SPI_CS		(1 | 121 << 8)
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
 #define CONFIG_ENV_SPI_BUS		0
 #define CONFIG_ENV_SPI_MAX_HZ		25000000
 #define CONFIG_ENV_SPI_MODE		(SPI_MODE_0)
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index e59a3b4..2d93d6c 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -74,7 +74,7 @@
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
-#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(4, 9) << 8))
+#define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED		20000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 3d05a64..5b8309b 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -203,7 +203,7 @@
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
-#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(4, 11) << 8))
+#define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED		20000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index b2b17ce..d266f7d 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -53,7 +53,7 @@
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS  0
-#define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(3, 19)<<8))
+#define CONFIG_SF_DEFAULT_CS   0
 #define CONFIG_SF_DEFAULT_SPEED 25000000
 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
 #endif
diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index 6891bf8..3f35076 100644
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -57,11 +57,11 @@
  * Use gpio 4 pin 25 as chip select for SPI flash
  * This corresponds to gpio 121
  */
-#define CONFIG_SF_DEFAULT_CS	(1 | (121 << 8))
+#define CONFIG_SF_DEFAULT_CS	 1
 #define CONFIG_SF_DEFAULT_MODE   SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED  25000000
 
-#define CONFIG_ENV_SPI_CS	(1 | (121 << 8))
+#define CONFIG_ENV_SPI_CS	CONFIG_SF_DEFAULT_CS
 #define CONFIG_ENV_SPI_BUS      0
 #define CONFIG_ENV_SPI_MAX_HZ	25000000
 #define CONFIG_ENV_SPI_MODE	SPI_MODE_0
-- 
1.9.1

[U-Boot] [PATCH V4 04/19] mtd: spi: add support for M25PE16 and M25PX16

[Nikita Kiryanov]

Add support for M25PE16 and M25PX16

Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes.

Changes in V3:
	- No changes.

Changes in V2:
	- No changes.

 drivers/mtd/spi/sf_params.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index ac886fd..3a4beb0 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -68,6 +68,8 @@ const struct spi_flash_params spi_flash_params_table[] = {
 	{"M25P40",	   0x202013, 0x0,       64 * 1024,     8,	0,			  0},
 	{"M25P80",	   0x202014, 0x0,       64 * 1024,    16,	0,			  0},
 	{"M25P16",	   0x202015, 0x0,       64 * 1024,    32,	0,			  0},
+	{"M25PE16",	   0x208015, 0x1000,    64 * 1024,    32,	0,			  0},
+	{"M25PX16",	   0x207115, 0x1000,    64 * 1024,    32, RD_EXTN,			  0},
 	{"M25P32",	   0x202016, 0x0,       64 * 1024,    64,	0,			  0},
 	{"M25P64",	   0x202017, 0x0,       64 * 1024,   128,	0,			  0},
 	{"M25P128",	   0x202018, 0x0,      256 * 1024,    64,	0,			  0},
-- 
1.9.1

[U-Boot] [PATCH V4 05/19] compulab: eeprom: add support for defining eeprom i2c bus

[Nikita Kiryanov]

Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM
module what I2C bus the EEPROM is located at. Make cl_eeprom_read()
switch to that bus when reading EEPROM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Dmitry Lifshitz <lifshitz@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes.

Changes in V3:
	- No changes.

Changes in V2:
	- Check return value of i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS)

 board/compulab/common/eeprom.c | 13 ++++++++++++-
 include/configs/cm_t335.h      |  1 +
 include/configs/cm_t35.h       |  1 +
 include/configs/cm_t54.h       |  1 +
 4 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c
index 20fe3e1..85442cd 100644
--- a/board/compulab/common/eeprom.c
+++ b/board/compulab/common/eeprom.c
@@ -31,8 +31,19 @@ static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */
 
 static int cl_eeprom_read(uint offset, uchar *buf, int len)
 {
-	return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
+	int res;
+	unsigned int current_i2c_bus = i2c_get_bus_num();
+
+	res = i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
+	if (res < 0)
+		return res;
+
+	res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
 			CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len);
+
+	i2c_set_bus_num(current_i2c_bus);
+
+	return res;
 }
 
 static int cl_eeprom_setup_layout(void)
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index a3e6452..767ef3a 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -107,6 +107,7 @@
 /* I2C Configuration */
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
 
 /* SPL */
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index c63608c..174f76b 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -136,6 +136,7 @@
 #define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
 #define CONFIG_I2C_MULTI_BUS
 
 /*
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index db04095..aa97823 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -27,6 +27,7 @@
 #define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
 
 /* Enable SD/MMC CD and WP GPIOs */
 #define OMAP_HSMMC_USE_GPIO
-- 
1.9.1

[U-Boot] [PATCH V4 06/19] sata: dwc_ahsata: implement sata_port_status

[Nikita Kiryanov]

Define the new common function sata_port_status() which can be
used to query the sata driver for the state of ports, and implement it
for dwc_ahsata.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes.

Changes in V3:
	- No changes.

Changes in V2:
	- Use errno values.

 drivers/block/dwc_ahsata.c | 17 +++++++++++++++++
 include/sata.h             |  1 +
 2 files changed, 18 insertions(+)

diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 15d65d7..29f478b 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -864,6 +864,23 @@ u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
 	return blkcnt;
 }
 
+int sata_port_status(int dev, int port)
+{
+	struct sata_port_regs *port_mmio;
+	struct ahci_probe_ent *probe_ent = NULL;
+
+	if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
+		return -EINVAL;
+
+	if (sata_dev_desc[dev].priv == NULL)
+		return -ENODEV;
+
+	probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+	port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio;
+
+	return readl(&(port_mmio->ssts)) && SATA_PORT_SSTS_DET_MASK;
+}
+
 /*
  * SATA interface between low level driver and command layer
  */
diff --git a/include/sata.h b/include/sata.h
index c95dc56..38f4b4a 100644
--- a/include/sata.h
+++ b/include/sata.h
@@ -9,6 +9,7 @@ ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
 
 int sata_initialize(void);
 int __sata_initialize(void);
+int sata_port_status(int dev, int port);
 
 extern block_dev_desc_t sata_dev_desc[];
 
-- 
1.9.1

[U-Boot] [PATCH V4 07/19] i2c: imx: add macros to setup pads for multiple SoC types

[Nikita Kiryanov]

Add macro which defines i2c_pads_info structs for multiple SoC types,
and a macro which selects the appropriate struct based on CPU type,
thus eliminating the need to manage multiple i2c pad configurations
manually when supporting multiple SoC types.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes.

Changes in V3:
	- No changes.

Changes in V2:
	- No changes.

 arch/arm/include/asm/imx-common/mxc_i2c.h | 33 +++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h b/arch/arm/include/asm/imx-common/mxc_i2c.h
index 47a9edc..182c2f3 100644
--- a/arch/arm/include/asm/imx-common/mxc_i2c.h
+++ b/arch/arm/include/asm/imx-common/mxc_i2c.h
@@ -19,6 +19,39 @@ struct i2c_pads_info {
 	struct i2c_pin_ctrl sda;
 };
 
+#if defined(CONFIG_MX6QDL)
+#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
+	struct i2c_pads_info mx6q_##name = {		\
+		.scl = {				\
+			.i2c_mode = MX6Q_##scl_i2c,	\
+			.gpio_mode = MX6Q_##scl_gpio,	\
+			.gp = scl_gp,			\
+		},					\
+		.sda = {				\
+			.i2c_mode = MX6Q_##sda_i2c,	\
+			.gpio_mode = MX6Q_##sda_gpio,	\
+			.gp = sda_gp,			\
+		}					\
+	};						\
+	struct i2c_pads_info mx6s_##name = {		\
+		.scl = {				\
+			.i2c_mode = MX6DL_##scl_i2c,	\
+			.gpio_mode = MX6DL_##scl_gpio,	\
+			.gp = scl_gp,			\
+		},					\
+		.sda = {				\
+			.i2c_mode = MX6DL_##sda_i2c,	\
+			.gpio_mode = MX6DL_##sda_gpio,	\
+			.gp = sda_gp,			\
+		}					\
+	};
+
+
+#define I2C_PADS_INFO(name)	\
+	(is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \
+					&mx6q_##name : &mx6s_##name
+#endif
+
 void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
 		struct i2c_pads_info *p);
 void bus_i2c_init(void *base, int speed, int slave_addr,
-- 
1.9.1

[U-Boot] [PATCH V4 08/19] arm: mx6: ddr: cleanup

[Nikita Kiryanov]

No functional changes.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes.

Changes in V3:
	- No changes.

Changes in V2:
	- No changes.

 arch/arm/cpu/armv7/mx6/ddr.c | 272 +++++++++++++++++++++----------------------
 1 file changed, 134 insertions(+), 138 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 0434211..af91314 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -184,18 +184,18 @@ void mx6sdl_dram_iocfg(unsigned width,
  */
 #define MR(val, ba, cmd, cs1) \
 	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
-void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
-		  const struct mx6_mmdc_calibration *c,
-		  const struct mx6_ddr3_cfg *m)
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
+		  const struct mx6_mmdc_calibration *calib,
+		  const struct mx6_ddr3_cfg *ddr3_cfg)
 {
 	volatile struct mmdc_p_regs *mmdc0;
 	volatile struct mmdc_p_regs *mmdc1;
-	u32 reg;
+	u32 val;
 	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
 	u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
 	u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
 	u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
-	u16 CS0_END;
+	u16 cs0_end;
 	u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
 	int clkper; /* clock period in picoseconds */
 	int clock; /* clock freq in mHz */
@@ -214,13 +214,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 		clock = 400;
 		tcwl = 3;
 	}
-	clkper = (1000*1000)/clock; /* ps */
+	clkper = (1000 * 1000) / clock; /* pico seconds */
 	todtlon = tcwl;
 	taxpd = tcwl;
 	tanpd = tcwl;
-	tcwl = tcwl;
 
-	switch (m->density) {
+	switch (ddr3_cfg->density) {
 	case 1: /* 1Gb per chip */
 		trfc = DIV_ROUND_UP(110000, clkper) - 1;
 		txs = DIV_ROUND_UP(120000, clkper) - 1;
@@ -239,80 +238,84 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 		break;
 	default:
 		/* invalid density */
-		printf("invalid chip density\n");
+		puts("invalid chip density\n");
 		hang();
 		break;
 	}
 	txpr = txs;
 
-	switch (m->mem_speed) {
+	switch (ddr3_cfg->mem_speed) {
 	case 800:
-		txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
-		tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
-		if (m->pagesz == 1) {
+		txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+		tcke = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+		if (ddr3_cfg->pagesz == 1) {
 			tfaw = DIV_ROUND_UP(40000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
 		} else {
 			tfaw = DIV_ROUND_UP(50000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
 		}
 		break;
 	case 1066:
-		txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
-		tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
-		if (m->pagesz == 1) {
+		txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+		tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
+		if (ddr3_cfg->pagesz == 1) {
 			tfaw = DIV_ROUND_UP(37500, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
 		} else {
 			tfaw = DIV_ROUND_UP(50000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
 		}
 		break;
 	case 1333:
-		txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
-		tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
-		if (m->pagesz == 1) {
+		txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
+		tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
+		if (ddr3_cfg->pagesz == 1) {
 			tfaw = DIV_ROUND_UP(30000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
 		} else {
 			tfaw = DIV_ROUND_UP(45000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
 		}
 		break;
 	case 1600:
-		txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
-		tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;
-		if (m->pagesz == 1) {
+		txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
+		tcke = DIV_ROUND_UP(MAX(3 * clkper, 5000), clkper) - 1;
+		if (ddr3_cfg->pagesz == 1) {
 			tfaw = DIV_ROUND_UP(30000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
 		} else {
 			tfaw = DIV_ROUND_UP(40000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
 		}
 		break;
 	default:
-		printf("invalid memory speed\n");
+		puts("invalid memory speed\n");
 		hang();
 		break;
 	}
-	txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;
-	tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;
-	tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
-	tcksrx = tcksre;
+	txpdll = DIV_ROUND_UP(MAX(10 * clkper, 24000), clkper) - 1;
+	tcksre = DIV_ROUND_UP(MAX(5 * clkper, 10000), clkper);
 	taonpd = DIV_ROUND_UP(2000, clkper) - 1;
+	tcksrx = tcksre;
 	taofpd = taonpd;
-	trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
+	twr  = DIV_ROUND_UP(15000, clkper) - 1;
+	tmrd = DIV_ROUND_UP(MAX(12 * clkper, 15000), clkper) - 1;
+	trc  = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
+	tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
+	tcl  = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
+	trp  = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
+	twtr = ROUND(MAX(4 * clkper, 7500) / clkper, 1) - 1;
 	trcd = trp;
-	trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
-	tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
-	twr = DIV_ROUND_UP(15000, clkper) - 1;
-	tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
-	twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
 	trtp = twtr;
-	CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;
-	debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
+	cs0_end = (4 * sysinfo->cs_density <= 120) ?
+		   4 * sysinfo->cs_density + 7 :
+		   127;
+
+	debug("density:%d Gb (%d Gb per chip)\n",
+	      sysinfo->cs_density, ddr3_cfg->density);
 	debug("clock: %dMHz (%d ps)\n", clock, clkper);
-	debug("memspd:%d\n", m->mem_speed);
+	debug("memspd:%d\n", ddr3_cfg->mem_speed);
 	debug("tcke=%d\n", tcke);
 	debug("tcksrx=%d\n", tcksrx);
 	debug("tcksre=%d\n", tcksre);
@@ -339,11 +342,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 	debug("twtr=%d\n", twtr);
 	debug("trrd=%d\n", trrd);
 	debug("txpr=%d\n", txpr);
-	debug("CS0_END=%d\n", CS0_END);
-	debug("ncs=%d\n", i->ncs);
-	debug("Rtt_wr=%d\n", i->rtt_wr);
-	debug("Rtt_nom=%d\n", i->rtt_nom);
-	debug("SRT=%d\n", m->SRT);
+	debug("cs0_end=%d\n", cs0_end);
+	debug("ncs=%d\n", sysinfo->ncs);
+	debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
+	debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
+	debug("SRT=%d\n", ddr3_cfg->SRT);
 	debug("tcl=%d\n", tcl);
 	debug("twr=%d\n", twr);
 
@@ -353,137 +356,130 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 	 *  see:
 	 *   appnote, ddr3 spreadsheet
 	 */
-	mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;
-	mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;
-	mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;
-	mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;
-	mmdc0->mprddlctl = c->p0_mprddlctl;
-	mmdc0->mpwrdlctl = c->p0_mpwrdlctl;
-	if (i->dsize > 1) {
-		mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;
-		mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;
-		mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;
-		mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;
-		mmdc1->mprddlctl = c->p1_mprddlctl;
-		mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
+	mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
+	mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
+	mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
+	mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
+	mmdc0->mprddlctl = calib->p0_mprddlctl;
+	mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
+	if (sysinfo->dsize > 1) {
+		mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
+		mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
+		mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
+		mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
+		mmdc1->mprddlctl = calib->p1_mprddlctl;
+		mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
 	}
 
 	/* Read data DQ Byte0-3 delay */
-	mmdc0->mprddqby0dl = (u32)0x33333333;
-	mmdc0->mprddqby1dl = (u32)0x33333333;
-	if (i->dsize > 0) {
-		mmdc0->mprddqby2dl = (u32)0x33333333;
-		mmdc0->mprddqby3dl = (u32)0x33333333;
+	mmdc0->mprddqby0dl = 0x33333333;
+	mmdc0->mprddqby1dl = 0x33333333;
+	if (sysinfo->dsize > 0) {
+		mmdc0->mprddqby2dl = 0x33333333;
+		mmdc0->mprddqby3dl = 0x33333333;
 	}
-	if (i->dsize > 1) {
-		mmdc1->mprddqby0dl = (u32)0x33333333;
-		mmdc1->mprddqby1dl = (u32)0x33333333;
-		mmdc1->mprddqby2dl = (u32)0x33333333;
-		mmdc1->mprddqby3dl = (u32)0x33333333;
+
+	if (sysinfo->dsize > 1) {
+		mmdc1->mprddqby0dl = 0x33333333;
+		mmdc1->mprddqby1dl = 0x33333333;
+		mmdc1->mprddqby2dl = 0x33333333;
+		mmdc1->mprddqby3dl = 0x33333333;
 	}
 
 	/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
-	reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;
-	mmdc0->mpodtctrl = reg;
-	if (i->dsize > 1)
-		mmdc1->mpodtctrl = reg;
+	val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
+	mmdc0->mpodtctrl = val;
+	if (sysinfo->dsize > 1)
+		mmdc1->mpodtctrl = val;
 
 	/* complete calibration */
-	reg = (1 << 11); /* Force measurement on delay-lines */
-	mmdc0->mpmur0 = reg;
-	if (i->dsize > 1)
-		mmdc1->mpmur0 = reg;
+	val = (1 << 11); /* Force measurement on delay-lines */
+	mmdc0->mpmur0 = val;
+	if (sysinfo->dsize > 1)
+		mmdc1->mpmur0 = val;
 
 	/* Step 1: configuration request */
 	mmdc0->mdscr = (u32)(1 << 15); /* config request */
 
 	/* Step 2: Timing configuration */
-	reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |
-	      (tfaw << 4) | tcl;
-	mmdc0->mdcfg0 = reg;
-	reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |
-	      (1 << 15) |		/* trpa */
-	      (twr << 9) | (tmrd << 5) | tcwl;
-	mmdc0->mdcfg1 = reg;
-	reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
-	mmdc0->mdcfg2 = reg;
-	reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
-	      (todtlon << 12) | (todt_idle_off << 4);
-	mmdc0->mdotc = reg;
-	mmdc0->mdasp = CS0_END; /* CS addressing */
+	mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
+			(txpdll << 9) | (tfaw << 4) | tcl;
+	mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
+			(tras << 16) | (1 << 15) /* trpa */ |
+			(twr << 9) | (tmrd << 5) | tcwl;
+	mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
+	mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
+		       (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
+	mmdc0->mdasp = cs0_end; /* CS addressing */
 
 	/* Step 3: Configure DDR type */
-	reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |
-	      (i->mif3_mode << 9) | (i->ralat << 6);
-	mmdc0->mdmisc = reg;
+	mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
+			(sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
+			(sysinfo->ralat << 6);
 
 	/* Step 4: Configure delay while leaving reset */
-	reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);
-	mmdc0->mdor = reg;
+	mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
+		      (sysinfo->rst_to_cke << 0);
 
 	/* Step 5: Configure DDR physical parameters (density and burst len) */
-	reg = (m->rowaddr - 11) << 24 |		/* ROW */
-	      (m->coladdr - 9) << 20 |		/* COL */
-	      (1 << 19) |			/* Burst Length = 8 for DDR3 */
-	      (i->dsize << 16);			/* DDR data bus size */
-	mmdc0->mdctl = reg;
+	mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 |		/* ROW */
+		       (ddr3_cfg->coladdr - 9) << 20 |		/* COL */
+		       (1 << 19) |		/* Burst Length = 8 for DDR3 */
+		       (sysinfo->dsize << 16);		/* DDR data bus size */
 
 	/* Step 6: Perform ZQ calibration */
-	reg = (u32)0xa1390001; /* one-time HW ZQ calib */
-	mmdc0->mpzqhwctrl = reg;
-	if (i->dsize > 1)
-		mmdc1->mpzqhwctrl = reg;
+	val = 0xa1390001; /* one-time HW ZQ calib */
+	mmdc0->mpzqhwctrl = val;
+	if (sysinfo->dsize > 1)
+		mmdc1->mpzqhwctrl = val;
 
 	/* Step 7: Enable MMDC with desired chip select */
-	reg = mmdc0->mdctl |
-	      (1 << 31) |			/* SDE_0 for CS0 */
-	      ((i->ncs == 2) ? 1 : 0) << 30;	/* SDE_1 for CS1 */
-	mmdc0->mdctl = reg;
+	mmdc0->mdctl |= (1 << 31) |			     /* SDE_0 for CS0 */
+			((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
 
 	/* Step 8: Write Mode Registers to Init DDR3 devices */
-	for (cs = 0; cs < i->ncs; cs++) {
+	for (cs = 0; cs < sysinfo->ncs; cs++) {
 		/* MR2 */
-		reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
+		val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
 		      ((tcwl - 3) & 3) << 3;
-		mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
+		mmdc0->mdscr = MR(val, 2, 3, cs);
 		/* MR3 */
-		mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
+		mmdc0->mdscr = MR(0, 3, 3, cs);
 		/* MR1 */
-		reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |
-		      ((i->rtt_nom & 2) ? 1 : 0) << 6;
-		mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);
-		reg = ((tcl - 1) << 4) |	/* CAS */
+		val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
+		      ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
+		mmdc0->mdscr = MR(val, 1, 3, cs);
+		/* MR0 */
+		val = ((tcl - 1) << 4) |	/* CAS */
 		      (1 << 8)   |		/* DLL Reset */
 		      ((twr - 3) << 9);		/* Write Recovery */
-		/* MR0 */
-		mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
+		mmdc0->mdscr = MR(val, 0, 3, cs);
 		/* ZQ calibration */
-		reg = (1 << 10);
-		mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
+		val = (1 << 10);
+		mmdc0->mdscr = MR(val, 0, 4, cs);
 	}
 
 	/* Step 10: Power down control and self-refresh */
-	reg = (tcke & 0x7) << 16 |
-	      5            << 12 |  /* PWDT_1: 256 cycles */
-	      5            <<  8 |  /* PWDT_0: 256 cycles */
-	      1            <<  6 |  /* BOTH_CS_PD */
-	      (tcksrx & 0x7) << 3 |
-	      (tcksre & 0x7);
-	mmdc0->mdpdc = reg;
-	mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
+	mmdc0->mdpdc = (tcke & 0x7) << 16 |
+			5            << 12 |  /* PWDT_1: 256 cycles */
+			5            <<  8 |  /* PWDT_0: 256 cycles */
+			1            <<  6 |  /* BOTH_CS_PD */
+			(tcksrx & 0x7) << 3 |
+			(tcksre & 0x7);
+	mmdc0->mapsr = 0x00011006; /* ADOPT power down enabled */
 
 	/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
-	mmdc0->mpzqhwctrl = (u32)0xa1390003;
-	if (i->dsize > 1)
-		mmdc1->mpzqhwctrl = (u32)0xa1390003;
+	val = 0xa1390003;
+	mmdc0->mpzqhwctrl = val;
+	if (sysinfo->dsize > 1)
+		mmdc1->mpzqhwctrl = val;
 
 	/* Step 12: Configure and activate periodic refresh */
-	reg = (1 << 14) |	/* REF_SEL: Periodic refresh cycles of 32kHz */
-	      (7 << 11);	/* REFR: Refresh Rate - 8 refreshes */
-	mmdc0->mdref = reg;
+	mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
+		       (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */
 
 	/* Step 13: Deassert config request - init complete */
-	mmdc0->mdscr = (u32)0x00000000;
+	mmdc0->mdscr = 0x00000000;
 
 	/* wait for auto-ZQ calibration to complete */
 	mdelay(1);
-- 
1.9.1

[U-Boot] [PATCH V4 09/19] arm: mx6: ddr: do not write into reserved bit

[Nikita Kiryanov]

Bit 16 in mapsr register is in a reserved field. Don't write to it.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes.

Changes in V3:
	- No changes.

Changes in V2:
	- No changes.

 arch/arm/cpu/armv7/mx6/ddr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index af91314..70ce38f 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -466,7 +466,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 			1            <<  6 |  /* BOTH_CS_PD */
 			(tcksrx & 0x7) << 3 |
 			(tcksre & 0x7);
-	mmdc0->mapsr = 0x00011006; /* ADOPT power down enabled */
+	mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
 
 	/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
 	val = 0xa1390003;
-- 
1.9.1

[U-Boot] [PATCH V4 10/19] arm: mx6: ddr: configure MMDC for slow_pd

[Nikita Kiryanov]

According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).

Configure MMDC for slow pd.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes.

Changes in V3:
	- No changes.

Changes in V2:
	- Updated commit message to explain which bits in which registers
	  correspond to which settings.

 arch/arm/cpu/armv7/mx6/ddr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 70ce38f..c0fb749 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -463,6 +463,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	mmdc0->mdpdc = (tcke & 0x7) << 16 |
 			5            << 12 |  /* PWDT_1: 256 cycles */
 			5            <<  8 |  /* PWDT_0: 256 cycles */
+			1            <<  7 |  /* SLOW_PD */
 			1            <<  6 |  /* BOTH_CS_PD */
 			(tcksrx & 0x7) << 3 |
 			(tcksre & 0x7);
-- 
1.9.1

[U-Boot] [PATCH V4 11/19] arm: mx6: ddr: fix cs0_end calculation

[Nikita Kiryanov]

Current way of calculation CS0_END field for MMDCx_MDASP register
is problematic because in most cases the user is forced to define
cs_density in an unnatural way: as value - 2, instead of value.

This breaks the abstraction provided by struct mx6_ddr_sysinfo
because the user is forced to be aware of the way the calculation
is performed.

Refactor the calculation.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes

Changes in V3:
	- No changes

Changes in V2:
	- No changes

 arch/arm/cpu/armv7/mx6/ddr.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index c0fb749..d3891dc 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -308,9 +308,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	twtr = ROUND(MAX(4 * clkper, 7500) / clkper, 1) - 1;
 	trcd = trp;
 	trtp = twtr;
-	cs0_end = (4 * sysinfo->cs_density <= 120) ?
-		   4 * sysinfo->cs_density + 7 :
-		   127;
+	cs0_end = 4 * sysinfo->cs_density - 1;
 
 	debug("density:%d Gb (%d Gb per chip)\n",
 	      sysinfo->cs_density, ddr3_cfg->density);
-- 
1.9.1

[U-Boot] [PATCH V4 12/19] arm: mx6: add get_cpu_type()

[Nikita Kiryanov]

Define get_cpu_type(). Reuse it in is_cpu_type().

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
New patch for V4 of series.

 arch/arm/include/asm/arch-mx6/sys_proto.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 42d30f5..ba0a66e 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -19,8 +19,9 @@ u32 get_cpu_rev(void);
 /* returns MXC_CPU_ value */
 #define cpu_type(rev) (((rev) >> 12)&0xff)
 
-/* use with MXC_CPU_ constants */
-#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
+/* both macros return/take MXC_CPU_ constants */
+#define get_cpu_type()	(cpu_type(get_cpu_rev()))
+#define is_cpu_type(cpu) (get_cpu_type() == cpu)
 
 const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
-- 
1.9.1

[U-Boot] [PATCH V4 13/19] arm: mx6: add support for Compulab cm-fx6 CoM

[Nikita Kiryanov]

Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- Adapt to use Kconfig
	- Refactor code to work without ulong bank(1|2)_size variables
	- Remove get_board_rev(); reintroduce in a later patch
	- Move usdhc structs to cm_fx6.c
	- Initialize all ddr related structs statically
	- Use get_cpu_type() and spl_boot_device()
	- Kill #define CONFIG_SYS_L2CACHE_OFF
	- Use load instead of fatload in environment scripts
	- Remove nand related environment variables; reintroduce in a later patch
	- Move usdhc3 clock initialization to another patch.

Changes in V3:
	- Remove CONFIG_SYS_TEXT_BASE from config file to not clash with the
	  one supplied by imx6_spl.h

Changes in V2:
	- Remove unnecessary line removal from arch/arm/cpu/armv7/mx6/ddr.c
	- Move probe_mmdc_config() code straight to dram_init()
	- Use imx6_spl.h
	- Use imx_ddr_size()
	  NOTE: the correctness of this patch now depends on https://patchwork.ozlabs.org/patch/376095/

 arch/arm/Kconfig                   |   4 +
 board/compulab/cm_fx6/Kconfig      |  23 +++
 board/compulab/cm_fx6/MAINTAINERS  |   6 +
 board/compulab/cm_fx6/Makefile     |  12 ++
 board/compulab/cm_fx6/cm_fx6.c     | 111 ++++++++++++
 board/compulab/cm_fx6/common.c     |  84 +++++++++
 board/compulab/cm_fx6/common.h     |  20 +++
 board/compulab/cm_fx6/imximage.cfg |   8 +
 board/compulab/cm_fx6/spl.c        | 355 +++++++++++++++++++++++++++++++++++++
 configs/cm_fx6_defconfig           |   4 +
 include/configs/cm_fx6.h           | 192 ++++++++++++++++++++
 11 files changed, 819 insertions(+)
 create mode 100644 board/compulab/cm_fx6/Kconfig
 create mode 100644 board/compulab/cm_fx6/MAINTAINERS
 create mode 100644 board/compulab/cm_fx6/Makefile
 create mode 100644 board/compulab/cm_fx6/cm_fx6.c
 create mode 100644 board/compulab/cm_fx6/common.c
 create mode 100644 board/compulab/cm_fx6/common.h
 create mode 100644 board/compulab/cm_fx6/imximage.cfg
 create mode 100644 board/compulab/cm_fx6/spl.c
 create mode 100644 configs/cm_fx6_defconfig
 create mode 100644 include/configs/cm_fx6.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e385eda..5db7708 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -611,6 +611,9 @@ config TARGET_OMAP4_SDP4430
 config TARGET_CM_T54
 	bool "Support cm_t54"
 
+config TARGET_CM_FX6
+	bool "Support cm_fx6"
+
 config TARGET_DRA7XX_EVM
 	bool "Support dra7xx_evm"
 
@@ -836,6 +839,7 @@ source "board/compal/paz00/Kconfig"
 source "board/compulab/cm_t335/Kconfig"
 source "board/compulab/cm_t35/Kconfig"
 source "board/compulab/cm_t54/Kconfig"
+source "board/compulab/cm_fx6/Kconfig"
 source "board/compulab/trimslice/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/corscience/tricorder/Kconfig"
diff --git a/board/compulab/cm_fx6/Kconfig b/board/compulab/cm_fx6/Kconfig
new file mode 100644
index 0000000..42a8438
--- /dev/null
+++ b/board/compulab/cm_fx6/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_CM_FX6
+
+config SYS_CPU
+	string
+	default "armv7"
+
+config SYS_BOARD
+	string
+	default "cm_fx6"
+
+config SYS_VENDOR
+	string
+	default "compulab"
+
+config SYS_SOC
+	string
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	string
+	default "cm_fx6"
+
+endif
diff --git a/board/compulab/cm_fx6/MAINTAINERS b/board/compulab/cm_fx6/MAINTAINERS
new file mode 100644
index 0000000..5b2623a
--- /dev/null
+++ b/board/compulab/cm_fx6/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_FX6 BOARD
+M:	Nikita Kiryanov <nikita@compulab.co.il>
+S:	Maintained
+F:	board/compulab/cm_fx6/
+F:	include/configs/cm_fx6.h
+F:	configs/cm_fx6_defconfig
diff --git a/board/compulab/cm_fx6/Makefile b/board/compulab/cm_fx6/Makefile
new file mode 100644
index 0000000..3e5c903
--- /dev/null
+++ b/board/compulab/cm_fx6/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Nikita Kiryanov <nikita@compulab.co.il>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+obj-y = common.o spl.o
+else
+obj-y = common.o cm_fx6.o
+endif
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
new file mode 100644
index 0000000..b589581
--- /dev/null
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -0,0 +1,111 @@
+/*
+ * Board functions for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/sys_proto.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC1_BASE_ADDR},
+	{USDHC2_BASE_ADDR},
+	{USDHC3_BASE_ADDR},
+};
+
+static enum mxc_clock usdhc_clk[3] = {
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int i;
+
+	cm_fx6_set_usdhc_iomux();
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
+		usdhc_cfg[i].max_bus_width = 4;
+		fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		enable_usdhc_clk(1, i);
+	}
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: CM-FX6\n");
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+
+	switch (gd->ram_size) {
+	case 0x10000000: /* DDR_16BIT_256MB */
+		gd->bd->bi_dram[0].size = 0x10000000;
+		gd->bd->bi_dram[1].size = 0;
+		break;
+	case 0x20000000: /* DDR_32BIT_512MB */
+		gd->bd->bi_dram[0].size = 0x20000000;
+		gd->bd->bi_dram[1].size = 0;
+		break;
+	case 0x40000000:
+		if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
+			gd->bd->bi_dram[0].size = 0x20000000;
+			gd->bd->bi_dram[1].size = 0x20000000;
+		} else { /* DDR_64BIT_1GB */
+			gd->bd->bi_dram[0].size = 0x40000000;
+			gd->bd->bi_dram[1].size = 0;
+		}
+		break;
+	case 0x80000000: /* DDR_64BIT_2GB */
+		gd->bd->bi_dram[0].size = 0x40000000;
+		gd->bd->bi_dram[1].size = 0x40000000;
+		break;
+	case 0xEFF00000: /* DDR_64BIT_4GB */
+		gd->bd->bi_dram[0].size = 0x70000000;
+		gd->bd->bi_dram[1].size = 0x7FF00000;
+		break;
+	}
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	switch (gd->ram_size) {
+	case 0x10000000:
+	case 0x20000000:
+	case 0x40000000:
+	case 0x80000000:
+		break;
+	case 0xF0000000:
+		gd->ram_size -= 0x100000;
+		break;
+	default:
+		printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c
new file mode 100644
index 0000000..1f39679
--- /dev/null
+++ b/board/compulab/cm_fx6/common.c
@@ -0,0 +1,84 @@
+/*
+ * Code used by both U-Boot and SPL for Compulab CM-FX6
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc_pads[] = {
+	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+void cm_fx6_set_usdhc_iomux(void)
+{
+	SETUP_IOMUX_PADS(usdhc_pads);
+}
+
+/* CINS bit doesn't work, so always try to access the MMC card */
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#define ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+		PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const ecspi_pads[] = {
+	IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30  | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__ECSPI1_SS1  | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+};
+
+void cm_fx6_set_ecspi_iomux(void)
+{
+	SETUP_IOMUX_PADS(ecspi_pads);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1;
+}
+#endif
diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h
new file mode 100644
index 0000000..347d07b
--- /dev/null
+++ b/board/compulab/cm_fx6/common.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/clock.h>
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |	\
+			PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+			PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define CM_FX6_ECSPI_BUS0_CS0	IMX_GPIO_NR(2, 30)
+#define CM_FX6_GREEN_LED	IMX_GPIO_NR(2, 31)
+
+void cm_fx6_set_usdhc_iomux(void);
+void cm_fx6_set_ecspi_iomux(void);
diff --git a/board/compulab/cm_fx6/imximage.cfg b/board/compulab/cm_fx6/imximage.cfg
new file mode 100644
index 0000000..420947e
--- /dev/null
+++ b/board/compulab/cm_fx6/imximage.cfg
@@ -0,0 +1,8 @@
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM	sd
diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
new file mode 100644
index 0000000..a3abc7b
--- /dev/null
+++ b/board/compulab/cm_fx6/spl.c
@@ -0,0 +1,355 @@
+/*
+ * SPL specific code for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <fsl_esdhc.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ddr_config {
+	DDR_16BIT_256MB,
+	DDR_32BIT_512MB,
+	DDR_32BIT_1GB,
+	DDR_64BIT_1GB,
+	DDR_64BIT_2GB,
+	DDR_64BIT_4GB,
+	DDR_UNKNOWN,
+};
+
+/*
+ * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
+ * Freescale QRM, but this is exactly the value used by the automatic
+ * calibration script and it works also in all our tests, so we leave
+ * it as is at this point.
+ */
+#define CM_FX6_DDR_IOMUX_CFG \
+	.dram_sdqs0	= 0x00000038, \
+	.dram_sdqs1	= 0x00000038, \
+	.dram_sdqs2	= 0x00000038, \
+	.dram_sdqs3	= 0x00000038, \
+	.dram_sdqs4	= 0x00000038, \
+	.dram_sdqs5	= 0x00000038, \
+	.dram_sdqs6	= 0x00000038, \
+	.dram_sdqs7	= 0x00000038, \
+	.dram_dqm0	= 0x00000038, \
+	.dram_dqm1	= 0x00000038, \
+	.dram_dqm2	= 0x00000038, \
+	.dram_dqm3	= 0x00000038, \
+	.dram_dqm4	= 0x00000038, \
+	.dram_dqm5	= 0x00000038, \
+	.dram_dqm6	= 0x00000038, \
+	.dram_dqm7	= 0x00000038, \
+	.dram_cas	= 0x00000038, \
+	.dram_ras	= 0x00000038, \
+	.dram_sdclk_0	= 0x00000038, \
+	.dram_sdclk_1	= 0x00000038, \
+	.dram_sdcke0	= 0x00003000, \
+	.dram_sdcke1	= 0x00003000, \
+	.dram_reset	= 0x00000038, \
+	.dram_sdba2	= 0x00000000, \
+	.dram_sdodt0	= 0x00000038, \
+	.dram_sdodt1	= 0x00000038,
+
+#define CM_FX6_GPR_IOMUX_CFG \
+	.grp_b0ds	= 0x00000038, \
+	.grp_b1ds	= 0x00000038, \
+	.grp_b2ds	= 0x00000038, \
+	.grp_b3ds	= 0x00000038, \
+	.grp_b4ds	= 0x00000038, \
+	.grp_b5ds	= 0x00000038, \
+	.grp_b6ds	= 0x00000038, \
+	.grp_b7ds	= 0x00000038, \
+	.grp_addds	= 0x00000038, \
+	.grp_ddrmode_ctl = 0x00020000, \
+	.grp_ddrpke	= 0x00000000, \
+	.grp_ddrmode	= 0x00020000, \
+	.grp_ctlds	= 0x00000038, \
+	.grp_ddr_type	= 0x000C0000,
+
+static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
+static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
+static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
+static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
+
+static struct mx6_mmdc_calibration cm_fx6_calib_s = {
+	.p0_mpwldectrl0	= 0x005B0061,
+	.p0_mpwldectrl1	= 0x004F0055,
+	.p0_mpdgctrl0	= 0x0314030C,
+	.p0_mpdgctrl1	= 0x025C0268,
+	.p0_mprddlctl	= 0x42464646,
+	.p0_mpwrdlctl	= 0x36322C34,
+};
+
+static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
+	.cs1_mirror	= 1,
+	.cs_density	= 16,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 1,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
+	.mem_speed	= 800,
+	.density	= 4,
+	.rowaddr	= 14,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1800,
+	.trcmin		= 5200,
+	.trasmin	= 3600,
+	.SRT		= 0,
+};
+
+static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
+{
+	if (reset)
+		((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
+
+	switch (dram_config) {
+	case DDR_16BIT_256MB:
+		cm_fx6_sysinfo_s.dsize = 0;
+		cm_fx6_sysinfo_s.ncs = 1;
+		break;
+	case DDR_32BIT_512MB:
+		cm_fx6_sysinfo_s.dsize = 1;
+		cm_fx6_sysinfo_s.ncs = 1;
+		break;
+	case DDR_32BIT_1GB:
+		cm_fx6_sysinfo_s.dsize = 1;
+		cm_fx6_sysinfo_s.ncs = 2;
+		break;
+	default:
+		puts("Tried to setup invalid DDR configuration\n");
+		hang();
+	}
+
+	mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
+	udelay(100);
+}
+
+static struct mx6_mmdc_calibration cm_fx6_calib_q = {
+	.p0_mpwldectrl0	= 0x00630068,
+	.p0_mpwldectrl1	= 0x0068005D,
+	.p0_mpdgctrl0	= 0x04140428,
+	.p0_mpdgctrl1	= 0x037C037C,
+	.p0_mprddlctl	= 0x3C30303A,
+	.p0_mpwrdlctl	= 0x3A344038,
+	.p1_mpwldectrl0	= 0x0035004C,
+	.p1_mpwldectrl1	= 0x00170026,
+	.p1_mpdgctrl0	= 0x0374037C,
+	.p1_mpdgctrl1	= 0x0350032C,
+	.p1_mprddlctl	= 0x30322A3C,
+	.p1_mpwrdlctl	= 0x48304A3E,
+};
+
+static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
+	.cs_density	= 16,
+	.cs1_mirror	= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 1,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
+	.mem_speed	= 1066,
+	.density	= 4,
+	.rowaddr	= 14,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1324,
+	.trcmin		= 59500,
+	.trasmin	= 9750,
+	.SRT		= 0,
+};
+
+static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
+{
+	if (reset)
+		((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
+
+	cm_fx6_ddr3_cfg_q.rowaddr = 14;
+	switch (dram_config) {
+	case DDR_16BIT_256MB:
+		cm_fx6_sysinfo_q.dsize = 0;
+		cm_fx6_sysinfo_q.ncs = 1;
+		break;
+	case DDR_32BIT_512MB:
+		cm_fx6_sysinfo_q.dsize = 1;
+		cm_fx6_sysinfo_q.ncs = 1;
+		break;
+	case DDR_64BIT_1GB:
+		cm_fx6_sysinfo_q.dsize = 2;
+		cm_fx6_sysinfo_q.ncs = 1;
+		break;
+	case DDR_64BIT_2GB:
+		cm_fx6_sysinfo_q.dsize = 2;
+		cm_fx6_sysinfo_q.ncs = 2;
+		break;
+	case DDR_64BIT_4GB:
+		cm_fx6_sysinfo_q.dsize = 2;
+		cm_fx6_sysinfo_q.ncs = 2;
+		cm_fx6_ddr3_cfg_q.rowaddr = 15;
+		break;
+	default:
+		puts("Tried to setup invalid DDR configuration\n");
+		hang();
+	}
+
+	mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
+	udelay(100);
+}
+
+static int cm_fx6_spl_dram_init(void)
+{
+	unsigned long bank1_size, bank2_size;
+
+	switch (get_cpu_type()) {
+	case MXC_CPU_MX6SOLO:
+		mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
+
+		spl_mx6s_dram_init(DDR_32BIT_1GB, false);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x40000000)
+			return 0;
+
+		if (bank1_size == 0x20000000) {
+			spl_mx6s_dram_init(DDR_32BIT_512MB, true);
+			return 0;
+		}
+
+		spl_mx6s_dram_init(DDR_16BIT_256MB, true);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x10000000)
+			return 0;
+
+		break;
+	case MXC_CPU_MX6D:
+	case MXC_CPU_MX6Q:
+		mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
+
+		spl_mx6q_dram_init(DDR_64BIT_4GB, false);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x80000000)
+			return 0;
+
+		if (bank1_size == 0x40000000) {
+			bank2_size = get_ram_size((long int *)PHYS_SDRAM_2,
+								0x80000000);
+			if (bank2_size == 0x40000000) {
+				/* Don't do a full reset here */
+				spl_mx6q_dram_init(DDR_64BIT_2GB, false);
+			} else {
+				spl_mx6q_dram_init(DDR_64BIT_1GB, true);
+			}
+
+			return 0;
+		}
+
+		spl_mx6q_dram_init(DDR_32BIT_512MB, true);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x20000000)
+			return 0;
+
+		spl_mx6q_dram_init(DDR_16BIT_256MB, true);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x10000000)
+			return 0;
+
+		break;
+	}
+
+	return -1;
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_uart(void)
+{
+	SETUP_IOMUX_PADS(uart4_pads);
+	enable_uart_clk(1);
+}
+
+#ifdef CONFIG_SPL_SPI_SUPPORT
+static void cm_fx6_setup_ecspi(void)
+{
+	cm_fx6_set_ecspi_iomux();
+	enable_cspi_clock(1, 0);
+}
+#else
+static void cm_fx6_setup_ecspi(void) { }
+#endif
+
+void board_init_f(ulong dummy)
+{
+	gd = &gdata;
+	arch_cpu_init();
+	timer_init();
+	cm_fx6_setup_ecspi();
+	cm_fx6_setup_uart();
+	get_clocks();
+	preloader_console_init();
+	gpio_direction_output(CM_FX6_GREEN_LED, 1);
+	if (cm_fx6_spl_dram_init()) {
+		puts("!!!ERROR!!! DRAM detection failed!!!\n");
+		hang();
+	}
+
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+	u32 boot_device = spl_boot_device();
+
+	if (boot_device == BOOT_DEVICE_SPI)
+		puts("Booting from SPI flash\n");
+	else if (boot_device == BOOT_DEVICE_MMC1)
+		puts("Booting from MMC\n");
+	else
+		puts("Unknown boot device\n");
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+static struct fsl_esdhc_cfg usdhc_cfg = {
+	.esdhc_base = USDHC3_BASE_ADDR,
+	.max_bus_width = 4,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	cm_fx6_set_usdhc_iomux();
+
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
new file mode 100644
index 0000000..50c06f7
--- /dev/null
+++ b/configs/cm_fx6_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/cm_fx6/imximage.cfg,MX6QDL,SPL"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_CM_FX6=y
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
new file mode 100644
index 0000000..15c55be
--- /dev/null
+++ b/include/configs/cm_fx6.h
@@ -0,0 +1,192 @@
+/*
+ * Config file for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_CM_FX6_H
+#define __CONFIG_CM_FX6_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+/* Machine config */
+#define CONFIG_MX6
+#define CONFIG_SYS_LITTLE_ENDIAN
+#define CONFIG_MACH_TYPE		4273
+#define CONFIG_SYS_HZ			1000
+
+/* Display information on boot */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_TIMESTAMP
+
+/* CMD */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_GREPENV
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* RAM */
+#define PHYS_SDRAM_1			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_2			MMDC1_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x10010000
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Serial console */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART4_BASE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/* Shell */
+#define CONFIG_SYS_PROMPT	"CM-FX6 # "
+#define CONFIG_SYS_CBSIZE	1024
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* SPI flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		25000000
+#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel=uImage-cm-fx6\0" \
+	"autoload=no\0" \
+	"loadaddr=0x10800000\0" \
+	"fdtaddr=0x11000000\0" \
+	"console=ttymxc3,115200\0" \
+	"ethprime=FEC0\0" \
+	"bootscr=boot.scr\0" \
+	"bootm_low=18000000\0" \
+	"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32 at 50,if=RGB32\0" \
+	"video_dvi=mxcfb0:dev=dvi,1280x800M-32 at 50,if=RGB32\0" \
+	"fdtfile=cm-fx6.dtb\0" \
+	"doboot=bootm ${loadaddr}\0" \
+	"loadfdt=false\0" \
+	"setboottypez=setenv kernel zImage-cm-fx6;" \
+		"setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
+		"setenv loadfdt true;\0" \
+	"setboottypem=setenv kernel uImage-cm-fx6;" \
+		"setenv doboot bootm ${loadaddr};" \
+		"setenv loadfdt false;\0"\
+	"run_eboot=echo Starting EBOOT ...; "\
+		"mmc dev ${mmcdev} && " \
+		"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
+	"mmcdev=2\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"loadmmcbootscript=load mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \
+	"mmcbootscript=echo Running bootscript from mmc ...; "\
+		"source ${loadaddr}\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"${video}\0" \
+	"mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
+	"mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"run doboot\0" \
+	"boot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"if run loadmmcbootscript; then " \
+				"run mmcbootscript;" \
+			"else " \
+				"if run mmcloadkernel; then " \
+					"if ${loadfdt}; then " \
+						"run mmcloadfdt;" \
+					"fi;" \
+					"run mmcboot;" \
+				"fi;" \
+			"fi;" \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"run setboottypem; run boot"
+
+/* SPI */
+#define CONFIG_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_WINBOND
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+
+/* Boot */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_LOADADDR			0x10800000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SYS_BOOTMAPSZ	        (8 << 20)
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* misc */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_STACKSIZE			(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN			(2 * 1024 * 1024)
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	800 /* 400 KB */
+
+/* SPL */
+#include "imx6_spl.h"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x80 /* offset 64 kb */
+#define CONFIG_SYS_MONITOR_LEN	(CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024)
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
+#define CONFIG_SPL_SPI_LOAD
+
+#endif	/* __CONFIG_CM_FX6_H */
-- 
1.9.1

[U-Boot] [PATCH V4 14/19] arm: mx6: cm_fx6: add nand support

[Nikita Kiryanov]

Add NAND support for Compulab CM-FX6 CoM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- Introduce nand environment variables and nand boot command here
	- Initialize usdhc3 clock in spl here

Changes in V3:
	- No changes

Changes in V2:
	- No changes

 board/compulab/cm_fx6/cm_fx6.c | 37 +++++++++++++++++++++++++++++++++++++
 board/compulab/cm_fx6/spl.c    | 11 +++++++++++
 include/configs/cm_fx6.h       | 31 ++++++++++++++++++++++++++++++-
 3 files changed, 78 insertions(+), 1 deletion(-)

diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index b589581..17c3ee5 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -10,11 +10,46 @@
 
 #include <common.h>
 #include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/io.h>
 #include "common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const nand_pads[] = {
+	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_gpmi_nand(void)
+{
+	SETUP_IOMUX_PADS(nand_pads);
+	/* Enable clock roots */
+	enable_usdhc_clk(1, 3);
+	enable_usdhc_clk(1, 4);
+
+	setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
+			  MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
+			  MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
+}
+#else
+static void cm_fx6_setup_gpmi_nand(void) {}
+#endif
+
 #ifdef CONFIG_FSL_ESDHC
 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 	{USDHC1_BASE_ADDR},
@@ -47,6 +82,8 @@ int board_mmc_init(bd_t *bis)
 int board_init(void)
 {
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+	cm_fx6_setup_gpmi_nand();
+
 	return 0;
 }
 
diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
index a3abc7b..3948ba2 100644
--- a/board/compulab/cm_fx6/spl.c
+++ b/board/compulab/cm_fx6/spl.c
@@ -15,6 +15,7 @@
 #include <asm/arch/mx6-ddr.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <fsl_esdhc.h>
 #include "common.h"
@@ -309,7 +310,17 @@ static void cm_fx6_setup_ecspi(void) { }
 
 void board_init_f(ulong dummy)
 {
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
 	gd = &gdata;
+	/*
+	 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
+	 * initializes DMA very early (before all board code), so the only
+	 * opportunity we have to initialize APBHDMA clocks is in SPL.
+	 */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+	enable_usdhc_clk(1, 2);
+
 	arch_cpu_init();
 	timer_init();
 	cm_fx6_setup_ecspi();
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 15c55be..4c1bcb9 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -130,6 +130,20 @@
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"run doboot\0" \
+	"nandroot=/dev/mtdblock4 rw\0" \
+	"nandrootfstype=ubifs\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} " \
+		"${video}\0" \
+	"nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 0 780000; " \
+		"if ${loadfdt}; then " \
+			"run nandloadfdt;" \
+		"fi; " \
+		"run doboot\0" \
 	"boot=mmc dev ${mmcdev}; " \
 		"if mmc rescan; then " \
 			"if run loadmmcbootscript; then " \
@@ -142,7 +156,8 @@
 					"run mmcboot;" \
 				"fi;" \
 			"fi;" \
-		"fi;\0"
+		"fi;" \
+		"run nandboot\0"
 
 #define CONFIG_BOOTCOMMAND \
 	"run setboottypem; run boot"
@@ -160,6 +175,20 @@
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_SPI_FLASH_WINBOND
 
+/* NAND */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* APBH DMA is required for NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#endif
+
 /* GPIO */
 #define CONFIG_MXC_GPIO
 
-- 
1.9.1

[U-Boot] [PATCH V4 15/19] arm: mx6: cm_fx6: add ethernet support

[Nikita Kiryanov]

Add ethernet support for Compulab CM-FX6 CoM

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes

Changes in V3:
	- No changes

Changes in V2:
	- No changes

 board/compulab/cm_fx6/cm_fx6.c | 100 +++++++++++++++++++++++++++++++++++++++++
 board/compulab/cm_fx6/common.h |   1 +
 include/configs/cm_fx6.h       |  16 ++++++-
 3 files changed, 115 insertions(+), 2 deletions(-)

diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 17c3ee5..681b1ee 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -10,13 +10,100 @@
 
 #include <common.h>
 #include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <fdt_support.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include "common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_FEC_MXC
+#define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+				 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* Ar8031 phy SmartEEE feature cause link status generates glitch,
+	 * which cause ethernet link down/up issue, so disable SmartEEE
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= ~(0x1 << 8);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+
+	if (phydev->drv->config)
+		return phydev->drv->config(phydev);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
+	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+};
+
+int board_eth_init(bd_t *bis)
+{
+	SETUP_IOMUX_PADS(enet_pads);
+	/* phy reset */
+	gpio_direction_output(CM_FX6_ENET_NRST, 0);
+	udelay(500);
+	gpio_set_value(CM_FX6_ENET_NRST, 1);
+	enable_enet_clk(1);
+	return cpu_eth_init(bis);
+}
+#endif
+
 #ifdef CONFIG_NAND_MXS
 static iomux_v3_cfg_t const nand_pads[] = {
 	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
@@ -79,6 +166,19 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	uint8_t enetaddr[6];
+
+	/* MAC addr */
+	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		fdt_find_and_setprop(blob, "/fec", "local-mac-address",
+				     enetaddr, 6, 1);
+	}
+}
+#endif
+
 int board_init(void)
 {
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h
index 347d07b..1b19f16 100644
--- a/board/compulab/cm_fx6/common.h
+++ b/board/compulab/cm_fx6/common.h
@@ -15,6 +15,7 @@
 
 #define CM_FX6_ECSPI_BUS0_CS0	IMX_GPIO_NR(2, 30)
 #define CM_FX6_GREEN_LED	IMX_GPIO_NR(2, 31)
+#define CM_FX6_ENET_NRST	IMX_GPIO_NR(2, 8)
 
 void cm_fx6_set_usdhc_iomux(void);
 void cm_fx6_set_ecspi_iomux(void);
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 4c1bcb9..22b3376 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -35,8 +35,6 @@
 #undef CONFIG_CMD_XIMG
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
 
 /* MMC */
 #define CONFIG_MMC
@@ -189,6 +187,19 @@
 #define CONFIG_APBH_DMA_BURST8
 #endif
 
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_MII
+#define CONFIG_ETHPRIME			"FEC0"
+#define CONFIG_ARP_TIMEOUT		200UL
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_NET_RETRY_COUNT		5
+
 /* GPIO */
 #define CONFIG_MXC_GPIO
 
@@ -206,6 +217,7 @@
 #define CONFIG_STACKSIZE			(128 * 1024)
 #define CONFIG_SYS_MALLOC_LEN			(2 * 1024 * 1024)
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	800 /* 400 KB */
+#define CONFIG_OF_BOARD_SETUP
 
 /* SPL */
 #include "imx6_spl.h"
-- 
1.9.1

[U-Boot] [PATCH V4 16/19] arm: mx6: cm_fx6: add usb support

[Nikita Kiryanov]

Add USB and USB OTG host support for Compulab CM-FX6 CoM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- cm_fx6_init_usb_otg() returns an int
	- Use setbits_le32()
	- Don't treat int port as a bool in board_ehci_power()

Changes in V3:
	- No changes

Changes in V2:
	- No changes

 board/compulab/cm_fx6/cm_fx6.c | 76 ++++++++++++++++++++++++++++++++++++++++++
 board/compulab/cm_fx6/common.h |  3 ++
 include/configs/cm_fx6.h       | 10 ++++++
 3 files changed, 89 insertions(+)

diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 681b1ee..26f0417 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -15,12 +15,88 @@
 #include <fdt_support.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include "common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
+			PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+			PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+static int cm_fx6_usb_hub_reset(void)
+{
+	int err;
+
+	err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
+	if (err) {
+		printf("USB hub rst gpio request failed: %d\n", err);
+		return -1;
+	}
+
+	SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
+	gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
+	udelay(10);
+	gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
+	mdelay(1);
+
+	return 0;
+}
+
+static int cm_fx6_init_usb_otg(void)
+{
+	int ret;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	ret = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
+	if (ret) {
+		printf("USB OTG pwr gpio request failed: %d\n", ret);
+		return ret;
+	}
+
+	SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
+	SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
+						MUX_PAD_CTRL(WEAK_PULLDOWN));
+	clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
+	/* disable ext. charger detect, or it'll affect signal quality at dp. */
+	return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
+}
+
+#define MX6_USBNC_BASEADDR	0x2184800
+#define USBNC_USB_H1_PWR_POL	(1 << 9)
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
+
+	switch (port) {
+	case 0:
+		return cm_fx6_init_usb_otg();
+	case 1:
+		SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR |
+				MUX_PAD_CTRL(NO_PAD_CTRL));
+
+		/* Set PWR polarity to match power switch's enable polarity */
+		setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
+		return cm_fx6_usb_hub_reset();
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	if (port == 0)
+		return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 #define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 				 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h
index 1b19f16..f841c90 100644
--- a/board/compulab/cm_fx6/common.h
+++ b/board/compulab/cm_fx6/common.h
@@ -16,6 +16,9 @@
 #define CM_FX6_ECSPI_BUS0_CS0	IMX_GPIO_NR(2, 30)
 #define CM_FX6_GREEN_LED	IMX_GPIO_NR(2, 31)
 #define CM_FX6_ENET_NRST	IMX_GPIO_NR(2, 8)
+#define CM_FX6_ENET_NRST	IMX_GPIO_NR(2, 8)
+#define CM_FX6_USB_HUB_RST	IMX_GPIO_NR(7, 8)
+#define SB_FX6_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
 
 void cm_fx6_set_usdhc_iomux(void);
 void cm_fx6_set_ecspi_iomux(void);
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 22b3376..0c25dda 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -200,6 +200,16 @@
 #define CONFIG_NETMASK			255.255.255.0
 #define CONFIG_NET_RETRY_COUNT		5
 
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+
 /* GPIO */
 #define CONFIG_MXC_GPIO
 
-- 
1.9.1

[U-Boot] [PATCH V4 17/19] arm: mx6: cm_fx6: add i2c support

[Nikita Kiryanov]

Add support for all 3 I2C busses on Compulab CM-FX6 CoM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- No changes

Changes in V3:
	- No changes

Changes in V2:
	- No changes

 board/compulab/cm_fx6/cm_fx6.c | 42 ++++++++++++++++++++++++++++++++++++++++++
 include/configs/cm_fx6.h       | 11 +++++++++++
 2 files changed, 53 insertions(+)

diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 26f0417..d21c561 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -16,12 +16,53 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/iomux.h>
+#include <asm/imx-common/mxc_i2c.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include "common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_I2C_MXC
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+			PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+I2C_PADS(i2c0_pads,
+	 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(3, 21),
+	 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(3, 28));
+
+I2C_PADS(i2c1_pads,
+	 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(4, 12),
+	 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(4, 13));
+
+I2C_PADS(i2c2_pads,
+	 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(1, 3),
+	 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(1, 6));
+
+
+static void cm_fx6_setup_i2c(void)
+{
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c0_pads));
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c1_pads));
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c2_pads));
+}
+#else
+static void cm_fx6_setup_i2c(void) { }
+#endif
+
 #ifdef CONFIG_USB_EHCI_MX6
 #define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
 			PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
@@ -259,6 +300,7 @@ int board_init(void)
 {
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 	cm_fx6_setup_gpmi_nand();
+	cm_fx6_setup_i2c();
 
 	return 0;
 }
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 0c25dda..e70259e 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -210,6 +210,17 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
 
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_MXC_I2C3_SPEED	400000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	2
+
 /* GPIO */
 #define CONFIG_MXC_GPIO
 
-- 
1.9.1

[U-Boot] [PATCH V4 18/19] arm: mx6: cm_fx6: use eeprom

[Nikita Kiryanov]

Use Compulab eeprom module to obtain revision number, serial number, and
mac address from the EEPROM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- Introduce get_board_rev() here.

Changes in V3:
	- No changes

Changes in V2:
	- No changes

 board/compulab/cm_fx6/cm_fx6.c | 30 ++++++++++++++++++++++++++++++
 include/configs/cm_fx6.h       |  2 ++
 2 files changed, 32 insertions(+)

diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index d21c561..1664fe8 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -20,6 +20,7 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include "common.h"
+#include "../common/eeprom.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -209,8 +210,31 @@ static iomux_v3_cfg_t const enet_pads[] = {
 						MUX_PAD_CTRL(ENET_PAD_CTRL)),
 };
 
+static int handle_mac_address(void)
+{
+	unsigned char enetaddr[6];
+	int rc;
+
+	rc = eth_getenv_enetaddr("ethaddr", enetaddr);
+	if (rc)
+		return 0;
+
+	rc = cl_eeprom_read_mac_addr(enetaddr);
+	if (rc)
+		return rc;
+
+	if (!is_valid_ether_addr(enetaddr))
+		return -1;
+
+	return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
 int board_eth_init(bd_t *bis)
 {
+	int res = handle_mac_address();
+	if (res)
+		puts("No MAC address found\n");
+
 	SETUP_IOMUX_PADS(enet_pads);
 	/* phy reset */
 	gpio_direction_output(CM_FX6_ENET_NRST, 0);
@@ -364,3 +388,9 @@ int dram_init(void)
 
 	return 0;
 }
+
+u32 get_board_rev(void)
+{
+	return cl_eeprom_get_board_rev();
+}
+
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index e70259e..cccc989 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -232,6 +232,8 @@
 #define CONFIG_SYS_BOOTMAPSZ	        (8 << 20)
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
 
 /* misc */
 #define CONFIG_SYS_GENERIC_BOARD
-- 
1.9.1

[U-Boot] [PATCH V4 19/19] arm: mx6: cm_fx6: add sata support

[Nikita Kiryanov]

Add support for SATA.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V4:
	- Use load instead of fatload.
	- Removed default declaration of cm_fx6_setup_issd() for when CONFIG_DWC_AHSATA
	  is not defined.

Changes in V3:
	- No changes.

Changes in V2:
	- No changes.

 board/compulab/cm_fx6/cm_fx6.c | 87 ++++++++++++++++++++++++++++++++++++++++++
 board/compulab/cm_fx6/common.h | 13 +++++++
 include/configs/cm_fx6.h       | 34 +++++++++++++++++
 3 files changed, 134 insertions(+)

diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 1664fe8..fdb8ebf 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -13,10 +13,12 @@
 #include <miiphy.h>
 #include <netdev.h>
 #include <fdt_support.h>
+#include <sata.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/iomux.h>
 #include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include "common.h"
@@ -24,6 +26,91 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_DWC_AHSATA
+static int cm_fx6_issd_gpios[] = {
+	/* The order of the GPIOs in the array is important! */
+	CM_FX6_SATA_PHY_SLP,
+	CM_FX6_SATA_NRSTDLY,
+	CM_FX6_SATA_PWREN,
+	CM_FX6_SATA_NSTANDBY1,
+	CM_FX6_SATA_NSTANDBY2,
+	CM_FX6_SATA_LDO_EN,
+};
+
+static void cm_fx6_sata_power(int on)
+{
+	int i;
+
+	if (!on) { /* tell the iSSD that the power will be removed */
+		gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
+		mdelay(10);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
+		gpio_direction_output(cm_fx6_issd_gpios[i], on);
+		udelay(100);
+	}
+
+	if (!on) /* for compatibility lower the power loss interrupt */
+		gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
+}
+
+static iomux_v3_cfg_t const sata_pads[] = {
+	/* SATA PWR */
+	IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* SATA CTRL */
+	IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_issd(void)
+{
+	SETUP_IOMUX_PADS(sata_pads);
+	/* Make sure this gpio has logical 0 value */
+	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
+	udelay(100);
+
+	cm_fx6_sata_power(0);
+	mdelay(250);
+	cm_fx6_sata_power(1);
+}
+
+#define CM_FX6_SATA_INIT_RETRIES	10
+int sata_initialize(void)
+{
+	int err, i;
+
+	cm_fx6_setup_issd();
+	for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
+		err = setup_sata();
+		if (err) {
+			printf("SATA setup failed: %d\n", err);
+			return err;
+		}
+
+		udelay(100);
+
+		err = __sata_initialize();
+		if (!err)
+			break;
+
+		/* There is no device on the SATA port */
+		if (sata_port_status(0, 0) == 0)
+			break;
+
+		/* There's a device, but link not established. Retry */
+	}
+
+	return err;
+}
+#endif
+
 #ifdef CONFIG_SYS_I2C_MXC
 #define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 			PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h
index f841c90..76097f8 100644
--- a/board/compulab/cm_fx6/common.h
+++ b/board/compulab/cm_fx6/common.h
@@ -19,6 +19,19 @@
 #define CM_FX6_ENET_NRST	IMX_GPIO_NR(2, 8)
 #define CM_FX6_USB_HUB_RST	IMX_GPIO_NR(7, 8)
 #define SB_FX6_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
+#define CM_FX6_ENET_NRST	IMX_GPIO_NR(2, 8)
+#define CM_FX6_USB_HUB_RST	IMX_GPIO_NR(7, 8)
+#define SB_FX6_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
+#define CM_FX6_SATA_PWREN	IMX_GPIO_NR(1, 28)
+#define CM_FX6_SATA_VDDC_CTRL	IMX_GPIO_NR(1, 30)
+#define CM_FX6_SATA_LDO_EN	IMX_GPIO_NR(2, 16)
+#define CM_FX6_SATA_NSTANDBY1	IMX_GPIO_NR(3, 20)
+#define CM_FX6_SATA_PHY_SLP	IMX_GPIO_NR(3, 23)
+#define CM_FX6_SATA_STBY_REQ	IMX_GPIO_NR(3, 29)
+#define CM_FX6_SATA_NSTANDBY2	IMX_GPIO_NR(5, 2)
+#define CM_FX6_SATA_NRSTDLY	IMX_GPIO_NR(6, 6)
+#define CM_FX6_SATA_PWLOSS_INT	IMX_GPIO_NR(6, 31)
+
 
 void cm_fx6_set_usdhc_iomux(void);
 void cm_fx6_set_ecspi_iomux(void);
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index cccc989..10d02b4 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -128,6 +128,19 @@
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"run doboot\0" \
+	"satadev=0\0" \
+	"sataroot=/dev/sda2 rw rootwait\0" \
+	"sataargs=setenv bootargs console=${console} " \
+		"root=${sataroot} " \
+		"${video}\0" \
+	"loadsatabootscript=load sata ${satadev} ${loadaddr} ${bootscr}\0" \
+	"satabootscript=echo Running bootscript from sata ...; " \
+		"source ${loadaddr}\0" \
+	"sataloadkernel=load sata ${satadev} ${loadaddr} ${kernel}\0" \
+	"sataloadfdt=load sata ${satadev} ${fdtaddr} ${fdtfile}\0" \
+	"sataboot=echo Booting from sata ...; "\
+		"run sataargs; " \
+		"run doboot\0" \
 	"nandroot=/dev/mtdblock4 rw\0" \
 	"nandrootfstype=ubifs\0" \
 	"nandargs=setenv bootargs console=${console} " \
@@ -155,6 +168,18 @@
 				"fi;" \
 			"fi;" \
 		"fi;" \
+		"if sata init; then " \
+			"if run loadsatabootscript; then " \
+				"run satabootscript;" \
+			"else "\
+				"if run sataloadkernel; then " \
+					"if ${loadfdt}; then " \
+						"run sataloadfdt; " \
+					"fi;" \
+					"run sataboot;" \
+				"fi;" \
+			"fi;" \
+		"fi;" \
 		"run nandboot\0"
 
 #define CONFIG_BOOTCOMMAND \
@@ -221,6 +246,15 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_I2C_EEPROM_BUS	2
 
+/* SATA */
+#define CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_DWC_AHSATA
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+
 /* GPIO */
 #define CONFIG_MXC_GPIO
 
-- 
1.9.1

[U-Boot] [PATCH V4 01/19] spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*

[Jagan Teki]

On Wed, Aug 20, 2014 at 5:38 PM, Nikita Kiryanov <nikita@compulab.co.il> wrote:
> Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
> SPL. These #defines do not allow the user to select SPI mode for the SPI flash
> (there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
> spi_spl_load.c), and duplicate information already provided by
> CONFIG_SF_DEFAULT_* #defines.
>
> Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.
>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> Cc: Tom Rini <trini@ti.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
> Cc: Lokesh Vutla <lokeshvutla@ti.com>
> Cc: Vitaly Andrianov <vitalya@ti.com>
> Cc: Lars Poeschel <poeschel@lemonage.de>
> Cc: Bo Shen <voice.shen@atmel.com>
> Cc: Hannes Petermaier <hannes.petermaier@br-automation.com>
> Cc: Michal Simek <monstr@monstr.eu>
> Acked-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
> ---
> Changes in V4:
>         - No changes
>
> Changes in V3:
>         - No changes
>
> Changes in V2:
>         - New patch replacing "spl: improve spi configuration".
>
>  common/cmd_sf.c                        | 13 -------------
>  drivers/mtd/spi/spi_spl_load.c         |  6 ++++--
>  include/configs/am335x_evm.h           |  2 --
>  include/configs/da850evm.h             |  4 ----
>  include/configs/dra7xx_evm.h           |  2 --
>  include/configs/ks2_evm.h              |  2 --
>  include/configs/pcm051.h               |  2 --
>  include/configs/sama5d3xek.h           |  2 --
>  include/configs/siemens-am33x-common.h |  2 --
>  include/configs/tseries.h              |  2 --
>  include/configs/zynq-common.h          |  2 --
>  include/spi_flash.h                    | 13 +++++++++++++
>  12 files changed, 17 insertions(+), 35 deletions(-)
>
> diff --git a/common/cmd_sf.c b/common/cmd_sf.c
> index b4ceb71..c60e8d1 100644
> --- a/common/cmd_sf.c
> +++ b/common/cmd_sf.c
> @@ -13,19 +13,6 @@
>
>  #include <asm/io.h>
>
> -#ifndef CONFIG_SF_DEFAULT_SPEED
> -# define CONFIG_SF_DEFAULT_SPEED       1000000
> -#endif
> -#ifndef CONFIG_SF_DEFAULT_MODE
> -# define CONFIG_SF_DEFAULT_MODE                SPI_MODE_3
> -#endif
> -#ifndef CONFIG_SF_DEFAULT_CS
> -# define CONFIG_SF_DEFAULT_CS          0
> -#endif
> -#ifndef CONFIG_SF_DEFAULT_BUS
> -# define CONFIG_SF_DEFAULT_BUS         0
> -#endif
> -
>  static struct spi_flash *flash;
>
>
> diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
> index 1954b7e..59cca0f 100644
> --- a/drivers/mtd/spi/spi_spl_load.c
> +++ b/drivers/mtd/spi/spi_spl_load.c
> @@ -56,8 +56,10 @@ void spl_spi_load_image(void)
>          * Load U-Boot image from SPI flash into RAM
>          */
>
> -       flash = spi_flash_probe(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS,
> -                               CONFIG_SF_DEFAULT_SPEED, SPI_MODE_3);
> +       flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
> +                               CONFIG_SF_DEFAULT_CS,
> +                               CONFIG_SF_DEFAULT_SPEED,
> +                               CONFIG_SF_DEFAULT_MODE);
>         if (!flash) {
>                 puts("SPI probe failed.\n");
>                 hang();
> diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
> index 35ae0e6..750aedd 100644
> --- a/include/configs/am335x_evm.h
> +++ b/include/configs/am335x_evm.h
> @@ -381,8 +381,6 @@
>  #define CONFIG_SPL_SPI_SUPPORT
>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>  #define CONFIG_SPL_SPI_LOAD
> -#define CONFIG_SPL_SPI_BUS             0
> -#define CONFIG_SPL_SPI_CS              0
>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
>
>  #define CONFIG_ENV_IS_IN_SPI_FLASH
> diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
> index 1252d7a..5f85755 100644
> --- a/include/configs/da850evm.h
> +++ b/include/configs/da850evm.h
> @@ -157,8 +157,6 @@
>  #define CONFIG_SPL_SPI_SUPPORT
>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>  #define CONFIG_SPL_SPI_LOAD
> -#define CONFIG_SPL_SPI_BUS 0
> -#define CONFIG_SPL_SPI_CS 0
>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x8000
>  #define CONFIG_SYS_SPI_U_BOOT_SIZE     0x30000
>  #endif
> @@ -376,8 +374,6 @@
>  #define CONFIG_SPL_SPI_SUPPORT
>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>  #define CONFIG_SPL_SPI_LOAD
> -#define CONFIG_SPL_SPI_BUS 0
> -#define CONFIG_SPL_SPI_CS 0
>  #define CONFIG_SPL_SERIAL_SUPPORT
>  #define CONFIG_SPL_LIBCOMMON_SUPPORT
>  #define CONFIG_SPL_LIBGENERIC_SUPPORT
> diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
> index 8d0a0eb..0f91ef8 100644
> --- a/include/configs/dra7xx_evm.h
> +++ b/include/configs/dra7xx_evm.h
> @@ -115,8 +115,6 @@
>  #define CONFIG_SPL_SPI_SUPPORT
>  #define CONFIG_SPL_SPI_LOAD
>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
> -#define CONFIG_SPL_SPI_BUS             0
> -#define CONFIG_SPL_SPI_CS              0
>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000
>
>  #define CONFIG_SUPPORT_EMMC_BOOT
> diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
> index 43db581..51926f7 100644
> --- a/include/configs/ks2_evm.h
> +++ b/include/configs/ks2_evm.h
> @@ -58,8 +58,6 @@
>  #define CONFIG_SPL_SPI_SUPPORT
>  #define CONFIG_SPL_BOARD_INIT
>  #define CONFIG_SPL_SPI_LOAD
> -#define CONFIG_SPL_SPI_BUS             0
> -#define CONFIG_SPL_SPI_CS              0
>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
>  #define CONFIG_SPL_FRAMEWORK
>
> diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
> index dcf5537..19ce121 100644
> --- a/include/configs/pcm051.h
> +++ b/include/configs/pcm051.h
> @@ -232,8 +232,6 @@
>  #define CONFIG_SPL_SPI_SUPPORT
>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>  #define CONFIG_SPL_SPI_LOAD
> -#define CONFIG_SPL_SPI_BUS             0
> -#define CONFIG_SPL_SPI_CS              0
>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
>  #define CONFIG_SYS_SPI_U_BOOT_SIZE     0x40000
>  #define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/am33xx/u-boot-spl.lds"
> diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
> index 56c2454..da545c4 100644
> --- a/include/configs/sama5d3xek.h
> +++ b/include/configs/sama5d3xek.h
> @@ -287,8 +287,6 @@
>  #define CONFIG_SPL_SPI_SUPPORT
>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>  #define CONFIG_SPL_SPI_LOAD
> -#define CONFIG_SPL_SPI_BUS             0
> -#define CONFIG_SPL_SPI_CS              0
>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x8400
>
>  #endif
> diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
> index b8fb77e..bf9752f 100644
> --- a/include/configs/siemens-am33x-common.h
> +++ b/include/configs/siemens-am33x-common.h
> @@ -167,8 +167,6 @@
>  #define CONFIG_SPL_SPI_SUPPORT
>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>  #define CONFIG_SPL_SPI_LOAD
> -#define CONFIG_SPL_SPI_BUS             0
> -#define CONFIG_SPL_SPI_CS              0
>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
>
>  #define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/am33xx/u-boot-spl.lds"
> diff --git a/include/configs/tseries.h b/include/configs/tseries.h
> index 1fd6e32..2497a1e 100644
> --- a/include/configs/tseries.h
> +++ b/include/configs/tseries.h
> @@ -222,8 +222,6 @@
>  #define CONFIG_SPL_SPI_SUPPORT
>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>  #define CONFIG_SPL_SPI_LOAD
> -#define CONFIG_SPL_SPI_BUS             0
> -#define CONFIG_SPL_SPI_CS              0
>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
>  #undef CONFIG_ENV_IS_NOWHERE
>  #define CONFIG_ENV_IS_IN_SPI_FLASH
> diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
> index d57e9d5..b49de25 100644
> --- a/include/configs/zynq-common.h
> +++ b/include/configs/zynq-common.h
> @@ -304,9 +304,7 @@
>  #define CONFIG_SPL_SPI_SUPPORT
>  #define CONFIG_SPL_SPI_LOAD
>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
> -#define CONFIG_SPL_SPI_BUS     0
>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x100000
> -#define CONFIG_SPL_SPI_CS      0
>  #endif
>
>  /* for booting directly linux */
> diff --git a/include/spi_flash.h b/include/spi_flash.h
> index 2db53c7..43f7f2c 100644
> --- a/include/spi_flash.h
> +++ b/include/spi_flash.h
> @@ -19,6 +19,19 @@
>  #include <linux/types.h>
>  #include <linux/compiler.h>
>
> +#ifndef CONFIG_SF_DEFAULT_SPEED
> +       #define CONFIG_SF_DEFAULT_SPEED         1000000
> +#endif
> +#ifndef CONFIG_SF_DEFAULT_MODE
> +       #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_3
> +#endif
> +#ifndef CONFIG_SF_DEFAULT_CS
> +       #define CONFIG_SF_DEFAULT_CS            0
> +#endif
> +#ifndef CONFIG_SF_DEFAULT_BUS
> +       #define CONFIG_SF_DEFAULT_BUS           0
> +#endif
> +
>  /* sf param flags */
>  #define SECT_4K                1 << 1
>  #define SECT_32K       1 << 2
> --
> 1.9.1
>

Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

thanks!
-- 
Jagan.

[U-Boot] [PATCH V4 04/19] mtd: spi: add support for M25PE16 and M25PX16

[Jagan Teki]

On Wed, Aug 20, 2014 at 5:38 PM, Nikita Kiryanov <nikita@compulab.co.il> wrote:
> Add support for M25PE16 and M25PX16
>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> Cc: Marek Vasut <marex@denx.de>
> Acked-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
> ---
> Changes in V4:
>         - No changes.
>
> Changes in V3:
>         - No changes.
>
> Changes in V2:
>         - No changes.
>
>  drivers/mtd/spi/sf_params.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
> index ac886fd..3a4beb0 100644
> --- a/drivers/mtd/spi/sf_params.c
> +++ b/drivers/mtd/spi/sf_params.c
> @@ -68,6 +68,8 @@ const struct spi_flash_params spi_flash_params_table[] = {
>         {"M25P40",         0x202013, 0x0,       64 * 1024,     8,       0,                        0},
>         {"M25P80",         0x202014, 0x0,       64 * 1024,    16,       0,                        0},
>         {"M25P16",         0x202015, 0x0,       64 * 1024,    32,       0,                        0},
> +       {"M25PE16",        0x208015, 0x1000,    64 * 1024,    32,       0,                        0},
> +       {"M25PX16",        0x207115, 0x1000,    64 * 1024,    32, RD_EXTN,                        0},
>         {"M25P32",         0x202016, 0x0,       64 * 1024,    64,       0,                        0},
>         {"M25P64",         0x202017, 0x0,       64 * 1024,   128,       0,                        0},
>         {"M25P128",        0x202018, 0x0,      256 * 1024,    64,       0,                        0},
> --
> 1.9.1
>

Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

thanks!
-- 
Jagan.

[U-Boot] [PATCH V4 01/19] spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*

[Jagan Teki]

On Thu, Aug 21, 2014 at 11:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> On Wed, Aug 20, 2014 at 5:38 PM, Nikita Kiryanov <nikita@compulab.co.il> wrote:
>> Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
>> SPL. These #defines do not allow the user to select SPI mode for the SPI flash
>> (there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
>> spi_spl_load.c), and duplicate information already provided by
>> CONFIG_SF_DEFAULT_* #defines.
>>
>> Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.
>>
>> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
>> Cc: Tom Rini <trini@ti.com>
>> Cc: Marek Vasut <marex@denx.de>
>> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
>> Cc: Lokesh Vutla <lokeshvutla@ti.com>
>> Cc: Vitaly Andrianov <vitalya@ti.com>
>> Cc: Lars Poeschel <poeschel@lemonage.de>
>> Cc: Bo Shen <voice.shen@atmel.com>
>> Cc: Hannes Petermaier <hannes.petermaier@br-automation.com>
>> Cc: Michal Simek <monstr@monstr.eu>
>> Acked-by: Marek Vasut <marex@denx.de>
>> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
>> ---
>> Changes in V4:
>>         - No changes
>>
>> Changes in V3:
>>         - No changes
>>
>> Changes in V2:
>>         - New patch replacing "spl: improve spi configuration".
>>
>>  common/cmd_sf.c                        | 13 -------------
>>  drivers/mtd/spi/spi_spl_load.c         |  6 ++++--
>>  include/configs/am335x_evm.h           |  2 --
>>  include/configs/da850evm.h             |  4 ----
>>  include/configs/dra7xx_evm.h           |  2 --
>>  include/configs/ks2_evm.h              |  2 --
>>  include/configs/pcm051.h               |  2 --
>>  include/configs/sama5d3xek.h           |  2 --
>>  include/configs/siemens-am33x-common.h |  2 --
>>  include/configs/tseries.h              |  2 --
>>  include/configs/zynq-common.h          |  2 --
>>  include/spi_flash.h                    | 13 +++++++++++++
>>  12 files changed, 17 insertions(+), 35 deletions(-)
>>
>> diff --git a/common/cmd_sf.c b/common/cmd_sf.c
>> index b4ceb71..c60e8d1 100644
>> --- a/common/cmd_sf.c
>> +++ b/common/cmd_sf.c
>> @@ -13,19 +13,6 @@
>>
>>  #include <asm/io.h>
>>
>> -#ifndef CONFIG_SF_DEFAULT_SPEED
>> -# define CONFIG_SF_DEFAULT_SPEED       1000000
>> -#endif
>> -#ifndef CONFIG_SF_DEFAULT_MODE
>> -# define CONFIG_SF_DEFAULT_MODE                SPI_MODE_3
>> -#endif
>> -#ifndef CONFIG_SF_DEFAULT_CS
>> -# define CONFIG_SF_DEFAULT_CS          0
>> -#endif
>> -#ifndef CONFIG_SF_DEFAULT_BUS
>> -# define CONFIG_SF_DEFAULT_BUS         0
>> -#endif
>> -
>>  static struct spi_flash *flash;
>>
>>
>> diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
>> index 1954b7e..59cca0f 100644
>> --- a/drivers/mtd/spi/spi_spl_load.c
>> +++ b/drivers/mtd/spi/spi_spl_load.c
>> @@ -56,8 +56,10 @@ void spl_spi_load_image(void)
>>          * Load U-Boot image from SPI flash into RAM
>>          */
>>
>> -       flash = spi_flash_probe(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS,
>> -                               CONFIG_SF_DEFAULT_SPEED, SPI_MODE_3);
>> +       flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
>> +                               CONFIG_SF_DEFAULT_CS,
>> +                               CONFIG_SF_DEFAULT_SPEED,
>> +                               CONFIG_SF_DEFAULT_MODE);
>>         if (!flash) {
>>                 puts("SPI probe failed.\n");
>>                 hang();
>> diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
>> index 35ae0e6..750aedd 100644
>> --- a/include/configs/am335x_evm.h
>> +++ b/include/configs/am335x_evm.h
>> @@ -381,8 +381,6 @@
>>  #define CONFIG_SPL_SPI_SUPPORT
>>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>>  #define CONFIG_SPL_SPI_LOAD
>> -#define CONFIG_SPL_SPI_BUS             0
>> -#define CONFIG_SPL_SPI_CS              0
>>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
>>
>>  #define CONFIG_ENV_IS_IN_SPI_FLASH
>> diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
>> index 1252d7a..5f85755 100644
>> --- a/include/configs/da850evm.h
>> +++ b/include/configs/da850evm.h
>> @@ -157,8 +157,6 @@
>>  #define CONFIG_SPL_SPI_SUPPORT
>>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>>  #define CONFIG_SPL_SPI_LOAD
>> -#define CONFIG_SPL_SPI_BUS 0
>> -#define CONFIG_SPL_SPI_CS 0
>>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x8000
>>  #define CONFIG_SYS_SPI_U_BOOT_SIZE     0x30000
>>  #endif
>> @@ -376,8 +374,6 @@
>>  #define CONFIG_SPL_SPI_SUPPORT
>>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>>  #define CONFIG_SPL_SPI_LOAD
>> -#define CONFIG_SPL_SPI_BUS 0
>> -#define CONFIG_SPL_SPI_CS 0
>>  #define CONFIG_SPL_SERIAL_SUPPORT
>>  #define CONFIG_SPL_LIBCOMMON_SUPPORT
>>  #define CONFIG_SPL_LIBGENERIC_SUPPORT
>> diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
>> index 8d0a0eb..0f91ef8 100644
>> --- a/include/configs/dra7xx_evm.h
>> +++ b/include/configs/dra7xx_evm.h
>> @@ -115,8 +115,6 @@
>>  #define CONFIG_SPL_SPI_SUPPORT
>>  #define CONFIG_SPL_SPI_LOAD
>>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>> -#define CONFIG_SPL_SPI_BUS             0
>> -#define CONFIG_SPL_SPI_CS              0
>>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000
>>
>>  #define CONFIG_SUPPORT_EMMC_BOOT
>> diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
>> index 43db581..51926f7 100644
>> --- a/include/configs/ks2_evm.h
>> +++ b/include/configs/ks2_evm.h
>> @@ -58,8 +58,6 @@
>>  #define CONFIG_SPL_SPI_SUPPORT
>>  #define CONFIG_SPL_BOARD_INIT
>>  #define CONFIG_SPL_SPI_LOAD
>> -#define CONFIG_SPL_SPI_BUS             0
>> -#define CONFIG_SPL_SPI_CS              0
>>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
>>  #define CONFIG_SPL_FRAMEWORK
>>
>> diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
>> index dcf5537..19ce121 100644
>> --- a/include/configs/pcm051.h
>> +++ b/include/configs/pcm051.h
>> @@ -232,8 +232,6 @@
>>  #define CONFIG_SPL_SPI_SUPPORT
>>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>>  #define CONFIG_SPL_SPI_LOAD
>> -#define CONFIG_SPL_SPI_BUS             0
>> -#define CONFIG_SPL_SPI_CS              0
>>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
>>  #define CONFIG_SYS_SPI_U_BOOT_SIZE     0x40000
>>  #define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/am33xx/u-boot-spl.lds"
>> diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
>> index 56c2454..da545c4 100644
>> --- a/include/configs/sama5d3xek.h
>> +++ b/include/configs/sama5d3xek.h
>> @@ -287,8 +287,6 @@
>>  #define CONFIG_SPL_SPI_SUPPORT
>>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>>  #define CONFIG_SPL_SPI_LOAD
>> -#define CONFIG_SPL_SPI_BUS             0
>> -#define CONFIG_SPL_SPI_CS              0
>>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x8400
>>
>>  #endif
>> diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
>> index b8fb77e..bf9752f 100644
>> --- a/include/configs/siemens-am33x-common.h
>> +++ b/include/configs/siemens-am33x-common.h
>> @@ -167,8 +167,6 @@
>>  #define CONFIG_SPL_SPI_SUPPORT
>>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>>  #define CONFIG_SPL_SPI_LOAD
>> -#define CONFIG_SPL_SPI_BUS             0
>> -#define CONFIG_SPL_SPI_CS              0
>>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
>>
>>  #define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/am33xx/u-boot-spl.lds"
>> diff --git a/include/configs/tseries.h b/include/configs/tseries.h
>> index 1fd6e32..2497a1e 100644
>> --- a/include/configs/tseries.h
>> +++ b/include/configs/tseries.h
>> @@ -222,8 +222,6 @@
>>  #define CONFIG_SPL_SPI_SUPPORT
>>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>>  #define CONFIG_SPL_SPI_LOAD
>> -#define CONFIG_SPL_SPI_BUS             0
>> -#define CONFIG_SPL_SPI_CS              0
>>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
>>  #undef CONFIG_ENV_IS_NOWHERE
>>  #define CONFIG_ENV_IS_IN_SPI_FLASH
>> diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
>> index d57e9d5..b49de25 100644
>> --- a/include/configs/zynq-common.h
>> +++ b/include/configs/zynq-common.h
>> @@ -304,9 +304,7 @@
>>  #define CONFIG_SPL_SPI_SUPPORT
>>  #define CONFIG_SPL_SPI_LOAD
>>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
>> -#define CONFIG_SPL_SPI_BUS     0
>>  #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x100000
>> -#define CONFIG_SPL_SPI_CS      0
>>  #endif
>>
>>  /* for booting directly linux */
>> diff --git a/include/spi_flash.h b/include/spi_flash.h
>> index 2db53c7..43f7f2c 100644
>> --- a/include/spi_flash.h
>> +++ b/include/spi_flash.h
>> @@ -19,6 +19,19 @@
>>  #include <linux/types.h>
>>  #include <linux/compiler.h>
>>
>> +#ifndef CONFIG_SF_DEFAULT_SPEED
>> +       #define CONFIG_SF_DEFAULT_SPEED         1000000
>> +#endif
>> +#ifndef CONFIG_SF_DEFAULT_MODE
>> +       #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_3
>> +#endif
>> +#ifndef CONFIG_SF_DEFAULT_CS
>> +       #define CONFIG_SF_DEFAULT_CS            0
>> +#endif
>> +#ifndef CONFIG_SF_DEFAULT_BUS
>> +       #define CONFIG_SF_DEFAULT_BUS           0
>> +#endif
>> +
>>  /* sf param flags */
>>  #define SECT_4K                1 << 1
>>  #define SECT_32K       1 << 2
>> --
>> 1.9.1
>>
>
> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Applied to u-boot-spi/master

thanks!
-- 
Jagan.

[U-Boot] [PATCH V4 04/19] mtd: spi: add support for M25PE16 and M25PX16

[Jagan Teki]

On Thu, Aug 21, 2014 at 11:02 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> On Wed, Aug 20, 2014 at 5:38 PM, Nikita Kiryanov <nikita@compulab.co.il> wrote:
>> Add support for M25PE16 and M25PX16
>>
>> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
>> Cc: Marek Vasut <marex@denx.de>
>> Acked-by: Marek Vasut <marex@denx.de>
>> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
>> ---
>> Changes in V4:
>>         - No changes.
>>
>> Changes in V3:
>>         - No changes.
>>
>> Changes in V2:
>>         - No changes.
>>
>>  drivers/mtd/spi/sf_params.c | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
>> index ac886fd..3a4beb0 100644
>> --- a/drivers/mtd/spi/sf_params.c
>> +++ b/drivers/mtd/spi/sf_params.c
>> @@ -68,6 +68,8 @@ const struct spi_flash_params spi_flash_params_table[] = {
>>         {"M25P40",         0x202013, 0x0,       64 * 1024,     8,       0,                        0},
>>         {"M25P80",         0x202014, 0x0,       64 * 1024,    16,       0,                        0},
>>         {"M25P16",         0x202015, 0x0,       64 * 1024,    32,       0,                        0},
>> +       {"M25PE16",        0x208015, 0x1000,    64 * 1024,    32,       0,                        0},
>> +       {"M25PX16",        0x207115, 0x1000,    64 * 1024,    32, RD_EXTN,                        0},
>>         {"M25P32",         0x202016, 0x0,       64 * 1024,    64,       0,                        0},
>>         {"M25P64",         0x202017, 0x0,       64 * 1024,   128,       0,                        0},
>>         {"M25P128",        0x202018, 0x0,      256 * 1024,    64,       0,                        0},
>> --
>> 1.9.1
>>
>
> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Applied to u-boot-spi/master

thanks!
-- 
Jagan.

[U-Boot] [PATCH V4 03/19] spi: mxc: fix sf probe when using mxc_spi

[Jagan Teki]

On Wed, Aug 20, 2014 at 5:38 PM, Nikita Kiryanov <nikita@compulab.co.il> wrote:
> MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
> across multiple transactions. This is set up by embedding the GPIO information
> in the CS value:
>
> cs = (cs | gpio << 8)
>
> This merge of cs and gpio data into one value breaks the sf probe command:
> if the use of gpio is required, invoking "sf probe <cs>" will not work, because
> the CS argument doesn't have the GPIO information in it. Instead, the user must
> use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
> cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
> type "sf probe 15872".
>
> This is inconsistent with the description of the sf probe command, and forces
> the user to be aware of implementaiton details.
>
> Fix this by introducing a new board function: board_spi_cs_gpio(), which will
> accept a naked CS value, and provide the driver with the relevant GPIO, if one
> is necessary.
>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> Cc: Eric Nelson <eric.nelson@boundarydevices.com>
> Cc: Eric Benard <eric@eukrea.com>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> Cc: Tim Harvey <tharvey@gateworks.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tom Rini <trini@ti.com>
> Cc: Marek Vasut <marex@denx.de>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
> ---
> Changes in V4:
>         - No changes.
>
> Changes in V3:
>         - No changes.
>
> Changes in V2:
>         - Rewrote commit message, renaming the patch in the process (originally
>           "sf: fix sf probe").
>
>  board/boundary/nitrogen6x/nitrogen6x.c        |  5 +++
>  board/embest/mx6boards/mx6boards.c            |  5 +++
>  board/freescale/mx6qsabreauto/mx6qsabreauto.c |  7 ++++
>  board/freescale/mx6sabresd/mx6sabresd.c       |  7 ++++
>  board/freescale/mx6slevk/mx6slevk.c           |  5 +++
>  board/gateworks/gw_ventana/gw_ventana.c       |  7 +++-
>  board/genesi/mx51_efikamx/efikamx.c           |  5 +++
>  board/ttcontrol/vision2/vision2.c             |  5 +++
>  drivers/spi/mxc_spi.c                         | 48 ++++++++++++++-------------
>  include/configs/embestmx6boards.h             |  2 +-
>  include/configs/gw_ventana.h                  |  2 +-
>  include/configs/mx51_efikamx.h                |  4 +--
>  include/configs/mx6sabre_common.h             |  2 +-
>  include/configs/mx6slevk.h                    |  2 +-
>  include/configs/nitrogen6x.h                  |  2 +-
>  include/configs/vision2.h                     |  4 +--
>  16 files changed, 79 insertions(+), 33 deletions(-)
>
> diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
> index 84294db..aadddb9 100644
> --- a/board/boundary/nitrogen6x/nitrogen6x.c
> +++ b/board/boundary/nitrogen6x/nitrogen6x.c
> @@ -328,6 +328,11 @@ int board_mmc_init(bd_t *bis)
>  #endif
>
>  #ifdef CONFIG_MXC_SPI
> +int board_spi_cs_gpio(unsigned bus, unsigned cs)
> +{
> +       return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
> +}
> +
>  iomux_v3_cfg_t const ecspi1_pads[] = {
>         /* SS1 */
>         MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(NO_PAD_CTRL),
> diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
> index d06b57d..e8a11c2 100644
> --- a/board/embest/mx6boards/mx6boards.c
> +++ b/board/embest/mx6boards/mx6boards.c
> @@ -284,6 +284,11 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
>         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
>  };
>
> +int board_spi_cs_gpio(unsigned bus, unsigned cs)
> +{
> +       return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
> +}
> +
>  static void setup_spi(void)
>  {
>         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
> diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> index 928dadf..836d722 100644
> --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> @@ -259,6 +259,13 @@ int board_init(void)
>         return 0;
>  }
>
> +#ifdef CONFIG_MXC_SPI
> +int board_spi_cs_gpio(unsigned bus, unsigned cs)
> +{
> +       return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
> +}
> +#endif
> +
>  #ifdef CONFIG_CMD_BMODE
>  static const struct boot_mode board_boot_modes[] = {
>         /* 4 bit bus width */
> diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
> index d7c4b4f..c5f10f7 100644
> --- a/board/freescale/mx6sabresd/mx6sabresd.c
> +++ b/board/freescale/mx6sabresd/mx6sabresd.c
> @@ -513,6 +513,13 @@ static int pfuze_init(void)
>         return 0;
>  }
>
> +#ifdef CONFIG_MXC_SPI
> +int board_spi_cs_gpio(unsigned bus, unsigned cs)
> +{
> +       return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
> +}
> +#endif
> +
>  #ifdef CONFIG_CMD_BMODE
>  static const struct boot_mode board_boot_modes[] = {
>         /* 4 bit bus width */
> diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
> index d2b64cc..ec63d9e 100644
> --- a/board/freescale/mx6slevk/mx6slevk.c
> +++ b/board/freescale/mx6slevk/mx6slevk.c
> @@ -82,6 +82,11 @@ static iomux_v3_cfg_t ecspi1_pads[] = {
>         MX6_PAD_ECSPI1_SS0__GPIO4_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL),
>  };
>
> +int board_spi_cs_gpio(unsigned bus, unsigned cs)
> +{
> +       return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
> +}
> +
>  static void setup_spi(void)
>  {
>         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
> diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
> index 9d2651f..054f904 100644
> --- a/board/gateworks/gw_ventana/gw_ventana.c
> +++ b/board/gateworks/gw_ventana/gw_ventana.c
> @@ -353,9 +353,14 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
>         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
>  };
>
> +int board_spi_cs_gpio(unsigned bus, unsigned cs)
> +{
> +       return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
> +}
> +
>  static void setup_spi(void)
>  {
> -       gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
> +       gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
>         SETUP_IOMUX_PADS(ecspi1_pads);
>  }
>  #endif
> diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
> index 16769e5..137e4ed 100644
> --- a/board/genesi/mx51_efikamx/efikamx.c
> +++ b/board/genesi/mx51_efikamx/efikamx.c
> @@ -152,6 +152,11 @@ static iomux_v3_cfg_t const efikamx_spi_pads[] = {
>   * PMIC configuration
>   */
>  #ifdef CONFIG_MXC_SPI
> +int board_spi_cs_gpio(unsigned bus, unsigned cs)
> +{
> +       return (bus == 0 && cs == 1) ? 121 : -1;
> +}
> +
>  static void power_init(void)
>  {
>         unsigned int val;
> diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
> index b4d3994..b5249e7 100644
> --- a/board/ttcontrol/vision2/vision2.c
> +++ b/board/ttcontrol/vision2/vision2.c
> @@ -144,6 +144,11 @@ static void setup_uart(void)
>  }
>
>  #ifdef CONFIG_MXC_SPI
> +int board_spi_cs_gpio(unsigned bus, unsigned cs)
> +{
> +       return (bus == 0 && cs == 1) ? 121 : -1;
> +}
> +
>  void spi_io_init(void)
>  {
>         static const iomux_v3_cfg_t spi_pads[] = {
> diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
> index 2d5f385..026f680 100644
> --- a/drivers/spi/mxc_spi.c
> +++ b/drivers/spi/mxc_spi.c
> @@ -25,6 +25,11 @@ static unsigned long spi_bases[] = {
>         MXC_SPI_BASE_ADDRESSES
>  };
>
> +__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
> +{
> +       return -1;
> +}
> +
>  #define OUT    MXC_GPIO_DIRECTION_OUT
>
>  #define reg_read readl
> @@ -371,31 +376,30 @@ void spi_init(void)
>  {
>  }
>
> -static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
> +/*
> + * Some SPI devices require active chip-select over multiple
> + * transactions, we achieve this using a GPIO. Still, the SPI
> + * controller has to be configured to use one of its own chipselects.
> + * To use this feature you have to implement board_spi_cs_gpio() to assign
> + * a gpio value for each cs (-1 if cs doesn't need to use gpio).
> + * You must use some unused on this SPI controller cs between 0 and 3.
> + */
> +static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
> +                        unsigned int bus, unsigned int cs)
>  {
>         int ret;
>
> -       /*
> -        * Some SPI devices require active chip-select over multiple
> -        * transactions, we achieve this using a GPIO. Still, the SPI
> -        * controller has to be configured to use one of its own chipselects.
> -        * To use this feature you have to call spi_setup_slave() with
> -        * cs = internal_cs | (gpio << 8), and you have to use some unused
> -        * on this SPI controller cs between 0 and 3.
> -        */
> -       if (cs > 3) {
> -               mxcs->gpio = cs >> 8;
> -               cs &= 3;
> -               ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
> -               if (ret) {
> -                       printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
> -                       return -EINVAL;
> -               }
> -       } else {
> -               mxcs->gpio = -1;
> +       mxcs->gpio = board_spi_cs_gpio(bus, cs);
> +       if (mxcs->gpio == -1)
> +               return 0;
> +
> +       ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
> +       if (ret) {
> +               printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
> +               return -EINVAL;
>         }
>
> -       return cs;
> +       return 0;
>  }
>
>  struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> @@ -415,14 +419,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
>
>         mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
>
> -       ret = decode_cs(mxcs, cs);
> +       ret = setup_cs_gpio(mxcs, bus, cs);
>         if (ret < 0) {
>                 free(mxcs);
>                 return NULL;
>         }
>
> -       cs = ret;
> -
>         mxcs->base = spi_bases[bus];
>
>         ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
> diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
> index f1000f3..bcd5ea4 100644
> --- a/include/configs/embestmx6boards.h
> +++ b/include/configs/embestmx6boards.h
> @@ -100,7 +100,7 @@
>  #define CONFIG_SPI_FLASH_SST
>  #define CONFIG_MXC_SPI
>  #define CONFIG_SF_DEFAULT_BUS          0
> -#define CONFIG_SF_DEFAULT_CS           (0 | (IMX_GPIO_NR(2, 30) << 8))
> +#define CONFIG_SF_DEFAULT_CS           0
>  #define CONFIG_SF_DEFAULT_SPEED                20000000
>  #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
>  #endif
> diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
> index 8197a72..97398a8 100644
> --- a/include/configs/gw_ventana.h
> +++ b/include/configs/gw_ventana.h
> @@ -61,7 +61,7 @@
>    #define CONFIG_SPI_FLASH_BAR
>    #define CONFIG_SPI_FLASH_WINBOND
>    #define CONFIG_SF_DEFAULT_BUS              0
> -  #define CONFIG_SF_DEFAULT_CS               (0|(IMX_GPIO_NR(3, 19)<<8))
> +  #define CONFIG_SF_DEFAULT_CS               0
>                                              /* GPIO 3-19 (21248) */
>    #define CONFIG_SF_DEFAULT_SPEED            30000000
>    #define CONFIG_SF_DEFAULT_MODE             (SPI_MODE_0)
> diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h
> index 0f2a4ef..fce7ead 100644
> --- a/include/configs/mx51_efikamx.h
> +++ b/include/configs/mx51_efikamx.h
> @@ -96,11 +96,11 @@
>
>  #define CONFIG_SPI_FLASH
>  #define CONFIG_SPI_FLASH_SST
> -#define CONFIG_SF_DEFAULT_CS           (1 | 121 << 8)
> +#define CONFIG_SF_DEFAULT_CS           1
>  #define CONFIG_SF_DEFAULT_MODE         (SPI_MODE_0)
>  #define CONFIG_SF_DEFAULT_SPEED                25000000
>
> -#define CONFIG_ENV_SPI_CS              (1 | 121 << 8)
> +#define CONFIG_ENV_SPI_CS              CONFIG_SF_DEFAULT_CS
>  #define CONFIG_ENV_SPI_BUS             0
>  #define CONFIG_ENV_SPI_MAX_HZ          25000000
>  #define CONFIG_ENV_SPI_MODE            (SPI_MODE_0)
> diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
> index e59a3b4..2d93d6c 100644
> --- a/include/configs/mx6sabre_common.h
> +++ b/include/configs/mx6sabre_common.h
> @@ -74,7 +74,7 @@
>  #define CONFIG_SPI_FLASH_STMICRO
>  #define CONFIG_MXC_SPI
>  #define CONFIG_SF_DEFAULT_BUS          0
> -#define CONFIG_SF_DEFAULT_CS           (0 | (IMX_GPIO_NR(4, 9) << 8))
> +#define CONFIG_SF_DEFAULT_CS           0
>  #define CONFIG_SF_DEFAULT_SPEED                20000000
>  #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
>  #endif
> diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
> index 3d05a64..5b8309b 100644
> --- a/include/configs/mx6slevk.h
> +++ b/include/configs/mx6slevk.h
> @@ -203,7 +203,7 @@
>  #define CONFIG_SPI_FLASH_STMICRO
>  #define CONFIG_MXC_SPI
>  #define CONFIG_SF_DEFAULT_BUS          0
> -#define CONFIG_SF_DEFAULT_CS           (0 | (IMX_GPIO_NR(4, 11) << 8))
> +#define CONFIG_SF_DEFAULT_CS           0
>  #define CONFIG_SF_DEFAULT_SPEED                20000000
>  #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
>  #endif
> diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
> index b2b17ce..d266f7d 100644
> --- a/include/configs/nitrogen6x.h
> +++ b/include/configs/nitrogen6x.h
> @@ -53,7 +53,7 @@
>  #define CONFIG_SPI_FLASH_SST
>  #define CONFIG_MXC_SPI
>  #define CONFIG_SF_DEFAULT_BUS  0
> -#define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(3, 19)<<8))
> +#define CONFIG_SF_DEFAULT_CS   0
>  #define CONFIG_SF_DEFAULT_SPEED 25000000
>  #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
>  #endif
> diff --git a/include/configs/vision2.h b/include/configs/vision2.h
> index 6891bf8..3f35076 100644
> --- a/include/configs/vision2.h
> +++ b/include/configs/vision2.h
> @@ -57,11 +57,11 @@
>   * Use gpio 4 pin 25 as chip select for SPI flash
>   * This corresponds to gpio 121
>   */
> -#define CONFIG_SF_DEFAULT_CS   (1 | (121 << 8))
> +#define CONFIG_SF_DEFAULT_CS    1
>  #define CONFIG_SF_DEFAULT_MODE   SPI_MODE_0
>  #define CONFIG_SF_DEFAULT_SPEED  25000000
>
> -#define CONFIG_ENV_SPI_CS      (1 | (121 << 8))
> +#define CONFIG_ENV_SPI_CS      CONFIG_SF_DEFAULT_CS
>  #define CONFIG_ENV_SPI_BUS      0
>  #define CONFIG_ENV_SPI_MAX_HZ  25000000
>  #define CONFIG_ENV_SPI_MODE    SPI_MODE_0
> --
> 1.9.1
>

Applied to u-boot-spi/master

thanks!
-- 
Jagan.

[U-Boot] [PATCH V4 10/19] arm: mx6: ddr: configure MMDC for slow_pd

[Nikita Kiryanov]

On 20/08/14 15:08, Nikita Kiryanov wrote:
> According to MX6 TRM, both MMDC and DRAM should be configured to
> the same powerdown precharge. Currently, mx6_dram_cfg()
> configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
> 'slow exit (DLL off)' (MR0[12] = 0).
>
> Configure MMDC for slow pd.
>

We have confirmation from a Freescale representative that the
configurations should be aligned:

https://community.freescale.com/thread/328577

-- 
Regards,
Nikita Kiryanov

[U-Boot] [PATCH V4 10/19] arm: mx6: ddr: configure MMDC for slow_pd

[Tim Harvey]

On Mon, Aug 25, 2014 at 8:36 AM, Nikita Kiryanov <nikita@compulab.co.il> wrote:
>
> On 20/08/14 15:08, Nikita Kiryanov wrote:
>>
>> According to MX6 TRM, both MMDC and DRAM should be configured to
>> the same powerdown precharge. Currently, mx6_dram_cfg()
>> configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
>> 'slow exit (DLL off)' (MR0[12] = 0).
>>
>> Configure MMDC for slow pd.
>>
>
> We have confirmation from a Freescale representative that the
> configurations should be aligned:
>
> https://community.freescale.com/thread/328577
>
> --
> Regards,
> Nikita Kiryanov

Nikita,

Yep...

Acked-by: Tim Harvey <tharvey@gateworks.com>

(Next I'll ask them about that delay for ZQ calibration - it bugs me
that your finding you need an extra 100us delay on your boards, but
that shouldn't hold up any of your patches)

Tim

[U-Boot] [PATCH V4 00/19] Introduce cm-fx6 board

[Nikita Kiryanov]

Hi Tom, Stefano,

We really want this series to make it into the next release (V1 was
submitted only a day after the merge window closed). If there are no
other comments, can we maybe start applying it?

-- 
Regards,
Nikita Kiryanov

[U-Boot] [PATCH V4 00/19] Introduce cm-fx6 board

[Tom Rini]

On Sun, Aug 31, 2014 at 11:09:06AM +0300, Nikita Kiryanov wrote:

> Hi Tom, Stefano,
> 
> We really want this series to make it into the next release (V1 was
> submitted only a day after the merge window closed). If there are no
> other comments, can we maybe start applying it?

For the record, I don't object.

-- 
Tom
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[U-Boot] [PATCH V5 08/19] arm: mx6: ddr: cleanup

[Nikita Kiryanov]

No functional changes.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V5:
	- Rebased over latest mainline code.

Changes in V4:
	- No changes.

Changes in V3:
	- No changes.

Changes in V2:
	- No changes.

 arch/arm/cpu/armv7/mx6/ddr.c | 278 +++++++++++++++++++++----------------------
 1 file changed, 137 insertions(+), 141 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 1ab69f6..5fc4d95 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -184,18 +184,18 @@ void mx6sdl_dram_iocfg(unsigned width,
  */
 #define MR(val, ba, cmd, cs1) \
 	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
-void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
-		  const struct mx6_mmdc_calibration *c,
-		  const struct mx6_ddr3_cfg *m)
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
+		  const struct mx6_mmdc_calibration *calib,
+		  const struct mx6_ddr3_cfg *ddr3_cfg)
 {
 	volatile struct mmdc_p_regs *mmdc0;
 	volatile struct mmdc_p_regs *mmdc1;
-	u32 reg;
+	u32 val;
 	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
 	u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
 	u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
 	u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
-	u16 CS0_END;
+	u16 cs0_end;
 	u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
 	u8 coladdr;
 	int clkper; /* clock period in picoseconds */
@@ -215,13 +215,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 		clock = 400;
 		tcwl = 3;
 	}
-	clkper = (1000*1000)/clock; /* ps */
+	clkper = (1000 * 1000) / clock; /* pico seconds */
 	todtlon = tcwl;
 	taxpd = tcwl;
 	tanpd = tcwl;
-	tcwl = tcwl;
 
-	switch (m->density) {
+	switch (ddr3_cfg->density) {
 	case 1: /* 1Gb per chip */
 		trfc = DIV_ROUND_UP(110000, clkper) - 1;
 		txs = DIV_ROUND_UP(120000, clkper) - 1;
@@ -240,80 +239,84 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 		break;
 	default:
 		/* invalid density */
-		printf("invalid chip density\n");
+		puts("invalid chip density\n");
 		hang();
 		break;
 	}
 	txpr = txs;
 
-	switch (m->mem_speed) {
+	switch (ddr3_cfg->mem_speed) {
 	case 800:
-		txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
-		tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
-		if (m->pagesz == 1) {
+		txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+		tcke = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+		if (ddr3_cfg->pagesz == 1) {
 			tfaw = DIV_ROUND_UP(40000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
 		} else {
 			tfaw = DIV_ROUND_UP(50000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
 		}
 		break;
 	case 1066:
-		txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
-		tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
-		if (m->pagesz == 1) {
+		txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+		tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
+		if (ddr3_cfg->pagesz == 1) {
 			tfaw = DIV_ROUND_UP(37500, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
 		} else {
 			tfaw = DIV_ROUND_UP(50000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
 		}
 		break;
 	case 1333:
-		txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
-		tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
-		if (m->pagesz == 1) {
+		txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
+		tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
+		if (ddr3_cfg->pagesz == 1) {
 			tfaw = DIV_ROUND_UP(30000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
 		} else {
 			tfaw = DIV_ROUND_UP(45000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
 		}
 		break;
 	case 1600:
-		txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
-		tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;
-		if (m->pagesz == 1) {
+		txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
+		tcke = DIV_ROUND_UP(MAX(3 * clkper, 5000), clkper) - 1;
+		if (ddr3_cfg->pagesz == 1) {
 			tfaw = DIV_ROUND_UP(30000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
 		} else {
 			tfaw = DIV_ROUND_UP(40000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
 		}
 		break;
 	default:
-		printf("invalid memory speed\n");
+		puts("invalid memory speed\n");
 		hang();
 		break;
 	}
-	txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;
-	tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;
-	tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
-	tcksrx = tcksre;
+	txpdll = DIV_ROUND_UP(MAX(10 * clkper, 24000), clkper) - 1;
+	tcksre = DIV_ROUND_UP(MAX(5 * clkper, 10000), clkper);
 	taonpd = DIV_ROUND_UP(2000, clkper) - 1;
+	tcksrx = tcksre;
 	taofpd = taonpd;
-	trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
+	twr  = DIV_ROUND_UP(15000, clkper) - 1;
+	tmrd = DIV_ROUND_UP(MAX(12 * clkper, 15000), clkper) - 1;
+	trc  = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
+	tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
+	tcl  = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
+	trp  = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
+	twtr = ROUND(MAX(4 * clkper, 7500) / clkper, 1) - 1;
 	trcd = trp;
-	trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
-	tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
-	twr = DIV_ROUND_UP(15000, clkper) - 1;
-	tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
-	twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
 	trtp = twtr;
-	CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;
-	debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
+	cs0_end = (4 * sysinfo->cs_density <= 120) ?
+		   4 * sysinfo->cs_density + 7 :
+		   127;
+
+	debug("density:%d Gb (%d Gb per chip)\n",
+	      sysinfo->cs_density, ddr3_cfg->density);
 	debug("clock: %dMHz (%d ps)\n", clock, clkper);
-	debug("memspd:%d\n", m->mem_speed);
+	debug("memspd:%d\n", ddr3_cfg->mem_speed);
 	debug("tcke=%d\n", tcke);
 	debug("tcksrx=%d\n", tcksrx);
 	debug("tcksre=%d\n", tcksre);
@@ -340,11 +343,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 	debug("twtr=%d\n", twtr);
 	debug("trrd=%d\n", trrd);
 	debug("txpr=%d\n", txpr);
-	debug("CS0_END=%d\n", CS0_END);
-	debug("ncs=%d\n", i->ncs);
-	debug("Rtt_wr=%d\n", i->rtt_wr);
-	debug("Rtt_nom=%d\n", i->rtt_nom);
-	debug("SRT=%d\n", m->SRT);
+	debug("cs0_end=%d\n", cs0_end);
+	debug("ncs=%d\n", sysinfo->ncs);
+	debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
+	debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
+	debug("SRT=%d\n", ddr3_cfg->SRT);
 	debug("tcl=%d\n", tcl);
 	debug("twr=%d\n", twr);
 
@@ -354,142 +357,135 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 	 *  see:
 	 *   appnote, ddr3 spreadsheet
 	 */
-	mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;
-	mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;
-	mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;
-	mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;
-	mmdc0->mprddlctl = c->p0_mprddlctl;
-	mmdc0->mpwrdlctl = c->p0_mpwrdlctl;
-	if (i->dsize > 1) {
-		mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;
-		mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;
-		mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;
-		mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;
-		mmdc1->mprddlctl = c->p1_mprddlctl;
-		mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
+	mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
+	mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
+	mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
+	mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
+	mmdc0->mprddlctl = calib->p0_mprddlctl;
+	mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
+	if (sysinfo->dsize > 1) {
+		mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
+		mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
+		mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
+		mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
+		mmdc1->mprddlctl = calib->p1_mprddlctl;
+		mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
 	}
 
 	/* Read data DQ Byte0-3 delay */
-	mmdc0->mprddqby0dl = (u32)0x33333333;
-	mmdc0->mprddqby1dl = (u32)0x33333333;
-	if (i->dsize > 0) {
-		mmdc0->mprddqby2dl = (u32)0x33333333;
-		mmdc0->mprddqby3dl = (u32)0x33333333;
+	mmdc0->mprddqby0dl = 0x33333333;
+	mmdc0->mprddqby1dl = 0x33333333;
+	if (sysinfo->dsize > 0) {
+		mmdc0->mprddqby2dl = 0x33333333;
+		mmdc0->mprddqby3dl = 0x33333333;
 	}
-	if (i->dsize > 1) {
-		mmdc1->mprddqby0dl = (u32)0x33333333;
-		mmdc1->mprddqby1dl = (u32)0x33333333;
-		mmdc1->mprddqby2dl = (u32)0x33333333;
-		mmdc1->mprddqby3dl = (u32)0x33333333;
+
+	if (sysinfo->dsize > 1) {
+		mmdc1->mprddqby0dl = 0x33333333;
+		mmdc1->mprddqby1dl = 0x33333333;
+		mmdc1->mprddqby2dl = 0x33333333;
+		mmdc1->mprddqby3dl = 0x33333333;
 	}
 
 	/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
-	reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;
-	mmdc0->mpodtctrl = reg;
-	if (i->dsize > 1)
-		mmdc1->mpodtctrl = reg;
+	val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
+	mmdc0->mpodtctrl = val;
+	if (sysinfo->dsize > 1)
+		mmdc1->mpodtctrl = val;
 
 	/* complete calibration */
-	reg = (1 << 11); /* Force measurement on delay-lines */
-	mmdc0->mpmur0 = reg;
-	if (i->dsize > 1)
-		mmdc1->mpmur0 = reg;
+	val = (1 << 11); /* Force measurement on delay-lines */
+	mmdc0->mpmur0 = val;
+	if (sysinfo->dsize > 1)
+		mmdc1->mpmur0 = val;
 
 	/* Step 1: configuration request */
 	mmdc0->mdscr = (u32)(1 << 15); /* config request */
 
 	/* Step 2: Timing configuration */
-	reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |
-	      (tfaw << 4) | tcl;
-	mmdc0->mdcfg0 = reg;
-	reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |
-	      (1 << 15) |		/* trpa */
-	      (twr << 9) | (tmrd << 5) | tcwl;
-	mmdc0->mdcfg1 = reg;
-	reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
-	mmdc0->mdcfg2 = reg;
-	reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
-	      (todtlon << 12) | (todt_idle_off << 4);
-	mmdc0->mdotc = reg;
-	mmdc0->mdasp = CS0_END; /* CS addressing */
+	mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
+			(txpdll << 9) | (tfaw << 4) | tcl;
+	mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
+			(tras << 16) | (1 << 15) /* trpa */ |
+			(twr << 9) | (tmrd << 5) | tcwl;
+	mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
+	mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
+		       (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
+	mmdc0->mdasp = cs0_end; /* CS addressing */
 
 	/* Step 3: Configure DDR type */
-	reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |
-	      (i->mif3_mode << 9) | (i->ralat << 6);
-	mmdc0->mdmisc = reg;
+	mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
+			(sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
+			(sysinfo->ralat << 6);
 
 	/* Step 4: Configure delay while leaving reset */
-	reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);
-	mmdc0->mdor = reg;
+	mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
+		      (sysinfo->rst_to_cke << 0);
 
 	/* Step 5: Configure DDR physical parameters (density and burst len) */
-	coladdr = m->coladdr;
-	if (m->coladdr == 8)		/* 8-bit COL is 0x3 */
+	coladdr = ddr3_cfg->coladdr;
+	if (ddr3_cfg->coladdr == 8)		/* 8-bit COL is 0x3 */
 		coladdr += 4;
-	else if (m->coladdr == 12)	/* 12-bit COL is 0x4 */
+	else if (ddr3_cfg->coladdr == 12)	/* 12-bit COL is 0x4 */
 		coladdr += 1;
-	reg = (m->rowaddr - 11) << 24 |		/* ROW */
-	      (coladdr - 9) << 20 |		/* COL */
-	      (1 << 19) |			/* Burst Length = 8 for DDR3 */
-	      (i->dsize << 16);			/* DDR data bus size */
-	mmdc0->mdctl = reg;
+	mmdc0->mdctl =  (ddr3_cfg->rowaddr - 11) << 24 |	/* ROW */
+			(coladdr - 9) << 20 |			/* COL */
+			(1 << 19) |		/* Burst Length = 8 for DDR3 */
+			(sysinfo->dsize << 16);		/* DDR data bus size */
 
 	/* Step 6: Perform ZQ calibration */
-	reg = (u32)0xa1390001; /* one-time HW ZQ calib */
-	mmdc0->mpzqhwctrl = reg;
-	if (i->dsize > 1)
-		mmdc1->mpzqhwctrl = reg;
+	val = 0xa1390001; /* one-time HW ZQ calib */
+	mmdc0->mpzqhwctrl = val;
+	if (sysinfo->dsize > 1)
+		mmdc1->mpzqhwctrl = val;
 
 	/* Step 7: Enable MMDC with desired chip select */
-	reg = mmdc0->mdctl |
-	      (1 << 31) |			/* SDE_0 for CS0 */
-	      ((i->ncs == 2) ? 1 : 0) << 30;	/* SDE_1 for CS1 */
-	mmdc0->mdctl = reg;
+	mmdc0->mdctl |= (1 << 31) |			     /* SDE_0 for CS0 */
+			((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
 
 	/* Step 8: Write Mode Registers to Init DDR3 devices */
-	for (cs = 0; cs < i->ncs; cs++) {
+	for (cs = 0; cs < sysinfo->ncs; cs++) {
 		/* MR2 */
-		reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
+		val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
 		      ((tcwl - 3) & 3) << 3;
-		mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
+		mmdc0->mdscr = MR(val, 2, 3, cs);
 		/* MR3 */
-		mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
+		mmdc0->mdscr = MR(0, 3, 3, cs);
 		/* MR1 */
-		reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |
-		      ((i->rtt_nom & 2) ? 1 : 0) << 6;
-		mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);
-		reg = ((tcl - 1) << 4) |	/* CAS */
+		val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
+		      ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
+		mmdc0->mdscr = MR(val, 1, 3, cs);
+		/* MR0 */
+		val = ((tcl - 1) << 4) |	/* CAS */
 		      (1 << 8)   |		/* DLL Reset */
 		      ((twr - 3) << 9);		/* Write Recovery */
-		/* MR0 */
-		mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
+		mmdc0->mdscr = MR(val, 0, 3, cs);
 		/* ZQ calibration */
-		reg = (1 << 10);
-		mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
+		val = (1 << 10);
+		mmdc0->mdscr = MR(val, 0, 4, cs);
 	}
 
 	/* Step 10: Power down control and self-refresh */
-	reg = (tcke & 0x7) << 16 |
-	      5            << 12 |  /* PWDT_1: 256 cycles */
-	      5            <<  8 |  /* PWDT_0: 256 cycles */
-	      1            <<  6 |  /* BOTH_CS_PD */
-	      (tcksrx & 0x7) << 3 |
-	      (tcksre & 0x7);
-	mmdc0->mdpdc = reg;
-	mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
+	mmdc0->mdpdc = (tcke & 0x7) << 16 |
+			5            << 12 |  /* PWDT_1: 256 cycles */
+			5            <<  8 |  /* PWDT_0: 256 cycles */
+			1            <<  6 |  /* BOTH_CS_PD */
+			(tcksrx & 0x7) << 3 |
+			(tcksre & 0x7);
+	mmdc0->mapsr = 0x00011006; /* ADOPT power down enabled */
 
 	/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
-	mmdc0->mpzqhwctrl = (u32)0xa1390003;
-	if (i->dsize > 1)
-		mmdc1->mpzqhwctrl = (u32)0xa1390003;
+	val = 0xa1390003;
+	mmdc0->mpzqhwctrl = val;
+	if (sysinfo->dsize > 1)
+		mmdc1->mpzqhwctrl = val;
 
 	/* Step 12: Configure and activate periodic refresh */
-	reg = (1 << 14) |	/* REF_SEL: Periodic refresh cycles of 32kHz */
-	      (7 << 11);	/* REFR: Refresh Rate - 8 refreshes */
-	mmdc0->mdref = reg;
+	mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
+		       (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */
 
 	/* Step 13: Deassert config request - init complete */
-	mmdc0->mdscr = (u32)0x00000000;
+	mmdc0->mdscr = 0x00000000;
 
 	/* wait for auto-ZQ calibration to complete */
 	mdelay(1);
-- 
1.9.1

[U-Boot] [PATCH V5 13/19] arm: mx6: add support for Compulab cm-fx6 CoM

[Nikita Kiryanov]

Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
Changes in V5:
	- Rebased over current mainline code.

Changes in V4:
	- Adapt to use Kconfig
	- Refactor code to work without ulong bank(1|2)_size variables
	- Remove get_board_rev(); reintroduce in a later patch
	- Move usdhc structs to cm_fx6.c
	- Initialize all ddr related structs statically
	- Use get_cpu_type() and spl_boot_device()
	- Kill #define CONFIG_SYS_L2CACHE_OFF
	- Use load instead of fatload in environment scripts
	- Remove nand related environment variables; reintroduce in a later patch
	- Move usdhc3 clock initialization to another patch.

Changes in V3:
	- Remove CONFIG_SYS_TEXT_BASE from config file to not clash with the
	  one supplied by imx6_spl.h

Changes in V2:
	- Remove unnecessary line removal from arch/arm/cpu/armv7/mx6/ddr.c
	- Move probe_mmdc_config() code straight to dram_init()
	- Use imx6_spl.h
	- Use imx_ddr_size()
	  NOTE: the correctness of this patch now depends on https://patchwork.ozlabs.org/patch/376095/

 arch/arm/Kconfig                   |   4 +
 board/compulab/cm_fx6/Kconfig      |  23 +++
 board/compulab/cm_fx6/MAINTAINERS  |   6 +
 board/compulab/cm_fx6/Makefile     |  12 ++
 board/compulab/cm_fx6/cm_fx6.c     | 111 ++++++++++++
 board/compulab/cm_fx6/common.c     |  84 +++++++++
 board/compulab/cm_fx6/common.h     |  20 +++
 board/compulab/cm_fx6/imximage.cfg |   8 +
 board/compulab/cm_fx6/spl.c        | 355 +++++++++++++++++++++++++++++++++++++
 configs/cm_fx6_defconfig           |   4 +
 include/configs/cm_fx6.h           | 192 ++++++++++++++++++++
 11 files changed, 819 insertions(+)
 create mode 100644 board/compulab/cm_fx6/Kconfig
 create mode 100644 board/compulab/cm_fx6/MAINTAINERS
 create mode 100644 board/compulab/cm_fx6/Makefile
 create mode 100644 board/compulab/cm_fx6/cm_fx6.c
 create mode 100644 board/compulab/cm_fx6/common.c
 create mode 100644 board/compulab/cm_fx6/common.h
 create mode 100644 board/compulab/cm_fx6/imximage.cfg
 create mode 100644 board/compulab/cm_fx6/spl.c
 create mode 100644 configs/cm_fx6_defconfig
 create mode 100644 include/configs/cm_fx6.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22f0f09..f933123 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -424,6 +424,9 @@ config OMAP54XX
 config RMOBILE
 	bool "Renesas ARM SoCs"
 
+config TARGET_CM_FX6
+	bool "Support cm_fx6"
+
 config TARGET_S5P_GONI
 	bool "Support s5p_goni"
 
@@ -579,6 +582,7 @@ source "board/cirrus/edb93xx/Kconfig"
 source "board/cm4008/Kconfig"
 source "board/cm41xx/Kconfig"
 source "board/compulab/cm_t335/Kconfig"
+source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/creative/xfi3/Kconfig"
 source "board/davedenx/qong/Kconfig"
diff --git a/board/compulab/cm_fx6/Kconfig b/board/compulab/cm_fx6/Kconfig
new file mode 100644
index 0000000..42a8438
--- /dev/null
+++ b/board/compulab/cm_fx6/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_CM_FX6
+
+config SYS_CPU
+	string
+	default "armv7"
+
+config SYS_BOARD
+	string
+	default "cm_fx6"
+
+config SYS_VENDOR
+	string
+	default "compulab"
+
+config SYS_SOC
+	string
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	string
+	default "cm_fx6"
+
+endif
diff --git a/board/compulab/cm_fx6/MAINTAINERS b/board/compulab/cm_fx6/MAINTAINERS
new file mode 100644
index 0000000..5b2623a
--- /dev/null
+++ b/board/compulab/cm_fx6/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_FX6 BOARD
+M:	Nikita Kiryanov <nikita@compulab.co.il>
+S:	Maintained
+F:	board/compulab/cm_fx6/
+F:	include/configs/cm_fx6.h
+F:	configs/cm_fx6_defconfig
diff --git a/board/compulab/cm_fx6/Makefile b/board/compulab/cm_fx6/Makefile
new file mode 100644
index 0000000..3e5c903
--- /dev/null
+++ b/board/compulab/cm_fx6/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Nikita Kiryanov <nikita@compulab.co.il>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+obj-y = common.o spl.o
+else
+obj-y = common.o cm_fx6.o
+endif
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
new file mode 100644
index 0000000..b589581
--- /dev/null
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -0,0 +1,111 @@
+/*
+ * Board functions for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/sys_proto.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC1_BASE_ADDR},
+	{USDHC2_BASE_ADDR},
+	{USDHC3_BASE_ADDR},
+};
+
+static enum mxc_clock usdhc_clk[3] = {
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int i;
+
+	cm_fx6_set_usdhc_iomux();
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
+		usdhc_cfg[i].max_bus_width = 4;
+		fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		enable_usdhc_clk(1, i);
+	}
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: CM-FX6\n");
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+
+	switch (gd->ram_size) {
+	case 0x10000000: /* DDR_16BIT_256MB */
+		gd->bd->bi_dram[0].size = 0x10000000;
+		gd->bd->bi_dram[1].size = 0;
+		break;
+	case 0x20000000: /* DDR_32BIT_512MB */
+		gd->bd->bi_dram[0].size = 0x20000000;
+		gd->bd->bi_dram[1].size = 0;
+		break;
+	case 0x40000000:
+		if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
+			gd->bd->bi_dram[0].size = 0x20000000;
+			gd->bd->bi_dram[1].size = 0x20000000;
+		} else { /* DDR_64BIT_1GB */
+			gd->bd->bi_dram[0].size = 0x40000000;
+			gd->bd->bi_dram[1].size = 0;
+		}
+		break;
+	case 0x80000000: /* DDR_64BIT_2GB */
+		gd->bd->bi_dram[0].size = 0x40000000;
+		gd->bd->bi_dram[1].size = 0x40000000;
+		break;
+	case 0xEFF00000: /* DDR_64BIT_4GB */
+		gd->bd->bi_dram[0].size = 0x70000000;
+		gd->bd->bi_dram[1].size = 0x7FF00000;
+		break;
+	}
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	switch (gd->ram_size) {
+	case 0x10000000:
+	case 0x20000000:
+	case 0x40000000:
+	case 0x80000000:
+		break;
+	case 0xF0000000:
+		gd->ram_size -= 0x100000;
+		break;
+	default:
+		printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c
new file mode 100644
index 0000000..1f39679
--- /dev/null
+++ b/board/compulab/cm_fx6/common.c
@@ -0,0 +1,84 @@
+/*
+ * Code used by both U-Boot and SPL for Compulab CM-FX6
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc_pads[] = {
+	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+void cm_fx6_set_usdhc_iomux(void)
+{
+	SETUP_IOMUX_PADS(usdhc_pads);
+}
+
+/* CINS bit doesn't work, so always try to access the MMC card */
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#define ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+		PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const ecspi_pads[] = {
+	IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30  | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__ECSPI1_SS1  | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+};
+
+void cm_fx6_set_ecspi_iomux(void)
+{
+	SETUP_IOMUX_PADS(ecspi_pads);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1;
+}
+#endif
diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h
new file mode 100644
index 0000000..347d07b
--- /dev/null
+++ b/board/compulab/cm_fx6/common.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/clock.h>
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |	\
+			PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+			PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define CM_FX6_ECSPI_BUS0_CS0	IMX_GPIO_NR(2, 30)
+#define CM_FX6_GREEN_LED	IMX_GPIO_NR(2, 31)
+
+void cm_fx6_set_usdhc_iomux(void);
+void cm_fx6_set_ecspi_iomux(void);
diff --git a/board/compulab/cm_fx6/imximage.cfg b/board/compulab/cm_fx6/imximage.cfg
new file mode 100644
index 0000000..420947e
--- /dev/null
+++ b/board/compulab/cm_fx6/imximage.cfg
@@ -0,0 +1,8 @@
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM	sd
diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
new file mode 100644
index 0000000..a3abc7b
--- /dev/null
+++ b/board/compulab/cm_fx6/spl.c
@@ -0,0 +1,355 @@
+/*
+ * SPL specific code for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <fsl_esdhc.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ddr_config {
+	DDR_16BIT_256MB,
+	DDR_32BIT_512MB,
+	DDR_32BIT_1GB,
+	DDR_64BIT_1GB,
+	DDR_64BIT_2GB,
+	DDR_64BIT_4GB,
+	DDR_UNKNOWN,
+};
+
+/*
+ * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
+ * Freescale QRM, but this is exactly the value used by the automatic
+ * calibration script and it works also in all our tests, so we leave
+ * it as is at this point.
+ */
+#define CM_FX6_DDR_IOMUX_CFG \
+	.dram_sdqs0	= 0x00000038, \
+	.dram_sdqs1	= 0x00000038, \
+	.dram_sdqs2	= 0x00000038, \
+	.dram_sdqs3	= 0x00000038, \
+	.dram_sdqs4	= 0x00000038, \
+	.dram_sdqs5	= 0x00000038, \
+	.dram_sdqs6	= 0x00000038, \
+	.dram_sdqs7	= 0x00000038, \
+	.dram_dqm0	= 0x00000038, \
+	.dram_dqm1	= 0x00000038, \
+	.dram_dqm2	= 0x00000038, \
+	.dram_dqm3	= 0x00000038, \
+	.dram_dqm4	= 0x00000038, \
+	.dram_dqm5	= 0x00000038, \
+	.dram_dqm6	= 0x00000038, \
+	.dram_dqm7	= 0x00000038, \
+	.dram_cas	= 0x00000038, \
+	.dram_ras	= 0x00000038, \
+	.dram_sdclk_0	= 0x00000038, \
+	.dram_sdclk_1	= 0x00000038, \
+	.dram_sdcke0	= 0x00003000, \
+	.dram_sdcke1	= 0x00003000, \
+	.dram_reset	= 0x00000038, \
+	.dram_sdba2	= 0x00000000, \
+	.dram_sdodt0	= 0x00000038, \
+	.dram_sdodt1	= 0x00000038,
+
+#define CM_FX6_GPR_IOMUX_CFG \
+	.grp_b0ds	= 0x00000038, \
+	.grp_b1ds	= 0x00000038, \
+	.grp_b2ds	= 0x00000038, \
+	.grp_b3ds	= 0x00000038, \
+	.grp_b4ds	= 0x00000038, \
+	.grp_b5ds	= 0x00000038, \
+	.grp_b6ds	= 0x00000038, \
+	.grp_b7ds	= 0x00000038, \
+	.grp_addds	= 0x00000038, \
+	.grp_ddrmode_ctl = 0x00020000, \
+	.grp_ddrpke	= 0x00000000, \
+	.grp_ddrmode	= 0x00020000, \
+	.grp_ctlds	= 0x00000038, \
+	.grp_ddr_type	= 0x000C0000,
+
+static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
+static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
+static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
+static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
+
+static struct mx6_mmdc_calibration cm_fx6_calib_s = {
+	.p0_mpwldectrl0	= 0x005B0061,
+	.p0_mpwldectrl1	= 0x004F0055,
+	.p0_mpdgctrl0	= 0x0314030C,
+	.p0_mpdgctrl1	= 0x025C0268,
+	.p0_mprddlctl	= 0x42464646,
+	.p0_mpwrdlctl	= 0x36322C34,
+};
+
+static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
+	.cs1_mirror	= 1,
+	.cs_density	= 16,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 1,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
+	.mem_speed	= 800,
+	.density	= 4,
+	.rowaddr	= 14,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1800,
+	.trcmin		= 5200,
+	.trasmin	= 3600,
+	.SRT		= 0,
+};
+
+static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
+{
+	if (reset)
+		((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
+
+	switch (dram_config) {
+	case DDR_16BIT_256MB:
+		cm_fx6_sysinfo_s.dsize = 0;
+		cm_fx6_sysinfo_s.ncs = 1;
+		break;
+	case DDR_32BIT_512MB:
+		cm_fx6_sysinfo_s.dsize = 1;
+		cm_fx6_sysinfo_s.ncs = 1;
+		break;
+	case DDR_32BIT_1GB:
+		cm_fx6_sysinfo_s.dsize = 1;
+		cm_fx6_sysinfo_s.ncs = 2;
+		break;
+	default:
+		puts("Tried to setup invalid DDR configuration\n");
+		hang();
+	}
+
+	mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
+	udelay(100);
+}
+
+static struct mx6_mmdc_calibration cm_fx6_calib_q = {
+	.p0_mpwldectrl0	= 0x00630068,
+	.p0_mpwldectrl1	= 0x0068005D,
+	.p0_mpdgctrl0	= 0x04140428,
+	.p0_mpdgctrl1	= 0x037C037C,
+	.p0_mprddlctl	= 0x3C30303A,
+	.p0_mpwrdlctl	= 0x3A344038,
+	.p1_mpwldectrl0	= 0x0035004C,
+	.p1_mpwldectrl1	= 0x00170026,
+	.p1_mpdgctrl0	= 0x0374037C,
+	.p1_mpdgctrl1	= 0x0350032C,
+	.p1_mprddlctl	= 0x30322A3C,
+	.p1_mpwrdlctl	= 0x48304A3E,
+};
+
+static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
+	.cs_density	= 16,
+	.cs1_mirror	= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 1,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
+	.mem_speed	= 1066,
+	.density	= 4,
+	.rowaddr	= 14,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1324,
+	.trcmin		= 59500,
+	.trasmin	= 9750,
+	.SRT		= 0,
+};
+
+static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
+{
+	if (reset)
+		((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
+
+	cm_fx6_ddr3_cfg_q.rowaddr = 14;
+	switch (dram_config) {
+	case DDR_16BIT_256MB:
+		cm_fx6_sysinfo_q.dsize = 0;
+		cm_fx6_sysinfo_q.ncs = 1;
+		break;
+	case DDR_32BIT_512MB:
+		cm_fx6_sysinfo_q.dsize = 1;
+		cm_fx6_sysinfo_q.ncs = 1;
+		break;
+	case DDR_64BIT_1GB:
+		cm_fx6_sysinfo_q.dsize = 2;
+		cm_fx6_sysinfo_q.ncs = 1;
+		break;
+	case DDR_64BIT_2GB:
+		cm_fx6_sysinfo_q.dsize = 2;
+		cm_fx6_sysinfo_q.ncs = 2;
+		break;
+	case DDR_64BIT_4GB:
+		cm_fx6_sysinfo_q.dsize = 2;
+		cm_fx6_sysinfo_q.ncs = 2;
+		cm_fx6_ddr3_cfg_q.rowaddr = 15;
+		break;
+	default:
+		puts("Tried to setup invalid DDR configuration\n");
+		hang();
+	}
+
+	mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
+	udelay(100);
+}
+
+static int cm_fx6_spl_dram_init(void)
+{
+	unsigned long bank1_size, bank2_size;
+
+	switch (get_cpu_type()) {
+	case MXC_CPU_MX6SOLO:
+		mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
+
+		spl_mx6s_dram_init(DDR_32BIT_1GB, false);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x40000000)
+			return 0;
+
+		if (bank1_size == 0x20000000) {
+			spl_mx6s_dram_init(DDR_32BIT_512MB, true);
+			return 0;
+		}
+
+		spl_mx6s_dram_init(DDR_16BIT_256MB, true);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x10000000)
+			return 0;
+
+		break;
+	case MXC_CPU_MX6D:
+	case MXC_CPU_MX6Q:
+		mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
+
+		spl_mx6q_dram_init(DDR_64BIT_4GB, false);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x80000000)
+			return 0;
+
+		if (bank1_size == 0x40000000) {
+			bank2_size = get_ram_size((long int *)PHYS_SDRAM_2,
+								0x80000000);
+			if (bank2_size == 0x40000000) {
+				/* Don't do a full reset here */
+				spl_mx6q_dram_init(DDR_64BIT_2GB, false);
+			} else {
+				spl_mx6q_dram_init(DDR_64BIT_1GB, true);
+			}
+
+			return 0;
+		}
+
+		spl_mx6q_dram_init(DDR_32BIT_512MB, true);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x20000000)
+			return 0;
+
+		spl_mx6q_dram_init(DDR_16BIT_256MB, true);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x10000000)
+			return 0;
+
+		break;
+	}
+
+	return -1;
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_uart(void)
+{
+	SETUP_IOMUX_PADS(uart4_pads);
+	enable_uart_clk(1);
+}
+
+#ifdef CONFIG_SPL_SPI_SUPPORT
+static void cm_fx6_setup_ecspi(void)
+{
+	cm_fx6_set_ecspi_iomux();
+	enable_cspi_clock(1, 0);
+}
+#else
+static void cm_fx6_setup_ecspi(void) { }
+#endif
+
+void board_init_f(ulong dummy)
+{
+	gd = &gdata;
+	arch_cpu_init();
+	timer_init();
+	cm_fx6_setup_ecspi();
+	cm_fx6_setup_uart();
+	get_clocks();
+	preloader_console_init();
+	gpio_direction_output(CM_FX6_GREEN_LED, 1);
+	if (cm_fx6_spl_dram_init()) {
+		puts("!!!ERROR!!! DRAM detection failed!!!\n");
+		hang();
+	}
+
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+	u32 boot_device = spl_boot_device();
+
+	if (boot_device == BOOT_DEVICE_SPI)
+		puts("Booting from SPI flash\n");
+	else if (boot_device == BOOT_DEVICE_MMC1)
+		puts("Booting from MMC\n");
+	else
+		puts("Unknown boot device\n");
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+static struct fsl_esdhc_cfg usdhc_cfg = {
+	.esdhc_base = USDHC3_BASE_ADDR,
+	.max_bus_width = 4,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	cm_fx6_set_usdhc_iomux();
+
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
new file mode 100644
index 0000000..50c06f7
--- /dev/null
+++ b/configs/cm_fx6_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/cm_fx6/imximage.cfg,MX6QDL,SPL"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_CM_FX6=y
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
new file mode 100644
index 0000000..15c55be
--- /dev/null
+++ b/include/configs/cm_fx6.h
@@ -0,0 +1,192 @@
+/*
+ * Config file for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_CM_FX6_H
+#define __CONFIG_CM_FX6_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+/* Machine config */
+#define CONFIG_MX6
+#define CONFIG_SYS_LITTLE_ENDIAN
+#define CONFIG_MACH_TYPE		4273
+#define CONFIG_SYS_HZ			1000
+
+/* Display information on boot */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_TIMESTAMP
+
+/* CMD */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_GREPENV
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* RAM */
+#define PHYS_SDRAM_1			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_2			MMDC1_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x10010000
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Serial console */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART4_BASE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/* Shell */
+#define CONFIG_SYS_PROMPT	"CM-FX6 # "
+#define CONFIG_SYS_CBSIZE	1024
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* SPI flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		25000000
+#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel=uImage-cm-fx6\0" \
+	"autoload=no\0" \
+	"loadaddr=0x10800000\0" \
+	"fdtaddr=0x11000000\0" \
+	"console=ttymxc3,115200\0" \
+	"ethprime=FEC0\0" \
+	"bootscr=boot.scr\0" \
+	"bootm_low=18000000\0" \
+	"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32 at 50,if=RGB32\0" \
+	"video_dvi=mxcfb0:dev=dvi,1280x800M-32 at 50,if=RGB32\0" \
+	"fdtfile=cm-fx6.dtb\0" \
+	"doboot=bootm ${loadaddr}\0" \
+	"loadfdt=false\0" \
+	"setboottypez=setenv kernel zImage-cm-fx6;" \
+		"setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
+		"setenv loadfdt true;\0" \
+	"setboottypem=setenv kernel uImage-cm-fx6;" \
+		"setenv doboot bootm ${loadaddr};" \
+		"setenv loadfdt false;\0"\
+	"run_eboot=echo Starting EBOOT ...; "\
+		"mmc dev ${mmcdev} && " \
+		"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
+	"mmcdev=2\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"loadmmcbootscript=load mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \
+	"mmcbootscript=echo Running bootscript from mmc ...; "\
+		"source ${loadaddr}\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"${video}\0" \
+	"mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
+	"mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"run doboot\0" \
+	"boot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"if run loadmmcbootscript; then " \
+				"run mmcbootscript;" \
+			"else " \
+				"if run mmcloadkernel; then " \
+					"if ${loadfdt}; then " \
+						"run mmcloadfdt;" \
+					"fi;" \
+					"run mmcboot;" \
+				"fi;" \
+			"fi;" \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"run setboottypem; run boot"
+
+/* SPI */
+#define CONFIG_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_WINBOND
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+
+/* Boot */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_LOADADDR			0x10800000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SYS_BOOTMAPSZ	        (8 << 20)
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* misc */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_STACKSIZE			(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN			(2 * 1024 * 1024)
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	800 /* 400 KB */
+
+/* SPL */
+#include "imx6_spl.h"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x80 /* offset 64 kb */
+#define CONFIG_SYS_MONITOR_LEN	(CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024)
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
+#define CONFIG_SPL_SPI_LOAD
+
+#endif	/* __CONFIG_CM_FX6_H */
-- 
1.9.1

[U-Boot] [PATCH V5 13/19] arm: mx6: add support for Compulab cm-fx6 CoM

[Marek Vasut]

On Sunday, September 07, 2014 at 05:59:29 PM, Nikita Kiryanov wrote:
> Add initial support for Compulab CM-FX6 CoM.
> Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
> 
> Cc: Igor Grinberg <grinberg@compulab.co.il>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tom Rini <trini@ti.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Acked-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

Looks good, thanks!

Best regards,
Marek Vasut

[U-Boot] [PATCH V4 00/19] Introduce cm-fx6 board

[Stefano Babic]

Hi Nikita,

On 31/08/2014 10:09, Nikita Kiryanov wrote:
> Hi Tom, Stefano,
> 
> We really want this series to make it into the next release (V1 was
> submitted only a day after the merge window closed). If there are no
> other comments, can we maybe start applying it?
> 

Patch 1/19, 4/19 and 5/19 were already applied by Jagan - I do not merge
them into u-boot-imx.
I applied 2/19 after rebasing on current u-boot-imx.

I have nothing against the helper introduced in 3/19, but this touch
more boards - I will make a short check before applying it. However, it
is orthogonal and can be applied later.

I applied as well 6/19 through 19/19 into u-boot-imx - thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH V4 00/19] Introduce cm-fx6 board

[Nikita Kiryanov]

On 09/09/14 16:45, Stefano Babic wrote:
> Hi Nikita,
>
> On 31/08/2014 10:09, Nikita Kiryanov wrote:
>> Hi Tom, Stefano,
>>
>> We really want this series to make it into the next release (V1 was
>> submitted only a day after the merge window closed). If there are no
>> other comments, can we maybe start applying it?
>>
>
> Patch 1/19, 4/19 and 5/19 were already applied by Jagan - I do not merge
> them into u-boot-imx.
> I applied 2/19 after rebasing on current u-boot-imx.
>
> I have nothing against the helper introduced in 3/19, but this touch
> more boards - I will make a short check before applying it. However, it
> is orthogonal and can be applied later.
>
> I applied as well 6/19 through 19/19 into u-boot-imx - thanks !

Thanks!
I'm a little confused about what you meant by patch 3 though...
Jagan took patch number 3 (and 1, and 4), and I can see in your tree
that all 16 remaining patches are there. What patch were you referring
to?

>
> Best regards,
> Stefano Babic
>

-- 
Regards,
Nikita Kiryanov

[U-Boot] [PATCH V4 00/19] Introduce cm-fx6 board

[Stefano Babic]

Hi Nikita,

On 09/09/2014 17:00, Nikita Kiryanov wrote:
> 
> 
> On 09/09/14 16:45, Stefano Babic wrote:
>> Hi Nikita,
>>
>> On 31/08/2014 10:09, Nikita Kiryanov wrote:
>>> Hi Tom, Stefano,
>>>
>>> We really want this series to make it into the next release (V1 was
>>> submitted only a day after the merge window closed). If there are no
>>> other comments, can we maybe start applying it?
>>>
>>
>> Patch 1/19, 4/19 and 5/19 were already applied by Jagan - I do not merge
>> them into u-boot-imx.
>> I applied 2/19 after rebasing on current u-boot-imx.
>>
>> I have nothing against the helper introduced in 3/19, but this touch
>> more boards - I will make a short check before applying it. However, it
>> is orthogonal and can be applied later.
>>
>> I applied as well 6/19 through 19/19 into u-boot-imx - thanks !
> 
> Thanks!
> I'm a little confused about what you meant by patch 3 though...
> Jagan took patch number 3 (and 1, and 4),

I have not seen that Jagan picked up patch 3, I found only 1, 4 and 5.

> and I can see in your tree
> that all 16 remaining patches are there. What patch were you referring
> to?

Then all patches should be already merged and will flow into Tom's tree
at next pull request.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================