* [PATCH v4] coresight: bindings for coresight drivers
@ 2014-08-20 17:11 ` mathieu.poirier at linaro.org
0 siblings, 0 replies; 5+ messages in thread
From: mathieu.poirier @ 2014-08-20 17:11 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-kernel, linux-arm-kernel, mathieu.poirier
From: Pratik Patel <pratikp@codeaurora.org>
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Panchaxari Prasannamurthy <panchaxari.prasannamurthy@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../devicetree/bindings/arm/coresight.txt | 205 +++++++++++++++++++++
1 file changed, 205 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/coresight.txt
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
new file mode 100644
index 0000000..2ee594d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -0,0 +1,205 @@
+* CoreSight Components
+
+CoreSight components are compliant with the ARM CoreSight architecture
+specification and can be connected in various topologies to suit a particular
+SoCs tracing needs. These trace components can generally be classified as sinks,
+links and sources. Trace data produced by one or more sources flows through the
+intermediate links connecting the source to the currently selected sink. Each
+CoreSight component device should use these properties to describe its hardware
+characteristcs.
+
+Required properties for all components *except* non-configurable replicators:
+
+- compatible : name of the component used for driver matching. Possible values
+include: "arm,coresight-etb10", "arm,coresight-tpiu", "arm,coresight-tmc",
+"arm,coresight-funnel", and "arm,coresight-etm3x". All of these have to
+be supplemented with "arm,primecell" as drivers are using the AMBA bus
+interface. Since non-configurable replicators don't show up on the AMBA
+bus they don't need to be post-fixed with "arm,primecell".
+
+- reg : physical base address and length of the register set(s) of the component.
+
+- clocks : the clock associated to this component.
+
+- clock-names: the name of the clock as referenced by the code. Since we are
+using the AMBA framework, the name should be "apb_pclk".
+
+- ports or port: The representation of the component's port layout using the
+generic DT graph presentation found in "bindings/graph.txt".
+
+Non-configurable replicators:
+
+- compatible: currently supported value is "arm-replicator". Since non-configurable
+replicators don't show up on the AMBA hey don't need to be post-fixed with
+"arm,primecell".
+
+- id: a unique number that will identify this replicator.
+
+- ports or port: same as above.
+
+Optional properties for Sinks:
+
+- coresight-default-sink: must be specified for one of the sink devices that is
+intended to be made the default sink. Other sink devices must not have this
+specified. Not specifying this property on any of the sinks is invalid.
+
+Optional properties for ETM/PTMs:
+
+- arm,cp14: must be present if the system accesses ETM/PTM management registers
+via co-processor 14.
+
+- arm,cp14: access to ETM/PTM management registers is made via cp14.
+
+- cpu: the cpu phandle this ETM/PTM is affined to. When omitted the source is
+considered to belong to CPU0.
+
+Optional property for TMC:
+
+- arm,buffer-size: size of contiguous buffer space for TMC ETR (embedded trace router)
+
+
+Example:
+
+1. Sinks
+ etb: etb@20010000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0 0x20010000 0 0x1000>;
+
+ coresight-default-sink;
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ port {
+ etb_in_port: endpoint@0 {
+ slave-mode;
+ remote-endpoint = <&replicator_out_port0>;
+ };
+ };
+ };
+
+ tpiu: tpiu@20030000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0 0x20030000 0 0x1000>;
+
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ port {
+ tpiu_in_port: endpoint@0 {
+ slave-mode;
+ remote-endpoint = <&replicator_out_port1>;
+ };
+ };
+ };
+
+2. Links
+ replicator {
+ /* non-configurable replicators don't show up on the
+ * AMBA bus. As such no need to add "arm,primecell".
+ */
+ compatible = "arm,coresight-replicator";
+ /* this will show up in debugfs as "0.replicator" */
+ id = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&etb_in_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+
+ /* replicator input port */
+ port@2 {
+ reg = <0>;
+ replicator_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&funnel_out_port0>;
+ };
+ };
+ };
+ };
+
+ funnel@20040000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x20040000 0 0x1000>;
+
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* funnel output port */
+ port@0 {
+ reg = <0>;
+ funnel_out_port0: endpoint {
+ remote-endpoint = <&replicator_in_port0>;
+ };
+ };
+
+ /* funnel input ports */
+ port@1 {
+ reg = <0>;
+ funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&ptm0_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint = <&ptm1_out_port>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ funnel_in_port2: endpoint {
+ slave-mode;
+ remote-endpoint = <&etm0_out_port>;
+ };
+ };
+
+ };
+ };
+
+3. Sources
+ ptm0: ptm@2201c000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0 0x2201c000 0 0x1000>;
+
+ cpu = <&cpu0>;
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ port {
+ ptm0_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port0>;
+ };
+ };
+ };
+
+ ptm1: ptm@2201d000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0 0x2201d000 0 0x1000>;
+
+ cpu = <&cpu1>;
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ port {
+ ptm1_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port1>;
+ };
+ };
+ };
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v4] coresight: bindings for coresight drivers
@ 2014-08-20 17:11 ` mathieu.poirier at linaro.org
0 siblings, 0 replies; 5+ messages in thread
From: mathieu.poirier at linaro.org @ 2014-08-20 17:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratik Patel <pratikp@codeaurora.org>
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Panchaxari Prasannamurthy <panchaxari.prasannamurthy@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../devicetree/bindings/arm/coresight.txt | 205 +++++++++++++++++++++
1 file changed, 205 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/coresight.txt
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
new file mode 100644
index 0000000..2ee594d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -0,0 +1,205 @@
+* CoreSight Components
+
+CoreSight components are compliant with the ARM CoreSight architecture
+specification and can be connected in various topologies to suit a particular
+SoCs tracing needs. These trace components can generally be classified as sinks,
+links and sources. Trace data produced by one or more sources flows through the
+intermediate links connecting the source to the currently selected sink. Each
+CoreSight component device should use these properties to describe its hardware
+characteristcs.
+
+Required properties for all components *except* non-configurable replicators:
+
+- compatible : name of the component used for driver matching. Possible values
+include: "arm,coresight-etb10", "arm,coresight-tpiu", "arm,coresight-tmc",
+"arm,coresight-funnel", and "arm,coresight-etm3x". All of these have to
+be supplemented with "arm,primecell" as drivers are using the AMBA bus
+interface. Since non-configurable replicators don't show up on the AMBA
+bus they don't need to be post-fixed with "arm,primecell".
+
+- reg : physical base address and length of the register set(s) of the component.
+
+- clocks : the clock associated to this component.
+
+- clock-names: the name of the clock as referenced by the code. Since we are
+using the AMBA framework, the name should be "apb_pclk".
+
+- ports or port: The representation of the component's port layout using the
+generic DT graph presentation found in "bindings/graph.txt".
+
+Non-configurable replicators:
+
+- compatible: currently supported value is "arm-replicator". Since non-configurable
+replicators don't show up on the AMBA hey don't need to be post-fixed with
+"arm,primecell".
+
+- id: a unique number that will identify this replicator.
+
+- ports or port: same as above.
+
+Optional properties for Sinks:
+
+- coresight-default-sink: must be specified for one of the sink devices that is
+intended to be made the default sink. Other sink devices must not have this
+specified. Not specifying this property on any of the sinks is invalid.
+
+Optional properties for ETM/PTMs:
+
+- arm,cp14: must be present if the system accesses ETM/PTM management registers
+via co-processor 14.
+
+- arm,cp14: access to ETM/PTM management registers is made via cp14.
+
+- cpu: the cpu phandle this ETM/PTM is affined to. When omitted the source is
+considered to belong to CPU0.
+
+Optional property for TMC:
+
+- arm,buffer-size: size of contiguous buffer space for TMC ETR (embedded trace router)
+
+
+Example:
+
+1. Sinks
+ etb: etb at 20010000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0 0x20010000 0 0x1000>;
+
+ coresight-default-sink;
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ port {
+ etb_in_port: endpoint at 0 {
+ slave-mode;
+ remote-endpoint = <&replicator_out_port0>;
+ };
+ };
+ };
+
+ tpiu: tpiu at 20030000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0 0x20030000 0 0x1000>;
+
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ port {
+ tpiu_in_port: endpoint at 0 {
+ slave-mode;
+ remote-endpoint = <&replicator_out_port1>;
+ };
+ };
+ };
+
+2. Links
+ replicator {
+ /* non-configurable replicators don't show up on the
+ * AMBA bus. As such no need to add "arm,primecell".
+ */
+ compatible = "arm,coresight-replicator";
+ /* this will show up in debugfs as "0.replicator" */
+ id = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port at 0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&etb_in_port>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+
+ /* replicator input port */
+ port at 2 {
+ reg = <0>;
+ replicator_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&funnel_out_port0>;
+ };
+ };
+ };
+ };
+
+ funnel at 20040000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x20040000 0 0x1000>;
+
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* funnel output port */
+ port at 0 {
+ reg = <0>;
+ funnel_out_port0: endpoint {
+ remote-endpoint = <&replicator_in_port0>;
+ };
+ };
+
+ /* funnel input ports */
+ port at 1 {
+ reg = <0>;
+ funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&ptm0_out_port>;
+ };
+ };
+
+ port at 2 {
+ reg = <1>;
+ funnel_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint = <&ptm1_out_port>;
+ };
+ };
+
+ port at 3 {
+ reg = <2>;
+ funnel_in_port2: endpoint {
+ slave-mode;
+ remote-endpoint = <&etm0_out_port>;
+ };
+ };
+
+ };
+ };
+
+3. Sources
+ ptm0: ptm at 2201c000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0 0x2201c000 0 0x1000>;
+
+ cpu = <&cpu0>;
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ port {
+ ptm0_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port0>;
+ };
+ };
+ };
+
+ ptm1: ptm at 2201d000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0 0x2201d000 0 0x1000>;
+
+ cpu = <&cpu1>;
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ port {
+ ptm1_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port1>;
+ };
+ };
+ };
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v4] coresight: bindings for coresight drivers
@ 2014-08-21 11:15 ` Andreas Färber
0 siblings, 0 replies; 5+ messages in thread
From: Andreas Färber @ 2014-08-21 11:15 UTC (permalink / raw)
To: mathieu.poirier
Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
devicetree, linux-kernel, linux-arm-kernel
Hi,
Am 20.08.2014 19:11, schrieb mathieu.poirier@linaro.org:
> From: Pratik Patel <pratikp@codeaurora.org>
>
> Coresight IP blocks allow for the support of HW assisted tracing
> on ARM SoCs. Bindings for the currently available blocks are
> presented herein.
>
> Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
> Signed-off-by: Panchaxari Prasannamurthy <panchaxari.prasannamurthy@linaro.org>
> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> ---
> .../devicetree/bindings/arm/coresight.txt | 205 +++++++++++++++++++++
> 1 file changed, 205 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/coresight.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> new file mode 100644
> index 0000000..2ee594d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -0,0 +1,205 @@
> +* CoreSight Components
> +
> +CoreSight components are compliant with the ARM CoreSight architecture
> +specification and can be connected in various topologies to suit a particular
> +SoCs tracing needs. These trace components can generally be classified as sinks,
> +links and sources. Trace data produced by one or more sources flows through the
> +intermediate links connecting the source to the currently selected sink. Each
> +CoreSight component device should use these properties to describe its hardware
> +characteristcs.
> +
> +Required properties for all components *except* non-configurable replicators:
> +
> +- compatible : name of the component used for driver matching. Possible values
> +include: "arm,coresight-etb10", "arm,coresight-tpiu", "arm,coresight-tmc",
> +"arm,coresight-funnel", and "arm,coresight-etm3x". All of these have to
> +be supplemented with "arm,primecell" as drivers are using the AMBA bus
> +interface. Since non-configurable replicators don't show up on the AMBA
> +bus they don't need to be post-fixed with "arm,primecell".
I think this document would be much easier to read if you indented these
paragraphs below "name" here. That way the actual property names would
stand out more when looking up a particular property.
> +
> +- reg : physical base address and length of the register set(s) of the component.
> +
> +- clocks : the clock associated to this component.
> +
> +- clock-names: the name of the clock as referenced by the code. Since we are
> +using the AMBA framework, the name should be "apb_pclk".
> +
> +- ports or port: The representation of the component's port layout using the
> +generic DT graph presentation found in "bindings/graph.txt".
> +
> +Non-configurable replicators:
> +
> +- compatible: currently supported value is "arm-replicator". Since non-configurable
> +replicators don't show up on the AMBA hey don't need to be post-fixed with
> +"arm,primecell".
> +
> +- id: a unique number that will identify this replicator.
> +
> +- ports or port: same as above.
> +
> +Optional properties for Sinks:
> +
> +- coresight-default-sink: must be specified for one of the sink devices that is
> +intended to be made the default sink. Other sink devices must not have this
> +specified. Not specifying this property on any of the sinks is invalid.
> +
> +Optional properties for ETM/PTMs:
> +
> +- arm,cp14: must be present if the system accesses ETM/PTM management registers
> +via co-processor 14.
> +
> +- arm,cp14: access to ETM/PTM management registers is made via cp14.
> +
> +- cpu: the cpu phandle this ETM/PTM is affined to. When omitted the source is
> +considered to belong to CPU0.
> +
> +Optional property for TMC:
> +
> +- arm,buffer-size: size of contiguous buffer space for TMC ETR (embedded trace router)
> +
> +
> +Example:
> +
> +1. Sinks
> + etb: etb@20010000 {
> + compatible = "arm,coresight-etb10", "arm,primecell";
> + reg = <0 0x20010000 0 0x1000>;
You seem to be using two address cells (and two size cells). In that
case, I believe I read it were convention to use etb@0,20010000?
Regards,
Andreas
> +
> + coresight-default-sink;
> + clocks = <&oscclk6a>;
> + clock-names = "apb_pclk";
> + port {
> + etb_in_port: endpoint@0 {
> + slave-mode;
> + remote-endpoint = <&replicator_out_port0>;
> + };
> + };
> + };
[snip]
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v4] coresight: bindings for coresight drivers
@ 2014-08-21 11:15 ` Andreas Färber
0 siblings, 0 replies; 5+ messages in thread
From: Andreas Färber @ 2014-08-21 11:15 UTC (permalink / raw)
To: mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hi,
Am 20.08.2014 19:11, schrieb mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org:
> From: Pratik Patel <pratikp-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>
> Coresight IP blocks allow for the support of HW assisted tracing
> on ARM SoCs. Bindings for the currently available blocks are
> presented herein.
>
> Signed-off-by: Pratik Patel <pratikp-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Signed-off-by: Panchaxari Prasannamurthy <panchaxari.prasannamurthy@linaro.org>
> Signed-off-by: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> .../devicetree/bindings/arm/coresight.txt | 205 +++++++++++++++++++++
> 1 file changed, 205 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/coresight.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> new file mode 100644
> index 0000000..2ee594d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -0,0 +1,205 @@
> +* CoreSight Components
> +
> +CoreSight components are compliant with the ARM CoreSight architecture
> +specification and can be connected in various topologies to suit a particular
> +SoCs tracing needs. These trace components can generally be classified as sinks,
> +links and sources. Trace data produced by one or more sources flows through the
> +intermediate links connecting the source to the currently selected sink. Each
> +CoreSight component device should use these properties to describe its hardware
> +characteristcs.
> +
> +Required properties for all components *except* non-configurable replicators:
> +
> +- compatible : name of the component used for driver matching. Possible values
> +include: "arm,coresight-etb10", "arm,coresight-tpiu", "arm,coresight-tmc",
> +"arm,coresight-funnel", and "arm,coresight-etm3x". All of these have to
> +be supplemented with "arm,primecell" as drivers are using the AMBA bus
> +interface. Since non-configurable replicators don't show up on the AMBA
> +bus they don't need to be post-fixed with "arm,primecell".
I think this document would be much easier to read if you indented these
paragraphs below "name" here. That way the actual property names would
stand out more when looking up a particular property.
> +
> +- reg : physical base address and length of the register set(s) of the component.
> +
> +- clocks : the clock associated to this component.
> +
> +- clock-names: the name of the clock as referenced by the code. Since we are
> +using the AMBA framework, the name should be "apb_pclk".
> +
> +- ports or port: The representation of the component's port layout using the
> +generic DT graph presentation found in "bindings/graph.txt".
> +
> +Non-configurable replicators:
> +
> +- compatible: currently supported value is "arm-replicator". Since non-configurable
> +replicators don't show up on the AMBA hey don't need to be post-fixed with
> +"arm,primecell".
> +
> +- id: a unique number that will identify this replicator.
> +
> +- ports or port: same as above.
> +
> +Optional properties for Sinks:
> +
> +- coresight-default-sink: must be specified for one of the sink devices that is
> +intended to be made the default sink. Other sink devices must not have this
> +specified. Not specifying this property on any of the sinks is invalid.
> +
> +Optional properties for ETM/PTMs:
> +
> +- arm,cp14: must be present if the system accesses ETM/PTM management registers
> +via co-processor 14.
> +
> +- arm,cp14: access to ETM/PTM management registers is made via cp14.
> +
> +- cpu: the cpu phandle this ETM/PTM is affined to. When omitted the source is
> +considered to belong to CPU0.
> +
> +Optional property for TMC:
> +
> +- arm,buffer-size: size of contiguous buffer space for TMC ETR (embedded trace router)
> +
> +
> +Example:
> +
> +1. Sinks
> + etb: etb@20010000 {
> + compatible = "arm,coresight-etb10", "arm,primecell";
> + reg = <0 0x20010000 0 0x1000>;
You seem to be using two address cells (and two size cells). In that
case, I believe I read it were convention to use etb@0,20010000?
Regards,
Andreas
> +
> + coresight-default-sink;
> + clocks = <&oscclk6a>;
> + clock-names = "apb_pclk";
> + port {
> + etb_in_port: endpoint@0 {
> + slave-mode;
> + remote-endpoint = <&replicator_out_port0>;
> + };
> + };
> + };
[snip]
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GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4] coresight: bindings for coresight drivers
@ 2014-08-21 11:15 ` Andreas Färber
0 siblings, 0 replies; 5+ messages in thread
From: Andreas Färber @ 2014-08-21 11:15 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Am 20.08.2014 19:11, schrieb mathieu.poirier at linaro.org:
> From: Pratik Patel <pratikp@codeaurora.org>
>
> Coresight IP blocks allow for the support of HW assisted tracing
> on ARM SoCs. Bindings for the currently available blocks are
> presented herein.
>
> Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
> Signed-off-by: Panchaxari Prasannamurthy <panchaxari.prasannamurthy@linaro.org>
> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> ---
> .../devicetree/bindings/arm/coresight.txt | 205 +++++++++++++++++++++
> 1 file changed, 205 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/coresight.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> new file mode 100644
> index 0000000..2ee594d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -0,0 +1,205 @@
> +* CoreSight Components
> +
> +CoreSight components are compliant with the ARM CoreSight architecture
> +specification and can be connected in various topologies to suit a particular
> +SoCs tracing needs. These trace components can generally be classified as sinks,
> +links and sources. Trace data produced by one or more sources flows through the
> +intermediate links connecting the source to the currently selected sink. Each
> +CoreSight component device should use these properties to describe its hardware
> +characteristcs.
> +
> +Required properties for all components *except* non-configurable replicators:
> +
> +- compatible : name of the component used for driver matching. Possible values
> +include: "arm,coresight-etb10", "arm,coresight-tpiu", "arm,coresight-tmc",
> +"arm,coresight-funnel", and "arm,coresight-etm3x". All of these have to
> +be supplemented with "arm,primecell" as drivers are using the AMBA bus
> +interface. Since non-configurable replicators don't show up on the AMBA
> +bus they don't need to be post-fixed with "arm,primecell".
I think this document would be much easier to read if you indented these
paragraphs below "name" here. That way the actual property names would
stand out more when looking up a particular property.
> +
> +- reg : physical base address and length of the register set(s) of the component.
> +
> +- clocks : the clock associated to this component.
> +
> +- clock-names: the name of the clock as referenced by the code. Since we are
> +using the AMBA framework, the name should be "apb_pclk".
> +
> +- ports or port: The representation of the component's port layout using the
> +generic DT graph presentation found in "bindings/graph.txt".
> +
> +Non-configurable replicators:
> +
> +- compatible: currently supported value is "arm-replicator". Since non-configurable
> +replicators don't show up on the AMBA hey don't need to be post-fixed with
> +"arm,primecell".
> +
> +- id: a unique number that will identify this replicator.
> +
> +- ports or port: same as above.
> +
> +Optional properties for Sinks:
> +
> +- coresight-default-sink: must be specified for one of the sink devices that is
> +intended to be made the default sink. Other sink devices must not have this
> +specified. Not specifying this property on any of the sinks is invalid.
> +
> +Optional properties for ETM/PTMs:
> +
> +- arm,cp14: must be present if the system accesses ETM/PTM management registers
> +via co-processor 14.
> +
> +- arm,cp14: access to ETM/PTM management registers is made via cp14.
> +
> +- cpu: the cpu phandle this ETM/PTM is affined to. When omitted the source is
> +considered to belong to CPU0.
> +
> +Optional property for TMC:
> +
> +- arm,buffer-size: size of contiguous buffer space for TMC ETR (embedded trace router)
> +
> +
> +Example:
> +
> +1. Sinks
> + etb: etb at 20010000 {
> + compatible = "arm,coresight-etb10", "arm,primecell";
> + reg = <0 0x20010000 0 0x1000>;
You seem to be using two address cells (and two size cells). In that
case, I believe I read it were convention to use etb at 0,20010000?
Regards,
Andreas
> +
> + coresight-default-sink;
> + clocks = <&oscclk6a>;
> + clock-names = "apb_pclk";
> + port {
> + etb_in_port: endpoint at 0 {
> + slave-mode;
> + remote-endpoint = <&replicator_out_port0>;
> + };
> + };
> + };
[snip]
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 16746 AG N?rnberg
^ permalink raw reply [flat|nested] 5+ messages in thread
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2014-08-20 17:11 [PATCH v4] coresight: bindings for coresight drivers mathieu.poirier
2014-08-20 17:11 ` mathieu.poirier at linaro.org
2014-08-21 11:15 ` Andreas Färber
2014-08-21 11:15 ` Andreas Färber
2014-08-21 11:15 ` Andreas Färber
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