[PATCH v5 0/4] Tegra124 soctherm driver

[PATCH v5 0/4] Tegra124 soctherm driver

[Mikko Perttunen]

Hi,

this series adds support for the thermal monitoring features of the
soctherm unit on the Tegra124 SoC. 

The branch is also available in my github repo,
  git://github.com/cyndis/linux.git soctherm-v5

Thanks,
Mikko

Mikko Perttunen (4):
  of: Add bindings for nvidia,tegra124-soctherm
  ARM: tegra: Add soctherm and thermal zones to Tegra124 device tree
  ARM: tegra: Add thermal trip points for Jetson TK1
  thermal: Add Tegra SOCTHERM thermal management driver

 .../devicetree/bindings/thermal/tegra-soctherm.txt |  53 +++
 arch/arm/boot/dts/tegra124-jetson-tk1.dts          |  41 ++
 arch/arm/boot/dts/tegra124.dtsi                    |  47 ++
 drivers/thermal/Kconfig                            |  10 +
 drivers/thermal/Makefile                           |   1 +
 drivers/thermal/tegra_soctherm.c                   | 471 +++++++++++++++++++++
 include/dt-bindings/thermal/tegra124-soctherm.h    |  13 +
 7 files changed, 636 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
 create mode 100644 drivers/thermal/tegra_soctherm.c
 create mode 100644 include/dt-bindings/thermal/tegra124-soctherm.h

-- 
1.8.1.5

[PATCH v5 0/4] Tegra124 soctherm driver

[Mikko Perttunen]

Hi,

this series adds support for the thermal monitoring features of the
soctherm unit on the Tegra124 SoC. 

The branch is also available in my github repo,
  git://github.com/cyndis/linux.git soctherm-v5

Thanks,
Mikko

Mikko Perttunen (4):
  of: Add bindings for nvidia,tegra124-soctherm
  ARM: tegra: Add soctherm and thermal zones to Tegra124 device tree
  ARM: tegra: Add thermal trip points for Jetson TK1
  thermal: Add Tegra SOCTHERM thermal management driver

 .../devicetree/bindings/thermal/tegra-soctherm.txt |  53 +++
 arch/arm/boot/dts/tegra124-jetson-tk1.dts          |  41 ++
 arch/arm/boot/dts/tegra124.dtsi                    |  47 ++
 drivers/thermal/Kconfig                            |  10 +
 drivers/thermal/Makefile                           |   1 +
 drivers/thermal/tegra_soctherm.c                   | 471 +++++++++++++++++++++
 include/dt-bindings/thermal/tegra124-soctherm.h    |  13 +
 7 files changed, 636 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
 create mode 100644 drivers/thermal/tegra_soctherm.c
 create mode 100644 include/dt-bindings/thermal/tegra124-soctherm.h

-- 
1.8.1.5

[PATCH v5 0/4] Tegra124 soctherm driver

[Mikko Perttunen]

Hi,

this series adds support for the thermal monitoring features of the
soctherm unit on the Tegra124 SoC. 

The branch is also available in my github repo,
  git://github.com/cyndis/linux.git soctherm-v5

Thanks,
Mikko

Mikko Perttunen (4):
  of: Add bindings for nvidia,tegra124-soctherm
  ARM: tegra: Add soctherm and thermal zones to Tegra124 device tree
  ARM: tegra: Add thermal trip points for Jetson TK1
  thermal: Add Tegra SOCTHERM thermal management driver

 .../devicetree/bindings/thermal/tegra-soctherm.txt |  53 +++
 arch/arm/boot/dts/tegra124-jetson-tk1.dts          |  41 ++
 arch/arm/boot/dts/tegra124.dtsi                    |  47 ++
 drivers/thermal/Kconfig                            |  10 +
 drivers/thermal/Makefile                           |   1 +
 drivers/thermal/tegra_soctherm.c                   | 471 +++++++++++++++++++++
 include/dt-bindings/thermal/tegra124-soctherm.h    |  13 +
 7 files changed, 636 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
 create mode 100644 drivers/thermal/tegra_soctherm.c
 create mode 100644 include/dt-bindings/thermal/tegra124-soctherm.h

-- 
1.8.1.5

[PATCH v5 1/4] of: Add bindings for nvidia,tegra124-soctherm

[Mikko Perttunen]

This adds binding documentation and headers for the Tegra124
SOCTHERM device tree node.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
---
 .../devicetree/bindings/thermal/tegra-soctherm.txt | 53 ++++++++++++++++++++++
 include/dt-bindings/thermal/tegra124-soctherm.h    | 13 ++++++
 2 files changed, 66 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
 create mode 100644 include/dt-bindings/thermal/tegra124-soctherm.h

diff --git a/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
new file mode 100644
index 0000000..ecf3ed7
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
@@ -0,0 +1,53 @@
+Tegra124 SOCTHERM thermal management system
+
+The SOCTHERM IP block contains thermal sensors, support for polled
+or interrupt-based thermal monitoring, CPU and GPU throttling based
+on temperature trip points, and handling external overcurrent
+notifications. It is also used to manage emergency shutdown in an
+overheating situation.
+
+Required properties :
+- compatible : "nvidia,tegra124-soctherm".
+- reg : Should contain 1 entry:
+  - SOCTHERM register set
+- interrupts : Defines the interrupt used by SOCTHERM
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  - tsensor
+  - soctherm
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - soctherm
+- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description
+    of this property. See <dt-bindings/thermal/tegra124-soctherm.h> for a
+    list of valid values when referring to thermal sensors.
+
+
+Example :
+
+	soctherm@0,700e2000 {
+		compatible = "nvidia,tegra124-soctherm";
+		reg = <0x0 0x700e2000 0x0 0x1000>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
+			<&tegra_car TEGRA124_CLK_SOC_THERM>;
+		clock-names = "tsensor", "soctherm";
+		resets = <&tegra_car 78>;
+		reset-names = "soctherm";
+
+		#thermal-sensor-cells = <1>;
+	};
+
+Example: referring to thermal sensors :
+
+       thermal-zones {
+                cpu {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors =
+                                <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
+                };
+	};
diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
new file mode 100644
index 0000000..85aaf66
--- /dev/null
+++ b/include/dt-bindings/thermal/tegra124-soctherm.h
@@ -0,0 +1,13 @@
+/*
+ * This header provides constants for binding nvidia,tegra124-soctherm.
+ */
+
+#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
+#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
+
+#define TEGRA124_SOCTHERM_SENSOR_CPU 0
+#define TEGRA124_SOCTHERM_SENSOR_MEM 1
+#define TEGRA124_SOCTHERM_SENSOR_GPU 2
+#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
+
+#endif
-- 
1.8.1.5

[PATCH v5 1/4] of: Add bindings for nvidia,tegra124-soctherm

[Mikko Perttunen]

This adds binding documentation and headers for the Tegra124
SOCTHERM device tree node.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
---
 .../devicetree/bindings/thermal/tegra-soctherm.txt | 53 ++++++++++++++++++++++
 include/dt-bindings/thermal/tegra124-soctherm.h    | 13 ++++++
 2 files changed, 66 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
 create mode 100644 include/dt-bindings/thermal/tegra124-soctherm.h

diff --git a/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
new file mode 100644
index 0000000..ecf3ed7
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
@@ -0,0 +1,53 @@
+Tegra124 SOCTHERM thermal management system
+
+The SOCTHERM IP block contains thermal sensors, support for polled
+or interrupt-based thermal monitoring, CPU and GPU throttling based
+on temperature trip points, and handling external overcurrent
+notifications. It is also used to manage emergency shutdown in an
+overheating situation.
+
+Required properties :
+- compatible : "nvidia,tegra124-soctherm".
+- reg : Should contain 1 entry:
+  - SOCTHERM register set
+- interrupts : Defines the interrupt used by SOCTHERM
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  - tsensor
+  - soctherm
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - soctherm
+- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description
+    of this property. See <dt-bindings/thermal/tegra124-soctherm.h> for a
+    list of valid values when referring to thermal sensors.
+
+
+Example :
+
+	soctherm at 0,700e2000 {
+		compatible = "nvidia,tegra124-soctherm";
+		reg = <0x0 0x700e2000 0x0 0x1000>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
+			<&tegra_car TEGRA124_CLK_SOC_THERM>;
+		clock-names = "tsensor", "soctherm";
+		resets = <&tegra_car 78>;
+		reset-names = "soctherm";
+
+		#thermal-sensor-cells = <1>;
+	};
+
+Example: referring to thermal sensors :
+
+       thermal-zones {
+                cpu {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors =
+                                <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
+                };
+	};
diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
new file mode 100644
index 0000000..85aaf66
--- /dev/null
+++ b/include/dt-bindings/thermal/tegra124-soctherm.h
@@ -0,0 +1,13 @@
+/*
+ * This header provides constants for binding nvidia,tegra124-soctherm.
+ */
+
+#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
+#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
+
+#define TEGRA124_SOCTHERM_SENSOR_CPU 0
+#define TEGRA124_SOCTHERM_SENSOR_MEM 1
+#define TEGRA124_SOCTHERM_SENSOR_GPU 2
+#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
+
+#endif
-- 
1.8.1.5

[PATCH v5 1/4] of: Add bindings for nvidia,tegra124-soctherm

[Mikko Perttunen]

This adds binding documentation and headers for the Tegra124
SOCTHERM device tree node.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
---
 .../devicetree/bindings/thermal/tegra-soctherm.txt | 53 ++++++++++++++++++++++
 include/dt-bindings/thermal/tegra124-soctherm.h    | 13 ++++++
 2 files changed, 66 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
 create mode 100644 include/dt-bindings/thermal/tegra124-soctherm.h

diff --git a/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
new file mode 100644
index 0000000..ecf3ed7
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
@@ -0,0 +1,53 @@
+Tegra124 SOCTHERM thermal management system
+
+The SOCTHERM IP block contains thermal sensors, support for polled
+or interrupt-based thermal monitoring, CPU and GPU throttling based
+on temperature trip points, and handling external overcurrent
+notifications. It is also used to manage emergency shutdown in an
+overheating situation.
+
+Required properties :
+- compatible : "nvidia,tegra124-soctherm".
+- reg : Should contain 1 entry:
+  - SOCTHERM register set
+- interrupts : Defines the interrupt used by SOCTHERM
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  - tsensor
+  - soctherm
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - soctherm
+- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description
+    of this property. See <dt-bindings/thermal/tegra124-soctherm.h> for a
+    list of valid values when referring to thermal sensors.
+
+
+Example :
+
+	soctherm@0,700e2000 {
+		compatible = "nvidia,tegra124-soctherm";
+		reg = <0x0 0x700e2000 0x0 0x1000>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
+			<&tegra_car TEGRA124_CLK_SOC_THERM>;
+		clock-names = "tsensor", "soctherm";
+		resets = <&tegra_car 78>;
+		reset-names = "soctherm";
+
+		#thermal-sensor-cells = <1>;
+	};
+
+Example: referring to thermal sensors :
+
+       thermal-zones {
+                cpu {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors =
+                                <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
+                };
+	};
diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
new file mode 100644
index 0000000..85aaf66
--- /dev/null
+++ b/include/dt-bindings/thermal/tegra124-soctherm.h
@@ -0,0 +1,13 @@
+/*
+ * This header provides constants for binding nvidia,tegra124-soctherm.
+ */
+
+#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
+#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
+
+#define TEGRA124_SOCTHERM_SENSOR_CPU 0
+#define TEGRA124_SOCTHERM_SENSOR_MEM 1
+#define TEGRA124_SOCTHERM_SENSOR_GPU 2
+#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
+
+#endif
-- 
1.8.1.5

Re: [PATCH v5 1/4] of: Add bindings for nvidia,tegra124-soctherm

[Eduardo Valentin]

Hello,

On Thu, Aug 21, 2014 at 01:17:19PM +0300, Mikko Perttunen wrote:
> This adds binding documentation and headers for the Tegra124
> SOCTHERM device tree node.
> 
> Signed-off-by: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Acked-by: Eduardo Valentin <edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Stephen, are you still queueing this series in your tree?

> ---
>  .../devicetree/bindings/thermal/tegra-soctherm.txt | 53 ++++++++++++++++++++++
>  include/dt-bindings/thermal/tegra124-soctherm.h    | 13 ++++++
>  2 files changed, 66 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
>  create mode 100644 include/dt-bindings/thermal/tegra124-soctherm.h
> 
> diff --git a/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
> new file mode 100644
> index 0000000..ecf3ed7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
> @@ -0,0 +1,53 @@
> +Tegra124 SOCTHERM thermal management system
> +
> +The SOCTHERM IP block contains thermal sensors, support for polled
> +or interrupt-based thermal monitoring, CPU and GPU throttling based
> +on temperature trip points, and handling external overcurrent
> +notifications. It is also used to manage emergency shutdown in an
> +overheating situation.
> +
> +Required properties :
> +- compatible : "nvidia,tegra124-soctherm".
> +- reg : Should contain 1 entry:
> +  - SOCTHERM register set
> +- interrupts : Defines the interrupt used by SOCTHERM
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  - tsensor
> +  - soctherm
> +- resets : Must contain an entry for each entry in reset-names.
> +  See ../reset/reset.txt for details.
> +- reset-names : Must include the following entries:
> +  - soctherm
> +- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description
> +    of this property. See <dt-bindings/thermal/tegra124-soctherm.h> for a
> +    list of valid values when referring to thermal sensors.
> +
> +
> +Example :
> +
> +	soctherm@0,700e2000 {
> +		compatible = "nvidia,tegra124-soctherm";
> +		reg = <0x0 0x700e2000 0x0 0x1000>;
> +		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
> +			<&tegra_car TEGRA124_CLK_SOC_THERM>;
> +		clock-names = "tsensor", "soctherm";
> +		resets = <&tegra_car 78>;
> +		reset-names = "soctherm";
> +
> +		#thermal-sensor-cells = <1>;
> +	};
> +
> +Example: referring to thermal sensors :
> +
> +       thermal-zones {
> +                cpu {
> +                        polling-delay-passive = <1000>;
> +                        polling-delay = <1000>;
> +
> +                        thermal-sensors =
> +                                <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
> +                };
> +	};
> diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
> new file mode 100644
> index 0000000..85aaf66
> --- /dev/null
> +++ b/include/dt-bindings/thermal/tegra124-soctherm.h
> @@ -0,0 +1,13 @@
> +/*
> + * This header provides constants for binding nvidia,tegra124-soctherm.
> + */
> +
> +#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
> +#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
> +
> +#define TEGRA124_SOCTHERM_SENSOR_CPU 0
> +#define TEGRA124_SOCTHERM_SENSOR_MEM 1
> +#define TEGRA124_SOCTHERM_SENSOR_GPU 2
> +#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
> +
> +#endif
> -- 
> 1.8.1.5
> 

[PATCH v5 1/4] of: Add bindings for nvidia,tegra124-soctherm

[Eduardo Valentin]

Hello,

On Thu, Aug 21, 2014 at 01:17:19PM +0300, Mikko Perttunen wrote:
> This adds binding documentation and headers for the Tegra124
> SOCTHERM device tree node.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> Acked-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Eduardo Valentin <edubezval@gmail.com>

Stephen, are you still queueing this series in your tree?

> ---
>  .../devicetree/bindings/thermal/tegra-soctherm.txt | 53 ++++++++++++++++++++++
>  include/dt-bindings/thermal/tegra124-soctherm.h    | 13 ++++++
>  2 files changed, 66 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
>  create mode 100644 include/dt-bindings/thermal/tegra124-soctherm.h
> 
> diff --git a/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
> new file mode 100644
> index 0000000..ecf3ed7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
> @@ -0,0 +1,53 @@
> +Tegra124 SOCTHERM thermal management system
> +
> +The SOCTHERM IP block contains thermal sensors, support for polled
> +or interrupt-based thermal monitoring, CPU and GPU throttling based
> +on temperature trip points, and handling external overcurrent
> +notifications. It is also used to manage emergency shutdown in an
> +overheating situation.
> +
> +Required properties :
> +- compatible : "nvidia,tegra124-soctherm".
> +- reg : Should contain 1 entry:
> +  - SOCTHERM register set
> +- interrupts : Defines the interrupt used by SOCTHERM
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  - tsensor
> +  - soctherm
> +- resets : Must contain an entry for each entry in reset-names.
> +  See ../reset/reset.txt for details.
> +- reset-names : Must include the following entries:
> +  - soctherm
> +- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description
> +    of this property. See <dt-bindings/thermal/tegra124-soctherm.h> for a
> +    list of valid values when referring to thermal sensors.
> +
> +
> +Example :
> +
> +	soctherm at 0,700e2000 {
> +		compatible = "nvidia,tegra124-soctherm";
> +		reg = <0x0 0x700e2000 0x0 0x1000>;
> +		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
> +			<&tegra_car TEGRA124_CLK_SOC_THERM>;
> +		clock-names = "tsensor", "soctherm";
> +		resets = <&tegra_car 78>;
> +		reset-names = "soctherm";
> +
> +		#thermal-sensor-cells = <1>;
> +	};
> +
> +Example: referring to thermal sensors :
> +
> +       thermal-zones {
> +                cpu {
> +                        polling-delay-passive = <1000>;
> +                        polling-delay = <1000>;
> +
> +                        thermal-sensors =
> +                                <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
> +                };
> +	};
> diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
> new file mode 100644
> index 0000000..85aaf66
> --- /dev/null
> +++ b/include/dt-bindings/thermal/tegra124-soctherm.h
> @@ -0,0 +1,13 @@
> +/*
> + * This header provides constants for binding nvidia,tegra124-soctherm.
> + */
> +
> +#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
> +#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
> +
> +#define TEGRA124_SOCTHERM_SENSOR_CPU 0
> +#define TEGRA124_SOCTHERM_SENSOR_MEM 1
> +#define TEGRA124_SOCTHERM_SENSOR_GPU 2
> +#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
> +
> +#endif
> -- 
> 1.8.1.5
> 

Re: [PATCH v5 1/4] of: Add bindings for nvidia,tegra124-soctherm

[Eduardo Valentin]

Hello,

On Thu, Aug 21, 2014 at 01:17:19PM +0300, Mikko Perttunen wrote:
> This adds binding documentation and headers for the Tegra124
> SOCTHERM device tree node.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> Acked-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Eduardo Valentin <edubezval@gmail.com>

Stephen, are you still queueing this series in your tree?

> ---
>  .../devicetree/bindings/thermal/tegra-soctherm.txt | 53 ++++++++++++++++++++++
>  include/dt-bindings/thermal/tegra124-soctherm.h    | 13 ++++++
>  2 files changed, 66 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
>  create mode 100644 include/dt-bindings/thermal/tegra124-soctherm.h
> 
> diff --git a/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
> new file mode 100644
> index 0000000..ecf3ed7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
> @@ -0,0 +1,53 @@
> +Tegra124 SOCTHERM thermal management system
> +
> +The SOCTHERM IP block contains thermal sensors, support for polled
> +or interrupt-based thermal monitoring, CPU and GPU throttling based
> +on temperature trip points, and handling external overcurrent
> +notifications. It is also used to manage emergency shutdown in an
> +overheating situation.
> +
> +Required properties :
> +- compatible : "nvidia,tegra124-soctherm".
> +- reg : Should contain 1 entry:
> +  - SOCTHERM register set
> +- interrupts : Defines the interrupt used by SOCTHERM
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  - tsensor
> +  - soctherm
> +- resets : Must contain an entry for each entry in reset-names.
> +  See ../reset/reset.txt for details.
> +- reset-names : Must include the following entries:
> +  - soctherm
> +- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description
> +    of this property. See <dt-bindings/thermal/tegra124-soctherm.h> for a
> +    list of valid values when referring to thermal sensors.
> +
> +
> +Example :
> +
> +	soctherm@0,700e2000 {
> +		compatible = "nvidia,tegra124-soctherm";
> +		reg = <0x0 0x700e2000 0x0 0x1000>;
> +		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
> +			<&tegra_car TEGRA124_CLK_SOC_THERM>;
> +		clock-names = "tsensor", "soctherm";
> +		resets = <&tegra_car 78>;
> +		reset-names = "soctherm";
> +
> +		#thermal-sensor-cells = <1>;
> +	};
> +
> +Example: referring to thermal sensors :
> +
> +       thermal-zones {
> +                cpu {
> +                        polling-delay-passive = <1000>;
> +                        polling-delay = <1000>;
> +
> +                        thermal-sensors =
> +                                <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
> +                };
> +	};
> diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
> new file mode 100644
> index 0000000..85aaf66
> --- /dev/null
> +++ b/include/dt-bindings/thermal/tegra124-soctherm.h
> @@ -0,0 +1,13 @@
> +/*
> + * This header provides constants for binding nvidia,tegra124-soctherm.
> + */
> +
> +#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
> +#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
> +
> +#define TEGRA124_SOCTHERM_SENSOR_CPU 0
> +#define TEGRA124_SOCTHERM_SENSOR_MEM 1
> +#define TEGRA124_SOCTHERM_SENSOR_GPU 2
> +#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
> +
> +#endif
> -- 
> 1.8.1.5
> 

Re: [PATCH v5 1/4] of: Add bindings for nvidia,tegra124-soctherm

[Stephen Warren]

On 09/24/2014 12:40 PM, Eduardo Valentin wrote:
> Hello,
>
> On Thu, Aug 21, 2014 at 01:17:19PM +0300, Mikko Perttunen wrote:
>> This adds binding documentation and headers for the Tegra124
>> SOCTHERM device tree node.
>>
>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
>> Acked-by: Stephen Warren <swarren@nvidia.com>
>
> Acked-by: Eduardo Valentin <edubezval@gmail.com>
>
> Stephen, are you still queueing this series in your tree?

Yes, I except it makes sense to take this through the Tegra tree. 
However, it wont' be for 3.18, since I've already sent pull requests for 
this cycle.

[PATCH v5 1/4] of: Add bindings for nvidia,tegra124-soctherm

[Stephen Warren]

On 09/24/2014 12:40 PM, Eduardo Valentin wrote:
> Hello,
>
> On Thu, Aug 21, 2014 at 01:17:19PM +0300, Mikko Perttunen wrote:
>> This adds binding documentation and headers for the Tegra124
>> SOCTHERM device tree node.
>>
>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
>> Acked-by: Stephen Warren <swarren@nvidia.com>
>
> Acked-by: Eduardo Valentin <edubezval@gmail.com>
>
> Stephen, are you still queueing this series in your tree?

Yes, I except it makes sense to take this through the Tegra tree. 
However, it wont' be for 3.18, since I've already sent pull requests for 
this cycle.

[PATCH v5 2/4] ARM: tegra: Add soctherm and thermal zones to Tegra124 device tree

[Mikko Perttunen]

This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones corresponding
to the four thermal sensors provided by soctherm.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v5: reordered nodes

 arch/arm/boot/dts/tegra124.dtsi | 47 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 3cb1548..a7608a4 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -3,6 +3,7 @@
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/tegra124-soctherm.h>
 
 #include "skeleton.dtsi"
 
@@ -610,6 +611,18 @@
 		status = "disabled";
 	};
 
+	soctherm: thermal-sensor@0,700e2000 {
+		compatible = "nvidia,tegra124-soctherm";
+		reg = <0x0 0x700e2000 0x0 0x1000>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
+			<&tegra_car TEGRA124_CLK_SOC_THERM>;
+		clock-names = "tsensor", "soctherm";
+		resets = <&tegra_car 78>;
+		reset-names = "soctherm";
+		#thermal-sensor-cells = <1>;
+	};
+
 	ahub@0,70300000 {
 		compatible = "nvidia,tegra124-ahub";
 		reg = <0x0 0x70300000 0x0 0x200>,
@@ -851,6 +864,40 @@
 		};
 	};
 
+	thermal-zones {
+		cpu {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
+		};
+
+		mem {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
+		};
+
+		gpu {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
+		};
+
+		pllx {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13
-- 
1.8.1.5

[PATCH v5 2/4] ARM: tegra: Add soctherm and thermal zones to Tegra124 device tree

[Mikko Perttunen]

This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones corresponding
to the four thermal sensors provided by soctherm.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v5: reordered nodes

 arch/arm/boot/dts/tegra124.dtsi | 47 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 3cb1548..a7608a4 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -3,6 +3,7 @@
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/tegra124-soctherm.h>
 
 #include "skeleton.dtsi"
 
@@ -610,6 +611,18 @@
 		status = "disabled";
 	};
 
+	soctherm: thermal-sensor at 0,700e2000 {
+		compatible = "nvidia,tegra124-soctherm";
+		reg = <0x0 0x700e2000 0x0 0x1000>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
+			<&tegra_car TEGRA124_CLK_SOC_THERM>;
+		clock-names = "tsensor", "soctherm";
+		resets = <&tegra_car 78>;
+		reset-names = "soctherm";
+		#thermal-sensor-cells = <1>;
+	};
+
 	ahub at 0,70300000 {
 		compatible = "nvidia,tegra124-ahub";
 		reg = <0x0 0x70300000 0x0 0x200>,
@@ -851,6 +864,40 @@
 		};
 	};
 
+	thermal-zones {
+		cpu {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
+		};
+
+		mem {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
+		};
+
+		gpu {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
+		};
+
+		pllx {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13
-- 
1.8.1.5

[PATCH v5 2/4] ARM: tegra: Add soctherm and thermal zones to Tegra124 device tree

[Mikko Perttunen]

This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones corresponding
to the four thermal sensors provided by soctherm.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v5: reordered nodes

 arch/arm/boot/dts/tegra124.dtsi | 47 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 3cb1548..a7608a4 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -3,6 +3,7 @@
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/tegra124-soctherm.h>
 
 #include "skeleton.dtsi"
 
@@ -610,6 +611,18 @@
 		status = "disabled";
 	};
 
+	soctherm: thermal-sensor@0,700e2000 {
+		compatible = "nvidia,tegra124-soctherm";
+		reg = <0x0 0x700e2000 0x0 0x1000>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
+			<&tegra_car TEGRA124_CLK_SOC_THERM>;
+		clock-names = "tsensor", "soctherm";
+		resets = <&tegra_car 78>;
+		reset-names = "soctherm";
+		#thermal-sensor-cells = <1>;
+	};
+
 	ahub@0,70300000 {
 		compatible = "nvidia,tegra124-ahub";
 		reg = <0x0 0x70300000 0x0 0x200>,
@@ -851,6 +864,40 @@
 		};
 	};
 
+	thermal-zones {
+		cpu {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
+		};
+
+		mem {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
+		};
+
+		gpu {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
+		};
+
+		pllx {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13
-- 
1.8.1.5

[PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Mikko Perttunen]

This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees Celsius.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v5: added cooling-maps nodes

 arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 0cdb5cf..bcdab7f 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1876,4 +1876,45 @@
 			 <&tegra_car TEGRA124_CLK_EXTERN1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
+
+	thermal-zones {
+		cpu {
+			trips {
+				trip@0 {
+					temperature = <101000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+			};
+		};
+
+		mem {
+			trips {
+				trip@0 {
+					temperature = <101000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+			};
+		};
+
+		gpu {
+			trips {
+				trip@0 {
+					temperature = <101000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+			};
+		};
+	};
 };
-- 
1.8.1.5

[PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Mikko Perttunen]

This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees Celsius.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v5: added cooling-maps nodes

 arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 0cdb5cf..bcdab7f 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1876,4 +1876,45 @@
 			 <&tegra_car TEGRA124_CLK_EXTERN1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
+
+	thermal-zones {
+		cpu {
+			trips {
+				trip at 0 {
+					temperature = <101000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+			};
+		};
+
+		mem {
+			trips {
+				trip at 0 {
+					temperature = <101000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+			};
+		};
+
+		gpu {
+			trips {
+				trip at 0 {
+					temperature = <101000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+			};
+		};
+	};
 };
-- 
1.8.1.5

[PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Mikko Perttunen]

This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees Celsius.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v5: added cooling-maps nodes

 arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 0cdb5cf..bcdab7f 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1876,4 +1876,45 @@
 			 <&tegra_car TEGRA124_CLK_EXTERN1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
+
+	thermal-zones {
+		cpu {
+			trips {
+				trip@0 {
+					temperature = <101000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+			};
+		};
+
+		mem {
+			trips {
+				trip@0 {
+					temperature = <101000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+			};
+		};
+
+		gpu {
+			trips {
+				trip@0 {
+					temperature = <101000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+			};
+		};
+	};
 };
-- 
1.8.1.5

Re: [PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Eduardo Valentin]

Hello Mikko,

On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
> This adds critical trip points to the Jetson TK1 device tree.
> The device will do a controlled shutdown when either the CPU, GPU
> or MEM thermal zone reaches 101 degrees Celsius.
> 
> Signed-off-by: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> v5: added cooling-maps nodes
> 

OK. But no cooling map entry in it. What was the reason again you don't
need/want to add the maps?

>  arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> index 0cdb5cf..bcdab7f 100644
> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> @@ -1876,4 +1876,45 @@
>  			 <&tegra_car TEGRA124_CLK_EXTERN1>;
>  		clock-names = "pll_a", "pll_a_out0", "mclk";
>  	};
> +
> +	thermal-zones {
> +		cpu {
> +			trips {
> +				trip@0 {
> +					temperature = <101000>;
> +					hysteresis = <0>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +			};
> +		};
> +
> +		mem {
> +			trips {
> +				trip@0 {
> +					temperature = <101000>;
> +					hysteresis = <0>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +			};
> +		};
> +
> +		gpu {
> +			trips {
> +				trip@0 {
> +					temperature = <101000>;
> +					hysteresis = <0>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +			};
> +		};
> +	};
>  };
> -- 
> 1.8.1.5
> 

[PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Eduardo Valentin]

Hello Mikko,

On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
> This adds critical trip points to the Jetson TK1 device tree.
> The device will do a controlled shutdown when either the CPU, GPU
> or MEM thermal zone reaches 101 degrees Celsius.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> ---
> v5: added cooling-maps nodes
> 

OK. But no cooling map entry in it. What was the reason again you don't
need/want to add the maps?

>  arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> index 0cdb5cf..bcdab7f 100644
> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> @@ -1876,4 +1876,45 @@
>  			 <&tegra_car TEGRA124_CLK_EXTERN1>;
>  		clock-names = "pll_a", "pll_a_out0", "mclk";
>  	};
> +
> +	thermal-zones {
> +		cpu {
> +			trips {
> +				trip at 0 {
> +					temperature = <101000>;
> +					hysteresis = <0>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +			};
> +		};
> +
> +		mem {
> +			trips {
> +				trip at 0 {
> +					temperature = <101000>;
> +					hysteresis = <0>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +			};
> +		};
> +
> +		gpu {
> +			trips {
> +				trip at 0 {
> +					temperature = <101000>;
> +					hysteresis = <0>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +			};
> +		};
> +	};
>  };
> -- 
> 1.8.1.5
> 

Re: [PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Eduardo Valentin]

Hello Mikko,

On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
> This adds critical trip points to the Jetson TK1 device tree.
> The device will do a controlled shutdown when either the CPU, GPU
> or MEM thermal zone reaches 101 degrees Celsius.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> ---
> v5: added cooling-maps nodes
> 

OK. But no cooling map entry in it. What was the reason again you don't
need/want to add the maps?

>  arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> index 0cdb5cf..bcdab7f 100644
> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> @@ -1876,4 +1876,45 @@
>  			 <&tegra_car TEGRA124_CLK_EXTERN1>;
>  		clock-names = "pll_a", "pll_a_out0", "mclk";
>  	};
> +
> +	thermal-zones {
> +		cpu {
> +			trips {
> +				trip@0 {
> +					temperature = <101000>;
> +					hysteresis = <0>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +			};
> +		};
> +
> +		mem {
> +			trips {
> +				trip@0 {
> +					temperature = <101000>;
> +					hysteresis = <0>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +			};
> +		};
> +
> +		gpu {
> +			trips {
> +				trip@0 {
> +					temperature = <101000>;
> +					hysteresis = <0>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +			};
> +		};
> +	};
>  };
> -- 
> 1.8.1.5
> 

Re: [PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Mikko Perttunen]

On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
> Hello Mikko,
>
> On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
>> This adds critical trip points to the Jetson TK1 device tree.
>> The device will do a controlled shutdown when either the CPU, GPU
>> or MEM thermal zone reaches 101 degrees Celsius.
>>
>> Signed-off-by: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> v5: added cooling-maps nodes
>>
>
> OK. But no cooling map entry in it. What was the reason again you don't
> need/want to add the maps?

There is currently no cooling device to map to.

Mikko

>
>>   arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
>>   1 file changed, 41 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>> index 0cdb5cf..bcdab7f 100644
>> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>> @@ -1876,4 +1876,45 @@
>>   			 <&tegra_car TEGRA124_CLK_EXTERN1>;
>>   		clock-names = "pll_a", "pll_a_out0", "mclk";
>>   	};
>> +
>> +	thermal-zones {
>> +		cpu {
>> +			trips {
>> +				trip@0 {
>> +					temperature = <101000>;
>> +					hysteresis = <0>;
>> +					type = "critical";
>> +				};
>> +			};
>> +
>> +			cooling-maps {
>> +			};
>> +		};
>> +
>> +		mem {
>> +			trips {
>> +				trip@0 {
>> +					temperature = <101000>;
>> +					hysteresis = <0>;
>> +					type = "critical";
>> +				};
>> +			};
>> +
>> +			cooling-maps {
>> +			};
>> +		};
>> +
>> +		gpu {
>> +			trips {
>> +				trip@0 {
>> +					temperature = <101000>;
>> +					hysteresis = <0>;
>> +					type = "critical";
>> +				};
>> +			};
>> +
>> +			cooling-maps {
>> +			};
>> +		};
>> +	};
>>   };
>> --
>> 1.8.1.5
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

[PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Mikko Perttunen]

On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
> Hello Mikko,
>
> On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
>> This adds critical trip points to the Jetson TK1 device tree.
>> The device will do a controlled shutdown when either the CPU, GPU
>> or MEM thermal zone reaches 101 degrees Celsius.
>>
>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
>> ---
>> v5: added cooling-maps nodes
>>
>
> OK. But no cooling map entry in it. What was the reason again you don't
> need/want to add the maps?

There is currently no cooling device to map to.

Mikko

>
>>   arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
>>   1 file changed, 41 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>> index 0cdb5cf..bcdab7f 100644
>> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>> @@ -1876,4 +1876,45 @@
>>   			 <&tegra_car TEGRA124_CLK_EXTERN1>;
>>   		clock-names = "pll_a", "pll_a_out0", "mclk";
>>   	};
>> +
>> +	thermal-zones {
>> +		cpu {
>> +			trips {
>> +				trip at 0 {
>> +					temperature = <101000>;
>> +					hysteresis = <0>;
>> +					type = "critical";
>> +				};
>> +			};
>> +
>> +			cooling-maps {
>> +			};
>> +		};
>> +
>> +		mem {
>> +			trips {
>> +				trip at 0 {
>> +					temperature = <101000>;
>> +					hysteresis = <0>;
>> +					type = "critical";
>> +				};
>> +			};
>> +
>> +			cooling-maps {
>> +			};
>> +		};
>> +
>> +		gpu {
>> +			trips {
>> +				trip at 0 {
>> +					temperature = <101000>;
>> +					hysteresis = <0>;
>> +					type = "critical";
>> +				};
>> +			};
>> +
>> +			cooling-maps {
>> +			};
>> +		};
>> +	};
>>   };
>> --
>> 1.8.1.5
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

Re: [PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Mikko Perttunen]

On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
> Hello Mikko,
>
> On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
>> This adds critical trip points to the Jetson TK1 device tree.
>> The device will do a controlled shutdown when either the CPU, GPU
>> or MEM thermal zone reaches 101 degrees Celsius.
>>
>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
>> ---
>> v5: added cooling-maps nodes
>>
>
> OK. But no cooling map entry in it. What was the reason again you don't
> need/want to add the maps?

There is currently no cooling device to map to.

Mikko

>
>>   arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
>>   1 file changed, 41 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>> index 0cdb5cf..bcdab7f 100644
>> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>> @@ -1876,4 +1876,45 @@
>>   			 <&tegra_car TEGRA124_CLK_EXTERN1>;
>>   		clock-names = "pll_a", "pll_a_out0", "mclk";
>>   	};
>> +
>> +	thermal-zones {
>> +		cpu {
>> +			trips {
>> +				trip@0 {
>> +					temperature = <101000>;
>> +					hysteresis = <0>;
>> +					type = "critical";
>> +				};
>> +			};
>> +
>> +			cooling-maps {
>> +			};
>> +		};
>> +
>> +		mem {
>> +			trips {
>> +				trip@0 {
>> +					temperature = <101000>;
>> +					hysteresis = <0>;
>> +					type = "critical";
>> +				};
>> +			};
>> +
>> +			cooling-maps {
>> +			};
>> +		};
>> +
>> +		gpu {
>> +			trips {
>> +				trip@0 {
>> +					temperature = <101000>;
>> +					hysteresis = <0>;
>> +					type = "critical";
>> +				};
>> +			};
>> +
>> +			cooling-maps {
>> +			};
>> +		};
>> +	};
>>   };
>> --
>> 1.8.1.5
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

Re: [PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Eduardo Valentin]

On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
> On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
> > Hello Mikko,
> >
> > On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
> >> This adds critical trip points to the Jetson TK1 device tree.
> >> The device will do a controlled shutdown when either the CPU, GPU
> >> or MEM thermal zone reaches 101 degrees Celsius.
> >>
> >> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> >> ---
> >> v5: added cooling-maps nodes
> >>
> >
> > OK. But no cooling map entry in it. What was the reason again you don't
> > need/want to add the maps?
> 
> There is currently no cooling device to map to.

Not even cpufreq cooling? Is CPUfreq operational in Tegra?

> 
> Mikko
> 
> >
> >>   arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
> >>   1 file changed, 41 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> >> index 0cdb5cf..bcdab7f 100644
> >> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> >> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> >> @@ -1876,4 +1876,45 @@
> >>   			 <&tegra_car TEGRA124_CLK_EXTERN1>;
> >>   		clock-names = "pll_a", "pll_a_out0", "mclk";
> >>   	};
> >> +
> >> +	thermal-zones {
> >> +		cpu {
> >> +			trips {
> >> +				trip@0 {
> >> +					temperature = <101000>;
> >> +					hysteresis = <0>;
> >> +					type = "critical";
> >> +				};
> >> +			};
> >> +
> >> +			cooling-maps {
> >> +			};
> >> +		};
> >> +
> >> +		mem {
> >> +			trips {
> >> +				trip@0 {
> >> +					temperature = <101000>;
> >> +					hysteresis = <0>;
> >> +					type = "critical";
> >> +				};
> >> +			};
> >> +
> >> +			cooling-maps {
> >> +			};
> >> +		};
> >> +
> >> +		gpu {
> >> +			trips {
> >> +				trip@0 {
> >> +					temperature = <101000>;
> >> +					hysteresis = <0>;
> >> +					type = "critical";
> >> +				};
> >> +			};
> >> +
> >> +			cooling-maps {
> >> +			};
> >> +		};
> >> +	};
> >>   };
> >> --
> >> 1.8.1.5
> >>
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> >
> 

[PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Eduardo Valentin]

On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
> On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
> > Hello Mikko,
> >
> > On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
> >> This adds critical trip points to the Jetson TK1 device tree.
> >> The device will do a controlled shutdown when either the CPU, GPU
> >> or MEM thermal zone reaches 101 degrees Celsius.
> >>
> >> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> >> ---
> >> v5: added cooling-maps nodes
> >>
> >
> > OK. But no cooling map entry in it. What was the reason again you don't
> > need/want to add the maps?
> 
> There is currently no cooling device to map to.

Not even cpufreq cooling? Is CPUfreq operational in Tegra?

> 
> Mikko
> 
> >
> >>   arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
> >>   1 file changed, 41 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> >> index 0cdb5cf..bcdab7f 100644
> >> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> >> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> >> @@ -1876,4 +1876,45 @@
> >>   			 <&tegra_car TEGRA124_CLK_EXTERN1>;
> >>   		clock-names = "pll_a", "pll_a_out0", "mclk";
> >>   	};
> >> +
> >> +	thermal-zones {
> >> +		cpu {
> >> +			trips {
> >> +				trip at 0 {
> >> +					temperature = <101000>;
> >> +					hysteresis = <0>;
> >> +					type = "critical";
> >> +				};
> >> +			};
> >> +
> >> +			cooling-maps {
> >> +			};
> >> +		};
> >> +
> >> +		mem {
> >> +			trips {
> >> +				trip at 0 {
> >> +					temperature = <101000>;
> >> +					hysteresis = <0>;
> >> +					type = "critical";
> >> +				};
> >> +			};
> >> +
> >> +			cooling-maps {
> >> +			};
> >> +		};
> >> +
> >> +		gpu {
> >> +			trips {
> >> +				trip at 0 {
> >> +					temperature = <101000>;
> >> +					hysteresis = <0>;
> >> +					type = "critical";
> >> +				};
> >> +			};
> >> +
> >> +			cooling-maps {
> >> +			};
> >> +		};
> >> +	};
> >>   };
> >> --
> >> 1.8.1.5
> >>
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> >
> 

Re: [PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Mikko Perttunen]

On 09/24/2014 09:41 PM, Eduardo Valentin wrote:
> On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
>> On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
>>> Hello Mikko,
>>>
>>> On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
>>>> This adds critical trip points to the Jetson TK1 device tree.
>>>> The device will do a controlled shutdown when either the CPU, GPU
>>>> or MEM thermal zone reaches 101 degrees Celsius.
>>>>
>>>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
>>>> ---
>>>> v5: added cooling-maps nodes
>>>>
>>>
>>> OK. But no cooling map entry in it. What was the reason again you don't
>>> need/want to add the maps?
>>
>> There is currently no cooling device to map to.
>
> Not even cpufreq cooling? Is CPUfreq operational in Tegra?

Indeed, it is not currently operational (except on Tegra20). There is a 
series for Tegra124 but it needs more work. Not going in during this cycle.

>
>>
>> Mikko
>>
>>>
>>>>    arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
>>>>    1 file changed, 41 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>>> index 0cdb5cf..bcdab7f 100644
>>>> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>>> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>>> @@ -1876,4 +1876,45 @@
>>>>    			 <&tegra_car TEGRA124_CLK_EXTERN1>;
>>>>    		clock-names = "pll_a", "pll_a_out0", "mclk";
>>>>    	};
>>>> +
>>>> +	thermal-zones {
>>>> +		cpu {
>>>> +			trips {
>>>> +				trip@0 {
>>>> +					temperature = <101000>;
>>>> +					hysteresis = <0>;
>>>> +					type = "critical";
>>>> +				};
>>>> +			};
>>>> +
>>>> +			cooling-maps {
>>>> +			};
>>>> +		};
>>>> +
>>>> +		mem {
>>>> +			trips {
>>>> +				trip@0 {
>>>> +					temperature = <101000>;
>>>> +					hysteresis = <0>;
>>>> +					type = "critical";
>>>> +				};
>>>> +			};
>>>> +
>>>> +			cooling-maps {
>>>> +			};
>>>> +		};
>>>> +
>>>> +		gpu {
>>>> +			trips {
>>>> +				trip@0 {
>>>> +					temperature = <101000>;
>>>> +					hysteresis = <0>;
>>>> +					type = "critical";
>>>> +				};
>>>> +			};
>>>> +
>>>> +			cooling-maps {
>>>> +			};
>>>> +		};
>>>> +	};
>>>>    };
>>>> --
>>>> 1.8.1.5
>>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>
>>

[PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Mikko Perttunen]

On 09/24/2014 09:41 PM, Eduardo Valentin wrote:
> On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
>> On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
>>> Hello Mikko,
>>>
>>> On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
>>>> This adds critical trip points to the Jetson TK1 device tree.
>>>> The device will do a controlled shutdown when either the CPU, GPU
>>>> or MEM thermal zone reaches 101 degrees Celsius.
>>>>
>>>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
>>>> ---
>>>> v5: added cooling-maps nodes
>>>>
>>>
>>> OK. But no cooling map entry in it. What was the reason again you don't
>>> need/want to add the maps?
>>
>> There is currently no cooling device to map to.
>
> Not even cpufreq cooling? Is CPUfreq operational in Tegra?

Indeed, it is not currently operational (except on Tegra20). There is a 
series for Tegra124 but it needs more work. Not going in during this cycle.

>
>>
>> Mikko
>>
>>>
>>>>    arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
>>>>    1 file changed, 41 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>>> index 0cdb5cf..bcdab7f 100644
>>>> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>>> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>>> @@ -1876,4 +1876,45 @@
>>>>    			 <&tegra_car TEGRA124_CLK_EXTERN1>;
>>>>    		clock-names = "pll_a", "pll_a_out0", "mclk";
>>>>    	};
>>>> +
>>>> +	thermal-zones {
>>>> +		cpu {
>>>> +			trips {
>>>> +				trip at 0 {
>>>> +					temperature = <101000>;
>>>> +					hysteresis = <0>;
>>>> +					type = "critical";
>>>> +				};
>>>> +			};
>>>> +
>>>> +			cooling-maps {
>>>> +			};
>>>> +		};
>>>> +
>>>> +		mem {
>>>> +			trips {
>>>> +				trip at 0 {
>>>> +					temperature = <101000>;
>>>> +					hysteresis = <0>;
>>>> +					type = "critical";
>>>> +				};
>>>> +			};
>>>> +
>>>> +			cooling-maps {
>>>> +			};
>>>> +		};
>>>> +
>>>> +		gpu {
>>>> +			trips {
>>>> +				trip at 0 {
>>>> +					temperature = <101000>;
>>>> +					hysteresis = <0>;
>>>> +					type = "critical";
>>>> +				};
>>>> +			};
>>>> +
>>>> +			cooling-maps {
>>>> +			};
>>>> +		};
>>>> +	};
>>>>    };
>>>> --
>>>> 1.8.1.5
>>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
>>> the body of a message to majordomo at vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>
>>

Re: [PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Eduardo Valentin]

Hello Mikko,

On Wed, Sep 24, 2014 at 09:43:55PM +0300, Mikko Perttunen wrote:
> On 09/24/2014 09:41 PM, Eduardo Valentin wrote:
> > On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
> >> On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
> >>> Hello Mikko,
> >>>
> >>> On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
> >>>> This adds critical trip points to the Jetson TK1 device tree.
> >>>> The device will do a controlled shutdown when either the CPU, GPU
> >>>> or MEM thermal zone reaches 101 degrees Celsius.
> >>>>
> >>>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> >>>> ---
> >>>> v5: added cooling-maps nodes
> >>>>
> >>>
> >>> OK. But no cooling map entry in it. What was the reason again you don't
> >>> need/want to add the maps?
> >>
> >> There is currently no cooling device to map to.
> >
> > Not even cpufreq cooling? Is CPUfreq operational in Tegra?
> 
> Indeed, it is not currently operational (except on Tegra20). There is a 
> series for Tegra124 but it needs more work. Not going in during this cycle.
> 

OK. Now I understand. In this case, can you please explain the situation
with a TODO comment inside the cooling-maps?

The way it is now, looks awkwards.

> >
> >>
> >> Mikko
> >>
> >>>
> >>>>    arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
> >>>>    1 file changed, 41 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> >>>> index 0cdb5cf..bcdab7f 100644
> >>>> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> >>>> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> >>>> @@ -1876,4 +1876,45 @@
> >>>>    			 <&tegra_car TEGRA124_CLK_EXTERN1>;
> >>>>    		clock-names = "pll_a", "pll_a_out0", "mclk";
> >>>>    	};
> >>>> +
> >>>> +	thermal-zones {
> >>>> +		cpu {
> >>>> +			trips {
> >>>> +				trip@0 {
> >>>> +					temperature = <101000>;
> >>>> +					hysteresis = <0>;
> >>>> +					type = "critical";
> >>>> +				};
> >>>> +			};
> >>>> +
> >>>> +			cooling-maps {
> >>>> +			};
> >>>> +		};
> >>>> +
> >>>> +		mem {
> >>>> +			trips {
> >>>> +				trip@0 {
> >>>> +					temperature = <101000>;
> >>>> +					hysteresis = <0>;
> >>>> +					type = "critical";
> >>>> +				};
> >>>> +			};
> >>>> +
> >>>> +			cooling-maps {
> >>>> +			};
> >>>> +		};
> >>>> +
> >>>> +		gpu {
> >>>> +			trips {
> >>>> +				trip@0 {
> >>>> +					temperature = <101000>;
> >>>> +					hysteresis = <0>;
> >>>> +					type = "critical";
> >>>> +				};
> >>>> +			};
> >>>> +
> >>>> +			cooling-maps {
> >>>> +			};
> >>>> +		};
> >>>> +	};
> >>>>    };
> >>>> --
> >>>> 1.8.1.5
> >>>>
> >>> --
> >>> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> >>> the body of a message to majordomo@vger.kernel.org
> >>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> >>>
> >>
> 

[PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Eduardo Valentin]

Hello Mikko,

On Wed, Sep 24, 2014 at 09:43:55PM +0300, Mikko Perttunen wrote:
> On 09/24/2014 09:41 PM, Eduardo Valentin wrote:
> > On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
> >> On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
> >>> Hello Mikko,
> >>>
> >>> On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
> >>>> This adds critical trip points to the Jetson TK1 device tree.
> >>>> The device will do a controlled shutdown when either the CPU, GPU
> >>>> or MEM thermal zone reaches 101 degrees Celsius.
> >>>>
> >>>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> >>>> ---
> >>>> v5: added cooling-maps nodes
> >>>>
> >>>
> >>> OK. But no cooling map entry in it. What was the reason again you don't
> >>> need/want to add the maps?
> >>
> >> There is currently no cooling device to map to.
> >
> > Not even cpufreq cooling? Is CPUfreq operational in Tegra?
> 
> Indeed, it is not currently operational (except on Tegra20). There is a 
> series for Tegra124 but it needs more work. Not going in during this cycle.
> 

OK. Now I understand. In this case, can you please explain the situation
with a TODO comment inside the cooling-maps?

The way it is now, looks awkwards.

> >
> >>
> >> Mikko
> >>
> >>>
> >>>>    arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
> >>>>    1 file changed, 41 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> >>>> index 0cdb5cf..bcdab7f 100644
> >>>> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> >>>> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
> >>>> @@ -1876,4 +1876,45 @@
> >>>>    			 <&tegra_car TEGRA124_CLK_EXTERN1>;
> >>>>    		clock-names = "pll_a", "pll_a_out0", "mclk";
> >>>>    	};
> >>>> +
> >>>> +	thermal-zones {
> >>>> +		cpu {
> >>>> +			trips {
> >>>> +				trip at 0 {
> >>>> +					temperature = <101000>;
> >>>> +					hysteresis = <0>;
> >>>> +					type = "critical";
> >>>> +				};
> >>>> +			};
> >>>> +
> >>>> +			cooling-maps {
> >>>> +			};
> >>>> +		};
> >>>> +
> >>>> +		mem {
> >>>> +			trips {
> >>>> +				trip at 0 {
> >>>> +					temperature = <101000>;
> >>>> +					hysteresis = <0>;
> >>>> +					type = "critical";
> >>>> +				};
> >>>> +			};
> >>>> +
> >>>> +			cooling-maps {
> >>>> +			};
> >>>> +		};
> >>>> +
> >>>> +		gpu {
> >>>> +			trips {
> >>>> +				trip at 0 {
> >>>> +					temperature = <101000>;
> >>>> +					hysteresis = <0>;
> >>>> +					type = "critical";
> >>>> +				};
> >>>> +			};
> >>>> +
> >>>> +			cooling-maps {
> >>>> +			};
> >>>> +		};
> >>>> +	};
> >>>>    };
> >>>> --
> >>>> 1.8.1.5
> >>>>
> >>> --
> >>> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> >>> the body of a message to majordomo at vger.kernel.org
> >>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> >>>
> >>
> 

Re: [PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Mikko Perttunen]

On 09/24/2014 09:48 PM, Eduardo Valentin wrote:
> Hello Mikko,
>
> On Wed, Sep 24, 2014 at 09:43:55PM +0300, Mikko Perttunen wrote:
>> On 09/24/2014 09:41 PM, Eduardo Valentin wrote:
>>> On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
>>>> On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
>>>>> Hello Mikko,
>>>>>
>>>>> On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
>>>>>> This adds critical trip points to the Jetson TK1 device tree.
>>>>>> The device will do a controlled shutdown when either the CPU, GPU
>>>>>> or MEM thermal zone reaches 101 degrees Celsius.
>>>>>>
>>>>>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
>>>>>> ---
>>>>>> v5: added cooling-maps nodes
>>>>>>
>>>>>
>>>>> OK. But no cooling map entry in it. What was the reason again you don't
>>>>> need/want to add the maps?
>>>>
>>>> There is currently no cooling device to map to.
>>>
>>> Not even cpufreq cooling? Is CPUfreq operational in Tegra?
>>
>> Indeed, it is not currently operational (except on Tegra20). There is a
>> series for Tegra124 but it needs more work. Not going in during this cycle.
>>
>
> OK. Now I understand. In this case, can you please explain the situation
> with a TODO comment inside the cooling-maps?
>
> The way it is now, looks awkwards.

OK, I will add a comment.

>
>>>
>>>>
>>>> Mikko
>>>>
>>>>>
>>>>>>     arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
>>>>>>     1 file changed, 41 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>>>>> index 0cdb5cf..bcdab7f 100644
>>>>>> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>>>>> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>>>>> @@ -1876,4 +1876,45 @@
>>>>>>     			 <&tegra_car TEGRA124_CLK_EXTERN1>;
>>>>>>     		clock-names = "pll_a", "pll_a_out0", "mclk";
>>>>>>     	};
>>>>>> +
>>>>>> +	thermal-zones {
>>>>>> +		cpu {
>>>>>> +			trips {
>>>>>> +				trip@0 {
>>>>>> +					temperature = <101000>;
>>>>>> +					hysteresis = <0>;
>>>>>> +					type = "critical";
>>>>>> +				};
>>>>>> +			};
>>>>>> +
>>>>>> +			cooling-maps {
>>>>>> +			};
>>>>>> +		};
>>>>>> +
>>>>>> +		mem {
>>>>>> +			trips {
>>>>>> +				trip@0 {
>>>>>> +					temperature = <101000>;
>>>>>> +					hysteresis = <0>;
>>>>>> +					type = "critical";
>>>>>> +				};
>>>>>> +			};
>>>>>> +
>>>>>> +			cooling-maps {
>>>>>> +			};
>>>>>> +		};
>>>>>> +
>>>>>> +		gpu {
>>>>>> +			trips {
>>>>>> +				trip@0 {
>>>>>> +					temperature = <101000>;
>>>>>> +					hysteresis = <0>;
>>>>>> +					type = "critical";
>>>>>> +				};
>>>>>> +			};
>>>>>> +
>>>>>> +			cooling-maps {
>>>>>> +			};
>>>>>> +		};
>>>>>> +	};
>>>>>>     };
>>>>>> --
>>>>>> 1.8.1.5
>>>>>>
>>>>> --
>>>>> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
>>>>> the body of a message to majordomo@vger.kernel.org
>>>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>>>
>>>>
>>

[PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Mikko Perttunen]

On 09/24/2014 09:48 PM, Eduardo Valentin wrote:
> Hello Mikko,
>
> On Wed, Sep 24, 2014 at 09:43:55PM +0300, Mikko Perttunen wrote:
>> On 09/24/2014 09:41 PM, Eduardo Valentin wrote:
>>> On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
>>>> On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
>>>>> Hello Mikko,
>>>>>
>>>>> On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
>>>>>> This adds critical trip points to the Jetson TK1 device tree.
>>>>>> The device will do a controlled shutdown when either the CPU, GPU
>>>>>> or MEM thermal zone reaches 101 degrees Celsius.
>>>>>>
>>>>>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
>>>>>> ---
>>>>>> v5: added cooling-maps nodes
>>>>>>
>>>>>
>>>>> OK. But no cooling map entry in it. What was the reason again you don't
>>>>> need/want to add the maps?
>>>>
>>>> There is currently no cooling device to map to.
>>>
>>> Not even cpufreq cooling? Is CPUfreq operational in Tegra?
>>
>> Indeed, it is not currently operational (except on Tegra20). There is a
>> series for Tegra124 but it needs more work. Not going in during this cycle.
>>
>
> OK. Now I understand. In this case, can you please explain the situation
> with a TODO comment inside the cooling-maps?
>
> The way it is now, looks awkwards.

OK, I will add a comment.

>
>>>
>>>>
>>>> Mikko
>>>>
>>>>>
>>>>>>     arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41 +++++++++++++++++++++++++++++++
>>>>>>     1 file changed, 41 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>>>>> index 0cdb5cf..bcdab7f 100644
>>>>>> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>>>>> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>>>>> @@ -1876,4 +1876,45 @@
>>>>>>     			 <&tegra_car TEGRA124_CLK_EXTERN1>;
>>>>>>     		clock-names = "pll_a", "pll_a_out0", "mclk";
>>>>>>     	};
>>>>>> +
>>>>>> +	thermal-zones {
>>>>>> +		cpu {
>>>>>> +			trips {
>>>>>> +				trip at 0 {
>>>>>> +					temperature = <101000>;
>>>>>> +					hysteresis = <0>;
>>>>>> +					type = "critical";
>>>>>> +				};
>>>>>> +			};
>>>>>> +
>>>>>> +			cooling-maps {
>>>>>> +			};
>>>>>> +		};
>>>>>> +
>>>>>> +		mem {
>>>>>> +			trips {
>>>>>> +				trip at 0 {
>>>>>> +					temperature = <101000>;
>>>>>> +					hysteresis = <0>;
>>>>>> +					type = "critical";
>>>>>> +				};
>>>>>> +			};
>>>>>> +
>>>>>> +			cooling-maps {
>>>>>> +			};
>>>>>> +		};
>>>>>> +
>>>>>> +		gpu {
>>>>>> +			trips {
>>>>>> +				trip at 0 {
>>>>>> +					temperature = <101000>;
>>>>>> +					hysteresis = <0>;
>>>>>> +					type = "critical";
>>>>>> +				};
>>>>>> +			};
>>>>>> +
>>>>>> +			cooling-maps {
>>>>>> +			};
>>>>>> +		};
>>>>>> +	};
>>>>>>     };
>>>>>> --
>>>>>> 1.8.1.5
>>>>>>
>>>>> --
>>>>> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
>>>>> the body of a message to majordomo at vger.kernel.org
>>>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>>>
>>>>
>>

Re: [PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Pavel Machek]

On Wed 2014-09-24 14:32:06, Eduardo Valentin wrote:
> Hello Mikko,
> 
> On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
> > This adds critical trip points to the Jetson TK1 device tree.
> > The device will do a controlled shutdown when either the CPU, GPU
> > or MEM thermal zone reaches 101 degrees Celsius.

> > +			trips {
> > +				trip@0 {
> > +					temperature = <101000>;
> > +					hysteresis = <0>;
> > +					type = "critical";
> > +				};

Would it be still time to switch to some more reasonable unit, like
degrees celsius? milicelsius is a bit of overkill.. ACPI uses
deciCelsius, but .. celsius should be enough.

								Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Pavel Machek]

On Wed 2014-09-24 14:32:06, Eduardo Valentin wrote:
> Hello Mikko,
> 
> On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
> > This adds critical trip points to the Jetson TK1 device tree.
> > The device will do a controlled shutdown when either the CPU, GPU
> > or MEM thermal zone reaches 101 degrees Celsius.

> > +			trips {
> > +				trip at 0 {
> > +					temperature = <101000>;
> > +					hysteresis = <0>;
> > +					type = "critical";
> > +				};

Would it be still time to switch to some more reasonable unit, like
degrees celsius? milicelsius is a bit of overkill.. ACPI uses
deciCelsius, but .. celsius should be enough.

								Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Re: [PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Peter De Schrijver]

On Fri, Oct 03, 2014 at 09:57:24PM +0200, Pavel Machek wrote:
> On Wed 2014-09-24 14:32:06, Eduardo Valentin wrote:
> > Hello Mikko,
> > 
> > On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
> > > This adds critical trip points to the Jetson TK1 device tree.
> > > The device will do a controlled shutdown when either the CPU, GPU
> > > or MEM thermal zone reaches 101 degrees Celsius.
> 
> > > +			trips {
> > > +				trip@0 {
> > > +					temperature = <101000>;
> > > +					hysteresis = <0>;
> > > +					type = "critical";
> > > +				};
> 
> Would it be still time to switch to some more reasonable unit, like
> degrees celsius? milicelsius is a bit of overkill.. ACPI uses
> deciCelsius, but .. celsius should be enough.
> 

We should be using deciKelvin then.

Cheers,

Peter.

[PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Peter De Schrijver]

On Fri, Oct 03, 2014 at 09:57:24PM +0200, Pavel Machek wrote:
> On Wed 2014-09-24 14:32:06, Eduardo Valentin wrote:
> > Hello Mikko,
> > 
> > On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
> > > This adds critical trip points to the Jetson TK1 device tree.
> > > The device will do a controlled shutdown when either the CPU, GPU
> > > or MEM thermal zone reaches 101 degrees Celsius.
> 
> > > +			trips {
> > > +				trip at 0 {
> > > +					temperature = <101000>;
> > > +					hysteresis = <0>;
> > > +					type = "critical";
> > > +				};
> 
> Would it be still time to switch to some more reasonable unit, like
> degrees celsius? milicelsius is a bit of overkill.. ACPI uses
> deciCelsius, but .. celsius should be enough.
> 

We should be using deciKelvin then.

Cheers,

Peter.

Re: [PATCH v5 3/4] ARM: tegra: Add thermal trip points for Jetson TK1

[Peter De Schrijver]

On Fri, Oct 03, 2014 at 09:57:24PM +0200, Pavel Machek wrote:
> On Wed 2014-09-24 14:32:06, Eduardo Valentin wrote:
> > Hello Mikko,
> > 
> > On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
> > > This adds critical trip points to the Jetson TK1 device tree.
> > > The device will do a controlled shutdown when either the CPU, GPU
> > > or MEM thermal zone reaches 101 degrees Celsius.
> 
> > > +			trips {
> > > +				trip@0 {
> > > +					temperature = <101000>;
> > > +					hysteresis = <0>;
> > > +					type = "critical";
> > > +				};
> 
> Would it be still time to switch to some more reasonable unit, like
> degrees celsius? milicelsius is a bit of overkill.. ACPI uses
> deciCelsius, but .. celsius should be enough.
> 

We should be using deciKelvin then.

Cheers,

Peter.

[PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Mikko Perttunen]

This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v5:
- changed tsample_ate to 480
- constified structs
- added missing --i
- read shifted_ft from TSENSOR8 fuse
- use precise divison function when calculating
  calibration values

 drivers/thermal/Kconfig          |  10 +
 drivers/thermal/Makefile         |   1 +
 drivers/thermal/tegra_soctherm.c | 471 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 482 insertions(+)
 create mode 100644 drivers/thermal/tegra_soctherm.c

diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 693208e..fd9d049 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -175,6 +175,16 @@ config ARMADA_THERMAL
 	  Enable this option if you want to have support for thermal management
 	  controller present in Armada 370 and Armada XP SoC.
 
+config TEGRA_SOCTHERM
+	tristate "Tegra SOCTHERM thermal management"
+	depends on ARCH_TEGRA
+	help
+	  Enable this option for integrated thermal management support on NVIDIA
+	  Tegra124 systems-on-chip. The driver supports four thermal zones
+	  (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
+	  zones to manage temperatures. This option is also required for the
+	  emergency thermal reset (thermtrip) feature to function.
+
 config DB8500_CPUFREQ_COOLING
 	tristate "DB8500 cpufreq cooling"
 	depends on ARCH_U8500
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 31e232f..f0b94d5 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_INTEL_SOC_DTS_THERMAL)	+= intel_soc_dts_thermal.o
 obj-$(CONFIG_TI_SOC_THERMAL)	+= ti-soc-thermal/
 obj-$(CONFIG_ACPI_INT3403_THERMAL)	+= int3403_thermal.o
 obj-$(CONFIG_ST_THERMAL)	+= st/
+obj-$(CONFIG_TEGRA_SOCTHERM)	+= tegra_soctherm.o
diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
new file mode 100644
index 0000000..3742e24
--- /dev/null
+++ b/drivers/thermal/tegra_soctherm.c
@@ -0,0 +1,471 @@
+/*
+ * drivers/thermal/tegra_soctherm.c
+ *
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author:
+ *	Mikko Perttunen <mperttunen@nvidia.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/thermal.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <soc/tegra/fuse.h>
+
+#define SENSOR_CONFIG0				0
+#define		SENSOR_CONFIG0_STOP		BIT(0)
+#define		SENSOR_CONFIG0_TALL_SHIFT	8
+#define		SENSOR_CONFIG0_TCALC_OVER	BIT(4)
+#define		SENSOR_CONFIG0_OVER		BIT(3)
+#define		SENSOR_CONFIG0_CPTR_OVER	BIT(2)
+#define SENSOR_CONFIG1				4
+#define		SENSOR_CONFIG1_TSAMPLE_SHIFT	0
+#define		SENSOR_CONFIG1_TIDDQ_EN_SHIFT	15
+#define		SENSOR_CONFIG1_TEN_COUNT_SHIFT	24
+#define		SENSOR_CONFIG1_TEMP_ENABLE	BIT(31)
+#define SENSOR_CONFIG2				8
+#define		SENSOR_CONFIG2_THERMA_SHIFT	16
+#define		SENSOR_CONFIG2_THERMB_SHIFT	0
+
+#define SENSOR_PDIV				0x1c0
+#define		SENSOR_PDIV_T124		0x8888
+#define SENSOR_HOTSPOT_OFF			0x1c4
+#define		SENSOR_HOTSPOT_OFF_T124		0x00060600
+#define SENSOR_TEMP1				0x1c8
+#define SENSOR_TEMP2				0x1cc
+
+#define SENSOR_TEMP_MASK			0xffff
+#define READBACK_VALUE_MASK			0xff00
+#define READBACK_VALUE_SHIFT			8
+#define READBACK_ADD_HALF			BIT(7)
+#define READBACK_NEGATE				BIT(1)
+
+#define FUSE_TSENSOR8_CALIB			0x180
+#define FUSE_SPARE_REALIGNMENT_REG_0		0x1fc
+
+#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK	0x1fff
+#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK	(0x1fff << 13)
+#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT	13
+
+#define FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK	0x3ff
+#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK	(0x7ff << 10)
+#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT	10
+
+#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_MASK 0x3f
+#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK (0x1f << 21)
+#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT 21
+
+#define NOMINAL_CALIB_FT_T124			105
+#define NOMINAL_CALIB_CP_T124			25
+
+struct tegra_tsensor_configuration {
+	u32 tall, tsample, tiddq_en, ten_count;
+	u32 pdiv, tsample_ate, pdiv_ate;
+};
+
+struct tegra_tsensor {
+	u32 base;
+	u32 calib_fuse_offset;
+	/* Correction values used to modify values read from calibration fuses */
+	s32 fuse_corr_alpha, fuse_corr_beta;
+};
+
+struct tegra_thermctl_zone {
+	void __iomem *temp_reg;
+	int temp_shift;
+};
+
+static const struct tegra_tsensor_configuration t124_tsensor_config = {
+	.tall = 16300,
+	.tsample = 120,
+	.tiddq_en = 1,
+	.ten_count = 1,
+	.pdiv = 8,
+	.tsample_ate = 480,
+	.pdiv_ate = 8
+};
+
+static const struct tegra_tsensor t124_tsensors[] = {
+	{
+		.base = 0xc0,
+		.calib_fuse_offset = 0x098,
+		.fuse_corr_alpha = 1135400,
+		.fuse_corr_beta = -6266900,
+	},
+	{
+		.base = 0xe0,
+		.calib_fuse_offset = 0x084,
+		.fuse_corr_alpha = 1122220,
+		.fuse_corr_beta = -5700700,
+	},
+	{
+		.base = 0x100,
+		.calib_fuse_offset = 0x088,
+		.fuse_corr_alpha = 1127000,
+		.fuse_corr_beta = -6768200,
+	},
+	{
+		.base = 0x120,
+		.calib_fuse_offset = 0x12c,
+		.fuse_corr_alpha = 1110900,
+		.fuse_corr_beta = -6232000,
+	},
+	{
+		.base = 0x140,
+		.calib_fuse_offset = 0x158,
+		.fuse_corr_alpha = 1122300,
+		.fuse_corr_beta = -5936400,
+	},
+	{
+		.base = 0x160,
+		.calib_fuse_offset = 0x15c,
+		.fuse_corr_alpha = 1145700,
+		.fuse_corr_beta = -7124600,
+	},
+	{
+		.base = 0x180,
+		.calib_fuse_offset = 0x154,
+		.fuse_corr_alpha = 1120100,
+		.fuse_corr_beta = -6000500,
+	},
+	{
+		.base = 0x1a0,
+		.calib_fuse_offset = 0x160,
+		.fuse_corr_alpha = 1106500,
+		.fuse_corr_beta = -6729300,
+	},
+};
+
+struct tegra_soctherm {
+	struct reset_control *reset;
+	struct clk *clock_tsensor;
+	struct clk *clock_soctherm;
+	void __iomem *regs;
+
+	struct thermal_zone_device *thermctl_tzs[4];
+};
+
+struct tsensor_shared_calibration {
+	u32 base_cp, base_ft;
+	u32 actual_temp_cp, actual_temp_ft;
+};
+
+static int calculate_shared_calibration(struct tsensor_shared_calibration *r)
+{
+	u32 val;
+	u32 shifted_cp, shifted_ft;
+	int err;
+
+	err = tegra_fuse_readl(FUSE_TSENSOR8_CALIB, &val);
+	if (err)
+		return err;
+	r->base_cp = val & FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK;
+	r->base_ft = (val & FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK)
+		>> FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT;
+	val = ((val & FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK)
+		>> FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT);
+	shifted_ft = sign_extend32(val, 4);
+
+	err = tegra_fuse_readl(FUSE_SPARE_REALIGNMENT_REG_0, &val);
+	if (err)
+		return err;
+	shifted_cp = sign_extend32(val, 5);
+
+	r->actual_temp_cp = 2 * NOMINAL_CALIB_CP_T124 + shifted_cp;
+	r->actual_temp_ft = 2 * NOMINAL_CALIB_FT_T124 + shifted_ft;
+
+	return 0;
+}
+
+static s64 div64_s64_precise(s64 a, s64 b)
+{
+	s64 r, al;
+
+	/* Scale up for increased precision division */
+	al = a << 16;
+
+	r = div64_s64(al * 2 + 1, 2 * b);
+	return r >> 16;
+}
+
+static int calculate_tsensor_calibration(
+	const struct tegra_tsensor *sensor,
+	struct tsensor_shared_calibration shared,
+	u32 *calib
+)
+{
+	u32 val;
+	s32 actual_tsensor_ft, actual_tsensor_cp;
+	s32 delta_sens, delta_temp;
+	s32 mult, div;
+	s16 therma, thermb;
+	int err;
+
+	err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
+	if (err)
+		return err;
+
+	actual_tsensor_cp = (shared.base_cp * 64) + sign_extend32(val, 12);
+	val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK)
+		>> FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
+	actual_tsensor_ft = (shared.base_ft * 32) + sign_extend32(val, 12);
+
+	delta_sens = actual_tsensor_ft - actual_tsensor_cp;
+	delta_temp = shared.actual_temp_ft - shared.actual_temp_cp;
+
+	mult = t124_tsensor_config.pdiv * t124_tsensor_config.tsample_ate;
+	div = t124_tsensor_config.tsample * t124_tsensor_config.pdiv_ate;
+
+	therma = div64_s64_precise((s64) delta_temp * (1LL << 13) * mult,
+		(s64) delta_sens * div);
+	thermb = div64_s64_precise(
+		((s64) actual_tsensor_ft * shared.actual_temp_cp) -
+		((s64) actual_tsensor_cp * shared.actual_temp_ft),
+		(s64) delta_sens);
+
+	therma = div64_s64_precise((s64) therma * sensor->fuse_corr_alpha,
+		(s64) 1000000LL);
+	thermb = div64_s64_precise((s64) thermb * sensor->fuse_corr_alpha +
+		sensor->fuse_corr_beta,
+		(s64) 1000000LL);
+
+	*calib = ((u16)(therma) << SENSOR_CONFIG2_THERMA_SHIFT) |
+		((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
+
+	return 0;
+}
+
+static int enable_tsensor(struct tegra_soctherm *tegra,
+			  const struct tegra_tsensor *sensor,
+			  struct tsensor_shared_calibration shared)
+{
+	void * __iomem base = tegra->regs + sensor->base;
+	unsigned int val;
+	u32 calib;
+	int err;
+
+	err = calculate_tsensor_calibration(sensor, shared, &calib);
+	if (err)
+		return err;
+
+	val = 0;
+	val |= t124_tsensor_config.tall << SENSOR_CONFIG0_TALL_SHIFT;
+	writel(val, base + SENSOR_CONFIG0);
+
+	val = 0;
+	val |= (t124_tsensor_config.tsample - 1) <<
+		SENSOR_CONFIG1_TSAMPLE_SHIFT;
+	val |= t124_tsensor_config.tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
+	val |= t124_tsensor_config.ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
+	val |= SENSOR_CONFIG1_TEMP_ENABLE;
+	writel(val, base + SENSOR_CONFIG1);
+
+	writel(calib, base + SENSOR_CONFIG2);
+
+	return 0;
+}
+
+/* Translate from soctherm readback format to millicelsius.
+ * The soctherm readback format in bits is as follows:
+ *   TTTTTTTT H______N
+ * where T's contain the temperature in Celsius,
+ * H denotes an addition of 0.5 Celsius and N denotes negation
+ * of the final value.
+ */
+static inline long translate_temp(u16 val)
+{
+	long t;
+
+	t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
+	if (val & READBACK_ADD_HALF)
+		t += 500;
+	if (val & READBACK_NEGATE)
+		t *= -1;
+
+	return t;
+}
+
+static int tegra_thermctl_get_temp(void *data, long *out_temp)
+{
+	struct tegra_thermctl_zone *zone = data;
+	u32 val;
+
+	val = (readl(zone->temp_reg) >> zone->temp_shift) & SENSOR_TEMP_MASK;
+	*out_temp = translate_temp(val);
+
+	return 0;
+}
+
+static const struct of_device_id tegra_soctherm_of_match[] = {
+	{ .compatible = "nvidia,tegra124-soctherm" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
+
+static const int thermctl_temp_offsets[] = {
+	SENSOR_TEMP1, SENSOR_TEMP2, SENSOR_TEMP1, SENSOR_TEMP2
+};
+
+static const int thermctl_temp_shifts[] = {
+	16, 16, 0, 0
+};
+
+static int tegra_soctherm_probe(struct platform_device *pdev)
+{
+	struct tegra_soctherm *tegra;
+	struct thermal_zone_device *tz;
+	struct tsensor_shared_calibration shared_calib;
+	int i;
+	int err = 0;
+
+	const struct tegra_tsensor *tsensors = t124_tsensors;
+
+	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
+	if (!tegra)
+		return -ENOMEM;
+
+	tegra->regs = devm_ioremap_resource(&pdev->dev,
+		platform_get_resource(pdev, IORESOURCE_MEM, 0));
+	if (IS_ERR(tegra->regs)) {
+		dev_err(&pdev->dev, "can't get registers");
+		return PTR_ERR(tegra->regs);
+	}
+
+	tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
+	if (IS_ERR(tegra->reset)) {
+		dev_err(&pdev->dev, "can't get soctherm reset\n");
+		return PTR_ERR(tegra->reset);
+	}
+
+	tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
+	if (IS_ERR(tegra->clock_tsensor)) {
+		dev_err(&pdev->dev, "can't get clock tsensor\n");
+		return PTR_ERR(tegra->clock_tsensor);
+	}
+
+	tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
+	if (IS_ERR(tegra->clock_soctherm)) {
+		dev_err(&pdev->dev, "can't get clock soctherm\n");
+		return PTR_ERR(tegra->clock_soctherm);
+	}
+
+	reset_control_assert(tegra->reset);
+
+	err = clk_prepare_enable(tegra->clock_soctherm);
+	if (err) {
+		reset_control_deassert(tegra->reset);
+		return err;
+	}
+
+	err = clk_prepare_enable(tegra->clock_tsensor);
+	if (err) {
+		clk_disable_unprepare(tegra->clock_soctherm);
+		reset_control_deassert(tegra->reset);
+		return err;
+	}
+
+	reset_control_deassert(tegra->reset);
+
+	/* Initialize raw sensors */
+
+	err = calculate_shared_calibration(&shared_calib);
+	if (err)
+		goto disable_clocks;
+
+	for (i = 0; i < ARRAY_SIZE(t124_tsensors); ++i) {
+		err = enable_tsensor(tegra, tsensors + i, shared_calib);
+		if (err)
+			goto disable_clocks;
+	}
+
+	writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
+	writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
+
+	/* Initialize thermctl sensors */
+
+	for (i = 0; i < ARRAY_SIZE(tegra->thermctl_tzs); ++i) {
+		struct tegra_thermctl_zone *zone =
+			devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
+		if (!zone) {
+			err = -ENOMEM;
+			--i;
+			goto unregister_tzs;
+		}
+
+		zone->temp_reg = tegra->regs + thermctl_temp_offsets[i];
+		zone->temp_shift = thermctl_temp_shifts[i];
+
+		tz = thermal_zone_of_sensor_register(
+			&pdev->dev, i, zone, tegra_thermctl_get_temp, NULL);
+		if (IS_ERR(tz)) {
+			err = PTR_ERR(tz);
+			dev_err(&pdev->dev, "failed to register sensor: %d\n",
+				err);
+			--i;
+			goto unregister_tzs;
+		}
+
+		tegra->thermctl_tzs[i] = tz;
+	}
+
+	return 0;
+
+unregister_tzs:
+	for (; i >= 0; i--)
+		thermal_zone_of_sensor_unregister(&pdev->dev,
+						  tegra->thermctl_tzs[i]);
+
+disable_clocks:
+	clk_disable_unprepare(tegra->clock_tsensor);
+	clk_disable_unprepare(tegra->clock_soctherm);
+
+	return err;
+}
+
+static int tegra_soctherm_remove(struct platform_device *pdev)
+{
+	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(tegra->thermctl_tzs); ++i) {
+		thermal_zone_of_sensor_unregister(&pdev->dev,
+						  tegra->thermctl_tzs[i]);
+	}
+
+	clk_disable_unprepare(tegra->clock_tsensor);
+	clk_disable_unprepare(tegra->clock_soctherm);
+
+	return 0;
+}
+
+static struct platform_driver tegra_soctherm_driver = {
+	.probe = tegra_soctherm_probe,
+	.remove = tegra_soctherm_remove,
+	.driver = {
+		.name = "tegra_soctherm",
+		.of_match_table = tegra_soctherm_of_match,
+	},
+};
+module_platform_driver(tegra_soctherm_driver);
+
+MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
+MODULE_DESCRIPTION("Tegra SOCTHERM thermal management driver");
+MODULE_LICENSE("GPL v2");
-- 
1.8.1.5

[PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Mikko Perttunen]

This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v5:
- changed tsample_ate to 480
- constified structs
- added missing --i
- read shifted_ft from TSENSOR8 fuse
- use precise divison function when calculating
  calibration values

 drivers/thermal/Kconfig          |  10 +
 drivers/thermal/Makefile         |   1 +
 drivers/thermal/tegra_soctherm.c | 471 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 482 insertions(+)
 create mode 100644 drivers/thermal/tegra_soctherm.c

diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 693208e..fd9d049 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -175,6 +175,16 @@ config ARMADA_THERMAL
 	  Enable this option if you want to have support for thermal management
 	  controller present in Armada 370 and Armada XP SoC.
 
+config TEGRA_SOCTHERM
+	tristate "Tegra SOCTHERM thermal management"
+	depends on ARCH_TEGRA
+	help
+	  Enable this option for integrated thermal management support on NVIDIA
+	  Tegra124 systems-on-chip. The driver supports four thermal zones
+	  (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
+	  zones to manage temperatures. This option is also required for the
+	  emergency thermal reset (thermtrip) feature to function.
+
 config DB8500_CPUFREQ_COOLING
 	tristate "DB8500 cpufreq cooling"
 	depends on ARCH_U8500
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 31e232f..f0b94d5 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_INTEL_SOC_DTS_THERMAL)	+= intel_soc_dts_thermal.o
 obj-$(CONFIG_TI_SOC_THERMAL)	+= ti-soc-thermal/
 obj-$(CONFIG_ACPI_INT3403_THERMAL)	+= int3403_thermal.o
 obj-$(CONFIG_ST_THERMAL)	+= st/
+obj-$(CONFIG_TEGRA_SOCTHERM)	+= tegra_soctherm.o
diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
new file mode 100644
index 0000000..3742e24
--- /dev/null
+++ b/drivers/thermal/tegra_soctherm.c
@@ -0,0 +1,471 @@
+/*
+ * drivers/thermal/tegra_soctherm.c
+ *
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author:
+ *	Mikko Perttunen <mperttunen@nvidia.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/thermal.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <soc/tegra/fuse.h>
+
+#define SENSOR_CONFIG0				0
+#define		SENSOR_CONFIG0_STOP		BIT(0)
+#define		SENSOR_CONFIG0_TALL_SHIFT	8
+#define		SENSOR_CONFIG0_TCALC_OVER	BIT(4)
+#define		SENSOR_CONFIG0_OVER		BIT(3)
+#define		SENSOR_CONFIG0_CPTR_OVER	BIT(2)
+#define SENSOR_CONFIG1				4
+#define		SENSOR_CONFIG1_TSAMPLE_SHIFT	0
+#define		SENSOR_CONFIG1_TIDDQ_EN_SHIFT	15
+#define		SENSOR_CONFIG1_TEN_COUNT_SHIFT	24
+#define		SENSOR_CONFIG1_TEMP_ENABLE	BIT(31)
+#define SENSOR_CONFIG2				8
+#define		SENSOR_CONFIG2_THERMA_SHIFT	16
+#define		SENSOR_CONFIG2_THERMB_SHIFT	0
+
+#define SENSOR_PDIV				0x1c0
+#define		SENSOR_PDIV_T124		0x8888
+#define SENSOR_HOTSPOT_OFF			0x1c4
+#define		SENSOR_HOTSPOT_OFF_T124		0x00060600
+#define SENSOR_TEMP1				0x1c8
+#define SENSOR_TEMP2				0x1cc
+
+#define SENSOR_TEMP_MASK			0xffff
+#define READBACK_VALUE_MASK			0xff00
+#define READBACK_VALUE_SHIFT			8
+#define READBACK_ADD_HALF			BIT(7)
+#define READBACK_NEGATE				BIT(1)
+
+#define FUSE_TSENSOR8_CALIB			0x180
+#define FUSE_SPARE_REALIGNMENT_REG_0		0x1fc
+
+#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK	0x1fff
+#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK	(0x1fff << 13)
+#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT	13
+
+#define FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK	0x3ff
+#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK	(0x7ff << 10)
+#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT	10
+
+#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_MASK 0x3f
+#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK (0x1f << 21)
+#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT 21
+
+#define NOMINAL_CALIB_FT_T124			105
+#define NOMINAL_CALIB_CP_T124			25
+
+struct tegra_tsensor_configuration {
+	u32 tall, tsample, tiddq_en, ten_count;
+	u32 pdiv, tsample_ate, pdiv_ate;
+};
+
+struct tegra_tsensor {
+	u32 base;
+	u32 calib_fuse_offset;
+	/* Correction values used to modify values read from calibration fuses */
+	s32 fuse_corr_alpha, fuse_corr_beta;
+};
+
+struct tegra_thermctl_zone {
+	void __iomem *temp_reg;
+	int temp_shift;
+};
+
+static const struct tegra_tsensor_configuration t124_tsensor_config = {
+	.tall = 16300,
+	.tsample = 120,
+	.tiddq_en = 1,
+	.ten_count = 1,
+	.pdiv = 8,
+	.tsample_ate = 480,
+	.pdiv_ate = 8
+};
+
+static const struct tegra_tsensor t124_tsensors[] = {
+	{
+		.base = 0xc0,
+		.calib_fuse_offset = 0x098,
+		.fuse_corr_alpha = 1135400,
+		.fuse_corr_beta = -6266900,
+	},
+	{
+		.base = 0xe0,
+		.calib_fuse_offset = 0x084,
+		.fuse_corr_alpha = 1122220,
+		.fuse_corr_beta = -5700700,
+	},
+	{
+		.base = 0x100,
+		.calib_fuse_offset = 0x088,
+		.fuse_corr_alpha = 1127000,
+		.fuse_corr_beta = -6768200,
+	},
+	{
+		.base = 0x120,
+		.calib_fuse_offset = 0x12c,
+		.fuse_corr_alpha = 1110900,
+		.fuse_corr_beta = -6232000,
+	},
+	{
+		.base = 0x140,
+		.calib_fuse_offset = 0x158,
+		.fuse_corr_alpha = 1122300,
+		.fuse_corr_beta = -5936400,
+	},
+	{
+		.base = 0x160,
+		.calib_fuse_offset = 0x15c,
+		.fuse_corr_alpha = 1145700,
+		.fuse_corr_beta = -7124600,
+	},
+	{
+		.base = 0x180,
+		.calib_fuse_offset = 0x154,
+		.fuse_corr_alpha = 1120100,
+		.fuse_corr_beta = -6000500,
+	},
+	{
+		.base = 0x1a0,
+		.calib_fuse_offset = 0x160,
+		.fuse_corr_alpha = 1106500,
+		.fuse_corr_beta = -6729300,
+	},
+};
+
+struct tegra_soctherm {
+	struct reset_control *reset;
+	struct clk *clock_tsensor;
+	struct clk *clock_soctherm;
+	void __iomem *regs;
+
+	struct thermal_zone_device *thermctl_tzs[4];
+};
+
+struct tsensor_shared_calibration {
+	u32 base_cp, base_ft;
+	u32 actual_temp_cp, actual_temp_ft;
+};
+
+static int calculate_shared_calibration(struct tsensor_shared_calibration *r)
+{
+	u32 val;
+	u32 shifted_cp, shifted_ft;
+	int err;
+
+	err = tegra_fuse_readl(FUSE_TSENSOR8_CALIB, &val);
+	if (err)
+		return err;
+	r->base_cp = val & FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK;
+	r->base_ft = (val & FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK)
+		>> FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT;
+	val = ((val & FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK)
+		>> FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT);
+	shifted_ft = sign_extend32(val, 4);
+
+	err = tegra_fuse_readl(FUSE_SPARE_REALIGNMENT_REG_0, &val);
+	if (err)
+		return err;
+	shifted_cp = sign_extend32(val, 5);
+
+	r->actual_temp_cp = 2 * NOMINAL_CALIB_CP_T124 + shifted_cp;
+	r->actual_temp_ft = 2 * NOMINAL_CALIB_FT_T124 + shifted_ft;
+
+	return 0;
+}
+
+static s64 div64_s64_precise(s64 a, s64 b)
+{
+	s64 r, al;
+
+	/* Scale up for increased precision division */
+	al = a << 16;
+
+	r = div64_s64(al * 2 + 1, 2 * b);
+	return r >> 16;
+}
+
+static int calculate_tsensor_calibration(
+	const struct tegra_tsensor *sensor,
+	struct tsensor_shared_calibration shared,
+	u32 *calib
+)
+{
+	u32 val;
+	s32 actual_tsensor_ft, actual_tsensor_cp;
+	s32 delta_sens, delta_temp;
+	s32 mult, div;
+	s16 therma, thermb;
+	int err;
+
+	err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
+	if (err)
+		return err;
+
+	actual_tsensor_cp = (shared.base_cp * 64) + sign_extend32(val, 12);
+	val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK)
+		>> FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
+	actual_tsensor_ft = (shared.base_ft * 32) + sign_extend32(val, 12);
+
+	delta_sens = actual_tsensor_ft - actual_tsensor_cp;
+	delta_temp = shared.actual_temp_ft - shared.actual_temp_cp;
+
+	mult = t124_tsensor_config.pdiv * t124_tsensor_config.tsample_ate;
+	div = t124_tsensor_config.tsample * t124_tsensor_config.pdiv_ate;
+
+	therma = div64_s64_precise((s64) delta_temp * (1LL << 13) * mult,
+		(s64) delta_sens * div);
+	thermb = div64_s64_precise(
+		((s64) actual_tsensor_ft * shared.actual_temp_cp) -
+		((s64) actual_tsensor_cp * shared.actual_temp_ft),
+		(s64) delta_sens);
+
+	therma = div64_s64_precise((s64) therma * sensor->fuse_corr_alpha,
+		(s64) 1000000LL);
+	thermb = div64_s64_precise((s64) thermb * sensor->fuse_corr_alpha +
+		sensor->fuse_corr_beta,
+		(s64) 1000000LL);
+
+	*calib = ((u16)(therma) << SENSOR_CONFIG2_THERMA_SHIFT) |
+		((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
+
+	return 0;
+}
+
+static int enable_tsensor(struct tegra_soctherm *tegra,
+			  const struct tegra_tsensor *sensor,
+			  struct tsensor_shared_calibration shared)
+{
+	void * __iomem base = tegra->regs + sensor->base;
+	unsigned int val;
+	u32 calib;
+	int err;
+
+	err = calculate_tsensor_calibration(sensor, shared, &calib);
+	if (err)
+		return err;
+
+	val = 0;
+	val |= t124_tsensor_config.tall << SENSOR_CONFIG0_TALL_SHIFT;
+	writel(val, base + SENSOR_CONFIG0);
+
+	val = 0;
+	val |= (t124_tsensor_config.tsample - 1) <<
+		SENSOR_CONFIG1_TSAMPLE_SHIFT;
+	val |= t124_tsensor_config.tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
+	val |= t124_tsensor_config.ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
+	val |= SENSOR_CONFIG1_TEMP_ENABLE;
+	writel(val, base + SENSOR_CONFIG1);
+
+	writel(calib, base + SENSOR_CONFIG2);
+
+	return 0;
+}
+
+/* Translate from soctherm readback format to millicelsius.
+ * The soctherm readback format in bits is as follows:
+ *   TTTTTTTT H______N
+ * where T's contain the temperature in Celsius,
+ * H denotes an addition of 0.5 Celsius and N denotes negation
+ * of the final value.
+ */
+static inline long translate_temp(u16 val)
+{
+	long t;
+
+	t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
+	if (val & READBACK_ADD_HALF)
+		t += 500;
+	if (val & READBACK_NEGATE)
+		t *= -1;
+
+	return t;
+}
+
+static int tegra_thermctl_get_temp(void *data, long *out_temp)
+{
+	struct tegra_thermctl_zone *zone = data;
+	u32 val;
+
+	val = (readl(zone->temp_reg) >> zone->temp_shift) & SENSOR_TEMP_MASK;
+	*out_temp = translate_temp(val);
+
+	return 0;
+}
+
+static const struct of_device_id tegra_soctherm_of_match[] = {
+	{ .compatible = "nvidia,tegra124-soctherm" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
+
+static const int thermctl_temp_offsets[] = {
+	SENSOR_TEMP1, SENSOR_TEMP2, SENSOR_TEMP1, SENSOR_TEMP2
+};
+
+static const int thermctl_temp_shifts[] = {
+	16, 16, 0, 0
+};
+
+static int tegra_soctherm_probe(struct platform_device *pdev)
+{
+	struct tegra_soctherm *tegra;
+	struct thermal_zone_device *tz;
+	struct tsensor_shared_calibration shared_calib;
+	int i;
+	int err = 0;
+
+	const struct tegra_tsensor *tsensors = t124_tsensors;
+
+	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
+	if (!tegra)
+		return -ENOMEM;
+
+	tegra->regs = devm_ioremap_resource(&pdev->dev,
+		platform_get_resource(pdev, IORESOURCE_MEM, 0));
+	if (IS_ERR(tegra->regs)) {
+		dev_err(&pdev->dev, "can't get registers");
+		return PTR_ERR(tegra->regs);
+	}
+
+	tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
+	if (IS_ERR(tegra->reset)) {
+		dev_err(&pdev->dev, "can't get soctherm reset\n");
+		return PTR_ERR(tegra->reset);
+	}
+
+	tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
+	if (IS_ERR(tegra->clock_tsensor)) {
+		dev_err(&pdev->dev, "can't get clock tsensor\n");
+		return PTR_ERR(tegra->clock_tsensor);
+	}
+
+	tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
+	if (IS_ERR(tegra->clock_soctherm)) {
+		dev_err(&pdev->dev, "can't get clock soctherm\n");
+		return PTR_ERR(tegra->clock_soctherm);
+	}
+
+	reset_control_assert(tegra->reset);
+
+	err = clk_prepare_enable(tegra->clock_soctherm);
+	if (err) {
+		reset_control_deassert(tegra->reset);
+		return err;
+	}
+
+	err = clk_prepare_enable(tegra->clock_tsensor);
+	if (err) {
+		clk_disable_unprepare(tegra->clock_soctherm);
+		reset_control_deassert(tegra->reset);
+		return err;
+	}
+
+	reset_control_deassert(tegra->reset);
+
+	/* Initialize raw sensors */
+
+	err = calculate_shared_calibration(&shared_calib);
+	if (err)
+		goto disable_clocks;
+
+	for (i = 0; i < ARRAY_SIZE(t124_tsensors); ++i) {
+		err = enable_tsensor(tegra, tsensors + i, shared_calib);
+		if (err)
+			goto disable_clocks;
+	}
+
+	writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
+	writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
+
+	/* Initialize thermctl sensors */
+
+	for (i = 0; i < ARRAY_SIZE(tegra->thermctl_tzs); ++i) {
+		struct tegra_thermctl_zone *zone =
+			devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
+		if (!zone) {
+			err = -ENOMEM;
+			--i;
+			goto unregister_tzs;
+		}
+
+		zone->temp_reg = tegra->regs + thermctl_temp_offsets[i];
+		zone->temp_shift = thermctl_temp_shifts[i];
+
+		tz = thermal_zone_of_sensor_register(
+			&pdev->dev, i, zone, tegra_thermctl_get_temp, NULL);
+		if (IS_ERR(tz)) {
+			err = PTR_ERR(tz);
+			dev_err(&pdev->dev, "failed to register sensor: %d\n",
+				err);
+			--i;
+			goto unregister_tzs;
+		}
+
+		tegra->thermctl_tzs[i] = tz;
+	}
+
+	return 0;
+
+unregister_tzs:
+	for (; i >= 0; i--)
+		thermal_zone_of_sensor_unregister(&pdev->dev,
+						  tegra->thermctl_tzs[i]);
+
+disable_clocks:
+	clk_disable_unprepare(tegra->clock_tsensor);
+	clk_disable_unprepare(tegra->clock_soctherm);
+
+	return err;
+}
+
+static int tegra_soctherm_remove(struct platform_device *pdev)
+{
+	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(tegra->thermctl_tzs); ++i) {
+		thermal_zone_of_sensor_unregister(&pdev->dev,
+						  tegra->thermctl_tzs[i]);
+	}
+
+	clk_disable_unprepare(tegra->clock_tsensor);
+	clk_disable_unprepare(tegra->clock_soctherm);
+
+	return 0;
+}
+
+static struct platform_driver tegra_soctherm_driver = {
+	.probe = tegra_soctherm_probe,
+	.remove = tegra_soctherm_remove,
+	.driver = {
+		.name = "tegra_soctherm",
+		.of_match_table = tegra_soctherm_of_match,
+	},
+};
+module_platform_driver(tegra_soctherm_driver);
+
+MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
+MODULE_DESCRIPTION("Tegra SOCTHERM thermal management driver");
+MODULE_LICENSE("GPL v2");
-- 
1.8.1.5

[PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Mikko Perttunen]

This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v5:
- changed tsample_ate to 480
- constified structs
- added missing --i
- read shifted_ft from TSENSOR8 fuse
- use precise divison function when calculating
  calibration values

 drivers/thermal/Kconfig          |  10 +
 drivers/thermal/Makefile         |   1 +
 drivers/thermal/tegra_soctherm.c | 471 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 482 insertions(+)
 create mode 100644 drivers/thermal/tegra_soctherm.c

diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 693208e..fd9d049 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -175,6 +175,16 @@ config ARMADA_THERMAL
 	  Enable this option if you want to have support for thermal management
 	  controller present in Armada 370 and Armada XP SoC.
 
+config TEGRA_SOCTHERM
+	tristate "Tegra SOCTHERM thermal management"
+	depends on ARCH_TEGRA
+	help
+	  Enable this option for integrated thermal management support on NVIDIA
+	  Tegra124 systems-on-chip. The driver supports four thermal zones
+	  (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
+	  zones to manage temperatures. This option is also required for the
+	  emergency thermal reset (thermtrip) feature to function.
+
 config DB8500_CPUFREQ_COOLING
 	tristate "DB8500 cpufreq cooling"
 	depends on ARCH_U8500
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 31e232f..f0b94d5 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_INTEL_SOC_DTS_THERMAL)	+= intel_soc_dts_thermal.o
 obj-$(CONFIG_TI_SOC_THERMAL)	+= ti-soc-thermal/
 obj-$(CONFIG_ACPI_INT3403_THERMAL)	+= int3403_thermal.o
 obj-$(CONFIG_ST_THERMAL)	+= st/
+obj-$(CONFIG_TEGRA_SOCTHERM)	+= tegra_soctherm.o
diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
new file mode 100644
index 0000000..3742e24
--- /dev/null
+++ b/drivers/thermal/tegra_soctherm.c
@@ -0,0 +1,471 @@
+/*
+ * drivers/thermal/tegra_soctherm.c
+ *
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author:
+ *	Mikko Perttunen <mperttunen@nvidia.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/thermal.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <soc/tegra/fuse.h>
+
+#define SENSOR_CONFIG0				0
+#define		SENSOR_CONFIG0_STOP		BIT(0)
+#define		SENSOR_CONFIG0_TALL_SHIFT	8
+#define		SENSOR_CONFIG0_TCALC_OVER	BIT(4)
+#define		SENSOR_CONFIG0_OVER		BIT(3)
+#define		SENSOR_CONFIG0_CPTR_OVER	BIT(2)
+#define SENSOR_CONFIG1				4
+#define		SENSOR_CONFIG1_TSAMPLE_SHIFT	0
+#define		SENSOR_CONFIG1_TIDDQ_EN_SHIFT	15
+#define		SENSOR_CONFIG1_TEN_COUNT_SHIFT	24
+#define		SENSOR_CONFIG1_TEMP_ENABLE	BIT(31)
+#define SENSOR_CONFIG2				8
+#define		SENSOR_CONFIG2_THERMA_SHIFT	16
+#define		SENSOR_CONFIG2_THERMB_SHIFT	0
+
+#define SENSOR_PDIV				0x1c0
+#define		SENSOR_PDIV_T124		0x8888
+#define SENSOR_HOTSPOT_OFF			0x1c4
+#define		SENSOR_HOTSPOT_OFF_T124		0x00060600
+#define SENSOR_TEMP1				0x1c8
+#define SENSOR_TEMP2				0x1cc
+
+#define SENSOR_TEMP_MASK			0xffff
+#define READBACK_VALUE_MASK			0xff00
+#define READBACK_VALUE_SHIFT			8
+#define READBACK_ADD_HALF			BIT(7)
+#define READBACK_NEGATE				BIT(1)
+
+#define FUSE_TSENSOR8_CALIB			0x180
+#define FUSE_SPARE_REALIGNMENT_REG_0		0x1fc
+
+#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK	0x1fff
+#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK	(0x1fff << 13)
+#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT	13
+
+#define FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK	0x3ff
+#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK	(0x7ff << 10)
+#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT	10
+
+#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_MASK 0x3f
+#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK (0x1f << 21)
+#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT 21
+
+#define NOMINAL_CALIB_FT_T124			105
+#define NOMINAL_CALIB_CP_T124			25
+
+struct tegra_tsensor_configuration {
+	u32 tall, tsample, tiddq_en, ten_count;
+	u32 pdiv, tsample_ate, pdiv_ate;
+};
+
+struct tegra_tsensor {
+	u32 base;
+	u32 calib_fuse_offset;
+	/* Correction values used to modify values read from calibration fuses */
+	s32 fuse_corr_alpha, fuse_corr_beta;
+};
+
+struct tegra_thermctl_zone {
+	void __iomem *temp_reg;
+	int temp_shift;
+};
+
+static const struct tegra_tsensor_configuration t124_tsensor_config = {
+	.tall = 16300,
+	.tsample = 120,
+	.tiddq_en = 1,
+	.ten_count = 1,
+	.pdiv = 8,
+	.tsample_ate = 480,
+	.pdiv_ate = 8
+};
+
+static const struct tegra_tsensor t124_tsensors[] = {
+	{
+		.base = 0xc0,
+		.calib_fuse_offset = 0x098,
+		.fuse_corr_alpha = 1135400,
+		.fuse_corr_beta = -6266900,
+	},
+	{
+		.base = 0xe0,
+		.calib_fuse_offset = 0x084,
+		.fuse_corr_alpha = 1122220,
+		.fuse_corr_beta = -5700700,
+	},
+	{
+		.base = 0x100,
+		.calib_fuse_offset = 0x088,
+		.fuse_corr_alpha = 1127000,
+		.fuse_corr_beta = -6768200,
+	},
+	{
+		.base = 0x120,
+		.calib_fuse_offset = 0x12c,
+		.fuse_corr_alpha = 1110900,
+		.fuse_corr_beta = -6232000,
+	},
+	{
+		.base = 0x140,
+		.calib_fuse_offset = 0x158,
+		.fuse_corr_alpha = 1122300,
+		.fuse_corr_beta = -5936400,
+	},
+	{
+		.base = 0x160,
+		.calib_fuse_offset = 0x15c,
+		.fuse_corr_alpha = 1145700,
+		.fuse_corr_beta = -7124600,
+	},
+	{
+		.base = 0x180,
+		.calib_fuse_offset = 0x154,
+		.fuse_corr_alpha = 1120100,
+		.fuse_corr_beta = -6000500,
+	},
+	{
+		.base = 0x1a0,
+		.calib_fuse_offset = 0x160,
+		.fuse_corr_alpha = 1106500,
+		.fuse_corr_beta = -6729300,
+	},
+};
+
+struct tegra_soctherm {
+	struct reset_control *reset;
+	struct clk *clock_tsensor;
+	struct clk *clock_soctherm;
+	void __iomem *regs;
+
+	struct thermal_zone_device *thermctl_tzs[4];
+};
+
+struct tsensor_shared_calibration {
+	u32 base_cp, base_ft;
+	u32 actual_temp_cp, actual_temp_ft;
+};
+
+static int calculate_shared_calibration(struct tsensor_shared_calibration *r)
+{
+	u32 val;
+	u32 shifted_cp, shifted_ft;
+	int err;
+
+	err = tegra_fuse_readl(FUSE_TSENSOR8_CALIB, &val);
+	if (err)
+		return err;
+	r->base_cp = val & FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK;
+	r->base_ft = (val & FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK)
+		>> FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT;
+	val = ((val & FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK)
+		>> FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT);
+	shifted_ft = sign_extend32(val, 4);
+
+	err = tegra_fuse_readl(FUSE_SPARE_REALIGNMENT_REG_0, &val);
+	if (err)
+		return err;
+	shifted_cp = sign_extend32(val, 5);
+
+	r->actual_temp_cp = 2 * NOMINAL_CALIB_CP_T124 + shifted_cp;
+	r->actual_temp_ft = 2 * NOMINAL_CALIB_FT_T124 + shifted_ft;
+
+	return 0;
+}
+
+static s64 div64_s64_precise(s64 a, s64 b)
+{
+	s64 r, al;
+
+	/* Scale up for increased precision division */
+	al = a << 16;
+
+	r = div64_s64(al * 2 + 1, 2 * b);
+	return r >> 16;
+}
+
+static int calculate_tsensor_calibration(
+	const struct tegra_tsensor *sensor,
+	struct tsensor_shared_calibration shared,
+	u32 *calib
+)
+{
+	u32 val;
+	s32 actual_tsensor_ft, actual_tsensor_cp;
+	s32 delta_sens, delta_temp;
+	s32 mult, div;
+	s16 therma, thermb;
+	int err;
+
+	err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
+	if (err)
+		return err;
+
+	actual_tsensor_cp = (shared.base_cp * 64) + sign_extend32(val, 12);
+	val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK)
+		>> FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
+	actual_tsensor_ft = (shared.base_ft * 32) + sign_extend32(val, 12);
+
+	delta_sens = actual_tsensor_ft - actual_tsensor_cp;
+	delta_temp = shared.actual_temp_ft - shared.actual_temp_cp;
+
+	mult = t124_tsensor_config.pdiv * t124_tsensor_config.tsample_ate;
+	div = t124_tsensor_config.tsample * t124_tsensor_config.pdiv_ate;
+
+	therma = div64_s64_precise((s64) delta_temp * (1LL << 13) * mult,
+		(s64) delta_sens * div);
+	thermb = div64_s64_precise(
+		((s64) actual_tsensor_ft * shared.actual_temp_cp) -
+		((s64) actual_tsensor_cp * shared.actual_temp_ft),
+		(s64) delta_sens);
+
+	therma = div64_s64_precise((s64) therma * sensor->fuse_corr_alpha,
+		(s64) 1000000LL);
+	thermb = div64_s64_precise((s64) thermb * sensor->fuse_corr_alpha +
+		sensor->fuse_corr_beta,
+		(s64) 1000000LL);
+
+	*calib = ((u16)(therma) << SENSOR_CONFIG2_THERMA_SHIFT) |
+		((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
+
+	return 0;
+}
+
+static int enable_tsensor(struct tegra_soctherm *tegra,
+			  const struct tegra_tsensor *sensor,
+			  struct tsensor_shared_calibration shared)
+{
+	void * __iomem base = tegra->regs + sensor->base;
+	unsigned int val;
+	u32 calib;
+	int err;
+
+	err = calculate_tsensor_calibration(sensor, shared, &calib);
+	if (err)
+		return err;
+
+	val = 0;
+	val |= t124_tsensor_config.tall << SENSOR_CONFIG0_TALL_SHIFT;
+	writel(val, base + SENSOR_CONFIG0);
+
+	val = 0;
+	val |= (t124_tsensor_config.tsample - 1) <<
+		SENSOR_CONFIG1_TSAMPLE_SHIFT;
+	val |= t124_tsensor_config.tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
+	val |= t124_tsensor_config.ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
+	val |= SENSOR_CONFIG1_TEMP_ENABLE;
+	writel(val, base + SENSOR_CONFIG1);
+
+	writel(calib, base + SENSOR_CONFIG2);
+
+	return 0;
+}
+
+/* Translate from soctherm readback format to millicelsius.
+ * The soctherm readback format in bits is as follows:
+ *   TTTTTTTT H______N
+ * where T's contain the temperature in Celsius,
+ * H denotes an addition of 0.5 Celsius and N denotes negation
+ * of the final value.
+ */
+static inline long translate_temp(u16 val)
+{
+	long t;
+
+	t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
+	if (val & READBACK_ADD_HALF)
+		t += 500;
+	if (val & READBACK_NEGATE)
+		t *= -1;
+
+	return t;
+}
+
+static int tegra_thermctl_get_temp(void *data, long *out_temp)
+{
+	struct tegra_thermctl_zone *zone = data;
+	u32 val;
+
+	val = (readl(zone->temp_reg) >> zone->temp_shift) & SENSOR_TEMP_MASK;
+	*out_temp = translate_temp(val);
+
+	return 0;
+}
+
+static const struct of_device_id tegra_soctherm_of_match[] = {
+	{ .compatible = "nvidia,tegra124-soctherm" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
+
+static const int thermctl_temp_offsets[] = {
+	SENSOR_TEMP1, SENSOR_TEMP2, SENSOR_TEMP1, SENSOR_TEMP2
+};
+
+static const int thermctl_temp_shifts[] = {
+	16, 16, 0, 0
+};
+
+static int tegra_soctherm_probe(struct platform_device *pdev)
+{
+	struct tegra_soctherm *tegra;
+	struct thermal_zone_device *tz;
+	struct tsensor_shared_calibration shared_calib;
+	int i;
+	int err = 0;
+
+	const struct tegra_tsensor *tsensors = t124_tsensors;
+
+	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
+	if (!tegra)
+		return -ENOMEM;
+
+	tegra->regs = devm_ioremap_resource(&pdev->dev,
+		platform_get_resource(pdev, IORESOURCE_MEM, 0));
+	if (IS_ERR(tegra->regs)) {
+		dev_err(&pdev->dev, "can't get registers");
+		return PTR_ERR(tegra->regs);
+	}
+
+	tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
+	if (IS_ERR(tegra->reset)) {
+		dev_err(&pdev->dev, "can't get soctherm reset\n");
+		return PTR_ERR(tegra->reset);
+	}
+
+	tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
+	if (IS_ERR(tegra->clock_tsensor)) {
+		dev_err(&pdev->dev, "can't get clock tsensor\n");
+		return PTR_ERR(tegra->clock_tsensor);
+	}
+
+	tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
+	if (IS_ERR(tegra->clock_soctherm)) {
+		dev_err(&pdev->dev, "can't get clock soctherm\n");
+		return PTR_ERR(tegra->clock_soctherm);
+	}
+
+	reset_control_assert(tegra->reset);
+
+	err = clk_prepare_enable(tegra->clock_soctherm);
+	if (err) {
+		reset_control_deassert(tegra->reset);
+		return err;
+	}
+
+	err = clk_prepare_enable(tegra->clock_tsensor);
+	if (err) {
+		clk_disable_unprepare(tegra->clock_soctherm);
+		reset_control_deassert(tegra->reset);
+		return err;
+	}
+
+	reset_control_deassert(tegra->reset);
+
+	/* Initialize raw sensors */
+
+	err = calculate_shared_calibration(&shared_calib);
+	if (err)
+		goto disable_clocks;
+
+	for (i = 0; i < ARRAY_SIZE(t124_tsensors); ++i) {
+		err = enable_tsensor(tegra, tsensors + i, shared_calib);
+		if (err)
+			goto disable_clocks;
+	}
+
+	writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
+	writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
+
+	/* Initialize thermctl sensors */
+
+	for (i = 0; i < ARRAY_SIZE(tegra->thermctl_tzs); ++i) {
+		struct tegra_thermctl_zone *zone =
+			devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
+		if (!zone) {
+			err = -ENOMEM;
+			--i;
+			goto unregister_tzs;
+		}
+
+		zone->temp_reg = tegra->regs + thermctl_temp_offsets[i];
+		zone->temp_shift = thermctl_temp_shifts[i];
+
+		tz = thermal_zone_of_sensor_register(
+			&pdev->dev, i, zone, tegra_thermctl_get_temp, NULL);
+		if (IS_ERR(tz)) {
+			err = PTR_ERR(tz);
+			dev_err(&pdev->dev, "failed to register sensor: %d\n",
+				err);
+			--i;
+			goto unregister_tzs;
+		}
+
+		tegra->thermctl_tzs[i] = tz;
+	}
+
+	return 0;
+
+unregister_tzs:
+	for (; i >= 0; i--)
+		thermal_zone_of_sensor_unregister(&pdev->dev,
+						  tegra->thermctl_tzs[i]);
+
+disable_clocks:
+	clk_disable_unprepare(tegra->clock_tsensor);
+	clk_disable_unprepare(tegra->clock_soctherm);
+
+	return err;
+}
+
+static int tegra_soctherm_remove(struct platform_device *pdev)
+{
+	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(tegra->thermctl_tzs); ++i) {
+		thermal_zone_of_sensor_unregister(&pdev->dev,
+						  tegra->thermctl_tzs[i]);
+	}
+
+	clk_disable_unprepare(tegra->clock_tsensor);
+	clk_disable_unprepare(tegra->clock_soctherm);
+
+	return 0;
+}
+
+static struct platform_driver tegra_soctherm_driver = {
+	.probe = tegra_soctherm_probe,
+	.remove = tegra_soctherm_remove,
+	.driver = {
+		.name = "tegra_soctherm",
+		.of_match_table = tegra_soctherm_of_match,
+	},
+};
+module_platform_driver(tegra_soctherm_driver);
+
+MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
+MODULE_DESCRIPTION("Tegra SOCTHERM thermal management driver");
+MODULE_LICENSE("GPL v2");
-- 
1.8.1.5

Re: [PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Eduardo Valentin]

Mikko,

On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
> This adds support for the Tegra SOCTHERM thermal sensing and management
> system found in the Tegra124 system-on-chip. This initial driver supports
> temperature polling for four thermal zones.
> 
> Signed-off-by: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> v5:
> - changed tsample_ate to 480
> - constified structs
> - added missing --i
> - read shifted_ft from TSENSOR8 fuse
> - use precise divison function when calculating
>   calibration values
> 
>  drivers/thermal/Kconfig          |  10 +
>  drivers/thermal/Makefile         |   1 +
>  drivers/thermal/tegra_soctherm.c | 471 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 482 insertions(+)
>  create mode 100644 drivers/thermal/tegra_soctherm.c
> 
> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index 693208e..fd9d049 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -175,6 +175,16 @@ config ARMADA_THERMAL
>  	  Enable this option if you want to have support for thermal management
>  	  controller present in Armada 370 and Armada XP SoC.
>  
> +config TEGRA_SOCTHERM
> +	tristate "Tegra SOCTHERM thermal management"
> +	depends on ARCH_TEGRA
> +	help
> +	  Enable this option for integrated thermal management support on NVIDIA
> +	  Tegra124 systems-on-chip. The driver supports four thermal zones
> +	  (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
> +	  zones to manage temperatures. This option is also required for the
> +	  emergency thermal reset (thermtrip) feature to function.
> +
>  config DB8500_CPUFREQ_COOLING
>  	tristate "DB8500 cpufreq cooling"
>  	depends on ARCH_U8500
> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
> index 31e232f..f0b94d5 100644
> --- a/drivers/thermal/Makefile
> +++ b/drivers/thermal/Makefile
> @@ -33,3 +33,4 @@ obj-$(CONFIG_INTEL_SOC_DTS_THERMAL)	+= intel_soc_dts_thermal.o
>  obj-$(CONFIG_TI_SOC_THERMAL)	+= ti-soc-thermal/
>  obj-$(CONFIG_ACPI_INT3403_THERMAL)	+= int3403_thermal.o
>  obj-$(CONFIG_ST_THERMAL)	+= st/
> +obj-$(CONFIG_TEGRA_SOCTHERM)	+= tegra_soctherm.o
> diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
> new file mode 100644
> index 0000000..3742e24
> --- /dev/null
> +++ b/drivers/thermal/tegra_soctherm.c
> @@ -0,0 +1,471 @@
> +/*
> + * drivers/thermal/tegra_soctherm.c
> + *
> + * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
> + *
> + * Author:
> + *	Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include <linux/thermal.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/bitops.h>
> +#include <soc/tegra/fuse.h>
> +
> +#define SENSOR_CONFIG0				0
> +#define		SENSOR_CONFIG0_STOP		BIT(0)
> +#define		SENSOR_CONFIG0_TALL_SHIFT	8
> +#define		SENSOR_CONFIG0_TCALC_OVER	BIT(4)
> +#define		SENSOR_CONFIG0_OVER		BIT(3)
> +#define		SENSOR_CONFIG0_CPTR_OVER	BIT(2)
> +#define SENSOR_CONFIG1				4
> +#define		SENSOR_CONFIG1_TSAMPLE_SHIFT	0
> +#define		SENSOR_CONFIG1_TIDDQ_EN_SHIFT	15
> +#define		SENSOR_CONFIG1_TEN_COUNT_SHIFT	24
> +#define		SENSOR_CONFIG1_TEMP_ENABLE	BIT(31)
> +#define SENSOR_CONFIG2				8
> +#define		SENSOR_CONFIG2_THERMA_SHIFT	16
> +#define		SENSOR_CONFIG2_THERMB_SHIFT	0
> +
> +#define SENSOR_PDIV				0x1c0
> +#define		SENSOR_PDIV_T124		0x8888
> +#define SENSOR_HOTSPOT_OFF			0x1c4
> +#define		SENSOR_HOTSPOT_OFF_T124		0x00060600
> +#define SENSOR_TEMP1				0x1c8
> +#define SENSOR_TEMP2				0x1cc
> +
> +#define SENSOR_TEMP_MASK			0xffff
> +#define READBACK_VALUE_MASK			0xff00
> +#define READBACK_VALUE_SHIFT			8
> +#define READBACK_ADD_HALF			BIT(7)
> +#define READBACK_NEGATE				BIT(1)
> +
> +#define FUSE_TSENSOR8_CALIB			0x180
> +#define FUSE_SPARE_REALIGNMENT_REG_0		0x1fc
> +
> +#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK	0x1fff
> +#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK	(0x1fff << 13)
> +#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT	13
> +
> +#define FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK	0x3ff
> +#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK	(0x7ff << 10)
> +#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT	10
> +
> +#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_MASK 0x3f
> +#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK (0x1f << 21)
> +#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT 21
> +
> +#define NOMINAL_CALIB_FT_T124			105
> +#define NOMINAL_CALIB_CP_T124			25
> +
> +struct tegra_tsensor_configuration {
> +	u32 tall, tsample, tiddq_en, ten_count;
> +	u32 pdiv, tsample_ate, pdiv_ate;
> +};
> +
> +struct tegra_tsensor {
> +	u32 base;
> +	u32 calib_fuse_offset;
> +	/* Correction values used to modify values read from calibration fuses */
> +	s32 fuse_corr_alpha, fuse_corr_beta;
> +};
> +
> +struct tegra_thermctl_zone {
> +	void __iomem *temp_reg;
> +	int temp_shift;
> +};
> +
> +static const struct tegra_tsensor_configuration t124_tsensor_config = {
> +	.tall = 16300,
> +	.tsample = 120,
> +	.tiddq_en = 1,
> +	.ten_count = 1,
> +	.pdiv = 8,
> +	.tsample_ate = 480,
> +	.pdiv_ate = 8
> +};
> +
> +static const struct tegra_tsensor t124_tsensors[] = {
> +	{
> +		.base = 0xc0,
> +		.calib_fuse_offset = 0x098,
> +		.fuse_corr_alpha = 1135400,
> +		.fuse_corr_beta = -6266900,
> +	},
> +	{
> +		.base = 0xe0,
> +		.calib_fuse_offset = 0x084,
> +		.fuse_corr_alpha = 1122220,
> +		.fuse_corr_beta = -5700700,
> +	},
> +	{
> +		.base = 0x100,
> +		.calib_fuse_offset = 0x088,
> +		.fuse_corr_alpha = 1127000,
> +		.fuse_corr_beta = -6768200,
> +	},
> +	{
> +		.base = 0x120,
> +		.calib_fuse_offset = 0x12c,
> +		.fuse_corr_alpha = 1110900,
> +		.fuse_corr_beta = -6232000,
> +	},
> +	{
> +		.base = 0x140,
> +		.calib_fuse_offset = 0x158,
> +		.fuse_corr_alpha = 1122300,
> +		.fuse_corr_beta = -5936400,
> +	},
> +	{
> +		.base = 0x160,
> +		.calib_fuse_offset = 0x15c,
> +		.fuse_corr_alpha = 1145700,
> +		.fuse_corr_beta = -7124600,
> +	},
> +	{
> +		.base = 0x180,
> +		.calib_fuse_offset = 0x154,
> +		.fuse_corr_alpha = 1120100,
> +		.fuse_corr_beta = -6000500,
> +	},
> +	{
> +		.base = 0x1a0,
> +		.calib_fuse_offset = 0x160,
> +		.fuse_corr_alpha = 1106500,
> +		.fuse_corr_beta = -6729300,
> +	},
> +};
> +
> +struct tegra_soctherm {
> +	struct reset_control *reset;
> +	struct clk *clock_tsensor;
> +	struct clk *clock_soctherm;
> +	void __iomem *regs;
> +
> +	struct thermal_zone_device *thermctl_tzs[4];
> +};
> +
> +struct tsensor_shared_calibration {
> +	u32 base_cp, base_ft;
> +	u32 actual_temp_cp, actual_temp_ft;
> +};
> +
> +static int calculate_shared_calibration(struct tsensor_shared_calibration *r)
> +{
> +	u32 val;
> +	u32 shifted_cp, shifted_ft;
> +	int err;
> +
> +	err = tegra_fuse_readl(FUSE_TSENSOR8_CALIB, &val);
> +	if (err)
> +		return err;
> +	r->base_cp = val & FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK;
> +	r->base_ft = (val & FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK)
> +		>> FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT;
> +	val = ((val & FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK)
> +		>> FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT);
> +	shifted_ft = sign_extend32(val, 4);
> +
> +	err = tegra_fuse_readl(FUSE_SPARE_REALIGNMENT_REG_0, &val);
> +	if (err)
> +		return err;
> +	shifted_cp = sign_extend32(val, 5);
> +
> +	r->actual_temp_cp = 2 * NOMINAL_CALIB_CP_T124 + shifted_cp;
> +	r->actual_temp_ft = 2 * NOMINAL_CALIB_FT_T124 + shifted_ft;
> +
> +	return 0;
> +}
> +
> +static s64 div64_s64_precise(s64 a, s64 b)
> +{
> +	s64 r, al;
> +
> +	/* Scale up for increased precision division */
> +	al = a << 16;
> +
> +	r = div64_s64(al * 2 + 1, 2 * b);
> +	return r >> 16;
> +}
> +
> +static int calculate_tsensor_calibration(
> +	const struct tegra_tsensor *sensor,
> +	struct tsensor_shared_calibration shared,
> +	u32 *calib
> +)
> +{
> +	u32 val;
> +	s32 actual_tsensor_ft, actual_tsensor_cp;
> +	s32 delta_sens, delta_temp;
> +	s32 mult, div;
> +	s16 therma, thermb;
> +	int err;
> +
> +	err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
> +	if (err)
> +		return err;
> +
> +	actual_tsensor_cp = (shared.base_cp * 64) + sign_extend32(val, 12);
> +	val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK)
> +		>> FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
> +	actual_tsensor_ft = (shared.base_ft * 32) + sign_extend32(val, 12);
> +
> +	delta_sens = actual_tsensor_ft - actual_tsensor_cp;
> +	delta_temp = shared.actual_temp_ft - shared.actual_temp_cp;
> +
> +	mult = t124_tsensor_config.pdiv * t124_tsensor_config.tsample_ate;
> +	div = t124_tsensor_config.tsample * t124_tsensor_config.pdiv_ate;
> +
> +	therma = div64_s64_precise((s64) delta_temp * (1LL << 13) * mult,
> +		(s64) delta_sens * div);
> +	thermb = div64_s64_precise(
> +		((s64) actual_tsensor_ft * shared.actual_temp_cp) -
> +		((s64) actual_tsensor_cp * shared.actual_temp_ft),
> +		(s64) delta_sens);
> +
> +	therma = div64_s64_precise((s64) therma * sensor->fuse_corr_alpha,
> +		(s64) 1000000LL);
> +	thermb = div64_s64_precise((s64) thermb * sensor->fuse_corr_alpha +
> +		sensor->fuse_corr_beta,
> +		(s64) 1000000LL);
> +
> +	*calib = ((u16)(therma) << SENSOR_CONFIG2_THERMA_SHIFT) |
> +		((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
> +
> +	return 0;
> +}
> +
> +static int enable_tsensor(struct tegra_soctherm *tegra,
> +			  const struct tegra_tsensor *sensor,
> +			  struct tsensor_shared_calibration shared)
> +{
> +	void * __iomem base = tegra->regs + sensor->base;

I get sparse complaining about this declaration. For the sake of keeping
a clean static checks, can you please:
-       void * __iomem base = tegra->regs + sensor->base;
+       void __iomem * base = tegra->regs + sensor->base;


Can you also please check the remaining sparse errors?
  CHECK   drivers/thermal/tegra_soctherm.c
  drivers/thermal/tegra_soctherm.c:260:43: warning: incorrect type in
  initializer (different address spaces)
  drivers/thermal/tegra_soctherm.c:260:43:    expected void *[noderef]
  <asn:2>base
  drivers/thermal/tegra_soctherm.c:260:43:    got void [noderef]
  <asn:2>*
  drivers/thermal/tegra_soctherm.c:271:9: warning: incorrect type in
  argument 2 (different address spaces)
  drivers/thermal/tegra_soctherm.c:271:9:    expected void volatile
  [noderef] <asn:2>*addr
  drivers/thermal/tegra_soctherm.c:271:9:    got void *
  drivers/thermal/tegra_soctherm.c:279:9: warning: incorrect type in
  argument 2 (different address spaces)
  drivers/thermal/tegra_soctherm.c:279:9:    expected void volatile
  [noderef] <asn:2>*addr
  drivers/thermal/tegra_soctherm.c:279:9:    got void *
  drivers/thermal/tegra_soctherm.c:281:9: warning: incorrect type in
  argument 2 (different address spaces)
  drivers/thermal/tegra_soctherm.c:281:9:    expected void volatile
  [noderef] <asn:2>*addr
  drivers/thermal/tegra_soctherm.c:281:9:    got void *
  drivers/thermal/tegra_soctherm.c:347:25: warning: incorrect type in
  argument 1 (different address spaces)
  drivers/thermal/tegra_soctherm.c:347:25:    expected void const *ptr
  drivers/thermal/tegra_soctherm.c:347:25:    got void [noderef]
  <asn:2>*regs
  drivers/thermal/tegra_soctherm.c:349:37: warning: incorrect type in
  argument 1 (different address spaces)
  drivers/thermal/tegra_soctherm.c:349:37:    expected void const *ptr
  drivers/thermal/tegra_soctherm.c:349:37:    got void [noderef]
  <asn:2>*regs
  drivers/thermal/tegra_soctherm.c:271:9: warning: dereference of
  noderef expression
  drivers/thermal/tegra_soctherm.c:279:9: warning: dereference of
  noderef expression
  drivers/thermal/tegra_soctherm.c:281:9: warning: dereference of
  noderef expression

> +	unsigned int val;
> +	u32 calib;
> +	int err;
> +
> +	err = calculate_tsensor_calibration(sensor, shared, &calib);
> +	if (err)
> +		return err;
> +
> +	val = 0;
> +	val |= t124_tsensor_config.tall << SENSOR_CONFIG0_TALL_SHIFT;
> +	writel(val, base + SENSOR_CONFIG0);
> +
> +	val = 0;
> +	val |= (t124_tsensor_config.tsample - 1) <<
> +		SENSOR_CONFIG1_TSAMPLE_SHIFT;
> +	val |= t124_tsensor_config.tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
> +	val |= t124_tsensor_config.ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
> +	val |= SENSOR_CONFIG1_TEMP_ENABLE;
> +	writel(val, base + SENSOR_CONFIG1);
> +
> +	writel(calib, base + SENSOR_CONFIG2);
> +
> +	return 0;
> +}
> +
> +/* Translate from soctherm readback format to millicelsius.
> + * The soctherm readback format in bits is as follows:
> + *   TTTTTTTT H______N
> + * where T's contain the temperature in Celsius,
> + * H denotes an addition of 0.5 Celsius and N denotes negation
> + * of the final value.
> + */
> +static inline long translate_temp(u16 val)
> +{
> +	long t;
> +
> +	t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
> +	if (val & READBACK_ADD_HALF)
> +		t += 500;
> +	if (val & READBACK_NEGATE)
> +		t *= -1;
> +
> +	return t;
> +}
> +
> +static int tegra_thermctl_get_temp(void *data, long *out_temp)
> +{
> +	struct tegra_thermctl_zone *zone = data;
> +	u32 val;
> +
> +	val = (readl(zone->temp_reg) >> zone->temp_shift) & SENSOR_TEMP_MASK;
> +	*out_temp = translate_temp(val);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id tegra_soctherm_of_match[] = {
> +	{ .compatible = "nvidia,tegra124-soctherm" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
> +
> +static const int thermctl_temp_offsets[] = {
> +	SENSOR_TEMP1, SENSOR_TEMP2, SENSOR_TEMP1, SENSOR_TEMP2
> +};
> +
> +static const int thermctl_temp_shifts[] = {
> +	16, 16, 0, 0
> +};
> +
> +static int tegra_soctherm_probe(struct platform_device *pdev)
> +{
> +	struct tegra_soctherm *tegra;
> +	struct thermal_zone_device *tz;
> +	struct tsensor_shared_calibration shared_calib;
> +	int i;
> +	int err = 0;
> +
> +	const struct tegra_tsensor *tsensors = t124_tsensors;
> +
> +	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
> +	if (!tegra)
> +		return -ENOMEM;
> +
> +	tegra->regs = devm_ioremap_resource(&pdev->dev,
> +		platform_get_resource(pdev, IORESOURCE_MEM, 0));
> +	if (IS_ERR(tegra->regs)) {
> +		dev_err(&pdev->dev, "can't get registers");
> +		return PTR_ERR(tegra->regs);
> +	}
> +
> +	tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
> +	if (IS_ERR(tegra->reset)) {
> +		dev_err(&pdev->dev, "can't get soctherm reset\n");
> +		return PTR_ERR(tegra->reset);
> +	}
> +
> +	tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
> +	if (IS_ERR(tegra->clock_tsensor)) {
> +		dev_err(&pdev->dev, "can't get clock tsensor\n");
> +		return PTR_ERR(tegra->clock_tsensor);
> +	}
> +
> +	tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
> +	if (IS_ERR(tegra->clock_soctherm)) {
> +		dev_err(&pdev->dev, "can't get clock soctherm\n");
> +		return PTR_ERR(tegra->clock_soctherm);
> +	}
> +
> +	reset_control_assert(tegra->reset);
> +
> +	err = clk_prepare_enable(tegra->clock_soctherm);
> +	if (err) {
> +		reset_control_deassert(tegra->reset);
> +		return err;
> +	}
> +
> +	err = clk_prepare_enable(tegra->clock_tsensor);
> +	if (err) {
> +		clk_disable_unprepare(tegra->clock_soctherm);
> +		reset_control_deassert(tegra->reset);
> +		return err;
> +	}
> +
> +	reset_control_deassert(tegra->reset);
> +
> +	/* Initialize raw sensors */
> +
> +	err = calculate_shared_calibration(&shared_calib);
> +	if (err)
> +		goto disable_clocks;
> +
> +	for (i = 0; i < ARRAY_SIZE(t124_tsensors); ++i) {
> +		err = enable_tsensor(tegra, tsensors + i, shared_calib);
> +		if (err)
> +			goto disable_clocks;
> +	}
> +
> +	writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
> +	writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
> +
> +	/* Initialize thermctl sensors */
> +
> +	for (i = 0; i < ARRAY_SIZE(tegra->thermctl_tzs); ++i) {
> +		struct tegra_thermctl_zone *zone =
> +			devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
> +		if (!zone) {
> +			err = -ENOMEM;
> +			--i;
> +			goto unregister_tzs;
> +		}
> +
> +		zone->temp_reg = tegra->regs + thermctl_temp_offsets[i];
> +		zone->temp_shift = thermctl_temp_shifts[i];
> +
> +		tz = thermal_zone_of_sensor_register(
> +			&pdev->dev, i, zone, tegra_thermctl_get_temp, NULL);
> +		if (IS_ERR(tz)) {
> +			err = PTR_ERR(tz);
> +			dev_err(&pdev->dev, "failed to register sensor: %d\n",
> +				err);
> +			--i;
> +			goto unregister_tzs;
> +		}
> +
> +		tegra->thermctl_tzs[i] = tz;
> +	}
> +
> +	return 0;
> +
> +unregister_tzs:
> +	for (; i >= 0; i--)
> +		thermal_zone_of_sensor_unregister(&pdev->dev,
> +						  tegra->thermctl_tzs[i]);
> +
> +disable_clocks:
> +	clk_disable_unprepare(tegra->clock_tsensor);
> +	clk_disable_unprepare(tegra->clock_soctherm);
> +
> +	return err;
> +}
> +
> +static int tegra_soctherm_remove(struct platform_device *pdev)
> +{
> +	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(tegra->thermctl_tzs); ++i) {
> +		thermal_zone_of_sensor_unregister(&pdev->dev,
> +						  tegra->thermctl_tzs[i]);
> +	}
> +
> +	clk_disable_unprepare(tegra->clock_tsensor);
> +	clk_disable_unprepare(tegra->clock_soctherm);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver tegra_soctherm_driver = {
> +	.probe = tegra_soctherm_probe,
> +	.remove = tegra_soctherm_remove,
> +	.driver = {
> +		.name = "tegra_soctherm",
> +		.of_match_table = tegra_soctherm_of_match,
> +	},
> +};
> +module_platform_driver(tegra_soctherm_driver);
> +
> +MODULE_AUTHOR("Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>");
> +MODULE_DESCRIPTION("Tegra SOCTHERM thermal management driver");
> +MODULE_LICENSE("GPL v2");
> -- 
> 1.8.1.5
> 

[PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Eduardo Valentin]

Mikko,

On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
> This adds support for the Tegra SOCTHERM thermal sensing and management
> system found in the Tegra124 system-on-chip. This initial driver supports
> temperature polling for four thermal zones.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> ---
> v5:
> - changed tsample_ate to 480
> - constified structs
> - added missing --i
> - read shifted_ft from TSENSOR8 fuse
> - use precise divison function when calculating
>   calibration values
> 
>  drivers/thermal/Kconfig          |  10 +
>  drivers/thermal/Makefile         |   1 +
>  drivers/thermal/tegra_soctherm.c | 471 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 482 insertions(+)
>  create mode 100644 drivers/thermal/tegra_soctherm.c
> 
> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index 693208e..fd9d049 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -175,6 +175,16 @@ config ARMADA_THERMAL
>  	  Enable this option if you want to have support for thermal management
>  	  controller present in Armada 370 and Armada XP SoC.
>  
> +config TEGRA_SOCTHERM
> +	tristate "Tegra SOCTHERM thermal management"
> +	depends on ARCH_TEGRA
> +	help
> +	  Enable this option for integrated thermal management support on NVIDIA
> +	  Tegra124 systems-on-chip. The driver supports four thermal zones
> +	  (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
> +	  zones to manage temperatures. This option is also required for the
> +	  emergency thermal reset (thermtrip) feature to function.
> +
>  config DB8500_CPUFREQ_COOLING
>  	tristate "DB8500 cpufreq cooling"
>  	depends on ARCH_U8500
> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
> index 31e232f..f0b94d5 100644
> --- a/drivers/thermal/Makefile
> +++ b/drivers/thermal/Makefile
> @@ -33,3 +33,4 @@ obj-$(CONFIG_INTEL_SOC_DTS_THERMAL)	+= intel_soc_dts_thermal.o
>  obj-$(CONFIG_TI_SOC_THERMAL)	+= ti-soc-thermal/
>  obj-$(CONFIG_ACPI_INT3403_THERMAL)	+= int3403_thermal.o
>  obj-$(CONFIG_ST_THERMAL)	+= st/
> +obj-$(CONFIG_TEGRA_SOCTHERM)	+= tegra_soctherm.o
> diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
> new file mode 100644
> index 0000000..3742e24
> --- /dev/null
> +++ b/drivers/thermal/tegra_soctherm.c
> @@ -0,0 +1,471 @@
> +/*
> + * drivers/thermal/tegra_soctherm.c
> + *
> + * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
> + *
> + * Author:
> + *	Mikko Perttunen <mperttunen@nvidia.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include <linux/thermal.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/bitops.h>
> +#include <soc/tegra/fuse.h>
> +
> +#define SENSOR_CONFIG0				0
> +#define		SENSOR_CONFIG0_STOP		BIT(0)
> +#define		SENSOR_CONFIG0_TALL_SHIFT	8
> +#define		SENSOR_CONFIG0_TCALC_OVER	BIT(4)
> +#define		SENSOR_CONFIG0_OVER		BIT(3)
> +#define		SENSOR_CONFIG0_CPTR_OVER	BIT(2)
> +#define SENSOR_CONFIG1				4
> +#define		SENSOR_CONFIG1_TSAMPLE_SHIFT	0
> +#define		SENSOR_CONFIG1_TIDDQ_EN_SHIFT	15
> +#define		SENSOR_CONFIG1_TEN_COUNT_SHIFT	24
> +#define		SENSOR_CONFIG1_TEMP_ENABLE	BIT(31)
> +#define SENSOR_CONFIG2				8
> +#define		SENSOR_CONFIG2_THERMA_SHIFT	16
> +#define		SENSOR_CONFIG2_THERMB_SHIFT	0
> +
> +#define SENSOR_PDIV				0x1c0
> +#define		SENSOR_PDIV_T124		0x8888
> +#define SENSOR_HOTSPOT_OFF			0x1c4
> +#define		SENSOR_HOTSPOT_OFF_T124		0x00060600
> +#define SENSOR_TEMP1				0x1c8
> +#define SENSOR_TEMP2				0x1cc
> +
> +#define SENSOR_TEMP_MASK			0xffff
> +#define READBACK_VALUE_MASK			0xff00
> +#define READBACK_VALUE_SHIFT			8
> +#define READBACK_ADD_HALF			BIT(7)
> +#define READBACK_NEGATE				BIT(1)
> +
> +#define FUSE_TSENSOR8_CALIB			0x180
> +#define FUSE_SPARE_REALIGNMENT_REG_0		0x1fc
> +
> +#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK	0x1fff
> +#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK	(0x1fff << 13)
> +#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT	13
> +
> +#define FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK	0x3ff
> +#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK	(0x7ff << 10)
> +#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT	10
> +
> +#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_MASK 0x3f
> +#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK (0x1f << 21)
> +#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT 21
> +
> +#define NOMINAL_CALIB_FT_T124			105
> +#define NOMINAL_CALIB_CP_T124			25
> +
> +struct tegra_tsensor_configuration {
> +	u32 tall, tsample, tiddq_en, ten_count;
> +	u32 pdiv, tsample_ate, pdiv_ate;
> +};
> +
> +struct tegra_tsensor {
> +	u32 base;
> +	u32 calib_fuse_offset;
> +	/* Correction values used to modify values read from calibration fuses */
> +	s32 fuse_corr_alpha, fuse_corr_beta;
> +};
> +
> +struct tegra_thermctl_zone {
> +	void __iomem *temp_reg;
> +	int temp_shift;
> +};
> +
> +static const struct tegra_tsensor_configuration t124_tsensor_config = {
> +	.tall = 16300,
> +	.tsample = 120,
> +	.tiddq_en = 1,
> +	.ten_count = 1,
> +	.pdiv = 8,
> +	.tsample_ate = 480,
> +	.pdiv_ate = 8
> +};
> +
> +static const struct tegra_tsensor t124_tsensors[] = {
> +	{
> +		.base = 0xc0,
> +		.calib_fuse_offset = 0x098,
> +		.fuse_corr_alpha = 1135400,
> +		.fuse_corr_beta = -6266900,
> +	},
> +	{
> +		.base = 0xe0,
> +		.calib_fuse_offset = 0x084,
> +		.fuse_corr_alpha = 1122220,
> +		.fuse_corr_beta = -5700700,
> +	},
> +	{
> +		.base = 0x100,
> +		.calib_fuse_offset = 0x088,
> +		.fuse_corr_alpha = 1127000,
> +		.fuse_corr_beta = -6768200,
> +	},
> +	{
> +		.base = 0x120,
> +		.calib_fuse_offset = 0x12c,
> +		.fuse_corr_alpha = 1110900,
> +		.fuse_corr_beta = -6232000,
> +	},
> +	{
> +		.base = 0x140,
> +		.calib_fuse_offset = 0x158,
> +		.fuse_corr_alpha = 1122300,
> +		.fuse_corr_beta = -5936400,
> +	},
> +	{
> +		.base = 0x160,
> +		.calib_fuse_offset = 0x15c,
> +		.fuse_corr_alpha = 1145700,
> +		.fuse_corr_beta = -7124600,
> +	},
> +	{
> +		.base = 0x180,
> +		.calib_fuse_offset = 0x154,
> +		.fuse_corr_alpha = 1120100,
> +		.fuse_corr_beta = -6000500,
> +	},
> +	{
> +		.base = 0x1a0,
> +		.calib_fuse_offset = 0x160,
> +		.fuse_corr_alpha = 1106500,
> +		.fuse_corr_beta = -6729300,
> +	},
> +};
> +
> +struct tegra_soctherm {
> +	struct reset_control *reset;
> +	struct clk *clock_tsensor;
> +	struct clk *clock_soctherm;
> +	void __iomem *regs;
> +
> +	struct thermal_zone_device *thermctl_tzs[4];
> +};
> +
> +struct tsensor_shared_calibration {
> +	u32 base_cp, base_ft;
> +	u32 actual_temp_cp, actual_temp_ft;
> +};
> +
> +static int calculate_shared_calibration(struct tsensor_shared_calibration *r)
> +{
> +	u32 val;
> +	u32 shifted_cp, shifted_ft;
> +	int err;
> +
> +	err = tegra_fuse_readl(FUSE_TSENSOR8_CALIB, &val);
> +	if (err)
> +		return err;
> +	r->base_cp = val & FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK;
> +	r->base_ft = (val & FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK)
> +		>> FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT;
> +	val = ((val & FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK)
> +		>> FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT);
> +	shifted_ft = sign_extend32(val, 4);
> +
> +	err = tegra_fuse_readl(FUSE_SPARE_REALIGNMENT_REG_0, &val);
> +	if (err)
> +		return err;
> +	shifted_cp = sign_extend32(val, 5);
> +
> +	r->actual_temp_cp = 2 * NOMINAL_CALIB_CP_T124 + shifted_cp;
> +	r->actual_temp_ft = 2 * NOMINAL_CALIB_FT_T124 + shifted_ft;
> +
> +	return 0;
> +}
> +
> +static s64 div64_s64_precise(s64 a, s64 b)
> +{
> +	s64 r, al;
> +
> +	/* Scale up for increased precision division */
> +	al = a << 16;
> +
> +	r = div64_s64(al * 2 + 1, 2 * b);
> +	return r >> 16;
> +}
> +
> +static int calculate_tsensor_calibration(
> +	const struct tegra_tsensor *sensor,
> +	struct tsensor_shared_calibration shared,
> +	u32 *calib
> +)
> +{
> +	u32 val;
> +	s32 actual_tsensor_ft, actual_tsensor_cp;
> +	s32 delta_sens, delta_temp;
> +	s32 mult, div;
> +	s16 therma, thermb;
> +	int err;
> +
> +	err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
> +	if (err)
> +		return err;
> +
> +	actual_tsensor_cp = (shared.base_cp * 64) + sign_extend32(val, 12);
> +	val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK)
> +		>> FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
> +	actual_tsensor_ft = (shared.base_ft * 32) + sign_extend32(val, 12);
> +
> +	delta_sens = actual_tsensor_ft - actual_tsensor_cp;
> +	delta_temp = shared.actual_temp_ft - shared.actual_temp_cp;
> +
> +	mult = t124_tsensor_config.pdiv * t124_tsensor_config.tsample_ate;
> +	div = t124_tsensor_config.tsample * t124_tsensor_config.pdiv_ate;
> +
> +	therma = div64_s64_precise((s64) delta_temp * (1LL << 13) * mult,
> +		(s64) delta_sens * div);
> +	thermb = div64_s64_precise(
> +		((s64) actual_tsensor_ft * shared.actual_temp_cp) -
> +		((s64) actual_tsensor_cp * shared.actual_temp_ft),
> +		(s64) delta_sens);
> +
> +	therma = div64_s64_precise((s64) therma * sensor->fuse_corr_alpha,
> +		(s64) 1000000LL);
> +	thermb = div64_s64_precise((s64) thermb * sensor->fuse_corr_alpha +
> +		sensor->fuse_corr_beta,
> +		(s64) 1000000LL);
> +
> +	*calib = ((u16)(therma) << SENSOR_CONFIG2_THERMA_SHIFT) |
> +		((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
> +
> +	return 0;
> +}
> +
> +static int enable_tsensor(struct tegra_soctherm *tegra,
> +			  const struct tegra_tsensor *sensor,
> +			  struct tsensor_shared_calibration shared)
> +{
> +	void * __iomem base = tegra->regs + sensor->base;

I get sparse complaining about this declaration. For the sake of keeping
a clean static checks, can you please:
-       void * __iomem base = tegra->regs + sensor->base;
+       void __iomem * base = tegra->regs + sensor->base;


Can you also please check the remaining sparse errors?
  CHECK   drivers/thermal/tegra_soctherm.c
  drivers/thermal/tegra_soctherm.c:260:43: warning: incorrect type in
  initializer (different address spaces)
  drivers/thermal/tegra_soctherm.c:260:43:    expected void *[noderef]
  <asn:2>base
  drivers/thermal/tegra_soctherm.c:260:43:    got void [noderef]
  <asn:2>*
  drivers/thermal/tegra_soctherm.c:271:9: warning: incorrect type in
  argument 2 (different address spaces)
  drivers/thermal/tegra_soctherm.c:271:9:    expected void volatile
  [noderef] <asn:2>*addr
  drivers/thermal/tegra_soctherm.c:271:9:    got void *
  drivers/thermal/tegra_soctherm.c:279:9: warning: incorrect type in
  argument 2 (different address spaces)
  drivers/thermal/tegra_soctherm.c:279:9:    expected void volatile
  [noderef] <asn:2>*addr
  drivers/thermal/tegra_soctherm.c:279:9:    got void *
  drivers/thermal/tegra_soctherm.c:281:9: warning: incorrect type in
  argument 2 (different address spaces)
  drivers/thermal/tegra_soctherm.c:281:9:    expected void volatile
  [noderef] <asn:2>*addr
  drivers/thermal/tegra_soctherm.c:281:9:    got void *
  drivers/thermal/tegra_soctherm.c:347:25: warning: incorrect type in
  argument 1 (different address spaces)
  drivers/thermal/tegra_soctherm.c:347:25:    expected void const *ptr
  drivers/thermal/tegra_soctherm.c:347:25:    got void [noderef]
  <asn:2>*regs
  drivers/thermal/tegra_soctherm.c:349:37: warning: incorrect type in
  argument 1 (different address spaces)
  drivers/thermal/tegra_soctherm.c:349:37:    expected void const *ptr
  drivers/thermal/tegra_soctherm.c:349:37:    got void [noderef]
  <asn:2>*regs
  drivers/thermal/tegra_soctherm.c:271:9: warning: dereference of
  noderef expression
  drivers/thermal/tegra_soctherm.c:279:9: warning: dereference of
  noderef expression
  drivers/thermal/tegra_soctherm.c:281:9: warning: dereference of
  noderef expression

> +	unsigned int val;
> +	u32 calib;
> +	int err;
> +
> +	err = calculate_tsensor_calibration(sensor, shared, &calib);
> +	if (err)
> +		return err;
> +
> +	val = 0;
> +	val |= t124_tsensor_config.tall << SENSOR_CONFIG0_TALL_SHIFT;
> +	writel(val, base + SENSOR_CONFIG0);
> +
> +	val = 0;
> +	val |= (t124_tsensor_config.tsample - 1) <<
> +		SENSOR_CONFIG1_TSAMPLE_SHIFT;
> +	val |= t124_tsensor_config.tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
> +	val |= t124_tsensor_config.ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
> +	val |= SENSOR_CONFIG1_TEMP_ENABLE;
> +	writel(val, base + SENSOR_CONFIG1);
> +
> +	writel(calib, base + SENSOR_CONFIG2);
> +
> +	return 0;
> +}
> +
> +/* Translate from soctherm readback format to millicelsius.
> + * The soctherm readback format in bits is as follows:
> + *   TTTTTTTT H______N
> + * where T's contain the temperature in Celsius,
> + * H denotes an addition of 0.5 Celsius and N denotes negation
> + * of the final value.
> + */
> +static inline long translate_temp(u16 val)
> +{
> +	long t;
> +
> +	t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
> +	if (val & READBACK_ADD_HALF)
> +		t += 500;
> +	if (val & READBACK_NEGATE)
> +		t *= -1;
> +
> +	return t;
> +}
> +
> +static int tegra_thermctl_get_temp(void *data, long *out_temp)
> +{
> +	struct tegra_thermctl_zone *zone = data;
> +	u32 val;
> +
> +	val = (readl(zone->temp_reg) >> zone->temp_shift) & SENSOR_TEMP_MASK;
> +	*out_temp = translate_temp(val);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id tegra_soctherm_of_match[] = {
> +	{ .compatible = "nvidia,tegra124-soctherm" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
> +
> +static const int thermctl_temp_offsets[] = {
> +	SENSOR_TEMP1, SENSOR_TEMP2, SENSOR_TEMP1, SENSOR_TEMP2
> +};
> +
> +static const int thermctl_temp_shifts[] = {
> +	16, 16, 0, 0
> +};
> +
> +static int tegra_soctherm_probe(struct platform_device *pdev)
> +{
> +	struct tegra_soctherm *tegra;
> +	struct thermal_zone_device *tz;
> +	struct tsensor_shared_calibration shared_calib;
> +	int i;
> +	int err = 0;
> +
> +	const struct tegra_tsensor *tsensors = t124_tsensors;
> +
> +	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
> +	if (!tegra)
> +		return -ENOMEM;
> +
> +	tegra->regs = devm_ioremap_resource(&pdev->dev,
> +		platform_get_resource(pdev, IORESOURCE_MEM, 0));
> +	if (IS_ERR(tegra->regs)) {
> +		dev_err(&pdev->dev, "can't get registers");
> +		return PTR_ERR(tegra->regs);
> +	}
> +
> +	tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
> +	if (IS_ERR(tegra->reset)) {
> +		dev_err(&pdev->dev, "can't get soctherm reset\n");
> +		return PTR_ERR(tegra->reset);
> +	}
> +
> +	tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
> +	if (IS_ERR(tegra->clock_tsensor)) {
> +		dev_err(&pdev->dev, "can't get clock tsensor\n");
> +		return PTR_ERR(tegra->clock_tsensor);
> +	}
> +
> +	tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
> +	if (IS_ERR(tegra->clock_soctherm)) {
> +		dev_err(&pdev->dev, "can't get clock soctherm\n");
> +		return PTR_ERR(tegra->clock_soctherm);
> +	}
> +
> +	reset_control_assert(tegra->reset);
> +
> +	err = clk_prepare_enable(tegra->clock_soctherm);
> +	if (err) {
> +		reset_control_deassert(tegra->reset);
> +		return err;
> +	}
> +
> +	err = clk_prepare_enable(tegra->clock_tsensor);
> +	if (err) {
> +		clk_disable_unprepare(tegra->clock_soctherm);
> +		reset_control_deassert(tegra->reset);
> +		return err;
> +	}
> +
> +	reset_control_deassert(tegra->reset);
> +
> +	/* Initialize raw sensors */
> +
> +	err = calculate_shared_calibration(&shared_calib);
> +	if (err)
> +		goto disable_clocks;
> +
> +	for (i = 0; i < ARRAY_SIZE(t124_tsensors); ++i) {
> +		err = enable_tsensor(tegra, tsensors + i, shared_calib);
> +		if (err)
> +			goto disable_clocks;
> +	}
> +
> +	writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
> +	writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
> +
> +	/* Initialize thermctl sensors */
> +
> +	for (i = 0; i < ARRAY_SIZE(tegra->thermctl_tzs); ++i) {
> +		struct tegra_thermctl_zone *zone =
> +			devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
> +		if (!zone) {
> +			err = -ENOMEM;
> +			--i;
> +			goto unregister_tzs;
> +		}
> +
> +		zone->temp_reg = tegra->regs + thermctl_temp_offsets[i];
> +		zone->temp_shift = thermctl_temp_shifts[i];
> +
> +		tz = thermal_zone_of_sensor_register(
> +			&pdev->dev, i, zone, tegra_thermctl_get_temp, NULL);
> +		if (IS_ERR(tz)) {
> +			err = PTR_ERR(tz);
> +			dev_err(&pdev->dev, "failed to register sensor: %d\n",
> +				err);
> +			--i;
> +			goto unregister_tzs;
> +		}
> +
> +		tegra->thermctl_tzs[i] = tz;
> +	}
> +
> +	return 0;
> +
> +unregister_tzs:
> +	for (; i >= 0; i--)
> +		thermal_zone_of_sensor_unregister(&pdev->dev,
> +						  tegra->thermctl_tzs[i]);
> +
> +disable_clocks:
> +	clk_disable_unprepare(tegra->clock_tsensor);
> +	clk_disable_unprepare(tegra->clock_soctherm);
> +
> +	return err;
> +}
> +
> +static int tegra_soctherm_remove(struct platform_device *pdev)
> +{
> +	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(tegra->thermctl_tzs); ++i) {
> +		thermal_zone_of_sensor_unregister(&pdev->dev,
> +						  tegra->thermctl_tzs[i]);
> +	}
> +
> +	clk_disable_unprepare(tegra->clock_tsensor);
> +	clk_disable_unprepare(tegra->clock_soctherm);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver tegra_soctherm_driver = {
> +	.probe = tegra_soctherm_probe,
> +	.remove = tegra_soctherm_remove,
> +	.driver = {
> +		.name = "tegra_soctherm",
> +		.of_match_table = tegra_soctherm_of_match,
> +	},
> +};
> +module_platform_driver(tegra_soctherm_driver);
> +
> +MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
> +MODULE_DESCRIPTION("Tegra SOCTHERM thermal management driver");
> +MODULE_LICENSE("GPL v2");
> -- 
> 1.8.1.5
> 

Re: [PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Eduardo Valentin]

Mikko,

On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
> This adds support for the Tegra SOCTHERM thermal sensing and management
> system found in the Tegra124 system-on-chip. This initial driver supports
> temperature polling for four thermal zones.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> ---
> v5:
> - changed tsample_ate to 480
> - constified structs
> - added missing --i
> - read shifted_ft from TSENSOR8 fuse
> - use precise divison function when calculating
>   calibration values
> 
>  drivers/thermal/Kconfig          |  10 +
>  drivers/thermal/Makefile         |   1 +
>  drivers/thermal/tegra_soctherm.c | 471 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 482 insertions(+)
>  create mode 100644 drivers/thermal/tegra_soctherm.c
> 
> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index 693208e..fd9d049 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -175,6 +175,16 @@ config ARMADA_THERMAL
>  	  Enable this option if you want to have support for thermal management
>  	  controller present in Armada 370 and Armada XP SoC.
>  
> +config TEGRA_SOCTHERM
> +	tristate "Tegra SOCTHERM thermal management"
> +	depends on ARCH_TEGRA
> +	help
> +	  Enable this option for integrated thermal management support on NVIDIA
> +	  Tegra124 systems-on-chip. The driver supports four thermal zones
> +	  (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
> +	  zones to manage temperatures. This option is also required for the
> +	  emergency thermal reset (thermtrip) feature to function.
> +
>  config DB8500_CPUFREQ_COOLING
>  	tristate "DB8500 cpufreq cooling"
>  	depends on ARCH_U8500
> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
> index 31e232f..f0b94d5 100644
> --- a/drivers/thermal/Makefile
> +++ b/drivers/thermal/Makefile
> @@ -33,3 +33,4 @@ obj-$(CONFIG_INTEL_SOC_DTS_THERMAL)	+= intel_soc_dts_thermal.o
>  obj-$(CONFIG_TI_SOC_THERMAL)	+= ti-soc-thermal/
>  obj-$(CONFIG_ACPI_INT3403_THERMAL)	+= int3403_thermal.o
>  obj-$(CONFIG_ST_THERMAL)	+= st/
> +obj-$(CONFIG_TEGRA_SOCTHERM)	+= tegra_soctherm.o
> diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
> new file mode 100644
> index 0000000..3742e24
> --- /dev/null
> +++ b/drivers/thermal/tegra_soctherm.c
> @@ -0,0 +1,471 @@
> +/*
> + * drivers/thermal/tegra_soctherm.c
> + *
> + * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
> + *
> + * Author:
> + *	Mikko Perttunen <mperttunen@nvidia.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include <linux/thermal.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/bitops.h>
> +#include <soc/tegra/fuse.h>
> +
> +#define SENSOR_CONFIG0				0
> +#define		SENSOR_CONFIG0_STOP		BIT(0)
> +#define		SENSOR_CONFIG0_TALL_SHIFT	8
> +#define		SENSOR_CONFIG0_TCALC_OVER	BIT(4)
> +#define		SENSOR_CONFIG0_OVER		BIT(3)
> +#define		SENSOR_CONFIG0_CPTR_OVER	BIT(2)
> +#define SENSOR_CONFIG1				4
> +#define		SENSOR_CONFIG1_TSAMPLE_SHIFT	0
> +#define		SENSOR_CONFIG1_TIDDQ_EN_SHIFT	15
> +#define		SENSOR_CONFIG1_TEN_COUNT_SHIFT	24
> +#define		SENSOR_CONFIG1_TEMP_ENABLE	BIT(31)
> +#define SENSOR_CONFIG2				8
> +#define		SENSOR_CONFIG2_THERMA_SHIFT	16
> +#define		SENSOR_CONFIG2_THERMB_SHIFT	0
> +
> +#define SENSOR_PDIV				0x1c0
> +#define		SENSOR_PDIV_T124		0x8888
> +#define SENSOR_HOTSPOT_OFF			0x1c4
> +#define		SENSOR_HOTSPOT_OFF_T124		0x00060600
> +#define SENSOR_TEMP1				0x1c8
> +#define SENSOR_TEMP2				0x1cc
> +
> +#define SENSOR_TEMP_MASK			0xffff
> +#define READBACK_VALUE_MASK			0xff00
> +#define READBACK_VALUE_SHIFT			8
> +#define READBACK_ADD_HALF			BIT(7)
> +#define READBACK_NEGATE				BIT(1)
> +
> +#define FUSE_TSENSOR8_CALIB			0x180
> +#define FUSE_SPARE_REALIGNMENT_REG_0		0x1fc
> +
> +#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK	0x1fff
> +#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK	(0x1fff << 13)
> +#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT	13
> +
> +#define FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK	0x3ff
> +#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK	(0x7ff << 10)
> +#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT	10
> +
> +#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_MASK 0x3f
> +#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK (0x1f << 21)
> +#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT 21
> +
> +#define NOMINAL_CALIB_FT_T124			105
> +#define NOMINAL_CALIB_CP_T124			25
> +
> +struct tegra_tsensor_configuration {
> +	u32 tall, tsample, tiddq_en, ten_count;
> +	u32 pdiv, tsample_ate, pdiv_ate;
> +};
> +
> +struct tegra_tsensor {
> +	u32 base;
> +	u32 calib_fuse_offset;
> +	/* Correction values used to modify values read from calibration fuses */
> +	s32 fuse_corr_alpha, fuse_corr_beta;
> +};
> +
> +struct tegra_thermctl_zone {
> +	void __iomem *temp_reg;
> +	int temp_shift;
> +};
> +
> +static const struct tegra_tsensor_configuration t124_tsensor_config = {
> +	.tall = 16300,
> +	.tsample = 120,
> +	.tiddq_en = 1,
> +	.ten_count = 1,
> +	.pdiv = 8,
> +	.tsample_ate = 480,
> +	.pdiv_ate = 8
> +};
> +
> +static const struct tegra_tsensor t124_tsensors[] = {
> +	{
> +		.base = 0xc0,
> +		.calib_fuse_offset = 0x098,
> +		.fuse_corr_alpha = 1135400,
> +		.fuse_corr_beta = -6266900,
> +	},
> +	{
> +		.base = 0xe0,
> +		.calib_fuse_offset = 0x084,
> +		.fuse_corr_alpha = 1122220,
> +		.fuse_corr_beta = -5700700,
> +	},
> +	{
> +		.base = 0x100,
> +		.calib_fuse_offset = 0x088,
> +		.fuse_corr_alpha = 1127000,
> +		.fuse_corr_beta = -6768200,
> +	},
> +	{
> +		.base = 0x120,
> +		.calib_fuse_offset = 0x12c,
> +		.fuse_corr_alpha = 1110900,
> +		.fuse_corr_beta = -6232000,
> +	},
> +	{
> +		.base = 0x140,
> +		.calib_fuse_offset = 0x158,
> +		.fuse_corr_alpha = 1122300,
> +		.fuse_corr_beta = -5936400,
> +	},
> +	{
> +		.base = 0x160,
> +		.calib_fuse_offset = 0x15c,
> +		.fuse_corr_alpha = 1145700,
> +		.fuse_corr_beta = -7124600,
> +	},
> +	{
> +		.base = 0x180,
> +		.calib_fuse_offset = 0x154,
> +		.fuse_corr_alpha = 1120100,
> +		.fuse_corr_beta = -6000500,
> +	},
> +	{
> +		.base = 0x1a0,
> +		.calib_fuse_offset = 0x160,
> +		.fuse_corr_alpha = 1106500,
> +		.fuse_corr_beta = -6729300,
> +	},
> +};
> +
> +struct tegra_soctherm {
> +	struct reset_control *reset;
> +	struct clk *clock_tsensor;
> +	struct clk *clock_soctherm;
> +	void __iomem *regs;
> +
> +	struct thermal_zone_device *thermctl_tzs[4];
> +};
> +
> +struct tsensor_shared_calibration {
> +	u32 base_cp, base_ft;
> +	u32 actual_temp_cp, actual_temp_ft;
> +};
> +
> +static int calculate_shared_calibration(struct tsensor_shared_calibration *r)
> +{
> +	u32 val;
> +	u32 shifted_cp, shifted_ft;
> +	int err;
> +
> +	err = tegra_fuse_readl(FUSE_TSENSOR8_CALIB, &val);
> +	if (err)
> +		return err;
> +	r->base_cp = val & FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK;
> +	r->base_ft = (val & FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK)
> +		>> FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT;
> +	val = ((val & FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK)
> +		>> FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT);
> +	shifted_ft = sign_extend32(val, 4);
> +
> +	err = tegra_fuse_readl(FUSE_SPARE_REALIGNMENT_REG_0, &val);
> +	if (err)
> +		return err;
> +	shifted_cp = sign_extend32(val, 5);
> +
> +	r->actual_temp_cp = 2 * NOMINAL_CALIB_CP_T124 + shifted_cp;
> +	r->actual_temp_ft = 2 * NOMINAL_CALIB_FT_T124 + shifted_ft;
> +
> +	return 0;
> +}
> +
> +static s64 div64_s64_precise(s64 a, s64 b)
> +{
> +	s64 r, al;
> +
> +	/* Scale up for increased precision division */
> +	al = a << 16;
> +
> +	r = div64_s64(al * 2 + 1, 2 * b);
> +	return r >> 16;
> +}
> +
> +static int calculate_tsensor_calibration(
> +	const struct tegra_tsensor *sensor,
> +	struct tsensor_shared_calibration shared,
> +	u32 *calib
> +)
> +{
> +	u32 val;
> +	s32 actual_tsensor_ft, actual_tsensor_cp;
> +	s32 delta_sens, delta_temp;
> +	s32 mult, div;
> +	s16 therma, thermb;
> +	int err;
> +
> +	err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
> +	if (err)
> +		return err;
> +
> +	actual_tsensor_cp = (shared.base_cp * 64) + sign_extend32(val, 12);
> +	val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK)
> +		>> FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
> +	actual_tsensor_ft = (shared.base_ft * 32) + sign_extend32(val, 12);
> +
> +	delta_sens = actual_tsensor_ft - actual_tsensor_cp;
> +	delta_temp = shared.actual_temp_ft - shared.actual_temp_cp;
> +
> +	mult = t124_tsensor_config.pdiv * t124_tsensor_config.tsample_ate;
> +	div = t124_tsensor_config.tsample * t124_tsensor_config.pdiv_ate;
> +
> +	therma = div64_s64_precise((s64) delta_temp * (1LL << 13) * mult,
> +		(s64) delta_sens * div);
> +	thermb = div64_s64_precise(
> +		((s64) actual_tsensor_ft * shared.actual_temp_cp) -
> +		((s64) actual_tsensor_cp * shared.actual_temp_ft),
> +		(s64) delta_sens);
> +
> +	therma = div64_s64_precise((s64) therma * sensor->fuse_corr_alpha,
> +		(s64) 1000000LL);
> +	thermb = div64_s64_precise((s64) thermb * sensor->fuse_corr_alpha +
> +		sensor->fuse_corr_beta,
> +		(s64) 1000000LL);
> +
> +	*calib = ((u16)(therma) << SENSOR_CONFIG2_THERMA_SHIFT) |
> +		((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
> +
> +	return 0;
> +}
> +
> +static int enable_tsensor(struct tegra_soctherm *tegra,
> +			  const struct tegra_tsensor *sensor,
> +			  struct tsensor_shared_calibration shared)
> +{
> +	void * __iomem base = tegra->regs + sensor->base;

I get sparse complaining about this declaration. For the sake of keeping
a clean static checks, can you please:
-       void * __iomem base = tegra->regs + sensor->base;
+       void __iomem * base = tegra->regs + sensor->base;


Can you also please check the remaining sparse errors?
  CHECK   drivers/thermal/tegra_soctherm.c
  drivers/thermal/tegra_soctherm.c:260:43: warning: incorrect type in
  initializer (different address spaces)
  drivers/thermal/tegra_soctherm.c:260:43:    expected void *[noderef]
  <asn:2>base
  drivers/thermal/tegra_soctherm.c:260:43:    got void [noderef]
  <asn:2>*
  drivers/thermal/tegra_soctherm.c:271:9: warning: incorrect type in
  argument 2 (different address spaces)
  drivers/thermal/tegra_soctherm.c:271:9:    expected void volatile
  [noderef] <asn:2>*addr
  drivers/thermal/tegra_soctherm.c:271:9:    got void *
  drivers/thermal/tegra_soctherm.c:279:9: warning: incorrect type in
  argument 2 (different address spaces)
  drivers/thermal/tegra_soctherm.c:279:9:    expected void volatile
  [noderef] <asn:2>*addr
  drivers/thermal/tegra_soctherm.c:279:9:    got void *
  drivers/thermal/tegra_soctherm.c:281:9: warning: incorrect type in
  argument 2 (different address spaces)
  drivers/thermal/tegra_soctherm.c:281:9:    expected void volatile
  [noderef] <asn:2>*addr
  drivers/thermal/tegra_soctherm.c:281:9:    got void *
  drivers/thermal/tegra_soctherm.c:347:25: warning: incorrect type in
  argument 1 (different address spaces)
  drivers/thermal/tegra_soctherm.c:347:25:    expected void const *ptr
  drivers/thermal/tegra_soctherm.c:347:25:    got void [noderef]
  <asn:2>*regs
  drivers/thermal/tegra_soctherm.c:349:37: warning: incorrect type in
  argument 1 (different address spaces)
  drivers/thermal/tegra_soctherm.c:349:37:    expected void const *ptr
  drivers/thermal/tegra_soctherm.c:349:37:    got void [noderef]
  <asn:2>*regs
  drivers/thermal/tegra_soctherm.c:271:9: warning: dereference of
  noderef expression
  drivers/thermal/tegra_soctherm.c:279:9: warning: dereference of
  noderef expression
  drivers/thermal/tegra_soctherm.c:281:9: warning: dereference of
  noderef expression

> +	unsigned int val;
> +	u32 calib;
> +	int err;
> +
> +	err = calculate_tsensor_calibration(sensor, shared, &calib);
> +	if (err)
> +		return err;
> +
> +	val = 0;
> +	val |= t124_tsensor_config.tall << SENSOR_CONFIG0_TALL_SHIFT;
> +	writel(val, base + SENSOR_CONFIG0);
> +
> +	val = 0;
> +	val |= (t124_tsensor_config.tsample - 1) <<
> +		SENSOR_CONFIG1_TSAMPLE_SHIFT;
> +	val |= t124_tsensor_config.tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
> +	val |= t124_tsensor_config.ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
> +	val |= SENSOR_CONFIG1_TEMP_ENABLE;
> +	writel(val, base + SENSOR_CONFIG1);
> +
> +	writel(calib, base + SENSOR_CONFIG2);
> +
> +	return 0;
> +}
> +
> +/* Translate from soctherm readback format to millicelsius.
> + * The soctherm readback format in bits is as follows:
> + *   TTTTTTTT H______N
> + * where T's contain the temperature in Celsius,
> + * H denotes an addition of 0.5 Celsius and N denotes negation
> + * of the final value.
> + */
> +static inline long translate_temp(u16 val)
> +{
> +	long t;
> +
> +	t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
> +	if (val & READBACK_ADD_HALF)
> +		t += 500;
> +	if (val & READBACK_NEGATE)
> +		t *= -1;
> +
> +	return t;
> +}
> +
> +static int tegra_thermctl_get_temp(void *data, long *out_temp)
> +{
> +	struct tegra_thermctl_zone *zone = data;
> +	u32 val;
> +
> +	val = (readl(zone->temp_reg) >> zone->temp_shift) & SENSOR_TEMP_MASK;
> +	*out_temp = translate_temp(val);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id tegra_soctherm_of_match[] = {
> +	{ .compatible = "nvidia,tegra124-soctherm" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
> +
> +static const int thermctl_temp_offsets[] = {
> +	SENSOR_TEMP1, SENSOR_TEMP2, SENSOR_TEMP1, SENSOR_TEMP2
> +};
> +
> +static const int thermctl_temp_shifts[] = {
> +	16, 16, 0, 0
> +};
> +
> +static int tegra_soctherm_probe(struct platform_device *pdev)
> +{
> +	struct tegra_soctherm *tegra;
> +	struct thermal_zone_device *tz;
> +	struct tsensor_shared_calibration shared_calib;
> +	int i;
> +	int err = 0;
> +
> +	const struct tegra_tsensor *tsensors = t124_tsensors;
> +
> +	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
> +	if (!tegra)
> +		return -ENOMEM;
> +
> +	tegra->regs = devm_ioremap_resource(&pdev->dev,
> +		platform_get_resource(pdev, IORESOURCE_MEM, 0));
> +	if (IS_ERR(tegra->regs)) {
> +		dev_err(&pdev->dev, "can't get registers");
> +		return PTR_ERR(tegra->regs);
> +	}
> +
> +	tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
> +	if (IS_ERR(tegra->reset)) {
> +		dev_err(&pdev->dev, "can't get soctherm reset\n");
> +		return PTR_ERR(tegra->reset);
> +	}
> +
> +	tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
> +	if (IS_ERR(tegra->clock_tsensor)) {
> +		dev_err(&pdev->dev, "can't get clock tsensor\n");
> +		return PTR_ERR(tegra->clock_tsensor);
> +	}
> +
> +	tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
> +	if (IS_ERR(tegra->clock_soctherm)) {
> +		dev_err(&pdev->dev, "can't get clock soctherm\n");
> +		return PTR_ERR(tegra->clock_soctherm);
> +	}
> +
> +	reset_control_assert(tegra->reset);
> +
> +	err = clk_prepare_enable(tegra->clock_soctherm);
> +	if (err) {
> +		reset_control_deassert(tegra->reset);
> +		return err;
> +	}
> +
> +	err = clk_prepare_enable(tegra->clock_tsensor);
> +	if (err) {
> +		clk_disable_unprepare(tegra->clock_soctherm);
> +		reset_control_deassert(tegra->reset);
> +		return err;
> +	}
> +
> +	reset_control_deassert(tegra->reset);
> +
> +	/* Initialize raw sensors */
> +
> +	err = calculate_shared_calibration(&shared_calib);
> +	if (err)
> +		goto disable_clocks;
> +
> +	for (i = 0; i < ARRAY_SIZE(t124_tsensors); ++i) {
> +		err = enable_tsensor(tegra, tsensors + i, shared_calib);
> +		if (err)
> +			goto disable_clocks;
> +	}
> +
> +	writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
> +	writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
> +
> +	/* Initialize thermctl sensors */
> +
> +	for (i = 0; i < ARRAY_SIZE(tegra->thermctl_tzs); ++i) {
> +		struct tegra_thermctl_zone *zone =
> +			devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
> +		if (!zone) {
> +			err = -ENOMEM;
> +			--i;
> +			goto unregister_tzs;
> +		}
> +
> +		zone->temp_reg = tegra->regs + thermctl_temp_offsets[i];
> +		zone->temp_shift = thermctl_temp_shifts[i];
> +
> +		tz = thermal_zone_of_sensor_register(
> +			&pdev->dev, i, zone, tegra_thermctl_get_temp, NULL);
> +		if (IS_ERR(tz)) {
> +			err = PTR_ERR(tz);
> +			dev_err(&pdev->dev, "failed to register sensor: %d\n",
> +				err);
> +			--i;
> +			goto unregister_tzs;
> +		}
> +
> +		tegra->thermctl_tzs[i] = tz;
> +	}
> +
> +	return 0;
> +
> +unregister_tzs:
> +	for (; i >= 0; i--)
> +		thermal_zone_of_sensor_unregister(&pdev->dev,
> +						  tegra->thermctl_tzs[i]);
> +
> +disable_clocks:
> +	clk_disable_unprepare(tegra->clock_tsensor);
> +	clk_disable_unprepare(tegra->clock_soctherm);
> +
> +	return err;
> +}
> +
> +static int tegra_soctherm_remove(struct platform_device *pdev)
> +{
> +	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(tegra->thermctl_tzs); ++i) {
> +		thermal_zone_of_sensor_unregister(&pdev->dev,
> +						  tegra->thermctl_tzs[i]);
> +	}
> +
> +	clk_disable_unprepare(tegra->clock_tsensor);
> +	clk_disable_unprepare(tegra->clock_soctherm);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver tegra_soctherm_driver = {
> +	.probe = tegra_soctherm_probe,
> +	.remove = tegra_soctherm_remove,
> +	.driver = {
> +		.name = "tegra_soctherm",
> +		.of_match_table = tegra_soctherm_of_match,
> +	},
> +};
> +module_platform_driver(tegra_soctherm_driver);
> +
> +MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
> +MODULE_DESCRIPTION("Tegra SOCTHERM thermal management driver");
> +MODULE_LICENSE("GPL v2");
> -- 
> 1.8.1.5
> 

Re: [PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Mikko Perttunen]

On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
>
> Mikko,
>
> On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
>> ...
>> +
>> +static int enable_tsensor(struct tegra_soctherm *tegra,
>> +			  const struct tegra_tsensor *sensor,
>> +			  struct tsensor_shared_calibration shared)
>> +{
>> +	void * __iomem base = tegra->regs + sensor->base;
>
> I get sparse complaining about this declaration. For the sake of keeping
> a clean static checks, can you please:
> -       void * __iomem base = tegra->regs + sensor->base;
> +       void __iomem * base = tegra->regs + sensor->base;
>

Sure.

>
> Can you also please check the remaining sparse errors?
>    CHECK   drivers/thermal/tegra_soctherm.c
>    drivers/thermal/tegra_soctherm.c:260:43: warning: incorrect type in
>    initializer (different address spaces)
>    drivers/thermal/tegra_soctherm.c:260:43:    expected void *[noderef]
>    <asn:2>base
>    drivers/thermal/tegra_soctherm.c:260:43:    got void [noderef]
>    <asn:2>*
>    drivers/thermal/tegra_soctherm.c:271:9: warning: incorrect type in
>    argument 2 (different address spaces)
>    drivers/thermal/tegra_soctherm.c:271:9:    expected void volatile
>    [noderef] <asn:2>*addr
>    drivers/thermal/tegra_soctherm.c:271:9:    got void *
>    drivers/thermal/tegra_soctherm.c:279:9: warning: incorrect type in
>    argument 2 (different address spaces)
>    drivers/thermal/tegra_soctherm.c:279:9:    expected void volatile
>    [noderef] <asn:2>*addr
>    drivers/thermal/tegra_soctherm.c:279:9:    got void *
>    drivers/thermal/tegra_soctherm.c:281:9: warning: incorrect type in
>    argument 2 (different address spaces)
>    drivers/thermal/tegra_soctherm.c:281:9:    expected void volatile
>    [noderef] <asn:2>*addr
>    drivers/thermal/tegra_soctherm.c:281:9:    got void *
>    drivers/thermal/tegra_soctherm.c:347:25: warning: incorrect type in
>    argument 1 (different address spaces)
>    drivers/thermal/tegra_soctherm.c:347:25:    expected void const *ptr
>    drivers/thermal/tegra_soctherm.c:347:25:    got void [noderef]
>    <asn:2>*regs
>    drivers/thermal/tegra_soctherm.c:349:37: warning: incorrect type in
>    argument 1 (different address spaces)
>    drivers/thermal/tegra_soctherm.c:349:37:    expected void const *ptr
>    drivers/thermal/tegra_soctherm.c:349:37:    got void [noderef]
>    <asn:2>*regs
>    drivers/thermal/tegra_soctherm.c:271:9: warning: dereference of
>    noderef expression
>    drivers/thermal/tegra_soctherm.c:279:9: warning: dereference of
>    noderef expression
>    drivers/thermal/tegra_soctherm.c:281:9: warning: dereference of
>    noderef expression
>

Most of these seem to be caused by the above-mentioned swapping of 
__iomem and *. The ones on lines 347 and 349 are more peculiar, though. 
Apparently sparse doesn't like using IS_ERR and PTR_ERR on the void 
__iomem * pointer returned by devm_ioremap_resource. Looks like this has 
been discussed before (https://lkml.org/lkml/2013/6/17/216) and sparse 
should have been patched to ignore this situation, so I'm not sure why 
it's complaining about it. Anyway, there shouldn't be any issue here.

Mikko

[PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Mikko Perttunen]

On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
>
> Mikko,
>
> On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
>> ...
>> +
>> +static int enable_tsensor(struct tegra_soctherm *tegra,
>> +			  const struct tegra_tsensor *sensor,
>> +			  struct tsensor_shared_calibration shared)
>> +{
>> +	void * __iomem base = tegra->regs + sensor->base;
>
> I get sparse complaining about this declaration. For the sake of keeping
> a clean static checks, can you please:
> -       void * __iomem base = tegra->regs + sensor->base;
> +       void __iomem * base = tegra->regs + sensor->base;
>

Sure.

>
> Can you also please check the remaining sparse errors?
>    CHECK   drivers/thermal/tegra_soctherm.c
>    drivers/thermal/tegra_soctherm.c:260:43: warning: incorrect type in
>    initializer (different address spaces)
>    drivers/thermal/tegra_soctherm.c:260:43:    expected void *[noderef]
>    <asn:2>base
>    drivers/thermal/tegra_soctherm.c:260:43:    got void [noderef]
>    <asn:2>*
>    drivers/thermal/tegra_soctherm.c:271:9: warning: incorrect type in
>    argument 2 (different address spaces)
>    drivers/thermal/tegra_soctherm.c:271:9:    expected void volatile
>    [noderef] <asn:2>*addr
>    drivers/thermal/tegra_soctherm.c:271:9:    got void *
>    drivers/thermal/tegra_soctherm.c:279:9: warning: incorrect type in
>    argument 2 (different address spaces)
>    drivers/thermal/tegra_soctherm.c:279:9:    expected void volatile
>    [noderef] <asn:2>*addr
>    drivers/thermal/tegra_soctherm.c:279:9:    got void *
>    drivers/thermal/tegra_soctherm.c:281:9: warning: incorrect type in
>    argument 2 (different address spaces)
>    drivers/thermal/tegra_soctherm.c:281:9:    expected void volatile
>    [noderef] <asn:2>*addr
>    drivers/thermal/tegra_soctherm.c:281:9:    got void *
>    drivers/thermal/tegra_soctherm.c:347:25: warning: incorrect type in
>    argument 1 (different address spaces)
>    drivers/thermal/tegra_soctherm.c:347:25:    expected void const *ptr
>    drivers/thermal/tegra_soctherm.c:347:25:    got void [noderef]
>    <asn:2>*regs
>    drivers/thermal/tegra_soctherm.c:349:37: warning: incorrect type in
>    argument 1 (different address spaces)
>    drivers/thermal/tegra_soctherm.c:349:37:    expected void const *ptr
>    drivers/thermal/tegra_soctherm.c:349:37:    got void [noderef]
>    <asn:2>*regs
>    drivers/thermal/tegra_soctherm.c:271:9: warning: dereference of
>    noderef expression
>    drivers/thermal/tegra_soctherm.c:279:9: warning: dereference of
>    noderef expression
>    drivers/thermal/tegra_soctherm.c:281:9: warning: dereference of
>    noderef expression
>

Most of these seem to be caused by the above-mentioned swapping of 
__iomem and *. The ones on lines 347 and 349 are more peculiar, though. 
Apparently sparse doesn't like using IS_ERR and PTR_ERR on the void 
__iomem * pointer returned by devm_ioremap_resource. Looks like this has 
been discussed before (https://lkml.org/lkml/2013/6/17/216) and sparse 
should have been patched to ignore this situation, so I'm not sure why 
it's complaining about it. Anyway, there shouldn't be any issue here.

Mikko

Re: [PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Eduardo Valentin]

Hello,


On Wed, Sep 24, 2014 at 10:32:13PM +0300, Mikko Perttunen wrote:
> On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
> >
> > Mikko,
> >
> > On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
> >> ...
> >> +
> >> +static int enable_tsensor(struct tegra_soctherm *tegra,
> >> +			  const struct tegra_tsensor *sensor,
> >> +			  struct tsensor_shared_calibration shared)
> >> +{
> >> +	void * __iomem base = tegra->regs + sensor->base;
> >
> > I get sparse complaining about this declaration. For the sake of keeping
> > a clean static checks, can you please:
> > -       void * __iomem base = tegra->regs + sensor->base;
> > +       void __iomem * base = tegra->regs + sensor->base;
> >
> 
> Sure.


Good.

> 
> >
> > Can you also please check the remaining sparse errors?
> >    CHECK   drivers/thermal/tegra_soctherm.c
> >    drivers/thermal/tegra_soctherm.c:260:43: warning: incorrect type in
> >    initializer (different address spaces)
> >    drivers/thermal/tegra_soctherm.c:260:43:    expected void *[noderef]
> >    <asn:2>base
> >    drivers/thermal/tegra_soctherm.c:260:43:    got void [noderef]
> >    <asn:2>*
> >    drivers/thermal/tegra_soctherm.c:271:9: warning: incorrect type in
> >    argument 2 (different address spaces)
> >    drivers/thermal/tegra_soctherm.c:271:9:    expected void volatile
> >    [noderef] <asn:2>*addr
> >    drivers/thermal/tegra_soctherm.c:271:9:    got void *
> >    drivers/thermal/tegra_soctherm.c:279:9: warning: incorrect type in
> >    argument 2 (different address spaces)
> >    drivers/thermal/tegra_soctherm.c:279:9:    expected void volatile
> >    [noderef] <asn:2>*addr
> >    drivers/thermal/tegra_soctherm.c:279:9:    got void *
> >    drivers/thermal/tegra_soctherm.c:281:9: warning: incorrect type in
> >    argument 2 (different address spaces)
> >    drivers/thermal/tegra_soctherm.c:281:9:    expected void volatile
> >    [noderef] <asn:2>*addr
> >    drivers/thermal/tegra_soctherm.c:281:9:    got void *
> >    drivers/thermal/tegra_soctherm.c:347:25: warning: incorrect type in
> >    argument 1 (different address spaces)
> >    drivers/thermal/tegra_soctherm.c:347:25:    expected void const *ptr
> >    drivers/thermal/tegra_soctherm.c:347:25:    got void [noderef]
> >    <asn:2>*regs
> >    drivers/thermal/tegra_soctherm.c:349:37: warning: incorrect type in
> >    argument 1 (different address spaces)
> >    drivers/thermal/tegra_soctherm.c:349:37:    expected void const *ptr
> >    drivers/thermal/tegra_soctherm.c:349:37:    got void [noderef]
> >    <asn:2>*regs
> >    drivers/thermal/tegra_soctherm.c:271:9: warning: dereference of
> >    noderef expression
> >    drivers/thermal/tegra_soctherm.c:279:9: warning: dereference of
> >    noderef expression
> >    drivers/thermal/tegra_soctherm.c:281:9: warning: dereference of
> >    noderef expression
> >
> 
> Most of these seem to be caused by the above-mentioned swapping of 
> __iomem and *. The ones on lines 347 and 349 are more peculiar, though. 
> Apparently sparse doesn't like using IS_ERR and PTR_ERR on the void 
> __iomem * pointer returned by devm_ioremap_resource. Looks like this has 
> been discussed before (https://lkml.org/lkml/2013/6/17/216) and sparse 
> should have been patched to ignore this situation, so I'm not sure why 
> it's complaining about it. Anyway, there shouldn't be any issue here.

Sounds good to me.

> 
> Mikko
> 

[PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Eduardo Valentin]

Hello,


On Wed, Sep 24, 2014 at 10:32:13PM +0300, Mikko Perttunen wrote:
> On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
> >
> > Mikko,
> >
> > On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
> >> ...
> >> +
> >> +static int enable_tsensor(struct tegra_soctherm *tegra,
> >> +			  const struct tegra_tsensor *sensor,
> >> +			  struct tsensor_shared_calibration shared)
> >> +{
> >> +	void * __iomem base = tegra->regs + sensor->base;
> >
> > I get sparse complaining about this declaration. For the sake of keeping
> > a clean static checks, can you please:
> > -       void * __iomem base = tegra->regs + sensor->base;
> > +       void __iomem * base = tegra->regs + sensor->base;
> >
> 
> Sure.


Good.

> 
> >
> > Can you also please check the remaining sparse errors?
> >    CHECK   drivers/thermal/tegra_soctherm.c
> >    drivers/thermal/tegra_soctherm.c:260:43: warning: incorrect type in
> >    initializer (different address spaces)
> >    drivers/thermal/tegra_soctherm.c:260:43:    expected void *[noderef]
> >    <asn:2>base
> >    drivers/thermal/tegra_soctherm.c:260:43:    got void [noderef]
> >    <asn:2>*
> >    drivers/thermal/tegra_soctherm.c:271:9: warning: incorrect type in
> >    argument 2 (different address spaces)
> >    drivers/thermal/tegra_soctherm.c:271:9:    expected void volatile
> >    [noderef] <asn:2>*addr
> >    drivers/thermal/tegra_soctherm.c:271:9:    got void *
> >    drivers/thermal/tegra_soctherm.c:279:9: warning: incorrect type in
> >    argument 2 (different address spaces)
> >    drivers/thermal/tegra_soctherm.c:279:9:    expected void volatile
> >    [noderef] <asn:2>*addr
> >    drivers/thermal/tegra_soctherm.c:279:9:    got void *
> >    drivers/thermal/tegra_soctherm.c:281:9: warning: incorrect type in
> >    argument 2 (different address spaces)
> >    drivers/thermal/tegra_soctherm.c:281:9:    expected void volatile
> >    [noderef] <asn:2>*addr
> >    drivers/thermal/tegra_soctherm.c:281:9:    got void *
> >    drivers/thermal/tegra_soctherm.c:347:25: warning: incorrect type in
> >    argument 1 (different address spaces)
> >    drivers/thermal/tegra_soctherm.c:347:25:    expected void const *ptr
> >    drivers/thermal/tegra_soctherm.c:347:25:    got void [noderef]
> >    <asn:2>*regs
> >    drivers/thermal/tegra_soctherm.c:349:37: warning: incorrect type in
> >    argument 1 (different address spaces)
> >    drivers/thermal/tegra_soctherm.c:349:37:    expected void const *ptr
> >    drivers/thermal/tegra_soctherm.c:349:37:    got void [noderef]
> >    <asn:2>*regs
> >    drivers/thermal/tegra_soctherm.c:271:9: warning: dereference of
> >    noderef expression
> >    drivers/thermal/tegra_soctherm.c:279:9: warning: dereference of
> >    noderef expression
> >    drivers/thermal/tegra_soctherm.c:281:9: warning: dereference of
> >    noderef expression
> >
> 
> Most of these seem to be caused by the above-mentioned swapping of 
> __iomem and *. The ones on lines 347 and 349 are more peculiar, though. 
> Apparently sparse doesn't like using IS_ERR and PTR_ERR on the void 
> __iomem * pointer returned by devm_ioremap_resource. Looks like this has 
> been discussed before (https://lkml.org/lkml/2013/6/17/216) and sparse 
> should have been patched to ignore this situation, so I'm not sure why 
> it's complaining about it. Anyway, there shouldn't be any issue here.

Sounds good to me.

> 
> Mikko
> 

Re: [PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 3577 bytes --]

On Wed, Sep 24, 2014 at 10:32:13PM +0300, Mikko Perttunen wrote:
> On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
> >
> >Mikko,
> >
> >On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
> >>...
> >>+
> >>+static int enable_tsensor(struct tegra_soctherm *tegra,
> >>+			  const struct tegra_tsensor *sensor,
> >>+			  struct tsensor_shared_calibration shared)
> >>+{
> >>+	void * __iomem base = tegra->regs + sensor->base;
> >
> >I get sparse complaining about this declaration. For the sake of keeping
> >a clean static checks, can you please:
> >-       void * __iomem base = tegra->regs + sensor->base;
> >+       void __iomem * base = tegra->regs + sensor->base;
> >
> 
> Sure.
> 
> >Can you also please check the remaining sparse errors?
> >   CHECK   drivers/thermal/tegra_soctherm.c
> >   drivers/thermal/tegra_soctherm.c:260:43: warning: incorrect type in
> >   initializer (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:260:43:    expected void *[noderef]
> >   <asn:2>base
> >   drivers/thermal/tegra_soctherm.c:260:43:    got void [noderef]
> >   <asn:2>*
> >   drivers/thermal/tegra_soctherm.c:271:9: warning: incorrect type in
> >   argument 2 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:271:9:    expected void volatile
> >   [noderef] <asn:2>*addr
> >   drivers/thermal/tegra_soctherm.c:271:9:    got void *
> >   drivers/thermal/tegra_soctherm.c:279:9: warning: incorrect type in
> >   argument 2 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:279:9:    expected void volatile
> >   [noderef] <asn:2>*addr
> >   drivers/thermal/tegra_soctherm.c:279:9:    got void *
> >   drivers/thermal/tegra_soctherm.c:281:9: warning: incorrect type in
> >   argument 2 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:281:9:    expected void volatile
> >   [noderef] <asn:2>*addr
> >   drivers/thermal/tegra_soctherm.c:281:9:    got void *
> >   drivers/thermal/tegra_soctherm.c:347:25: warning: incorrect type in
> >   argument 1 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:347:25:    expected void const *ptr
> >   drivers/thermal/tegra_soctherm.c:347:25:    got void [noderef]
> >   <asn:2>*regs
> >   drivers/thermal/tegra_soctherm.c:349:37: warning: incorrect type in
> >   argument 1 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:349:37:    expected void const *ptr
> >   drivers/thermal/tegra_soctherm.c:349:37:    got void [noderef]
> >   <asn:2>*regs
> >   drivers/thermal/tegra_soctherm.c:271:9: warning: dereference of
> >   noderef expression
> >   drivers/thermal/tegra_soctherm.c:279:9: warning: dereference of
> >   noderef expression
> >   drivers/thermal/tegra_soctherm.c:281:9: warning: dereference of
> >   noderef expression
> >
> 
> Most of these seem to be caused by the above-mentioned swapping of __iomem
> and *. The ones on lines 347 and 349 are more peculiar, though. Apparently
> sparse doesn't like using IS_ERR and PTR_ERR on the void __iomem * pointer
> returned by devm_ioremap_resource. Looks like this has been discussed before
> (https://lkml.org/lkml/2013/6/17/216) and sparse should have been patched to
> ignore this situation, so I'm not sure why it's complaining about it.
> Anyway, there shouldn't be any issue here.

If I apply the change suggested by Eduardo above then all of the above
warnings go away for me. That's with sparse 0.5.0. According to the
email thread above a patch for this was applied in 0.4.5.

Thierry

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[PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Thierry Reding]

On Wed, Sep 24, 2014 at 10:32:13PM +0300, Mikko Perttunen wrote:
> On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
> >
> >Mikko,
> >
> >On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
> >>...
> >>+
> >>+static int enable_tsensor(struct tegra_soctherm *tegra,
> >>+			  const struct tegra_tsensor *sensor,
> >>+			  struct tsensor_shared_calibration shared)
> >>+{
> >>+	void * __iomem base = tegra->regs + sensor->base;
> >
> >I get sparse complaining about this declaration. For the sake of keeping
> >a clean static checks, can you please:
> >-       void * __iomem base = tegra->regs + sensor->base;
> >+       void __iomem * base = tegra->regs + sensor->base;
> >
> 
> Sure.
> 
> >Can you also please check the remaining sparse errors?
> >   CHECK   drivers/thermal/tegra_soctherm.c
> >   drivers/thermal/tegra_soctherm.c:260:43: warning: incorrect type in
> >   initializer (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:260:43:    expected void *[noderef]
> >   <asn:2>base
> >   drivers/thermal/tegra_soctherm.c:260:43:    got void [noderef]
> >   <asn:2>*
> >   drivers/thermal/tegra_soctherm.c:271:9: warning: incorrect type in
> >   argument 2 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:271:9:    expected void volatile
> >   [noderef] <asn:2>*addr
> >   drivers/thermal/tegra_soctherm.c:271:9:    got void *
> >   drivers/thermal/tegra_soctherm.c:279:9: warning: incorrect type in
> >   argument 2 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:279:9:    expected void volatile
> >   [noderef] <asn:2>*addr
> >   drivers/thermal/tegra_soctherm.c:279:9:    got void *
> >   drivers/thermal/tegra_soctherm.c:281:9: warning: incorrect type in
> >   argument 2 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:281:9:    expected void volatile
> >   [noderef] <asn:2>*addr
> >   drivers/thermal/tegra_soctherm.c:281:9:    got void *
> >   drivers/thermal/tegra_soctherm.c:347:25: warning: incorrect type in
> >   argument 1 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:347:25:    expected void const *ptr
> >   drivers/thermal/tegra_soctherm.c:347:25:    got void [noderef]
> >   <asn:2>*regs
> >   drivers/thermal/tegra_soctherm.c:349:37: warning: incorrect type in
> >   argument 1 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:349:37:    expected void const *ptr
> >   drivers/thermal/tegra_soctherm.c:349:37:    got void [noderef]
> >   <asn:2>*regs
> >   drivers/thermal/tegra_soctherm.c:271:9: warning: dereference of
> >   noderef expression
> >   drivers/thermal/tegra_soctherm.c:279:9: warning: dereference of
> >   noderef expression
> >   drivers/thermal/tegra_soctherm.c:281:9: warning: dereference of
> >   noderef expression
> >
> 
> Most of these seem to be caused by the above-mentioned swapping of __iomem
> and *. The ones on lines 347 and 349 are more peculiar, though. Apparently
> sparse doesn't like using IS_ERR and PTR_ERR on the void __iomem * pointer
> returned by devm_ioremap_resource. Looks like this has been discussed before
> (https://lkml.org/lkml/2013/6/17/216) and sparse should have been patched to
> ignore this situation, so I'm not sure why it's complaining about it.
> Anyway, there shouldn't be any issue here.

If I apply the change suggested by Eduardo above then all of the above
warnings go away for me. That's with sparse 0.5.0. According to the
email thread above a patch for this was applied in 0.4.5.

Thierry
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Re: [PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 3577 bytes --]

On Wed, Sep 24, 2014 at 10:32:13PM +0300, Mikko Perttunen wrote:
> On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
> >
> >Mikko,
> >
> >On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
> >>...
> >>+
> >>+static int enable_tsensor(struct tegra_soctherm *tegra,
> >>+			  const struct tegra_tsensor *sensor,
> >>+			  struct tsensor_shared_calibration shared)
> >>+{
> >>+	void * __iomem base = tegra->regs + sensor->base;
> >
> >I get sparse complaining about this declaration. For the sake of keeping
> >a clean static checks, can you please:
> >-       void * __iomem base = tegra->regs + sensor->base;
> >+       void __iomem * base = tegra->regs + sensor->base;
> >
> 
> Sure.
> 
> >Can you also please check the remaining sparse errors?
> >   CHECK   drivers/thermal/tegra_soctherm.c
> >   drivers/thermal/tegra_soctherm.c:260:43: warning: incorrect type in
> >   initializer (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:260:43:    expected void *[noderef]
> >   <asn:2>base
> >   drivers/thermal/tegra_soctherm.c:260:43:    got void [noderef]
> >   <asn:2>*
> >   drivers/thermal/tegra_soctherm.c:271:9: warning: incorrect type in
> >   argument 2 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:271:9:    expected void volatile
> >   [noderef] <asn:2>*addr
> >   drivers/thermal/tegra_soctherm.c:271:9:    got void *
> >   drivers/thermal/tegra_soctherm.c:279:9: warning: incorrect type in
> >   argument 2 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:279:9:    expected void volatile
> >   [noderef] <asn:2>*addr
> >   drivers/thermal/tegra_soctherm.c:279:9:    got void *
> >   drivers/thermal/tegra_soctherm.c:281:9: warning: incorrect type in
> >   argument 2 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:281:9:    expected void volatile
> >   [noderef] <asn:2>*addr
> >   drivers/thermal/tegra_soctherm.c:281:9:    got void *
> >   drivers/thermal/tegra_soctherm.c:347:25: warning: incorrect type in
> >   argument 1 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:347:25:    expected void const *ptr
> >   drivers/thermal/tegra_soctherm.c:347:25:    got void [noderef]
> >   <asn:2>*regs
> >   drivers/thermal/tegra_soctherm.c:349:37: warning: incorrect type in
> >   argument 1 (different address spaces)
> >   drivers/thermal/tegra_soctherm.c:349:37:    expected void const *ptr
> >   drivers/thermal/tegra_soctherm.c:349:37:    got void [noderef]
> >   <asn:2>*regs
> >   drivers/thermal/tegra_soctherm.c:271:9: warning: dereference of
> >   noderef expression
> >   drivers/thermal/tegra_soctherm.c:279:9: warning: dereference of
> >   noderef expression
> >   drivers/thermal/tegra_soctherm.c:281:9: warning: dereference of
> >   noderef expression
> >
> 
> Most of these seem to be caused by the above-mentioned swapping of __iomem
> and *. The ones on lines 347 and 349 are more peculiar, though. Apparently
> sparse doesn't like using IS_ERR and PTR_ERR on the void __iomem * pointer
> returned by devm_ioremap_resource. Looks like this has been discussed before
> (https://lkml.org/lkml/2013/6/17/216) and sparse should have been patched to
> ignore this situation, so I'm not sure why it's complaining about it.
> Anyway, there shouldn't be any issue here.

If I apply the change suggested by Eduardo above then all of the above
warnings go away for me. That's with sparse 0.5.0. According to the
email thread above a patch for this was applied in 0.4.5.

Thierry

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Re: [PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Mikko Perttunen]

On 09/25/2014 08:59 AM, Thierry Reding wrote:
> On Wed, Sep 24, 2014 at 10:32:13PM +0300, Mikko Perttunen wrote:
>> On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
>>>
>>> Mikko,
>>>
>>> On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
>>>> ...
>>>> +
>>>> +static int enable_tsensor(struct tegra_soctherm *tegra,
>>>> +			  const struct tegra_tsensor *sensor,
>>>> +			  struct tsensor_shared_calibration shared)
>>>> +{
>>>> +	void * __iomem base = tegra->regs + sensor->base;
>>>
>>> I get sparse complaining about this declaration. For the sake of keeping
>>> a clean static checks, can you please:
>>> -       void * __iomem base = tegra->regs + sensor->base;
>>> +       void __iomem * base = tegra->regs + sensor->base;
>>>
>>
>> Sure.
>>
>>> Can you also please check the remaining sparse errors?
>>>    CHECK   drivers/thermal/tegra_soctherm.c
>>>    drivers/thermal/tegra_soctherm.c:260:43: warning: incorrect type in
>>>    initializer (different address spaces)
>>>    drivers/thermal/tegra_soctherm.c:260:43:    expected void *[noderef]
>>>    <asn:2>base
>>>    drivers/thermal/tegra_soctherm.c:260:43:    got void [noderef]
>>>    <asn:2>*
>>>    drivers/thermal/tegra_soctherm.c:271:9: warning: incorrect type in
>>>    argument 2 (different address spaces)
>>>    drivers/thermal/tegra_soctherm.c:271:9:    expected void volatile
>>>    [noderef] <asn:2>*addr
>>>    drivers/thermal/tegra_soctherm.c:271:9:    got void *
>>>    drivers/thermal/tegra_soctherm.c:279:9: warning: incorrect type in
>>>    argument 2 (different address spaces)
>>>    drivers/thermal/tegra_soctherm.c:279:9:    expected void volatile
>>>    [noderef] <asn:2>*addr
>>>    drivers/thermal/tegra_soctherm.c:279:9:    got void *
>>>    drivers/thermal/tegra_soctherm.c:281:9: warning: incorrect type in
>>>    argument 2 (different address spaces)
>>>    drivers/thermal/tegra_soctherm.c:281:9:    expected void volatile
>>>    [noderef] <asn:2>*addr
>>>    drivers/thermal/tegra_soctherm.c:281:9:    got void *
>>>    drivers/thermal/tegra_soctherm.c:347:25: warning: incorrect type in
>>>    argument 1 (different address spaces)
>>>    drivers/thermal/tegra_soctherm.c:347:25:    expected void const *ptr
>>>    drivers/thermal/tegra_soctherm.c:347:25:    got void [noderef]
>>>    <asn:2>*regs
>>>    drivers/thermal/tegra_soctherm.c:349:37: warning: incorrect type in
>>>    argument 1 (different address spaces)
>>>    drivers/thermal/tegra_soctherm.c:349:37:    expected void const *ptr
>>>    drivers/thermal/tegra_soctherm.c:349:37:    got void [noderef]
>>>    <asn:2>*regs
>>>    drivers/thermal/tegra_soctherm.c:271:9: warning: dereference of
>>>    noderef expression
>>>    drivers/thermal/tegra_soctherm.c:279:9: warning: dereference of
>>>    noderef expression
>>>    drivers/thermal/tegra_soctherm.c:281:9: warning: dereference of
>>>    noderef expression
>>>
>>
>> Most of these seem to be caused by the above-mentioned swapping of __iomem
>> and *. The ones on lines 347 and 349 are more peculiar, though. Apparently
>> sparse doesn't like using IS_ERR and PTR_ERR on the void __iomem * pointer
>> returned by devm_ioremap_resource. Looks like this has been discussed before
>> (https://lkml.org/lkml/2013/6/17/216) and sparse should have been patched to
>> ignore this situation, so I'm not sure why it's complaining about it.
>> Anyway, there shouldn't be any issue here.
>
> If I apply the change suggested by Eduardo above then all of the above
> warnings go away for me. That's with sparse 0.5.0. According to the
> email thread above a patch for this was applied in 0.4.5.

Ah, good. I didn't actually run sparse, just checked by eye. Maybe I 
should have run it.

>
> Thierry
>

[PATCH v5 4/4] thermal: Add Tegra SOCTHERM thermal management driver

[Mikko Perttunen]

On 09/25/2014 08:59 AM, Thierry Reding wrote:
> On Wed, Sep 24, 2014 at 10:32:13PM +0300, Mikko Perttunen wrote:
>> On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
>>>
>>> Mikko,
>>>
>>> On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
>>>> ...
>>>> +
>>>> +static int enable_tsensor(struct tegra_soctherm *tegra,
>>>> +			  const struct tegra_tsensor *sensor,
>>>> +			  struct tsensor_shared_calibration shared)
>>>> +{
>>>> +	void * __iomem base = tegra->regs + sensor->base;
>>>
>>> I get sparse complaining about this declaration. For the sake of keeping
>>> a clean static checks, can you please:
>>> -       void * __iomem base = tegra->regs + sensor->base;
>>> +       void __iomem * base = tegra->regs + sensor->base;
>>>
>>
>> Sure.
>>
>>> Can you also please check the remaining sparse errors?
>>>    CHECK   drivers/thermal/tegra_soctherm.c
>>>    drivers/thermal/tegra_soctherm.c:260:43: warning: incorrect type in
>>>    initializer (different address spaces)
>>>    drivers/thermal/tegra_soctherm.c:260:43:    expected void *[noderef]
>>>    <asn:2>base
>>>    drivers/thermal/tegra_soctherm.c:260:43:    got void [noderef]
>>>    <asn:2>*
>>>    drivers/thermal/tegra_soctherm.c:271:9: warning: incorrect type in
>>>    argument 2 (different address spaces)
>>>    drivers/thermal/tegra_soctherm.c:271:9:    expected void volatile
>>>    [noderef] <asn:2>*addr
>>>    drivers/thermal/tegra_soctherm.c:271:9:    got void *
>>>    drivers/thermal/tegra_soctherm.c:279:9: warning: incorrect type in
>>>    argument 2 (different address spaces)
>>>    drivers/thermal/tegra_soctherm.c:279:9:    expected void volatile
>>>    [noderef] <asn:2>*addr
>>>    drivers/thermal/tegra_soctherm.c:279:9:    got void *
>>>    drivers/thermal/tegra_soctherm.c:281:9: warning: incorrect type in
>>>    argument 2 (different address spaces)
>>>    drivers/thermal/tegra_soctherm.c:281:9:    expected void volatile
>>>    [noderef] <asn:2>*addr
>>>    drivers/thermal/tegra_soctherm.c:281:9:    got void *
>>>    drivers/thermal/tegra_soctherm.c:347:25: warning: incorrect type in
>>>    argument 1 (different address spaces)
>>>    drivers/thermal/tegra_soctherm.c:347:25:    expected void const *ptr
>>>    drivers/thermal/tegra_soctherm.c:347:25:    got void [noderef]
>>>    <asn:2>*regs
>>>    drivers/thermal/tegra_soctherm.c:349:37: warning: incorrect type in
>>>    argument 1 (different address spaces)
>>>    drivers/thermal/tegra_soctherm.c:349:37:    expected void const *ptr
>>>    drivers/thermal/tegra_soctherm.c:349:37:    got void [noderef]
>>>    <asn:2>*regs
>>>    drivers/thermal/tegra_soctherm.c:271:9: warning: dereference of
>>>    noderef expression
>>>    drivers/thermal/tegra_soctherm.c:279:9: warning: dereference of
>>>    noderef expression
>>>    drivers/thermal/tegra_soctherm.c:281:9: warning: dereference of
>>>    noderef expression
>>>
>>
>> Most of these seem to be caused by the above-mentioned swapping of __iomem
>> and *. The ones on lines 347 and 349 are more peculiar, though. Apparently
>> sparse doesn't like using IS_ERR and PTR_ERR on the void __iomem * pointer
>> returned by devm_ioremap_resource. Looks like this has been discussed before
>> (https://lkml.org/lkml/2013/6/17/216) and sparse should have been patched to
>> ignore this situation, so I'm not sure why it's complaining about it.
>> Anyway, there shouldn't be any issue here.
>
> If I apply the change suggested by Eduardo above then all of the above
> warnings go away for me. That's with sparse 0.5.0. According to the
> email thread above a patch for this was applied in 0.4.5.

Ah, good. I didn't actually run sparse, just checked by eye. Maybe I 
should have run it.

>
> Thierry
>

Re: [PATCH v5 0/4] Tegra124 soctherm driver

[Juha-Matti Tilli]

On Thu, Aug 21, 2014 at 01:17:18PM +0300, Mikko Perttunen wrote:
> this series adds support for the thermal monitoring features of the
> soctherm unit on the Tegra124 SoC. 

For all patches in this series:

Reviewed-by: Juha-Matti Tilli <jtilli@nvidia.com>
Tested-by: Juha-Matti Tilli <jtilli@nvidia.com>

[PATCH v5 0/4] Tegra124 soctherm driver

[Juha-Matti Tilli]

On Thu, Aug 21, 2014 at 01:17:18PM +0300, Mikko Perttunen wrote:
> this series adds support for the thermal monitoring features of the
> soctherm unit on the Tegra124 SoC. 

For all patches in this series:

Reviewed-by: Juha-Matti Tilli <jtilli@nvidia.com>
Tested-by: Juha-Matti Tilli <jtilli@nvidia.com>

Re: [PATCH v5 0/4] Tegra124 soctherm driver

[Eduardo Valentin]

Hello Juha-Matti,

On Thu, Aug 21, 2014 at 03:20:11PM +0300, Juha-Matti Tilli wrote:
> On Thu, Aug 21, 2014 at 01:17:18PM +0300, Mikko Perttunen wrote:
> > this series adds support for the thermal monitoring features of the
> > soctherm unit on the Tegra124 SoC. 
> 
> For all patches in this series:
> 
> Reviewed-by: Juha-Matti Tilli <jtilli@nvidia.com>
> Tested-by: Juha-Matti Tilli <jtilli@nvidia.com>

I suppose the 4 C to 5 C difference is not seen anymore in this version,
right?

Cheers,

Eduardo

[PATCH v5 0/4] Tegra124 soctherm driver

[Eduardo Valentin]

Hello Juha-Matti,

On Thu, Aug 21, 2014 at 03:20:11PM +0300, Juha-Matti Tilli wrote:
> On Thu, Aug 21, 2014 at 01:17:18PM +0300, Mikko Perttunen wrote:
> > this series adds support for the thermal monitoring features of the
> > soctherm unit on the Tegra124 SoC. 
> 
> For all patches in this series:
> 
> Reviewed-by: Juha-Matti Tilli <jtilli@nvidia.com>
> Tested-by: Juha-Matti Tilli <jtilli@nvidia.com>

I suppose the 4 C to 5 C difference is not seen anymore in this version,
right?

Cheers,

Eduardo

Re: [PATCH v5 0/4] Tegra124 soctherm driver

[Juha-Matti Tilli]

On Thu, Aug 21, 2014 at 12:01:29PM -0400, Eduardo Valentin wrote:
> I suppose the 4 C to 5 C difference is not seen anymore in this version,
> right?

Yes, I verified that this newest version writes identical calibration
values to the CONFIG2 registers than the NVIDIA's internal downstream
driver and therefore the temperature difference is not seen anymore.
All the bugs I reported have been fixed in this version.

[PATCH v5 0/4] Tegra124 soctherm driver

[Juha-Matti Tilli]

On Thu, Aug 21, 2014 at 12:01:29PM -0400, Eduardo Valentin wrote:
> I suppose the 4 C to 5 C difference is not seen anymore in this version,
> right?

Yes, I verified that this newest version writes identical calibration
values to the CONFIG2 registers than the NVIDIA's internal downstream
driver and therefore the temperature difference is not seen anymore.
All the bugs I reported have been fixed in this version.

Re: [PATCH v5 0/4] Tegra124 soctherm driver

[Mikko Perttunen]

Moi Eduardo,

can you ack this series or is there still something to do?

Thanks,
Mikko

On 21/08/14 19:01, Eduardo Valentin wrote:
> Hello Juha-Matti,
>
> On Thu, Aug 21, 2014 at 03:20:11PM +0300, Juha-Matti Tilli wrote:
>> On Thu, Aug 21, 2014 at 01:17:18PM +0300, Mikko Perttunen wrote:
>>> this series adds support for the thermal monitoring features of the
>>> soctherm unit on the Tegra124 SoC.
>>
>> For all patches in this series:
>>
>> Reviewed-by: Juha-Matti Tilli <jtilli@nvidia.com>
>> Tested-by: Juha-Matti Tilli <jtilli@nvidia.com>
>
> I suppose the 4 C to 5 C difference is not seen anymore in this version,
> right?
>
> Cheers,
>
> Eduardo
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

[PATCH v5 0/4] Tegra124 soctherm driver

[Mikko Perttunen]

Moi Eduardo,

can you ack this series or is there still something to do?

Thanks,
Mikko

On 21/08/14 19:01, Eduardo Valentin wrote:
> Hello Juha-Matti,
>
> On Thu, Aug 21, 2014 at 03:20:11PM +0300, Juha-Matti Tilli wrote:
>> On Thu, Aug 21, 2014 at 01:17:18PM +0300, Mikko Perttunen wrote:
>>> this series adds support for the thermal monitoring features of the
>>> soctherm unit on the Tegra124 SoC.
>>
>> For all patches in this series:
>>
>> Reviewed-by: Juha-Matti Tilli <jtilli@nvidia.com>
>> Tested-by: Juha-Matti Tilli <jtilli@nvidia.com>
>
> I suppose the 4 C to 5 C difference is not seen anymore in this version,
> right?
>
> Cheers,
>
> Eduardo
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

Re: [PATCH v5 0/4] Tegra124 soctherm driver

[Mikko Perttunen]

Moi Eduardo,

can you ack this series or is there still something to do?

Thanks,
Mikko

On 21/08/14 19:01, Eduardo Valentin wrote:
> Hello Juha-Matti,
>
> On Thu, Aug 21, 2014 at 03:20:11PM +0300, Juha-Matti Tilli wrote:
>> On Thu, Aug 21, 2014 at 01:17:18PM +0300, Mikko Perttunen wrote:
>>> this series adds support for the thermal monitoring features of the
>>> soctherm unit on the Tegra124 SoC.
>>
>> For all patches in this series:
>>
>> Reviewed-by: Juha-Matti Tilli <jtilli@nvidia.com>
>> Tested-by: Juha-Matti Tilli <jtilli@nvidia.com>
>
> I suppose the 4 C to 5 C difference is not seen anymore in this version,
> right?
>
> Cheers,
>
> Eduardo
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>