From: "Christian König" <deathsimple@vodafone.de>
To: dri-devel@lists.freedesktop.org
Subject: [PATCH 5/6] drm/radeon: implement UVD hw workarounds for R6xx v3
Date: Sun, 24 Aug 2014 15:14:29 +0200 [thread overview]
Message-ID: <1408886070-31983-6-git-send-email-deathsimple@vodafone.de> (raw)
In-Reply-To: <1408886070-31983-1-git-send-email-deathsimple@vodafone.de>
From: Christian König <christian.koenig@amd.com>
Only the essentials, cause this hw generation is really buggy.
v2: start supporting RV670,RV620 and RV635 as well
v3: activate more workarounds
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/radeon/r600d.h | 3 +++
drivers/gpu/drm/radeon/uvd_v1_0.c | 26 +++++++++++++++++++++++++-
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index ab200c4..e80153b 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -330,6 +330,7 @@
#define HDP_TILING_CONFIG 0x2F3C
#define HDP_DEBUG1 0x2F34
+#define MC_CONFIG 0x2000
#define MC_VM_AGP_TOP 0x2184
#define MC_VM_AGP_BOT 0x2188
#define MC_VM_AGP_BASE 0x218C
@@ -375,6 +376,8 @@
#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
+#define RS_DQ_RD_RET_CONF 0x2348
+
#define PA_CL_ENHANCE 0x8A14
#define CLIP_VTX_REORDER_ENA (1 << 0)
#define NUM_CLIP_SEQ(x) ((x) << 1)
diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c b/drivers/gpu/drm/radeon/uvd_v1_0.c
index 4d95a7d..e251624 100644
--- a/drivers/gpu/drm/radeon/uvd_v1_0.c
+++ b/drivers/gpu/drm/radeon/uvd_v1_0.c
@@ -207,8 +207,32 @@ done:
/* lower clocks again */
radeon_set_uvd_clocks(rdev, 0, 0);
- if (!r)
+ if (!r) {
+ switch (rdev->family) {
+ case CHIP_RV610:
+ case CHIP_RV630:
+ case CHIP_RV620:
+ /* 64byte granularity workaround */
+ WREG32(MC_CONFIG, 0);
+ WREG32(MC_CONFIG, 1 << 4);
+ WREG32(RS_DQ_RD_RET_CONF, 0x3f);
+ WREG32(MC_CONFIG, 0x1f);
+
+ /* fall through */
+ case CHIP_RV670:
+ case CHIP_RV635:
+
+ /* write clean workaround */
+ WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10);
+ break;
+
+ default:
+ /* TODO: Do we need more? */
+ break;
+ }
+
DRM_INFO("UVD initialized successfully.\n");
+ }
return r;
}
--
1.9.1
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next prev parent reply other threads:[~2014-08-24 13:15 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <UVD support for older ASICs>
2014-08-24 13:14 ` (unknown), Christian König
2014-08-24 13:14 ` [PATCH 1/6] drm/radeon: force UVD buffers into VRAM on RS[78]80 v2 Christian König
2014-08-25 17:14 ` Alex Deucher
2014-08-24 13:14 ` [PATCH 2/6] drm/radeon: properly init UVD MC bits on R600 Christian König
2014-08-24 13:14 ` [PATCH 3/6] drm/radeon: add set_uvd_clocks callback for r6xx v4 Christian König
2014-08-24 13:14 ` [PATCH 4/6] drm/radeon: add UVD support for older asics v4 Christian König
2014-08-24 13:14 ` Christian König [this message]
2014-08-24 13:14 ` [PATCH 6/6] drm/radeon: add UVD fw names for older asic Christian König
2014-08-24 13:34 ` Mike Lothian
2014-08-25 9:10 ` Re: Christian König
2014-08-26 14:14 ` (UVD RS780 first impression) Stefan Lange
2014-08-27 3:40 ` Michel Dänzer
2014-08-27 7:00 ` Christian König
2014-08-28 19:25 ` Stefan Lange
2014-08-30 15:58 ` Stefan Lange
2014-09-07 13:24 ` Markus Trippelsdorf
2014-09-08 3:47 ` Re: Alex Deucher
2014-09-08 7:13 ` Re: Markus Trippelsdorf
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