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* [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes
@ 2014-08-26 11:30 ` Kiran Padwal
  0 siblings, 0 replies; 12+ messages in thread
From: Kiran Padwal @ 2014-08-26 11:30 UTC (permalink / raw)
  To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, davidb,
	afaerber
  Cc: devicetree, linux, linux-arm-kernel, linux-arm-msm, linux-kernel,
	Kiran Padwal

This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
It also adds necessary DT support for i2c eeprom which is present on
IFC6410.

Tested on IFC6410 board.

Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
---
Changes since v2:
 - Renamed pinmux i2c subnode "i2c1_pinmux" to "i2c1".
 - Removed labes of node.
 - Used canonical value as "okay" instead of "ok".
 - Used macros.

Changes since v1:
 - Renamed pinmux phandle "qcom_pinmux" to "tlmm_pinmux".
 - Updated pinmux interrupt.

 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts |   27 ++++++++++++++
 arch/arm/boot/dts/qcom-apq8064.dtsi        |   53 ++++++++++++++++++++++++++++
 2 files changed, 80 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 7c2441d..ef0857e 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -5,6 +5,24 @@
 	compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
 
 	soc {
+		gsbi@12440000 {
+			status = "okay";
+			qcom,mode = <GSBI_PROT_I2C>;
+
+			i2c@12460000 {
+				status = "okay";
+				clock-frequency = <200000>;
+				pinctrl-0 = <&i2c1_pins>;
+				pinctrl-names = "default";
+
+				eeprom: eeprom@52 {
+					compatible = "atmel,24c128";
+					reg = <0x52>;
+					pagesize = <32>;
+				};
+			};
+		};
+
 		gsbi@16600000 {
 			status = "ok";
 			qcom,mode = <GSBI_PROT_I2C_UART>;
@@ -12,5 +30,14 @@
 				status = "ok";
 			};
 		};
+
+		pinmux@800000 {
+			i2c1_pins: i2c1 {
+				mux {
+					pins = "gpio20", "gpio21";
+					function = "gsbi1";
+				};
+			};
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 92bf793..5dddbf3 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -89,6 +89,17 @@
 			cpu-offset = <0x80000>;
 		};
 
+		tlmm_pinmux: pinmux@800000 {
+			compatible = "qcom,apq8064-pinctrl";
+			reg = <0x800000 0x4000>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		acc0: clock-controller@2088000 {
 			compatible = "qcom,kpss-acc-v1";
 			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
@@ -133,6 +144,48 @@
 			regulator;
 		};
 
+		gsbi1: gsbi@12440000 {
+			status = "disabled";
+			compatible = "qcom,gsbi-v1.0.0";
+			reg = <0x12440000 0x100>;
+			clocks = <&gcc GSBI1_H_CLK>;
+			clock-names = "iface";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			i2c1: i2c@12460000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x12460000 0x1000>;
+				interrupts = <0 194 IRQ_TYPE_NONE>;
+				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+				clock-names = "core", "iface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		gsbi2: gsbi@12480000 {
+			status = "disabled";
+			compatible = "qcom,gsbi-v1.0.0";
+			reg = <0x12480000 0x100>;
+			clocks = <&gcc GSBI2_H_CLK>;
+			clock-names = "iface";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			i2c2: i2c@124a0000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x124a0000 0x1000>;
+				interrupts = <0 196 IRQ_TYPE_NONE>;
+				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
+				clock-names = "core", "iface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		gsbi7: gsbi@16600000 {
 			status = "disabled";
 			compatible = "qcom,gsbi-v1.0.0";
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes
@ 2014-08-26 11:30 ` Kiran Padwal
  0 siblings, 0 replies; 12+ messages in thread
From: Kiran Padwal @ 2014-08-26 11:30 UTC (permalink / raw)
  To: linux-arm-kernel

This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
It also adds necessary DT support for i2c eeprom which is present on
IFC6410.

Tested on IFC6410 board.

Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
---
Changes since v2:
 - Renamed pinmux i2c subnode "i2c1_pinmux" to "i2c1".
 - Removed labes of node.
 - Used canonical value as "okay" instead of "ok".
 - Used macros.

Changes since v1:
 - Renamed pinmux phandle "qcom_pinmux" to "tlmm_pinmux".
 - Updated pinmux interrupt.

 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts |   27 ++++++++++++++
 arch/arm/boot/dts/qcom-apq8064.dtsi        |   53 ++++++++++++++++++++++++++++
 2 files changed, 80 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 7c2441d..ef0857e 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -5,6 +5,24 @@
 	compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
 
 	soc {
+		gsbi at 12440000 {
+			status = "okay";
+			qcom,mode = <GSBI_PROT_I2C>;
+
+			i2c at 12460000 {
+				status = "okay";
+				clock-frequency = <200000>;
+				pinctrl-0 = <&i2c1_pins>;
+				pinctrl-names = "default";
+
+				eeprom: eeprom at 52 {
+					compatible = "atmel,24c128";
+					reg = <0x52>;
+					pagesize = <32>;
+				};
+			};
+		};
+
 		gsbi at 16600000 {
 			status = "ok";
 			qcom,mode = <GSBI_PROT_I2C_UART>;
@@ -12,5 +30,14 @@
 				status = "ok";
 			};
 		};
+
+		pinmux at 800000 {
+			i2c1_pins: i2c1 {
+				mux {
+					pins = "gpio20", "gpio21";
+					function = "gsbi1";
+				};
+			};
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 92bf793..5dddbf3 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -89,6 +89,17 @@
 			cpu-offset = <0x80000>;
 		};
 
+		tlmm_pinmux: pinmux at 800000 {
+			compatible = "qcom,apq8064-pinctrl";
+			reg = <0x800000 0x4000>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		acc0: clock-controller at 2088000 {
 			compatible = "qcom,kpss-acc-v1";
 			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
@@ -133,6 +144,48 @@
 			regulator;
 		};
 
+		gsbi1: gsbi at 12440000 {
+			status = "disabled";
+			compatible = "qcom,gsbi-v1.0.0";
+			reg = <0x12440000 0x100>;
+			clocks = <&gcc GSBI1_H_CLK>;
+			clock-names = "iface";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			i2c1: i2c at 12460000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x12460000 0x1000>;
+				interrupts = <0 194 IRQ_TYPE_NONE>;
+				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+				clock-names = "core", "iface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		gsbi2: gsbi at 12480000 {
+			status = "disabled";
+			compatible = "qcom,gsbi-v1.0.0";
+			reg = <0x12480000 0x100>;
+			clocks = <&gcc GSBI2_H_CLK>;
+			clock-names = "iface";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			i2c2: i2c at 124a0000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x124a0000 0x1000>;
+				interrupts = <0 196 IRQ_TYPE_NONE>;
+				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
+				clock-names = "core", "iface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		gsbi7: gsbi at 16600000 {
 			status = "disabled";
 			compatible = "qcom,gsbi-v1.0.0";
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* Re: [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes
  2014-08-26 11:30 ` Kiran Padwal
  (?)
@ 2014-09-16  2:39     ` Andy Gross
  -1 siblings, 0 replies; 12+ messages in thread
From: Andy Gross @ 2014-09-16  2:39 UTC (permalink / raw)
  To: Kiran Padwal
  Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, davidb-sgV2jX0FEOL9JmXXK+q4OQ,
	afaerber-l3A5Bk7waGM, devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-lFZ/pmaqli7XmaaqVzeoHQ,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA

On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
> This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
> It also adds necessary DT support for i2c eeprom which is present on
> IFC6410.
> 
> Tested on IFC6410 board.

Looks fine

> 
> Signed-off-by: Kiran Padwal <kiran.padwal-edOiRQu9Xnj5XLMNweQjbQ@public.gmane.org>
> ---
> Changes since v2:
>  - Renamed pinmux i2c subnode "i2c1_pinmux" to "i2c1".
>  - Removed labes of node.
>  - Used canonical value as "okay" instead of "ok".
>  - Used macros.
> 
> Changes since v1:
>  - Renamed pinmux phandle "qcom_pinmux" to "tlmm_pinmux".
>  - Updated pinmux interrupt.
> 
>  arch/arm/boot/dts/qcom-apq8064-ifc6410.dts |   27 ++++++++++++++
>  arch/arm/boot/dts/qcom-apq8064.dtsi        |   53 ++++++++++++++++++++++++++++
>  2 files changed, 80 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> index 7c2441d..ef0857e 100644
> --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> @@ -5,6 +5,24 @@
>  	compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
>  
>  	soc {
> +		gsbi@12440000 {
> +			status = "okay";
> +			qcom,mode = <GSBI_PROT_I2C>;
> +
> +			i2c@12460000 {
> +				status = "okay";
> +				clock-frequency = <200000>;
> +				pinctrl-0 = <&i2c1_pins>;
> +				pinctrl-names = "default";
> +
> +				eeprom: eeprom@52 {
> +					compatible = "atmel,24c128";
> +					reg = <0x52>;
> +					pagesize = <32>;
> +				};

don't need read only here.  the eeprom is not being used by anything....
thankfully.

> +			};
> +		};
> +
>  		gsbi@16600000 {
>  			status = "ok";
>  			qcom,mode = <GSBI_PROT_I2C_UART>;
> @@ -12,5 +30,14 @@
>  				status = "ok";
>  			};
>  		};
> +
> +		pinmux@800000 {
> +			i2c1_pins: i2c1 {
> +				mux {
> +					pins = "gpio20", "gpio21";
> +					function = "gsbi1";
> +				};
> +			};
> +		};
>  	};
>  };
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 92bf793..5dddbf3 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -89,6 +89,17 @@
>  			cpu-offset = <0x80000>;
>  		};
>  
> +		tlmm_pinmux: pinmux@800000 {
> +			compatible = "qcom,apq8064-pinctrl";
> +			reg = <0x800000 0x4000>;
> +
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
>  		acc0: clock-controller@2088000 {
>  			compatible = "qcom,kpss-acc-v1";
>  			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
> @@ -133,6 +144,48 @@
>  			regulator;
>  		};
>  
> +		gsbi1: gsbi@12440000 {
> +			status = "disabled";
> +			compatible = "qcom,gsbi-v1.0.0";
> +			reg = <0x12440000 0x100>;
> +			clocks = <&gcc GSBI1_H_CLK>;
> +			clock-names = "iface";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			i2c1: i2c@12460000 {
> +				compatible = "qcom,i2c-qup-v1.1.1";
> +				reg = <0x12460000 0x1000>;
> +				interrupts = <0 194 IRQ_TYPE_NONE>;
> +				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
> +				clock-names = "core", "iface";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +			};
> +		};
> +
> +		gsbi2: gsbi@12480000 {
> +			status = "disabled";
> +			compatible = "qcom,gsbi-v1.0.0";
> +			reg = <0x12480000 0x100>;
> +			clocks = <&gcc GSBI2_H_CLK>;
> +			clock-names = "iface";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			i2c2: i2c@124a0000 {
> +				compatible = "qcom,i2c-qup-v1.1.1";
> +				reg = <0x124a0000 0x1000>;
> +				interrupts = <0 196 IRQ_TYPE_NONE>;
> +				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
> +				clock-names = "core", "iface";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +			};
> +		};
> +
>  		gsbi7: gsbi@16600000 {
>  			status = "disabled";
>  			compatible = "qcom,gsbi-v1.0.0";
> -- 
> 1.7.9.5
> 
> --
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^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes
@ 2014-09-16  2:39     ` Andy Gross
  0 siblings, 0 replies; 12+ messages in thread
From: Andy Gross @ 2014-09-16  2:39 UTC (permalink / raw)
  To: Kiran Padwal
  Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, davidb,
	afaerber, devicetree, linux, linux-arm-kernel, linux-arm-msm,
	linux-kernel

On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
> This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
> It also adds necessary DT support for i2c eeprom which is present on
> IFC6410.
> 
> Tested on IFC6410 board.

Looks fine

> 
> Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
> ---
> Changes since v2:
>  - Renamed pinmux i2c subnode "i2c1_pinmux" to "i2c1".
>  - Removed labes of node.
>  - Used canonical value as "okay" instead of "ok".
>  - Used macros.
> 
> Changes since v1:
>  - Renamed pinmux phandle "qcom_pinmux" to "tlmm_pinmux".
>  - Updated pinmux interrupt.
> 
>  arch/arm/boot/dts/qcom-apq8064-ifc6410.dts |   27 ++++++++++++++
>  arch/arm/boot/dts/qcom-apq8064.dtsi        |   53 ++++++++++++++++++++++++++++
>  2 files changed, 80 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> index 7c2441d..ef0857e 100644
> --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> @@ -5,6 +5,24 @@
>  	compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
>  
>  	soc {
> +		gsbi@12440000 {
> +			status = "okay";
> +			qcom,mode = <GSBI_PROT_I2C>;
> +
> +			i2c@12460000 {
> +				status = "okay";
> +				clock-frequency = <200000>;
> +				pinctrl-0 = <&i2c1_pins>;
> +				pinctrl-names = "default";
> +
> +				eeprom: eeprom@52 {
> +					compatible = "atmel,24c128";
> +					reg = <0x52>;
> +					pagesize = <32>;
> +				};

don't need read only here.  the eeprom is not being used by anything....
thankfully.

> +			};
> +		};
> +
>  		gsbi@16600000 {
>  			status = "ok";
>  			qcom,mode = <GSBI_PROT_I2C_UART>;
> @@ -12,5 +30,14 @@
>  				status = "ok";
>  			};
>  		};
> +
> +		pinmux@800000 {
> +			i2c1_pins: i2c1 {
> +				mux {
> +					pins = "gpio20", "gpio21";
> +					function = "gsbi1";
> +				};
> +			};
> +		};
>  	};
>  };
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 92bf793..5dddbf3 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -89,6 +89,17 @@
>  			cpu-offset = <0x80000>;
>  		};
>  
> +		tlmm_pinmux: pinmux@800000 {
> +			compatible = "qcom,apq8064-pinctrl";
> +			reg = <0x800000 0x4000>;
> +
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
>  		acc0: clock-controller@2088000 {
>  			compatible = "qcom,kpss-acc-v1";
>  			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
> @@ -133,6 +144,48 @@
>  			regulator;
>  		};
>  
> +		gsbi1: gsbi@12440000 {
> +			status = "disabled";
> +			compatible = "qcom,gsbi-v1.0.0";
> +			reg = <0x12440000 0x100>;
> +			clocks = <&gcc GSBI1_H_CLK>;
> +			clock-names = "iface";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			i2c1: i2c@12460000 {
> +				compatible = "qcom,i2c-qup-v1.1.1";
> +				reg = <0x12460000 0x1000>;
> +				interrupts = <0 194 IRQ_TYPE_NONE>;
> +				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
> +				clock-names = "core", "iface";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +			};
> +		};
> +
> +		gsbi2: gsbi@12480000 {
> +			status = "disabled";
> +			compatible = "qcom,gsbi-v1.0.0";
> +			reg = <0x12480000 0x100>;
> +			clocks = <&gcc GSBI2_H_CLK>;
> +			clock-names = "iface";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			i2c2: i2c@124a0000 {
> +				compatible = "qcom,i2c-qup-v1.1.1";
> +				reg = <0x124a0000 0x1000>;
> +				interrupts = <0 196 IRQ_TYPE_NONE>;
> +				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
> +				clock-names = "core", "iface";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +			};
> +		};
> +
>  		gsbi7: gsbi@16600000 {
>  			status = "disabled";
>  			compatible = "qcom,gsbi-v1.0.0";
> -- 
> 1.7.9.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes
@ 2014-09-16  2:39     ` Andy Gross
  0 siblings, 0 replies; 12+ messages in thread
From: Andy Gross @ 2014-09-16  2:39 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
> This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
> It also adds necessary DT support for i2c eeprom which is present on
> IFC6410.
> 
> Tested on IFC6410 board.

Looks fine

> 
> Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
> ---
> Changes since v2:
>  - Renamed pinmux i2c subnode "i2c1_pinmux" to "i2c1".
>  - Removed labes of node.
>  - Used canonical value as "okay" instead of "ok".
>  - Used macros.
> 
> Changes since v1:
>  - Renamed pinmux phandle "qcom_pinmux" to "tlmm_pinmux".
>  - Updated pinmux interrupt.
> 
>  arch/arm/boot/dts/qcom-apq8064-ifc6410.dts |   27 ++++++++++++++
>  arch/arm/boot/dts/qcom-apq8064.dtsi        |   53 ++++++++++++++++++++++++++++
>  2 files changed, 80 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> index 7c2441d..ef0857e 100644
> --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> @@ -5,6 +5,24 @@
>  	compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
>  
>  	soc {
> +		gsbi at 12440000 {
> +			status = "okay";
> +			qcom,mode = <GSBI_PROT_I2C>;
> +
> +			i2c at 12460000 {
> +				status = "okay";
> +				clock-frequency = <200000>;
> +				pinctrl-0 = <&i2c1_pins>;
> +				pinctrl-names = "default";
> +
> +				eeprom: eeprom at 52 {
> +					compatible = "atmel,24c128";
> +					reg = <0x52>;
> +					pagesize = <32>;
> +				};

don't need read only here.  the eeprom is not being used by anything....
thankfully.

> +			};
> +		};
> +
>  		gsbi at 16600000 {
>  			status = "ok";
>  			qcom,mode = <GSBI_PROT_I2C_UART>;
> @@ -12,5 +30,14 @@
>  				status = "ok";
>  			};
>  		};
> +
> +		pinmux at 800000 {
> +			i2c1_pins: i2c1 {
> +				mux {
> +					pins = "gpio20", "gpio21";
> +					function = "gsbi1";
> +				};
> +			};
> +		};
>  	};
>  };
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 92bf793..5dddbf3 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -89,6 +89,17 @@
>  			cpu-offset = <0x80000>;
>  		};
>  
> +		tlmm_pinmux: pinmux at 800000 {
> +			compatible = "qcom,apq8064-pinctrl";
> +			reg = <0x800000 0x4000>;
> +
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
>  		acc0: clock-controller at 2088000 {
>  			compatible = "qcom,kpss-acc-v1";
>  			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
> @@ -133,6 +144,48 @@
>  			regulator;
>  		};
>  
> +		gsbi1: gsbi at 12440000 {
> +			status = "disabled";
> +			compatible = "qcom,gsbi-v1.0.0";
> +			reg = <0x12440000 0x100>;
> +			clocks = <&gcc GSBI1_H_CLK>;
> +			clock-names = "iface";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			i2c1: i2c at 12460000 {
> +				compatible = "qcom,i2c-qup-v1.1.1";
> +				reg = <0x12460000 0x1000>;
> +				interrupts = <0 194 IRQ_TYPE_NONE>;
> +				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
> +				clock-names = "core", "iface";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +			};
> +		};
> +
> +		gsbi2: gsbi at 12480000 {
> +			status = "disabled";
> +			compatible = "qcom,gsbi-v1.0.0";
> +			reg = <0x12480000 0x100>;
> +			clocks = <&gcc GSBI2_H_CLK>;
> +			clock-names = "iface";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			i2c2: i2c at 124a0000 {
> +				compatible = "qcom,i2c-qup-v1.1.1";
> +				reg = <0x124a0000 0x1000>;
> +				interrupts = <0 196 IRQ_TYPE_NONE>;
> +				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
> +				clock-names = "core", "iface";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +			};
> +		};
> +
>  		gsbi7: gsbi at 16600000 {
>  			status = "disabled";
>  			compatible = "qcom,gsbi-v1.0.0";
> -- 
> 1.7.9.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes
  2014-09-16  2:39     ` Andy Gross
  (?)
@ 2014-09-16 12:36         ` kiran.padwal
  -1 siblings, 0 replies; 12+ messages in thread
From: kiran.padwal-edOiRQu9Xnj5XLMNweQjbQ @ 2014-09-16 12:36 UTC (permalink / raw)
  To: Andy Gross
  Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, davidb-sgV2jX0FEOL9JmXXK+q4OQ,
	afaerber-l3A5Bk7waGM, devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-lFZ/pmaqli7XmaaqVzeoHQ,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA



On Monday, September 15, 2014 10:39pm, "Andy Gross" <agross-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> said:

> On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
>> This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
>> It also adds necessary DT support for i2c eeprom which is present on
>> IFC6410.
>>
>> Tested on IFC6410 board.
> 
> Looks fine

Thanks for review.

> 
>>
>> Signed-off-by: Kiran Padwal <kiran.padwal-edOiRQu9Xnj5XLMNweQjbQ@public.gmane.org>
>> ---
>> Changes since v2:
>>  - Renamed pinmux i2c subnode "i2c1_pinmux" to "i2c1".
>>  - Removed labes of node.
>>  - Used canonical value as "okay" instead of "ok".
>>  - Used macros.
>>
>> Changes since v1:
>>  - Renamed pinmux phandle "qcom_pinmux" to "tlmm_pinmux".
>>  - Updated pinmux interrupt.
>>
>>  arch/arm/boot/dts/qcom-apq8064-ifc6410.dts |   27 ++++++++++++++
>>  arch/arm/boot/dts/qcom-apq8064.dtsi        |   53 ++++++++++++++++++++++++++++
>>  2 files changed, 80 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
>> b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
>> index 7c2441d..ef0857e 100644
>> --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
>> +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
>> @@ -5,6 +5,24 @@
>>  	compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
>>
>>  	soc {
>> +		gsbi@12440000 {
>> +			status = "okay";
>> +			qcom,mode = <GSBI_PROT_I2C>;
>> +
>> +			i2c@12460000 {
>> +				status = "okay";
>> +				clock-frequency = <200000>;
>> +				pinctrl-0 = <&i2c1_pins>;
>> +				pinctrl-names = "default";
>> +
>> +				eeprom: eeprom@52 {
>> +					compatible = "atmel,24c128";
>> +					reg = <0x52>;
>> +					pagesize = <32>;
>> +				};
> 
> don't need read only here.  the eeprom is not being used by anything....
> thankfully.
> 
>> +			};
>> +		};
>> +
>>  		gsbi@16600000 {
>>  			status = "ok";
>>  			qcom,mode = <GSBI_PROT_I2C_UART>;
>> @@ -12,5 +30,14 @@
>>  				status = "ok";
>>  			};
>>  		};
>> +
>> +		pinmux@800000 {
>> +			i2c1_pins: i2c1 {
>> +				mux {
>> +					pins = "gpio20", "gpio21";
>> +					function = "gsbi1";
>> +				};
>> +			};
>> +		};
>>  	};
>>  };
>> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
>> b/arch/arm/boot/dts/qcom-apq8064.dtsi
>> index 92bf793..5dddbf3 100644
>> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
>> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
>> @@ -89,6 +89,17 @@
>>  			cpu-offset = <0x80000>;
>>  		};
>>
>> +		tlmm_pinmux: pinmux@800000 {
>> +			compatible = "qcom,apq8064-pinctrl";
>> +			reg = <0x800000 0x4000>;
>> +
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
>> +
>>  		acc0: clock-controller@2088000 {
>>  			compatible = "qcom,kpss-acc-v1";
>>  			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
>> @@ -133,6 +144,48 @@
>>  			regulator;
>>  		};
>>
>> +		gsbi1: gsbi@12440000 {
>> +			status = "disabled";
>> +			compatible = "qcom,gsbi-v1.0.0";
>> +			reg = <0x12440000 0x100>;
>> +			clocks = <&gcc GSBI1_H_CLK>;
>> +			clock-names = "iface";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +
>> +			i2c1: i2c@12460000 {
>> +				compatible = "qcom,i2c-qup-v1.1.1";
>> +				reg = <0x12460000 0x1000>;
>> +				interrupts = <0 194 IRQ_TYPE_NONE>;
>> +				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
>> +				clock-names = "core", "iface";
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +			};
>> +		};
>> +
>> +		gsbi2: gsbi@12480000 {
>> +			status = "disabled";
>> +			compatible = "qcom,gsbi-v1.0.0";
>> +			reg = <0x12480000 0x100>;
>> +			clocks = <&gcc GSBI2_H_CLK>;
>> +			clock-names = "iface";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +
>> +			i2c2: i2c@124a0000 {
>> +				compatible = "qcom,i2c-qup-v1.1.1";
>> +				reg = <0x124a0000 0x1000>;
>> +				interrupts = <0 196 IRQ_TYPE_NONE>;
>> +				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
>> +				clock-names = "core", "iface";
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +			};
>> +		};
>> +
>>  		gsbi7: gsbi@16600000 {
>>  			status = "disabled";
>>  			compatible = "qcom,gsbi-v1.0.0";
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
>> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> --
> sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
> 


--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes
@ 2014-09-16 12:36         ` kiran.padwal
  0 siblings, 0 replies; 12+ messages in thread
From: kiran.padwal @ 2014-09-16 12:36 UTC (permalink / raw)
  To: Andy Gross
  Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, davidb,
	afaerber, devicetree, linux, linux-arm-kernel, linux-arm-msm,
	linux-kernel



On Monday, September 15, 2014 10:39pm, "Andy Gross" <agross@codeaurora.org> said:

> On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
>> This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
>> It also adds necessary DT support for i2c eeprom which is present on
>> IFC6410.
>>
>> Tested on IFC6410 board.
> 
> Looks fine

Thanks for review.

> 
>>
>> Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
>> ---
>> Changes since v2:
>>  - Renamed pinmux i2c subnode "i2c1_pinmux" to "i2c1".
>>  - Removed labes of node.
>>  - Used canonical value as "okay" instead of "ok".
>>  - Used macros.
>>
>> Changes since v1:
>>  - Renamed pinmux phandle "qcom_pinmux" to "tlmm_pinmux".
>>  - Updated pinmux interrupt.
>>
>>  arch/arm/boot/dts/qcom-apq8064-ifc6410.dts |   27 ++++++++++++++
>>  arch/arm/boot/dts/qcom-apq8064.dtsi        |   53 ++++++++++++++++++++++++++++
>>  2 files changed, 80 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
>> b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
>> index 7c2441d..ef0857e 100644
>> --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
>> +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
>> @@ -5,6 +5,24 @@
>>  	compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
>>
>>  	soc {
>> +		gsbi@12440000 {
>> +			status = "okay";
>> +			qcom,mode = <GSBI_PROT_I2C>;
>> +
>> +			i2c@12460000 {
>> +				status = "okay";
>> +				clock-frequency = <200000>;
>> +				pinctrl-0 = <&i2c1_pins>;
>> +				pinctrl-names = "default";
>> +
>> +				eeprom: eeprom@52 {
>> +					compatible = "atmel,24c128";
>> +					reg = <0x52>;
>> +					pagesize = <32>;
>> +				};
> 
> don't need read only here.  the eeprom is not being used by anything....
> thankfully.
> 
>> +			};
>> +		};
>> +
>>  		gsbi@16600000 {
>>  			status = "ok";
>>  			qcom,mode = <GSBI_PROT_I2C_UART>;
>> @@ -12,5 +30,14 @@
>>  				status = "ok";
>>  			};
>>  		};
>> +
>> +		pinmux@800000 {
>> +			i2c1_pins: i2c1 {
>> +				mux {
>> +					pins = "gpio20", "gpio21";
>> +					function = "gsbi1";
>> +				};
>> +			};
>> +		};
>>  	};
>>  };
>> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
>> b/arch/arm/boot/dts/qcom-apq8064.dtsi
>> index 92bf793..5dddbf3 100644
>> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
>> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
>> @@ -89,6 +89,17 @@
>>  			cpu-offset = <0x80000>;
>>  		};
>>
>> +		tlmm_pinmux: pinmux@800000 {
>> +			compatible = "qcom,apq8064-pinctrl";
>> +			reg = <0x800000 0x4000>;
>> +
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
>> +
>>  		acc0: clock-controller@2088000 {
>>  			compatible = "qcom,kpss-acc-v1";
>>  			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
>> @@ -133,6 +144,48 @@
>>  			regulator;
>>  		};
>>
>> +		gsbi1: gsbi@12440000 {
>> +			status = "disabled";
>> +			compatible = "qcom,gsbi-v1.0.0";
>> +			reg = <0x12440000 0x100>;
>> +			clocks = <&gcc GSBI1_H_CLK>;
>> +			clock-names = "iface";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +
>> +			i2c1: i2c@12460000 {
>> +				compatible = "qcom,i2c-qup-v1.1.1";
>> +				reg = <0x12460000 0x1000>;
>> +				interrupts = <0 194 IRQ_TYPE_NONE>;
>> +				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
>> +				clock-names = "core", "iface";
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +			};
>> +		};
>> +
>> +		gsbi2: gsbi@12480000 {
>> +			status = "disabled";
>> +			compatible = "qcom,gsbi-v1.0.0";
>> +			reg = <0x12480000 0x100>;
>> +			clocks = <&gcc GSBI2_H_CLK>;
>> +			clock-names = "iface";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +
>> +			i2c2: i2c@124a0000 {
>> +				compatible = "qcom,i2c-qup-v1.1.1";
>> +				reg = <0x124a0000 0x1000>;
>> +				interrupts = <0 196 IRQ_TYPE_NONE>;
>> +				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
>> +				clock-names = "core", "iface";
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +			};
>> +		};
>> +
>>  		gsbi7: gsbi@16600000 {
>>  			status = "disabled";
>>  			compatible = "qcom,gsbi-v1.0.0";
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> --
> sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
> 



^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes
@ 2014-09-16 12:36         ` kiran.padwal
  0 siblings, 0 replies; 12+ messages in thread
From: kiran.padwal at smartplayin.com @ 2014-09-16 12:36 UTC (permalink / raw)
  To: linux-arm-kernel



On Monday, September 15, 2014 10:39pm, "Andy Gross" <agross@codeaurora.org> said:

> On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
>> This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
>> It also adds necessary DT support for i2c eeprom which is present on
>> IFC6410.
>>
>> Tested on IFC6410 board.
> 
> Looks fine

Thanks for review.

> 
>>
>> Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
>> ---
>> Changes since v2:
>>  - Renamed pinmux i2c subnode "i2c1_pinmux" to "i2c1".
>>  - Removed labes of node.
>>  - Used canonical value as "okay" instead of "ok".
>>  - Used macros.
>>
>> Changes since v1:
>>  - Renamed pinmux phandle "qcom_pinmux" to "tlmm_pinmux".
>>  - Updated pinmux interrupt.
>>
>>  arch/arm/boot/dts/qcom-apq8064-ifc6410.dts |   27 ++++++++++++++
>>  arch/arm/boot/dts/qcom-apq8064.dtsi        |   53 ++++++++++++++++++++++++++++
>>  2 files changed, 80 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
>> b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
>> index 7c2441d..ef0857e 100644
>> --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
>> +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
>> @@ -5,6 +5,24 @@
>>  	compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
>>
>>  	soc {
>> +		gsbi at 12440000 {
>> +			status = "okay";
>> +			qcom,mode = <GSBI_PROT_I2C>;
>> +
>> +			i2c at 12460000 {
>> +				status = "okay";
>> +				clock-frequency = <200000>;
>> +				pinctrl-0 = <&i2c1_pins>;
>> +				pinctrl-names = "default";
>> +
>> +				eeprom: eeprom at 52 {
>> +					compatible = "atmel,24c128";
>> +					reg = <0x52>;
>> +					pagesize = <32>;
>> +				};
> 
> don't need read only here.  the eeprom is not being used by anything....
> thankfully.
> 
>> +			};
>> +		};
>> +
>>  		gsbi at 16600000 {
>>  			status = "ok";
>>  			qcom,mode = <GSBI_PROT_I2C_UART>;
>> @@ -12,5 +30,14 @@
>>  				status = "ok";
>>  			};
>>  		};
>> +
>> +		pinmux at 800000 {
>> +			i2c1_pins: i2c1 {
>> +				mux {
>> +					pins = "gpio20", "gpio21";
>> +					function = "gsbi1";
>> +				};
>> +			};
>> +		};
>>  	};
>>  };
>> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
>> b/arch/arm/boot/dts/qcom-apq8064.dtsi
>> index 92bf793..5dddbf3 100644
>> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
>> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
>> @@ -89,6 +89,17 @@
>>  			cpu-offset = <0x80000>;
>>  		};
>>
>> +		tlmm_pinmux: pinmux at 800000 {
>> +			compatible = "qcom,apq8064-pinctrl";
>> +			reg = <0x800000 0x4000>;
>> +
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
>> +
>>  		acc0: clock-controller at 2088000 {
>>  			compatible = "qcom,kpss-acc-v1";
>>  			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
>> @@ -133,6 +144,48 @@
>>  			regulator;
>>  		};
>>
>> +		gsbi1: gsbi at 12440000 {
>> +			status = "disabled";
>> +			compatible = "qcom,gsbi-v1.0.0";
>> +			reg = <0x12440000 0x100>;
>> +			clocks = <&gcc GSBI1_H_CLK>;
>> +			clock-names = "iface";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +
>> +			i2c1: i2c at 12460000 {
>> +				compatible = "qcom,i2c-qup-v1.1.1";
>> +				reg = <0x12460000 0x1000>;
>> +				interrupts = <0 194 IRQ_TYPE_NONE>;
>> +				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
>> +				clock-names = "core", "iface";
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +			};
>> +		};
>> +
>> +		gsbi2: gsbi at 12480000 {
>> +			status = "disabled";
>> +			compatible = "qcom,gsbi-v1.0.0";
>> +			reg = <0x12480000 0x100>;
>> +			clocks = <&gcc GSBI2_H_CLK>;
>> +			clock-names = "iface";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +
>> +			i2c2: i2c at 124a0000 {
>> +				compatible = "qcom,i2c-qup-v1.1.1";
>> +				reg = <0x124a0000 0x1000>;
>> +				interrupts = <0 196 IRQ_TYPE_NONE>;
>> +				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
>> +				clock-names = "core", "iface";
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +			};
>> +		};
>> +
>>  		gsbi7: gsbi at 16600000 {
>>  			status = "disabled";
>>  			compatible = "qcom,gsbi-v1.0.0";
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> --
> sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
> 

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes
  2014-09-16 12:36         ` kiran.padwal
@ 2014-09-16 19:00           ` Kumar Gala
  -1 siblings, 0 replies; 12+ messages in thread
From: Kumar Gala @ 2014-09-16 19:00 UTC (permalink / raw)
  To: kiran.padwal
  Cc: Andy Gross, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	davidb, afaerber, devicetree, linux, linux-arm-kernel,
	linux-arm-msm, linux-kernel


On Sep 16, 2014, at 5:36 AM, kiran.padwal@smartplayin.com wrote:

> 
> 
> On Monday, September 15, 2014 10:39pm, "Andy Gross" <agross@codeaurora.org> said:
> 
>> On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
>>> This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
>>> It also adds necessary DT support for i2c eeprom which is present on
>>> IFC6410.
>>> 
>>> Tested on IFC6410 board.
>> 
>> Looks fine
> 
> Thanks for review.

Can you rebase this on:

 git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-dt-for-3.18

- k

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes
@ 2014-09-16 19:00           ` Kumar Gala
  0 siblings, 0 replies; 12+ messages in thread
From: Kumar Gala @ 2014-09-16 19:00 UTC (permalink / raw)
  To: linux-arm-kernel


On Sep 16, 2014, at 5:36 AM, kiran.padwal at smartplayin.com wrote:

> 
> 
> On Monday, September 15, 2014 10:39pm, "Andy Gross" <agross@codeaurora.org> said:
> 
>> On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
>>> This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
>>> It also adds necessary DT support for i2c eeprom which is present on
>>> IFC6410.
>>> 
>>> Tested on IFC6410 board.
>> 
>> Looks fine
> 
> Thanks for review.

Can you rebase this on:

 git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-dt-for-3.18

- k

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes
  2014-09-16 19:00           ` Kumar Gala
@ 2014-09-17 10:26             ` kiran.padwal at smartplayin.com
  -1 siblings, 0 replies; 12+ messages in thread
From: kiran.padwal @ 2014-09-17 10:26 UTC (permalink / raw)
  To: Kumar Gala
  Cc: Andy Gross, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	davidb, afaerber, devicetree, linux, linux-arm-kernel,
	linux-arm-msm, linux-kernel



On Tuesday, September 16, 2014 3:00pm, "Kumar Gala" <galak@codeaurora.org> said:

> 
> On Sep 16, 2014, at 5:36 AM, kiran.padwal@smartplayin.com wrote:
> 
>>
>>
>> On Monday, September 15, 2014 10:39pm, "Andy Gross" <agross@codeaurora.org>
>> said:
>>
>>> On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
>>>> This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
>>>> It also adds necessary DT support for i2c eeprom which is present on
>>>> IFC6410.
>>>>
>>>> Tested on IFC6410 board.
>>>
>>> Looks fine
>>
>> Thanks for review.
> 
> Can you rebase this on:
> 
>  git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
> tags/qcom-dt-for-3.18

Sure, I will resend this patch gain.

> 
> - k
> 
> --
> Employee of Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The
> Linux Foundation
> 
> 

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes
@ 2014-09-17 10:26             ` kiran.padwal at smartplayin.com
  0 siblings, 0 replies; 12+ messages in thread
From: kiran.padwal at smartplayin.com @ 2014-09-17 10:26 UTC (permalink / raw)
  To: linux-arm-kernel



On Tuesday, September 16, 2014 3:00pm, "Kumar Gala" <galak@codeaurora.org> said:

> 
> On Sep 16, 2014, at 5:36 AM, kiran.padwal at smartplayin.com wrote:
> 
>>
>>
>> On Monday, September 15, 2014 10:39pm, "Andy Gross" <agross@codeaurora.org>
>> said:
>>
>>> On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
>>>> This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
>>>> It also adds necessary DT support for i2c eeprom which is present on
>>>> IFC6410.
>>>>
>>>> Tested on IFC6410 board.
>>>
>>> Looks fine
>>
>> Thanks for review.
> 
> Can you rebase this on:
> 
>  git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
> tags/qcom-dt-for-3.18

Sure, I will resend this patch gain.

> 
> - k
> 
> --
> Employee of Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The
> Linux Foundation
> 
> 

^ permalink raw reply	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2014-09-17 10:26 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-08-26 11:30 [PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes Kiran Padwal
2014-08-26 11:30 ` Kiran Padwal
     [not found] ` <1409052645-14984-1-git-send-email-kiran.padwal-edOiRQu9Xnj5XLMNweQjbQ@public.gmane.org>
2014-09-16  2:39   ` Andy Gross
2014-09-16  2:39     ` Andy Gross
2014-09-16  2:39     ` Andy Gross
     [not found]     ` <20140916023922.GB2386-zC7DfRvBq/JWk0Htik3J/w@public.gmane.org>
2014-09-16 12:36       ` kiran.padwal-edOiRQu9Xnj5XLMNweQjbQ
2014-09-16 12:36         ` kiran.padwal at smartplayin.com
2014-09-16 12:36         ` kiran.padwal
2014-09-16 19:00         ` Kumar Gala
2014-09-16 19:00           ` Kumar Gala
2014-09-17 10:26           ` kiran.padwal
2014-09-17 10:26             ` kiran.padwal at smartplayin.com

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