* [PATCH] drm/radeon: save/restore the PD addr on suspend/resume
@ 2014-08-26 12:45 Christian König
2014-08-26 13:15 ` Alex Deucher
2014-08-28 3:43 ` Michel Dänzer
0 siblings, 2 replies; 4+ messages in thread
From: Christian König @ 2014-08-26 12:45 UTC (permalink / raw)
To: dri-devel
From: Christian König <christian.koenig@amd.com>
This fixes a problem with GPU resets and TLB flushes on SI/CIK.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/radeon/cik.c | 20 ++++++++++++++------
drivers/gpu/drm/radeon/ni.c | 9 ++++++++-
drivers/gpu/drm/radeon/radeon.h | 2 ++
drivers/gpu/drm/radeon/si.c | 15 +++++++++++++--
4 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index b625646..db11446 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5732,20 +5732,17 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
WREG32(0x15D8, 0);
WREG32(0x15DC, 0);
- /* empty context1-15 */
- /* FIXME start with 4G, once using 2 level pt switch to full
- * vm size space
- */
+ /* restore context1-15 */
/* set vm size, must be a multiple of 4 */
WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
for (i = 1; i < 16; i++) {
if (i < 8)
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
- rdev->gart.table_addr >> 12);
+ rdev->vm_manager.saved_table_addr[i]);
else
WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
- rdev->gart.table_addr >> 12);
+ rdev->vm_manager.saved_table_addr[i]);
}
/* enable context1-15 */
@@ -5810,6 +5807,17 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
*/
static void cik_pcie_gart_disable(struct radeon_device *rdev)
{
+ unsigned i;
+
+ for (i = 1; i < 16; ++i) {
+ uint32_t reg;
+ if (i < 8)
+ reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
+ else
+ reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
+ rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
+ }
+
/* Disable all tables */
WREG32(VM_CONTEXT0_CNTL, 0);
WREG32(VM_CONTEXT1_CNTL, 0);
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 327b85f..2959d31 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1271,7 +1271,7 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
- rdev->gart.table_addr >> 12);
+ rdev->vm_manager.saved_table_addr[i]);
}
/* enable context1-7 */
@@ -1303,6 +1303,13 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
static void cayman_pcie_gart_disable(struct radeon_device *rdev)
{
+ unsigned i;
+
+ for (i = 1; i < 8; ++i) {
+ rdev->vm_manager.saved_table_addr[i] = RREG32(
+ VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2));
+ }
+
/* Disable all tables */
WREG32(VM_CONTEXT0_CNTL, 0);
WREG32(VM_CONTEXT1_CNTL, 0);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index f2dba50..8810df3 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -918,6 +918,8 @@ struct radeon_vm_manager {
u64 vram_base_offset;
/* is vm enabled? */
bool enabled;
+ /* for hw to save the PD addr on suspend/resume */
+ uint32_t saved_table_addr[RADEON_NUM_VM];
};
/*
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 011779b..28b5f06 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -4291,10 +4291,10 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
for (i = 1; i < 16; i++) {
if (i < 8)
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
- rdev->gart.table_addr >> 12);
+ rdev->vm_manager.saved_table_addr[i]);
else
WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
- rdev->gart.table_addr >> 12);
+ rdev->vm_manager.saved_table_addr[i]);
}
/* enable context1-15 */
@@ -4326,6 +4326,17 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
static void si_pcie_gart_disable(struct radeon_device *rdev)
{
+ unsigned i;
+
+ for (i = 1; i < 16; ++i) {
+ uint32_t reg;
+ if (i < 8)
+ reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
+ else
+ reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
+ rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
+ }
+
/* Disable all tables */
WREG32(VM_CONTEXT0_CNTL, 0);
WREG32(VM_CONTEXT1_CNTL, 0);
--
1.9.1
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http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/radeon: save/restore the PD addr on suspend/resume
2014-08-26 12:45 [PATCH] drm/radeon: save/restore the PD addr on suspend/resume Christian König
@ 2014-08-26 13:15 ` Alex Deucher
2014-08-28 3:43 ` Michel Dänzer
1 sibling, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2014-08-26 13:15 UTC (permalink / raw)
To: Christian König; +Cc: Maling list - DRI developers
On Tue, Aug 26, 2014 at 8:45 AM, Christian König
<deathsimple@vodafone.de> wrote:
> From: Christian König <christian.koenig@amd.com>
>
> This fixes a problem with GPU resets and TLB flushes on SI/CIK.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Applied to my fixes tree.
Alex
> ---
> drivers/gpu/drm/radeon/cik.c | 20 ++++++++++++++------
> drivers/gpu/drm/radeon/ni.c | 9 ++++++++-
> drivers/gpu/drm/radeon/radeon.h | 2 ++
> drivers/gpu/drm/radeon/si.c | 15 +++++++++++++--
> 4 files changed, 37 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
> index b625646..db11446 100644
> --- a/drivers/gpu/drm/radeon/cik.c
> +++ b/drivers/gpu/drm/radeon/cik.c
> @@ -5732,20 +5732,17 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
> WREG32(0x15D8, 0);
> WREG32(0x15DC, 0);
>
> - /* empty context1-15 */
> - /* FIXME start with 4G, once using 2 level pt switch to full
> - * vm size space
> - */
> + /* restore context1-15 */
> /* set vm size, must be a multiple of 4 */
> WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
> WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
> for (i = 1; i < 16; i++) {
> if (i < 8)
> WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
> - rdev->gart.table_addr >> 12);
> + rdev->vm_manager.saved_table_addr[i]);
> else
> WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
> - rdev->gart.table_addr >> 12);
> + rdev->vm_manager.saved_table_addr[i]);
> }
>
> /* enable context1-15 */
> @@ -5810,6 +5807,17 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
> */
> static void cik_pcie_gart_disable(struct radeon_device *rdev)
> {
> + unsigned i;
> +
> + for (i = 1; i < 16; ++i) {
> + uint32_t reg;
> + if (i < 8)
> + reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
> + else
> + reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
> + rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
> + }
> +
> /* Disable all tables */
> WREG32(VM_CONTEXT0_CNTL, 0);
> WREG32(VM_CONTEXT1_CNTL, 0);
> diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
> index 327b85f..2959d31 100644
> --- a/drivers/gpu/drm/radeon/ni.c
> +++ b/drivers/gpu/drm/radeon/ni.c
> @@ -1271,7 +1271,7 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
> WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
> WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
> WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
> - rdev->gart.table_addr >> 12);
> + rdev->vm_manager.saved_table_addr[i]);
> }
>
> /* enable context1-7 */
> @@ -1303,6 +1303,13 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
>
> static void cayman_pcie_gart_disable(struct radeon_device *rdev)
> {
> + unsigned i;
> +
> + for (i = 1; i < 8; ++i) {
> + rdev->vm_manager.saved_table_addr[i] = RREG32(
> + VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2));
> + }
> +
> /* Disable all tables */
> WREG32(VM_CONTEXT0_CNTL, 0);
> WREG32(VM_CONTEXT1_CNTL, 0);
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index f2dba50..8810df3 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -918,6 +918,8 @@ struct radeon_vm_manager {
> u64 vram_base_offset;
> /* is vm enabled? */
> bool enabled;
> + /* for hw to save the PD addr on suspend/resume */
> + uint32_t saved_table_addr[RADEON_NUM_VM];
> };
>
> /*
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> index 011779b..28b5f06 100644
> --- a/drivers/gpu/drm/radeon/si.c
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -4291,10 +4291,10 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
> for (i = 1; i < 16; i++) {
> if (i < 8)
> WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
> - rdev->gart.table_addr >> 12);
> + rdev->vm_manager.saved_table_addr[i]);
> else
> WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
> - rdev->gart.table_addr >> 12);
> + rdev->vm_manager.saved_table_addr[i]);
> }
>
> /* enable context1-15 */
> @@ -4326,6 +4326,17 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
>
> static void si_pcie_gart_disable(struct radeon_device *rdev)
> {
> + unsigned i;
> +
> + for (i = 1; i < 16; ++i) {
> + uint32_t reg;
> + if (i < 8)
> + reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
> + else
> + reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
> + rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
> + }
> +
> /* Disable all tables */
> WREG32(VM_CONTEXT0_CNTL, 0);
> WREG32(VM_CONTEXT1_CNTL, 0);
> --
> 1.9.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
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dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/radeon: save/restore the PD addr on suspend/resume
2014-08-26 12:45 [PATCH] drm/radeon: save/restore the PD addr on suspend/resume Christian König
2014-08-26 13:15 ` Alex Deucher
@ 2014-08-28 3:43 ` Michel Dänzer
2014-08-28 8:27 ` Christian König
1 sibling, 1 reply; 4+ messages in thread
From: Michel Dänzer @ 2014-08-28 3:43 UTC (permalink / raw)
To: Christian König; +Cc: dri-devel
On 26.08.2014 21:45, Christian König wrote:
> From: Christian König <christian.koenig@amd.com>
>
> This fixes a problem with GPU resets and TLB flushes on SI/CIK.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
[...]
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index f2dba50..8810df3 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -918,6 +918,8 @@ struct radeon_vm_manager {
> u64 vram_base_offset;
> /* is vm enabled? */
> bool enabled;
> + /* for hw to save the PD addr on suspend/resume */
> + uint32_t saved_table_addr[RADEON_NUM_VM];
> };
>
> /*
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> index 011779b..28b5f06 100644
> --- a/drivers/gpu/drm/radeon/si.c
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -4291,10 +4291,10 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
> for (i = 1; i < 16; i++) {
> if (i < 8)
> WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
> - rdev->gart.table_addr >> 12);
> + rdev->vm_manager.saved_table_addr[i]);
> else
> WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
> - rdev->gart.table_addr >> 12);
> + rdev->vm_manager.saved_table_addr[i]);
> }
>
> /* enable context1-15 */
rdev->vm_manager.saved_table_addr[] doesn't get initialized before
*_gart_enable() is first called from *_startup(), does it? I guess
that's fine, but the comments in *_gart_enable() should be adapted to
this change.
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/radeon: save/restore the PD addr on suspend/resume
2014-08-28 3:43 ` Michel Dänzer
@ 2014-08-28 8:27 ` Christian König
0 siblings, 0 replies; 4+ messages in thread
From: Christian König @ 2014-08-28 8:27 UTC (permalink / raw)
To: Michel Dänzer; +Cc: dri-devel
Am 28.08.2014 um 05:43 schrieb Michel Dänzer:
> On 26.08.2014 21:45, Christian König wrote:
>> From: Christian König <christian.koenig@amd.com>
>>
>> This fixes a problem with GPU resets and TLB flushes on SI/CIK.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>
> [...]
>
>> diff --git a/drivers/gpu/drm/radeon/radeon.h
>> b/drivers/gpu/drm/radeon/radeon.h
>> index f2dba50..8810df3 100644
>> --- a/drivers/gpu/drm/radeon/radeon.h
>> +++ b/drivers/gpu/drm/radeon/radeon.h
>> @@ -918,6 +918,8 @@ struct radeon_vm_manager {
>> u64 vram_base_offset;
>> /* is vm enabled? */
>> bool enabled;
>> + /* for hw to save the PD addr on suspend/resume */
>> + uint32_t saved_table_addr[RADEON_NUM_VM];
>> };
>>
>> /*
>> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
>> index 011779b..28b5f06 100644
>> --- a/drivers/gpu/drm/radeon/si.c
>> +++ b/drivers/gpu/drm/radeon/si.c
>> @@ -4291,10 +4291,10 @@ static int si_pcie_gart_enable(struct
>> radeon_device *rdev)
>> for (i = 1; i < 16; i++) {
>> if (i < 8)
>> WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
>> - rdev->gart.table_addr >> 12);
>> + rdev->vm_manager.saved_table_addr[i]);
>> else
>> WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
>> - rdev->gart.table_addr >> 12);
>> + rdev->vm_manager.saved_table_addr[i]);
>> }
>>
>> /* enable context1-15 */
>
> rdev->vm_manager.saved_table_addr[] doesn't get initialized before
> *_gart_enable() is first called from *_startup(), does it? I guess
> that's fine, but the comments in *_gart_enable() should be adapted to
> this change.
It gets zero initialized on allocation. But your right I only updated
the code comment on CIK, not on SI and NI.
Going to fix this in a follow up patch,
Christian.
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2014-08-28 8:28 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-08-26 12:45 [PATCH] drm/radeon: save/restore the PD addr on suspend/resume Christian König
2014-08-26 13:15 ` Alex Deucher
2014-08-28 3:43 ` Michel Dänzer
2014-08-28 8:27 ` Christian König
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