From: Ian Campbell <ian.campbell@citrix.com>
To: xen-devel@lists.xen.org
Cc: julien.grall@linaro.org, tim@xen.org,
Ian Campbell <ian.campbell@citrix.com>,
stefano.stabellini@eu.citrix.com
Subject: [PATCH 3/9] xen: arm: Handle 32-bit EL0 on 64-bit EL1 when advancing PC after trap
Date: Tue, 9 Sep 2014 17:23:02 +0100 [thread overview]
Message-ID: <1410279788-27167-3-git-send-email-ian.campbell@citrix.com> (raw)
In-Reply-To: <1410279730.8217.238.camel@kazak.uk.xensource.com>
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/traps.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 1b1d29f..353e38e 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1370,7 +1370,7 @@ static int check_conditional_instr(struct cpu_user_regs *regs, union hsr hsr)
{
unsigned long it;
- BUG_ON( !is_32bit_domain(current->domain) || !(cpsr&PSR_THUMB) );
+ BUG_ON( !psr_mode_is_32bit(regs->cpsr) || !(cpsr&PSR_THUMB) );
it = ( (cpsr >> (10-2)) & 0xfc) | ((cpsr >> 25) & 0x3 );
@@ -1379,7 +1379,7 @@ static int check_conditional_instr(struct cpu_user_regs *regs, union hsr hsr)
return 1;
/* The cond for this instruction works out as the top 4 bits. */
- cond = ( it >> 4 );
+ cond = ( it >> 4 );
}
cpsr_cond = cpsr >> 28;
@@ -1395,10 +1395,10 @@ static void advance_pc(struct cpu_user_regs *regs, union hsr hsr)
unsigned long itbits, cond, cpsr = regs->cpsr;
/* PSR_IT_MASK bits can only be set for 32-bit processors in Thumb mode. */
- BUG_ON( (!is_32bit_domain(current->domain)||!(cpsr&PSR_THUMB))
+ BUG_ON( (!psr_mode_is_32bit(cpsr)||!(cpsr&PSR_THUMB))
&& (cpsr&PSR_IT_MASK) );
- if ( is_32bit_domain(current->domain) && (cpsr&PSR_IT_MASK) )
+ if ( cpsr&PSR_IT_MASK )
{
/* The ITSTATE[7:0] block is contained in CPSR[15:10],CPSR[26:25]
*
--
1.7.10.4
next prev parent reply other threads:[~2014-09-09 16:23 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-09 16:22 [RFC PATCH 0/9] xen: arm: reenable support for 32-bit userspace running in 64-bit guest Ian Campbell
2014-09-09 16:23 ` [PATCH 1/9] xen: arm: Correct PMXEV cp register definitions Ian Campbell
2014-09-09 23:04 ` Julien Grall
2014-09-09 16:23 ` [PATCH 2/9] xen: arm: Factor out psr_mode_is_user Ian Campbell
2014-09-09 23:08 ` Julien Grall
2014-09-09 16:23 ` Ian Campbell [this message]
2014-09-09 23:12 ` [PATCH 3/9] xen: arm: Handle 32-bit EL0 on 64-bit EL1 when advancing PC after trap Julien Grall
2014-09-09 16:23 ` [PATCH 4/9] xen: arm: turn vtimer traps for cp32/64 and sysreg into #undef Ian Campbell
2014-09-09 23:31 ` Julien Grall
2014-09-10 9:46 ` Ian Campbell
2014-09-10 18:54 ` Julien Grall
2014-09-11 8:43 ` Ian Campbell
2015-01-14 16:33 ` Ian Campbell
2015-01-14 16:57 ` Julien Grall
2015-01-15 10:26 ` Ian Campbell
2015-01-15 12:27 ` Julien Grall
2015-01-15 12:35 ` Ian Campbell
2014-09-09 16:23 ` [PATCH 5/9] xen: arm: Handle CP15 register traps from userspace Ian Campbell
2014-09-09 23:42 ` Julien Grall
2014-09-10 9:48 ` Ian Campbell
2014-09-10 18:56 ` Julien Grall
2014-09-18 1:31 ` Ian Campbell
2014-09-09 16:23 ` [PATCH 6/9] xen: arm: Handle CP14 32-bit register accesses " Ian Campbell
2014-09-09 23:45 ` Julien Grall
2014-09-10 9:48 ` Ian Campbell
2015-02-10 3:40 ` Ian Campbell
2015-02-10 4:14 ` Julien Grall
2014-09-09 16:23 ` [PATCH 7/9] xen: arm: correctly handle sysreg " Ian Campbell
2014-09-09 16:23 ` [PATCH 8/9] xen: arm: handle remaining traps " Ian Campbell
2014-09-09 16:23 ` [PATCH 9/9] xen: arm: Allow traps from 32 bit userspace on 64 bit hypervisors again Ian Campbell
2014-09-09 16:23 ` [RFC PATCH 0/9] xen: arm: reenable support for 32-bit userspace running in 64-bit guest Ian Campbell
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