[RFC Part2 v1 0/2] Refine the way to initialize IRQ for apb timer

[RFC Part2 v1 0/2] Refine the way to initialize IRQ for apb timer

[Jiang Liu]

Hi David and Andy,
	Could you please help to test these two patches on Intel MID
platforms? It's based on Thomas patch to refine the way to initialize
IRQ for apb timers. It should apply to the mainstream kernel.

Jiang Liu (2):
  intel_mid: Kill unused function apbt_quick_calibrate()
  intel_mid: Refine the way to initialize IRQ for apb timer

 arch/x86/include/asm/apb_timer.h        |    2 -
 arch/x86/kernel/apb_timer.c             |   79 +++++--------------------------
 arch/x86/platform/intel-mid/intel-mid.c |   18 +++----
 arch/x86/platform/intel-mid/sfi.c       |   20 ++++----
 4 files changed, 30 insertions(+), 89 deletions(-)

-- 
1.7.10.4

[RFC Part2 v1 1/2] intel_mid: Kill unused function apbt_quick_calibrate()

[Jiang Liu]

There's no user of function apbt_quick_calibrate() anymore, so kill it.

Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
---
 arch/x86/include/asm/apb_timer.h |    2 --
 arch/x86/kernel/apb_timer.c      |   53 --------------------------------------
 2 files changed, 55 deletions(-)

diff --git a/arch/x86/include/asm/apb_timer.h b/arch/x86/include/asm/apb_timer.h
index 0acbac299e49..b61a3fe15d9b 100644
--- a/arch/x86/include/asm/apb_timer.h
+++ b/arch/x86/include/asm/apb_timer.h
@@ -32,7 +32,6 @@
 #define APBT_DEV_USED  1
 
 extern void apbt_time_init(void);
-extern unsigned long apbt_quick_calibrate(void);
 extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);
 extern void apbt_setup_secondary_clock(void);
 
@@ -42,7 +41,6 @@ extern int sfi_mtimer_num;
 
 #else /* CONFIG_APB_TIMER */
 
-static inline unsigned long apbt_quick_calibrate(void) {return 0; }
 static inline void apbt_time_init(void) { }
 
 #endif
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index af5b08ab3b71..59180cd0f462 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -372,56 +372,3 @@ out_noapbt:
 	apb_timer_block_enabled = 0;
 	panic("failed to enable APB timer\n");
 }
-
-/* called before apb_timer_enable, use early map */
-unsigned long apbt_quick_calibrate(void)
-{
-	int i, scale;
-	u64 old, new;
-	cycle_t t1, t2;
-	unsigned long khz = 0;
-	u32 loop, shift;
-
-	apbt_set_mapping();
-	dw_apb_clocksource_start(clocksource_apbt);
-
-	/* check if the timer can count down, otherwise return */
-	old = dw_apb_clocksource_read(clocksource_apbt);
-	i = 10000;
-	while (--i) {
-		if (old != dw_apb_clocksource_read(clocksource_apbt))
-			break;
-	}
-	if (!i)
-		goto failed;
-
-	/* count 16 ms */
-	loop = (apbt_freq / 1000) << 4;
-
-	/* restart the timer to ensure it won't get to 0 in the calibration */
-	dw_apb_clocksource_start(clocksource_apbt);
-
-	old = dw_apb_clocksource_read(clocksource_apbt);
-	old += loop;
-
-	t1 = __native_read_tsc();
-
-	do {
-		new = dw_apb_clocksource_read(clocksource_apbt);
-	} while (new < old);
-
-	t2 = __native_read_tsc();
-
-	shift = 5;
-	if (unlikely(loop >> shift == 0)) {
-		printk(KERN_INFO
-		       "APBT TSC calibration failed, not enough resolution\n");
-		return 0;
-	}
-	scale = (int)div_u64((t2 - t1), loop >> shift);
-	khz = (scale * (apbt_freq / 1000)) >> shift;
-	printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz);
-	return khz;
-failed:
-	return 0;
-}
-- 
1.7.10.4

[RFC Part2 v1 2/2] intel_mid: Refine the way to initialize IRQ for apb timer

[Jiang Liu]

Delay initialization of APB timer 0 after irqdomains for IOAPICs
have been initialized.

Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
---
 arch/x86/kernel/apb_timer.c             |   26 +++++++++++---------------
 arch/x86/platform/intel-mid/intel-mid.c |   18 ++++++++++--------
 arch/x86/platform/intel-mid/sfi.c       |   20 +++++++++-----------
 3 files changed, 30 insertions(+), 34 deletions(-)

diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index 59180cd0f462..4222ba9296de 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -143,6 +143,13 @@ static inline int is_apbt_capable(void)
 	return apbt_virt_address ? 1 : 0;
 }
 
+static void apbt_setup_irq(struct apbt_dev *adev)
+{
+	irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
+	irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
+	__irq_set_handler(adev->irq, handle_edge_irq, 0, "edge");
+}
+
 static int __init apbt_clockevent_register(void)
 {
 	struct sfi_timer_table_entry *mtmr;
@@ -155,11 +162,12 @@ static int __init apbt_clockevent_register(void)
 		return -ENODEV;
 	}
 
-	adev->num = smp_processor_id();
+	adev->cpu = adev->num = smp_processor_id();
+	apbt_setup_irq(adev);
 	adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0",
 		intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ?
 		APBT_CLOCKEVENT_RATING - 100 : APBT_CLOCKEVENT_RATING,
-		adev_virt_addr(adev), 0, apbt_freq);
+		adev_virt_addr(adev), adev->irq, apbt_freq);
 	/* Firmware does EOI handling for us. */
 	adev->timer->eoi = NULL;
 
@@ -177,18 +185,6 @@ static int __init apbt_clockevent_register(void)
 
 #ifdef CONFIG_SMP
 
-static void apbt_setup_irq(struct apbt_dev *adev)
-{
-	/* timer0 irq has been setup early */
-	if (adev->irq == 0)
-		return;
-
-	irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
-	irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
-	/* APB timer irqs are set up as mp_irqs, timer is edge type */
-	__irq_set_handler(adev->irq, handle_edge_irq, 0, "edge");
-}
-
 /* Should be called with per cpu */
 void apbt_setup_secondary_clock(void)
 {
@@ -202,6 +198,7 @@ void apbt_setup_secondary_clock(void)
 
 	adev = &__get_cpu_var(cpu_apbt_dev);
 	if (!adev->timer) {
+		apbt_setup_irq(adev);
 		adev->timer = dw_apb_clockevent_init(cpu, adev->name,
 			APBT_CLOCKEVENT_RATING, adev_virt_addr(adev),
 			adev->irq, apbt_freq);
@@ -213,7 +210,6 @@ void apbt_setup_secondary_clock(void)
 	printk(KERN_INFO "Registering CPU %d clockevent device %s, cpu %08x\n",
 	       cpu, adev->name, adev->cpu);
 
-	apbt_setup_irq(adev);
 	dw_apb_clockevent_register(adev->timer);
 
 	return;
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 1bbedc4b0f88..9d5d841a6ae5 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -81,6 +81,12 @@ static unsigned long __init intel_mid_calibrate_tsc(void)
 	return 0;
 }
 
+static void __init intel_mid_setup_timer(void)
+{
+	apbt_time_init();
+	setup_boot_APIC_clock();
+}
+
 static void __init intel_mid_time_init(void)
 {
 	sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
@@ -88,7 +94,7 @@ static void __init intel_mid_time_init(void)
 	case INTEL_MID_TIMER_APBT_ONLY:
 		break;
 	case INTEL_MID_TIMER_LAPIC_APBT:
-		x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
+		x86_init.timers.setup_percpu_clockev = intel_mid_setup_timer;
 		x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
 		break;
 	default:
@@ -96,11 +102,8 @@ static void __init intel_mid_time_init(void)
 			break;
 		x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
 		x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
-		return;
+		break;
 	}
-	/* we need at least one APB timer */
-	pre_init_apic_IRQ0();
-	apbt_time_init();
 }
 
 static void intel_mid_arch_setup(void)
@@ -165,14 +168,13 @@ void __init x86_intel_mid_early_setup(void)
 	x86_init.resources.reserve_resources = x86_init_noop;
 
 	x86_init.timers.timer_init = intel_mid_time_init;
-	x86_init.timers.setup_percpu_clockev = x86_init_noop;
+	x86_init.timers.setup_percpu_clockev = apbt_time_init;
+	x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
 
 	x86_init.irqs.pre_vector_init = x86_init_noop;
 
 	x86_init.oem.arch_setup = intel_mid_arch_setup;
 
-	x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
-
 	x86_platform.calibrate_tsc = intel_mid_calibrate_tsc;
 	x86_platform.i8042_detect = intel_mid_i8042_detect;
 	x86_init.timers.wallclock_init = intel_mid_rtc_init;
diff --git a/arch/x86/platform/intel-mid/sfi.c b/arch/x86/platform/intel-mid/sfi.c
index 3c53a90fdb18..1c012fc8373c 100644
--- a/arch/x86/platform/intel-mid/sfi.c
+++ b/arch/x86/platform/intel-mid/sfi.c
@@ -95,17 +95,15 @@ int __init sfi_parse_mtmr(struct sfi_table_header *table)
 		pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz, irq = %d\n",
 			totallen, (u32)pentry->phys_addr,
 			pentry->freq_hz, pentry->irq);
-			if (!pentry->irq)
-				continue;
-			mp_irq.type = MP_INTSRC;
-			mp_irq.irqtype = mp_INT;
-/* triggering mode edge bit 2-3, active high polarity bit 0-1 */
-			mp_irq.irqflag = 5;
-			mp_irq.srcbus = MP_BUS_ISA;
-			mp_irq.srcbusirq = pentry->irq;	/* IRQ */
-			mp_irq.dstapic = MP_APIC_ALL;
-			mp_irq.dstirq = pentry->irq;
-			mp_save_irq(&mp_irq);
+		mp_irq.type = MP_INTSRC;
+		mp_irq.irqtype = mp_INT;
+		/* triggering mode edge bit 2-3, active high polarity bit 0-1 */
+		mp_irq.irqflag = 5;
+		mp_irq.srcbus = MP_BUS_ISA;
+		mp_irq.srcbusirq = pentry->irq;	/* IRQ */
+		mp_irq.dstapic = MP_APIC_ALL;
+		mp_irq.dstirq = pentry->irq;
+		mp_save_irq(&mp_irq);
 	}
 
 	return 0;
-- 
1.7.10.4

Re: [RFC Part2 v1 0/2] Refine the way to initialize IRQ for apb timer

[Andy Shevchenko]

On Fri, 2014-09-12 at 16:20 +0800, Jiang Liu wrote:
> Hi David and Andy,
> 	Could you please help to test these two patches on Intel MID
> platforms? It's based on Thomas patch to refine the way to initialize
> IRQ for apb timers. It should apply to the mainstream kernel.
> 

1) clean command line — OK

2) x86_intel_mid_timer=apbt_only — HANGS in the same place as w/o
Thomas' patch (see my last mail), but no warnings are printed

3) x86_intel_mid_timer=lapic_and_apbt — HANGS: same as above which is
differs to the same conditions w/o any patches (yours and Thomas')


> Jiang Liu (2):
>   intel_mid: Kill unused function apbt_quick_calibrate()
>   intel_mid: Refine the way to initialize IRQ for apb timer
> 
>  arch/x86/include/asm/apb_timer.h        |    2 -
>  arch/x86/kernel/apb_timer.c             |   79 +++++--------------------------
>  arch/x86/platform/intel-mid/intel-mid.c |   18 +++----
>  arch/x86/platform/intel-mid/sfi.c       |   20 ++++----
>  4 files changed, 30 insertions(+), 89 deletions(-)
> 


-- 
Andy Shevchenko <andriy.shevchenko@intel.com>
Intel Finland Oy