All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids
@ 2014-09-26 13:19 Damien Lespiau
  2014-09-26 13:19 ` [PATCH libdrm 2/3] intel/skl: Add gen9 to the buffer manager init Damien Lespiau
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Damien Lespiau @ 2014-09-26 13:19 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

v2: Add more PCI IDs (Michael H. Nguyen)
v3: Synchronize one more with the kernel PCI IDs (Damien)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Michael H. Nguyen <michael.h.nguyen@intel.com>
---
 intel/intel_chipset.h | 43 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 6f9bfad..e22a867 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -165,6 +165,22 @@
 #define PCI_CHIP_CHERRYVIEW_2		0x22b2
 #define PCI_CHIP_CHERRYVIEW_3		0x22b3
 
+#define PCI_CHIP_SKYLAKE_ULT_GT2	0x1916
+#define PCI_CHIP_SKYLAKE_ULT_GT1	0x1906
+#define PCI_CHIP_SKYLAKE_ULT_GT3	0x1926
+#define PCI_CHIP_SKYLAKE_ULT_GT2F	0x1921
+#define PCI_CHIP_SKYLAKE_ULX_GT1	0x190E
+#define PCI_CHIP_SKYLAKE_ULX_GT2	0x191E
+#define PCI_CHIP_SKYLAKE_DT_GT2		0x1912
+#define PCI_CHIP_SKYLAKE_DT_GT1		0x1902
+#define PCI_CHIP_SKYLAKE_HALO_GT2	0x191B
+#define PCI_CHIP_SKYLAKE_HALO_GT3	0x192B
+#define PCI_CHIP_SKYLAKE_HALO_GT1 	0x190B
+#define PCI_CHIP_SKYLAKE_SRV_GT2	0x191A
+#define PCI_CHIP_SKYLAKE_SRV_GT3	0x192A
+#define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A
+#define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
+
 #define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \
 				 (devid) == PCI_CHIP_I915_GM || \
 				 (devid) == PCI_CHIP_I945_GM || \
@@ -324,12 +340,37 @@
 #define IS_GEN8(devid)		(IS_BROADWELL(devid) || \
 				 IS_CHERRYVIEW(devid))
 
+#define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
+
+#define IS_SKL_GT2(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT2	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_DT_GT2	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
+
+#define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT3	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
+
+#define IS_SKYLAKE(devid)	(IS_SKL_GT1(devid) || \
+				 IS_SKL_GT2(devid) || \
+				 IS_SKL_GT3(devid))
+
+#define IS_GEN9(devid)		IS_SKYLAKE(devid)
+
 #define IS_9XX(dev)		(IS_GEN3(dev) || \
 				 IS_GEN4(dev) || \
 				 IS_GEN5(dev) || \
 				 IS_GEN6(dev) || \
 				 IS_GEN7(dev) || \
-				 IS_GEN8(dev))
+				 IS_GEN8(dev) || \
+				 IS_GEN9(dev))
 
 
 #endif /* _INTEL_CHIPSET_H */
-- 
1.8.3.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH libdrm 2/3] intel/skl: Add gen9 to the buffer manager init
  2014-09-26 13:19 [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids Damien Lespiau
@ 2014-09-26 13:19 ` Damien Lespiau
  2014-09-26 13:19 ` [PATCH libdrm 3/3] intel/skl: add gen9 to the CS decoding init Damien Lespiau
  2014-09-30 10:19 ` [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids Thomas Wood
  2 siblings, 0 replies; 5+ messages in thread
From: Damien Lespiau @ 2014-09-26 13:19 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 intel/intel_bufmgr_gem.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index ba65527..a6fa224 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3479,6 +3479,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
 		bufmgr_gem->gen = 7;
 	else if (IS_GEN8(bufmgr_gem->pci_device))
 		bufmgr_gem->gen = 8;
+	else if (IS_GEN9(bufmgr_gem->pci_device))
+		bufmgr_gem->gen = 9;
 	else {
 		free(bufmgr_gem);
 		bufmgr_gem = NULL;
-- 
1.8.3.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH libdrm 3/3] intel/skl: add gen9 to the CS decoding init
  2014-09-26 13:19 [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids Damien Lespiau
  2014-09-26 13:19 ` [PATCH libdrm 2/3] intel/skl: Add gen9 to the buffer manager init Damien Lespiau
@ 2014-09-26 13:19 ` Damien Lespiau
  2014-09-30 10:19 ` [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids Thomas Wood
  2 siblings, 0 replies; 5+ messages in thread
From: Damien Lespiau @ 2014-09-26 13:19 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 intel/intel_decode.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index a5d6e04..7d5cbe5 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -3829,7 +3829,9 @@ drm_intel_decode_context_alloc(uint32_t devid)
 	ctx->devid = devid;
 	ctx->out = stdout;
 
-	if (IS_GEN8(devid))
+	if (IS_GEN9(devid))
+		ctx->gen = 9;
+	else if (IS_GEN8(devid))
 		ctx->gen = 8;
 	else if (IS_GEN7(devid))
 		ctx->gen = 7;
-- 
1.8.3.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids
  2014-09-26 13:19 [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids Damien Lespiau
  2014-09-26 13:19 ` [PATCH libdrm 2/3] intel/skl: Add gen9 to the buffer manager init Damien Lespiau
  2014-09-26 13:19 ` [PATCH libdrm 3/3] intel/skl: add gen9 to the CS decoding init Damien Lespiau
@ 2014-09-30 10:19 ` Thomas Wood
  2014-09-30 11:20   ` Damien Lespiau
  2 siblings, 1 reply; 5+ messages in thread
From: Thomas Wood @ 2014-09-30 10:19 UTC (permalink / raw)
  To: Damien Lespiau; +Cc: Intel Graphics Development, dri-devel

On 26 September 2014 14:19, Damien Lespiau <damien.lespiau@intel.com> wrote:
> v2: Add more PCI IDs (Michael H. Nguyen)
> v3: Synchronize one more with the kernel PCI IDs (Damien)
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> Signed-off-by: Michael H. Nguyen <michael.h.nguyen@intel.com>

Reviewed-by: Thomas Wood <thomas.wood@intel.com>

> ---
>  intel/intel_chipset.h | 43 ++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 42 insertions(+), 1 deletion(-)
>
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index 6f9bfad..e22a867 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -165,6 +165,22 @@
>  #define PCI_CHIP_CHERRYVIEW_2          0x22b2
>  #define PCI_CHIP_CHERRYVIEW_3          0x22b3
>
> +#define PCI_CHIP_SKYLAKE_ULT_GT2       0x1916
> +#define PCI_CHIP_SKYLAKE_ULT_GT1       0x1906
> +#define PCI_CHIP_SKYLAKE_ULT_GT3       0x1926
> +#define PCI_CHIP_SKYLAKE_ULT_GT2F      0x1921
> +#define PCI_CHIP_SKYLAKE_ULX_GT1       0x190E
> +#define PCI_CHIP_SKYLAKE_ULX_GT2       0x191E
> +#define PCI_CHIP_SKYLAKE_DT_GT2                0x1912
> +#define PCI_CHIP_SKYLAKE_DT_GT1                0x1902
> +#define PCI_CHIP_SKYLAKE_HALO_GT2      0x191B
> +#define PCI_CHIP_SKYLAKE_HALO_GT3      0x192B
> +#define PCI_CHIP_SKYLAKE_HALO_GT1      0x190B
> +#define PCI_CHIP_SKYLAKE_SRV_GT2       0x191A
> +#define PCI_CHIP_SKYLAKE_SRV_GT3       0x192A
> +#define PCI_CHIP_SKYLAKE_SRV_GT1       0x190A
> +#define PCI_CHIP_SKYLAKE_WKS_GT2       0x191D
> +
>  #define IS_MOBILE(devid)       ((devid) == PCI_CHIP_I855_GM || \
>                                  (devid) == PCI_CHIP_I915_GM || \
>                                  (devid) == PCI_CHIP_I945_GM || \
> @@ -324,12 +340,37 @@
>  #define IS_GEN8(devid)         (IS_BROADWELL(devid) || \
>                                  IS_CHERRYVIEW(devid))
>
> +#define IS_SKL_GT1(devid)      ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1    || \
> +                                (devid) == PCI_CHIP_SKYLAKE_ULX_GT1    || \
> +                                (devid) == PCI_CHIP_SKYLAKE_DT_GT1     || \
> +                                (devid) == PCI_CHIP_SKYLAKE_HALO_GT1   || \
> +                                (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
> +
> +#define IS_SKL_GT2(devid)      ((devid) == PCI_CHIP_SKYLAKE_ULT_GT2    || \
> +                                (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F   || \
> +                                (devid) == PCI_CHIP_SKYLAKE_ULX_GT2    || \
> +                                (devid) == PCI_CHIP_SKYLAKE_DT_GT2     || \
> +                                (devid) == PCI_CHIP_SKYLAKE_HALO_GT2   || \
> +                                (devid) == PCI_CHIP_SKYLAKE_SRV_GT2    || \
> +                                (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
> +
> +#define IS_SKL_GT3(devid)      ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3    || \
> +                                (devid) == PCI_CHIP_SKYLAKE_HALO_GT3   || \
> +                                (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
> +
> +#define IS_SKYLAKE(devid)      (IS_SKL_GT1(devid) || \
> +                                IS_SKL_GT2(devid) || \
> +                                IS_SKL_GT3(devid))
> +
> +#define IS_GEN9(devid)         IS_SKYLAKE(devid)
> +
>  #define IS_9XX(dev)            (IS_GEN3(dev) || \
>                                  IS_GEN4(dev) || \
>                                  IS_GEN5(dev) || \
>                                  IS_GEN6(dev) || \
>                                  IS_GEN7(dev) || \
> -                                IS_GEN8(dev))
> +                                IS_GEN8(dev) || \
> +                                IS_GEN9(dev))
>
>
>  #endif /* _INTEL_CHIPSET_H */
> --
> 1.8.3.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids
  2014-09-30 10:19 ` [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids Thomas Wood
@ 2014-09-30 11:20   ` Damien Lespiau
  0 siblings, 0 replies; 5+ messages in thread
From: Damien Lespiau @ 2014-09-30 11:20 UTC (permalink / raw)
  To: Thomas Wood; +Cc: Intel Graphics Development, dri-devel

On Tue, Sep 30, 2014 at 11:19:37AM +0100, Thomas Wood wrote:
> On 26 September 2014 14:19, Damien Lespiau <damien.lespiau@intel.com> wrote:
> > v2: Add more PCI IDs (Michael H. Nguyen)
> > v3: Synchronize one more with the kernel PCI IDs (Damien)
> >
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> > Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> > Signed-off-by: Michael H. Nguyen <michael.h.nguyen@intel.com>
> 
> Reviewed-by: Thomas Wood <thomas.wood@intel.com>

Thanks for the review, pushed the whole series (the other two patches
where already reviewed).

-- 
Damien

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2014-09-30 11:20 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-09-26 13:19 [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids Damien Lespiau
2014-09-26 13:19 ` [PATCH libdrm 2/3] intel/skl: Add gen9 to the buffer manager init Damien Lespiau
2014-09-26 13:19 ` [PATCH libdrm 3/3] intel/skl: add gen9 to the CS decoding init Damien Lespiau
2014-09-30 10:19 ` [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids Thomas Wood
2014-09-30 11:20   ` Damien Lespiau

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.