[PATCH 0/5] drm/i915: Random pile of VLV/CHV fixes

[PATCH 0/5] drm/i915: Random pile of VLV/CHV fixes

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I've been staring at the VLV/CHV code a lot lately and I spotted several
small issues here and there. A few of those are bugs I myself created by
acciend. This series fixes those.

I also included a patch to program some new plane/pipe registers on CHV
which are needed to get any kind of sane picture on the screen from pipe B.

Ville Syrjälä (5):
  drm/i915: Don't claim that we're resetting PCH ADPA register
  drm/i915: Fix GMBUSFREQ on vlv/chv
  drm/i915: Fix chv PCS DW11 register defines
  drm/i915: Do vlv cmnlane toggle w/a in more cases
  drm/i915: Initialize new chv primary plane and pipe blender registers

 drivers/gpu/drm/i915/i915_reg.h         | 29 ++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_crt.c        |  2 +-
 drivers/gpu/drm/i915/intel_display.c    | 15 ++++++++++++++-
 drivers/gpu/drm/i915/intel_runtime_pm.c |  7 ++-----
 drivers/gpu/drm/i915/intel_sprite.c     |  2 ++
 5 files changed, 45 insertions(+), 10 deletions(-)

-- 
2.0.4

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[PATCH 1/5] drm/i915: Don't claim that we're resetting PCH ADPA register

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_crt_reset() resets the ADPA register on all gen5+ platforms.
However the debug message claims it's touching the PCH ADPA register
which is clearly not what it does on VLV. Drop the PCH part from
the debug message.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index dacaad5..a9af9a4 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -775,7 +775,7 @@ static void intel_crt_reset(struct drm_connector *connector)
 		I915_WRITE(crt->adpa_reg, adpa);
 		POSTING_READ(crt->adpa_reg);
 
-		DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
+		DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 		crt->force_hotplug_required = 1;
 	}
 
-- 
2.0.4

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[PATCH 2/5] drm/i915: Fix GMBUSFREQ on vlv/chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

vlv_cdclk_freq is in kHz but we need MHz for the GMBUSFREQ divider.

This is a regression from:
 commit f8bf63fdcb1f82459dae7a3f22ee5ce92f3ea727
 Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
 Date:   Fri Jun 13 13:37:54 2014 +0300

    drm/i915: Kill duplicated cdclk readout code from i2c

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6e6f150..18b493f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4628,7 +4628,7 @@ static void vlv_update_cdclk(struct drm_device *dev)
 	 * BSpec erroneously claims we should aim for 4MHz, but
 	 * in fact 1MHz is the correct frequency.
 	 */
-	I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
+	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
 }
 
 /* Adjust CDclk dividers to allow high res or save power if possible */
-- 
2.0.4

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[PATCH 3/5] drm/i915: Fix chv PCS DW11 register defines

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I managed to fumble the per spline PCS DW11 register defines in:
 commit 9d4f193b077c1973add53e40ff9410a3371900af
 Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
 Date:   Thu Jun 26 13:47:19 2014 +0300

    drm/i915: Clear TX FIFO reset master override bits on chv

Fortunately the bit in DW0 that was cleared due to this didn't have
any effect as long as the bit we meant to clear was already zero.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6db369a..46cfbc7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -883,8 +883,8 @@ enum punit_power_well {
 #define _VLV_PCS23_DW11_CH0		0x042c
 #define _VLV_PCS01_DW11_CH1		0x262c
 #define _VLV_PCS23_DW11_CH1		0x282c
-#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
-#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
+#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
+#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
 
 #define _VLV_PCS_DW12_CH0		0x8230
 #define _VLV_PCS_DW12_CH1		0x8430
-- 
2.0.4

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[PATCH 4/5] drm/i915: Do vlv cmnlane toggle w/a in more cases

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In case the cmnlane power well is down but cmnreset isn't asserted we
would currently skip the off+on toggle for the power well. That could
leave cmnreset deasserted while cmnlane is powered down which might
lead to problems with the PHY.

To avoid such issues skip the cmnlane toggle only if both cmnlane and
disp2d wells are up and cmnreset is already deasserted. In all other
cases power down the cmnlane well which will also make sure cmnreset
gets asserted correctly while cmnlane is powered down.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 36749b9..f6b4e8d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1137,12 +1137,9 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
 	struct i915_power_well *disp2d =
 		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
 
-	/* nothing to do if common lane is already off */
-	if (!cmn->ops->is_enabled(dev_priv, cmn))
-		return;
-
 	/* If the display might be already active skip this */
-	if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
+	if (cmn->ops->is_enabled(dev_priv, cmn) &&
+	    disp2d->ops->is_enabled(dev_priv, disp2d) &&
 	    I915_READ(DPIO_CTL) & DPIO_CMNRST)
 		return;
 
-- 
2.0.4

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[PATCH 5/5] drm/i915: Initialize new chv primary plane and pipe blender registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV adds a bunch of new registers for primary plane size/position and
pipe blender setup. Initialize all those registers to avoid nasty
surprises. PRIMSIZE is especially important as without programming it
the outout will be garbled whenever the primary plane size would not
match what the BIOS set up.

Also program the sprite constant alpha register to disable the constant
alpha blending factor. This applies to vlv as well as chv.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 25 ++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  |  2 ++
 3 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 46cfbc7..c5c3b70 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4270,9 +4270,11 @@ enum punit_power_well {
 #define   DISPPLANE_NO_LINE_DOUBLE		0
 #define   DISPPLANE_STEREO_POLARITY_FIRST	0
 #define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
-#define   DISPPLANE_ROTATE_180         (1<<15)
+#define   DISPPLANE_ALPHA_PREMULTIPLY		(1<<16) /* CHV pipe B */
+#define   DISPPLANE_ROTATE_180			(1<<15)
 #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
 #define   DISPPLANE_TILED			(1<<10)
+#define   DISPPLANE_MIRROR			(1<<8) /* CHV pipe B */
 #define _DSPAADDR				0x70184
 #define _DSPASTRIDE				0x70188
 #define _DSPAPOS				0x7018C /* reserved */
@@ -4293,6 +4295,24 @@ enum punit_power_well {
 #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
 #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
 
+/* CHV pipe B blender and primary plane */
+#define _CHV_BLEND_A		0x60a00
+#define   CHV_BLEND_LEGACY		(0<<30)
+#define   CHV_BLEND_ANDROID		(1<<30)
+#define   CHV_BLEND_MPO			(2<<30)
+#define   CHV_BLEND_MASK		(3<<30)
+#define _CHV_CANVAS_A		0x60a04
+#define _PRIMPOS_A		0x60a08
+#define _PRIMSIZE_A		0x60a0c
+#define _PRIMCNSTALPHA_A	0x60a10
+#define   PRIM_CONST_ALPHA_ENABLE	(1<<31)
+
+#define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
+#define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
+#define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
+#define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
+#define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
+
 /* Display/Sprite base address macros */
 #define DISP_BASEADDR_MASK	(0xfffff000)
 #define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
@@ -4494,6 +4514,7 @@ enum punit_power_well {
 #define   SP_FORMAT_RGBA1010102		(9<<26)
 #define   SP_FORMAT_RGBX8888		(0xe<<26)
 #define   SP_FORMAT_RGBA8888		(0xf<<26)
+#define   SP_ALPHA_PREMULTIPLY		(1<<23) /* CHV pipe B */
 #define   SP_SOURCE_KEY			(1<<22)
 #define   SP_YUV_BYTE_ORDER_MASK	(3<<16)
 #define   SP_YUV_ORDER_YUYV		(0<<16)
@@ -4502,6 +4523,7 @@ enum punit_power_well {
 #define   SP_YUV_ORDER_VYUY		(3<<16)
 #define   SP_ROTATE_180			(1<<15)
 #define   SP_TILED			(1<<10)
+#define   SP_MIRROR			(1<<8) /* CHV pipe B */
 #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
 #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
 #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
@@ -4512,6 +4534,7 @@ enum punit_power_well {
 #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
 #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
 #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
+#define   SP_CONST_ALPHA_ENABLE		(1<<31)
 #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721f4)
 
 #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 18b493f..d901961 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2443,6 +2443,12 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 			   ((intel_crtc->config.pipe_src_h - 1) << 16) |
 			   (intel_crtc->config.pipe_src_w - 1));
 		I915_WRITE(DSPPOS(plane), 0);
+	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
+		I915_WRITE(PRIMSIZE(plane),
+			   ((intel_crtc->config.pipe_src_h - 1) << 16) |
+			   (intel_crtc->config.pipe_src_w - 1));
+		I915_WRITE(PRIMPOS(plane), 0);
+		I915_WRITE(PRIMCNSTALPHA(plane), 0);
 	}
 
 	switch (fb->pixel_format) {
@@ -4848,6 +4854,13 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	intel_set_pipe_timings(intel_crtc);
 
+	if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
+		struct drm_i915_private *dev_priv = dev->dev_private;
+
+		I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
+		I915_WRITE(CHV_CANVAS(pipe), 0);
+	}
+
 	i9xx_set_pipeconf(intel_crtc);
 
 	intel_crtc->active = true;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 2c060ad..a452819 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -438,6 +438,8 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	else
 		I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 
+	I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
+
 	I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 	I915_WRITE(SPCNTR(pipe, plane), sprctl);
 	I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
-- 
2.0.4

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Re: [PATCH 1/5] drm/i915: Don't claim that we're resetting PCH ADPA register

[Jani Nikula]

On Thu, 16 Oct 2014, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_crt_reset() resets the ADPA register on all gen5+ platforms.
> However the debug message claims it's touching the PCH ADPA register
> which is clearly not what it does on VLV. Drop the PCH part from
> the debug message.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_crt.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index dacaad5..a9af9a4 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -775,7 +775,7 @@ static void intel_crt_reset(struct drm_connector *connector)
>  		I915_WRITE(crt->adpa_reg, adpa);
>  		POSTING_READ(crt->adpa_reg);
>  
> -		DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
> +		DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
>  		crt->force_hotplug_required = 1;
>  	}
>  
> -- 
> 2.0.4
>
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-- 
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Re: [PATCH 2/5] drm/i915: Fix GMBUSFREQ on vlv/chv

[Jani Nikula]

On Thu, 16 Oct 2014, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> vlv_cdclk_freq is in kHz but we need MHz for the GMBUSFREQ divider.
>
> This is a regression from:
>  commit f8bf63fdcb1f82459dae7a3f22ee5ce92f3ea727
>  Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
>  Date:   Fri Jun 13 13:37:54 2014 +0300
>
>     drm/i915: Kill duplicated cdclk readout code from i2c
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6e6f150..18b493f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4628,7 +4628,7 @@ static void vlv_update_cdclk(struct drm_device *dev)
>  	 * BSpec erroneously claims we should aim for 4MHz, but
>  	 * in fact 1MHz is the correct frequency.
>  	 */
> -	I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
> +	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
>  }
>  
>  /* Adjust CDclk dividers to allow high res or save power if possible */
> -- 
> 2.0.4
>
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 2/5] drm/i915: Fix GMBUSFREQ on vlv/chv

[Jani Nikula]

On Thu, 16 Oct 2014, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> vlv_cdclk_freq is in kHz but we need MHz for the GMBUSFREQ divider.
>
> This is a regression from:
>  commit f8bf63fdcb1f82459dae7a3f22ee5ce92f3ea727
>  Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
>  Date:   Fri Jun 13 13:37:54 2014 +0300
>
>     drm/i915: Kill duplicated cdclk readout code from i2c
>

cc: stable

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6e6f150..18b493f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4628,7 +4628,7 @@ static void vlv_update_cdclk(struct drm_device *dev)
>  	 * BSpec erroneously claims we should aim for 4MHz, but
>  	 * in fact 1MHz is the correct frequency.
>  	 */
> -	I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
> +	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
>  }
>  
>  /* Adjust CDclk dividers to allow high res or save power if possible */
> -- 
> 2.0.4
>
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 3/5] drm/i915: Fix chv PCS DW11 register defines

[Jani Nikula]

On Thu, 16 Oct 2014, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I managed to fumble the per spline PCS DW11 register defines in:
>  commit 9d4f193b077c1973add53e40ff9410a3371900af

Looks like commit 570e2a747bc06cd8620662c5125ec2dc964c511b in my repo.

>  Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
>  Date:   Thu Jun 26 13:47:19 2014 +0300
>
>     drm/i915: Clear TX FIFO reset master override bits on chv
>
> Fortunately the bit in DW0 that was cleared due to this didn't have
> any effect as long as the bit we meant to clear was already zero.

I did not have a spec handy, so I didn't check the regs, but clearly the
DW11 macro referencing other DW11 macros instead of DW0 makes sense.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6db369a..46cfbc7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -883,8 +883,8 @@ enum punit_power_well {
>  #define _VLV_PCS23_DW11_CH0		0x042c
>  #define _VLV_PCS01_DW11_CH1		0x262c
>  #define _VLV_PCS23_DW11_CH1		0x282c
> -#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> -#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> +#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
> +#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
>  
>  #define _VLV_PCS_DW12_CH0		0x8230
>  #define _VLV_PCS_DW12_CH1		0x8430
> -- 
> 2.0.4
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 3/5] drm/i915: Fix chv PCS DW11 register defines

[Daniel Vetter]

On Fri, Oct 17, 2014 at 12:08:38PM +0300, Jani Nikula wrote:
> On Thu, 16 Oct 2014, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > I managed to fumble the per spline PCS DW11 register defines in:
> >  commit 9d4f193b077c1973add53e40ff9410a3371900af
> 
> Looks like commit 570e2a747bc06cd8620662c5125ec2dc964c511b in my repo.

Fixed.
> 
> >  Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >  Date:   Thu Jun 26 13:47:19 2014 +0300
> >
> >     drm/i915: Clear TX FIFO reset master override bits on chv
> >
> > Fortunately the bit in DW0 that was cleared due to this didn't have
> > any effect as long as the bit we meant to clear was already zero.
> 
> I did not have a spec handy, so I didn't check the regs, but clearly the
> DW11 macro referencing other DW11 macros instead of DW0 makes sense.
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Merged this and patch 1 to dinq, patch 2 indeed looks a bit more like
-fixes material.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 2/5] drm/i915: Fix GMBUSFREQ on vlv/chv

[Jani Nikula]

On Fri, 17 Oct 2014, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Thu, 16 Oct 2014, ville.syrjala@linux.intel.com wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> vlv_cdclk_freq is in kHz but we need MHz for the GMBUSFREQ divider.
>>
>> This is a regression from:
>>  commit f8bf63fdcb1f82459dae7a3f22ee5ce92f3ea727
>>  Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>  Date:   Fri Jun 13 13:37:54 2014 +0300
>>
>>     drm/i915: Kill duplicated cdclk readout code from i2c
>>
>
> cc: stable
>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pushed to drm-intel-fixes, thanks for the patch.

BR,
Jani.

-- 
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Re: [PATCH 4/5] drm/i915: Do vlv cmnlane toggle w/a in more cases

[Jesse Barnes]

On Thu, 16 Oct 2014 20:52:33 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> In case the cmnlane power well is down but cmnreset isn't asserted we
> would currently skip the off+on toggle for the power well. That could
> leave cmnreset deasserted while cmnlane is powered down which might
> lead to problems with the PHY.
> 
> To avoid such issues skip the cmnlane toggle only if both cmnlane and
> disp2d wells are up and cmnreset is already deasserted. In all other
> cases power down the cmnlane well which will also make sure cmnreset
> gets asserted correctly while cmnlane is powered down.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c index 36749b9..f6b4e8d
> 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1137,12 +1137,9 @@ static void vlv_cmnlane_wa(struct
> drm_i915_private *dev_priv) struct i915_power_well *disp2d =
>  		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
>  
> -	/* nothing to do if common lane is already off */
> -	if (!cmn->ops->is_enabled(dev_priv, cmn))
> -		return;
> -
>  	/* If the display might be already active skip this */
> -	if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
> +	if (cmn->ops->is_enabled(dev_priv, cmn) &&
> +	    disp2d->ops->is_enabled(dev_priv, disp2d) &&
>  	    I915_READ(DPIO_CTL) & DPIO_CMNRST)
>  		return;
>  


Yeah looks ok.  Do we have any bugs we know this fixes?  I'm hoping the
remaining VLV DP training failures are fixed either by something like
this or your panel power sequencer fixes.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 4/5] drm/i915: Do vlv cmnlane toggle w/a in more cases

[Ville Syrjälä]

On Tue, Oct 28, 2014 at 10:57:38AM -0700, Jesse Barnes wrote:
> On Thu, 16 Oct 2014 20:52:33 +0300
> ville.syrjala@linux.intel.com wrote:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > In case the cmnlane power well is down but cmnreset isn't asserted we
> > would currently skip the off+on toggle for the power well. That could
> > leave cmnreset deasserted while cmnlane is powered down which might
> > lead to problems with the PHY.
> > 
> > To avoid such issues skip the cmnlane toggle only if both cmnlane and
> > disp2d wells are up and cmnreset is already deasserted. In all other
> > cases power down the cmnlane well which will also make sure cmnreset
> > gets asserted correctly while cmnlane is powered down.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ++-----
> >  1 file changed, 2 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c index 36749b9..f6b4e8d
> > 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -1137,12 +1137,9 @@ static void vlv_cmnlane_wa(struct
> > drm_i915_private *dev_priv) struct i915_power_well *disp2d =
> >  		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
> >  
> > -	/* nothing to do if common lane is already off */
> > -	if (!cmn->ops->is_enabled(dev_priv, cmn))
> > -		return;
> > -
> >  	/* If the display might be already active skip this */
> > -	if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
> > +	if (cmn->ops->is_enabled(dev_priv, cmn) &&
> > +	    disp2d->ops->is_enabled(dev_priv, disp2d) &&
> >  	    I915_READ(DPIO_CTL) & DPIO_CMNRST)
> >  		return;
> >  
> 
> 
> Yeah looks ok.  Do we have any bugs we know this fixes?

Not sure. I don't really know if I ever saw a machine that really
needed this toggling. But I did simulate crappy BIOS for it once by
turning on the cmn well but leaving everything else off, and after the
toggle w/a nothing got stuck so it seemed to do the right thing at least :)

> I'm hoping the
> remaining VLV DP training failures are fixed either by something like
> this or your panel power sequencer fixes.

Me too. I think it should be pretty solid after those. Then we just need
to figure out how to make it fast again if it really got much slower.
But at least the massive init time increase might be fixed by the
timestamp init patch I posted today.

> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 5/5] drm/i915: Initialize new chv primary plane and pipe blender registers

[Rodrigo Vivi]

On Thu, Oct 16, 2014 at 10:52 AM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CHV adds a bunch of new registers for primary plane size/position and
> pipe blender setup. Initialize all those registers to avoid nasty
> surprises. PRIMSIZE is especially important as without programming it
> the outout will be garbled whenever the primary plane size would not
> match what the BIOS set up.
>
> Also program the sprite constant alpha register to disable the constant
> alpha blending factor. This applies to vlv as well as chv.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 25 ++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
>  drivers/gpu/drm/i915/intel_sprite.c  |  2 ++
>  3 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 46cfbc7..c5c3b70 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4270,9 +4270,11 @@ enum punit_power_well {
>  #define   DISPPLANE_NO_LINE_DOUBLE             0
>  #define   DISPPLANE_STEREO_POLARITY_FIRST      0
>  #define   DISPPLANE_STEREO_POLARITY_SECOND     (1<<18)
> -#define   DISPPLANE_ROTATE_180         (1<<15)
> +#define   DISPPLANE_ALPHA_PREMULTIPLY          (1<<16) /* CHV pipe B */
> +#define   DISPPLANE_ROTATE_180                 (1<<15)
>  #define   DISPPLANE_TRICKLE_FEED_DISABLE       (1<<14) /* Ironlake */
>  #define   DISPPLANE_TILED                      (1<<10)
> +#define   DISPPLANE_MIRROR                     (1<<8) /* CHV pipe B */
>  #define _DSPAADDR                              0x70184
>  #define _DSPASTRIDE                            0x70188
>  #define _DSPAPOS                               0x7018C /* reserved */
> @@ -4293,6 +4295,24 @@ enum punit_power_well {
>  #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
>  #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
>
> +/* CHV pipe B blender and primary plane */
> +#define _CHV_BLEND_A           0x60a00
> +#define   CHV_BLEND_LEGACY             (0<<30)
> +#define   CHV_BLEND_ANDROID            (1<<30)
> +#define   CHV_BLEND_MPO                        (2<<30)
> +#define   CHV_BLEND_MASK               (3<<30)
> +#define _CHV_CANVAS_A          0x60a04
> +#define _PRIMPOS_A             0x60a08
> +#define _PRIMSIZE_A            0x60a0c
> +#define _PRIMCNSTALPHA_A       0x60a10
> +#define   PRIM_CONST_ALPHA_ENABLE      (1<<31)
> +
> +#define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
> +#define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
> +#define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
> +#define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
> +#define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
> +
>  /* Display/Sprite base address macros */
>  #define DISP_BASEADDR_MASK     (0xfffff000)
>  #define I915_LO_DISPBASE(val)  (val & ~DISP_BASEADDR_MASK)
> @@ -4494,6 +4514,7 @@ enum punit_power_well {
>  #define   SP_FORMAT_RGBA1010102                (9<<26)
>  #define   SP_FORMAT_RGBX8888           (0xe<<26)
>  #define   SP_FORMAT_RGBA8888           (0xf<<26)
> +#define   SP_ALPHA_PREMULTIPLY         (1<<23) /* CHV pipe B */
>  #define   SP_SOURCE_KEY                        (1<<22)
>  #define   SP_YUV_BYTE_ORDER_MASK       (3<<16)
>  #define   SP_YUV_ORDER_YUYV            (0<<16)
> @@ -4502,6 +4523,7 @@ enum punit_power_well {
>  #define   SP_YUV_ORDER_VYUY            (3<<16)
>  #define   SP_ROTATE_180                        (1<<15)
>  #define   SP_TILED                     (1<<10)
> +#define   SP_MIRROR                    (1<<8) /* CHV pipe B */
>  #define _SPALINOFF             (VLV_DISPLAY_BASE + 0x72184)
>  #define _SPASTRIDE             (VLV_DISPLAY_BASE + 0x72188)
>  #define _SPAPOS                        (VLV_DISPLAY_BASE + 0x7218c)
> @@ -4512,6 +4534,7 @@ enum punit_power_well {
>  #define _SPAKEYMAXVAL          (VLV_DISPLAY_BASE + 0x721a0)
>  #define _SPATILEOFF            (VLV_DISPLAY_BASE + 0x721a4)
>  #define _SPACONSTALPHA         (VLV_DISPLAY_BASE + 0x721a8)
> +#define   SP_CONST_ALPHA_ENABLE                (1<<31)

I don't believe this is on the right place...

>  #define _SPAGAMC               (VLV_DISPLAY_BASE + 0x721f4)
>
>  #define _SPBCNTR               (VLV_DISPLAY_BASE + 0x72280)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 18b493f..d901961 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2443,6 +2443,12 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
>                            (intel_crtc->config.pipe_src_w - 1));
>                 I915_WRITE(DSPPOS(plane), 0);
> +       } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> +               I915_WRITE(PRIMSIZE(plane),
> +                          ((intel_crtc->config.pipe_src_h - 1) << 16) |
> +                          (intel_crtc->config.pipe_src_w - 1));
> +               I915_WRITE(PRIMPOS(plane), 0);
> +               I915_WRITE(PRIMCNSTALPHA(plane), 0);
>         }
>
>         switch (fb->pixel_format) {
> @@ -4848,6 +4854,13 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>
>         intel_set_pipe_timings(intel_crtc);
>
> +       if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
> +               struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +               I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
> +               I915_WRITE(CHV_CANVAS(pipe), 0);
> +       }
> +
>         i9xx_set_pipeconf(intel_crtc);
>
>         intel_crtc->active = true;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 2c060ad..a452819 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -438,6 +438,8 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
>         else
>                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
>
> +       I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
> +

Is this also valid for byt?

>         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
>         I915_WRITE(SPCNTR(pipe, plane), sprctl);
>         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
> --
> 2.0.4
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

rest looks good so if those explained/fixed feel free to use:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

-- 
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Blog: http://blog.vivi.eng.br
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Re: [PATCH 5/5] drm/i915: Initialize new chv primary plane and pipe blender registers

[Ville Syrjälä]

On Wed, Oct 29, 2014 at 02:18:49PM -0700, Rodrigo Vivi wrote:
> On Thu, Oct 16, 2014 at 10:52 AM,  <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > CHV adds a bunch of new registers for primary plane size/position and
> > pipe blender setup. Initialize all those registers to avoid nasty
> > surprises. PRIMSIZE is especially important as without programming it
> > the outout will be garbled whenever the primary plane size would not
> > match what the BIOS set up.
> >
> > Also program the sprite constant alpha register to disable the constant
> > alpha blending factor. This applies to vlv as well as chv.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      | 25 ++++++++++++++++++++++++-
> >  drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
> >  drivers/gpu/drm/i915/intel_sprite.c  |  2 ++
> >  3 files changed, 39 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 46cfbc7..c5c3b70 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4270,9 +4270,11 @@ enum punit_power_well {
> >  #define   DISPPLANE_NO_LINE_DOUBLE             0
> >  #define   DISPPLANE_STEREO_POLARITY_FIRST      0
> >  #define   DISPPLANE_STEREO_POLARITY_SECOND     (1<<18)
> > -#define   DISPPLANE_ROTATE_180         (1<<15)
> > +#define   DISPPLANE_ALPHA_PREMULTIPLY          (1<<16) /* CHV pipe B */
> > +#define   DISPPLANE_ROTATE_180                 (1<<15)
> >  #define   DISPPLANE_TRICKLE_FEED_DISABLE       (1<<14) /* Ironlake */
> >  #define   DISPPLANE_TILED                      (1<<10)
> > +#define   DISPPLANE_MIRROR                     (1<<8) /* CHV pipe B */
> >  #define _DSPAADDR                              0x70184
> >  #define _DSPASTRIDE                            0x70188
> >  #define _DSPAPOS                               0x7018C /* reserved */
> > @@ -4293,6 +4295,24 @@ enum punit_power_well {
> >  #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
> >  #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
> >
> > +/* CHV pipe B blender and primary plane */
> > +#define _CHV_BLEND_A           0x60a00
> > +#define   CHV_BLEND_LEGACY             (0<<30)
> > +#define   CHV_BLEND_ANDROID            (1<<30)
> > +#define   CHV_BLEND_MPO                        (2<<30)
> > +#define   CHV_BLEND_MASK               (3<<30)
> > +#define _CHV_CANVAS_A          0x60a04
> > +#define _PRIMPOS_A             0x60a08
> > +#define _PRIMSIZE_A            0x60a0c
> > +#define _PRIMCNSTALPHA_A       0x60a10
> > +#define   PRIM_CONST_ALPHA_ENABLE      (1<<31)
> > +
> > +#define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
> > +#define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
> > +#define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
> > +#define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
> > +#define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
> > +
> >  /* Display/Sprite base address macros */
> >  #define DISP_BASEADDR_MASK     (0xfffff000)
> >  #define I915_LO_DISPBASE(val)  (val & ~DISP_BASEADDR_MASK)
> > @@ -4494,6 +4514,7 @@ enum punit_power_well {
> >  #define   SP_FORMAT_RGBA1010102                (9<<26)
> >  #define   SP_FORMAT_RGBX8888           (0xe<<26)
> >  #define   SP_FORMAT_RGBA8888           (0xf<<26)
> > +#define   SP_ALPHA_PREMULTIPLY         (1<<23) /* CHV pipe B */
> >  #define   SP_SOURCE_KEY                        (1<<22)
> >  #define   SP_YUV_BYTE_ORDER_MASK       (3<<16)
> >  #define   SP_YUV_ORDER_YUYV            (0<<16)
> > @@ -4502,6 +4523,7 @@ enum punit_power_well {
> >  #define   SP_YUV_ORDER_VYUY            (3<<16)
> >  #define   SP_ROTATE_180                        (1<<15)
> >  #define   SP_TILED                     (1<<10)
> > +#define   SP_MIRROR                    (1<<8) /* CHV pipe B */
> >  #define _SPALINOFF             (VLV_DISPLAY_BASE + 0x72184)
> >  #define _SPASTRIDE             (VLV_DISPLAY_BASE + 0x72188)
> >  #define _SPAPOS                        (VLV_DISPLAY_BASE + 0x7218c)
> > @@ -4512,6 +4534,7 @@ enum punit_power_well {
> >  #define _SPAKEYMAXVAL          (VLV_DISPLAY_BASE + 0x721a0)
> >  #define _SPATILEOFF            (VLV_DISPLAY_BASE + 0x721a4)
> >  #define _SPACONSTALPHA         (VLV_DISPLAY_BASE + 0x721a8)
> > +#define   SP_CONST_ALPHA_ENABLE                (1<<31)
> 
> I don't believe this is on the right place...

Where should it be?

> 
> >  #define _SPAGAMC               (VLV_DISPLAY_BASE + 0x721f4)
> >
> >  #define _SPBCNTR               (VLV_DISPLAY_BASE + 0x72280)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 18b493f..d901961 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2443,6 +2443,12 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
> >                            (intel_crtc->config.pipe_src_w - 1));
> >                 I915_WRITE(DSPPOS(plane), 0);
> > +       } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> > +               I915_WRITE(PRIMSIZE(plane),
> > +                          ((intel_crtc->config.pipe_src_h - 1) << 16) |
> > +                          (intel_crtc->config.pipe_src_w - 1));
> > +               I915_WRITE(PRIMPOS(plane), 0);
> > +               I915_WRITE(PRIMCNSTALPHA(plane), 0);
> >         }
> >
> >         switch (fb->pixel_format) {
> > @@ -4848,6 +4854,13 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> >
> >         intel_set_pipe_timings(intel_crtc);
> >
> > +       if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
> > +               struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +               I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
> > +               I915_WRITE(CHV_CANVAS(pipe), 0);
> > +       }
> > +
> >         i9xx_set_pipeconf(intel_crtc);
> >
> >         intel_crtc->active = true;
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index 2c060ad..a452819 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -438,6 +438,8 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
> >         else
> >                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
> >
> > +       I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
> > +
> 
> Is this also valid for byt?

Yes. As stated in the commit message ;)

> 
> >         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
> >         I915_WRITE(SPCNTR(pipe, plane), sprctl);
> >         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
> > --
> > 2.0.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> rest looks good so if those explained/fixed feel free to use:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 5/5] drm/i915: Initialize new chv primary plane and pipe blender registers

[Rodrigo Vivi]

On Thu, Oct 30, 2014 at 1:33 AM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Wed, Oct 29, 2014 at 02:18:49PM -0700, Rodrigo Vivi wrote:
>> On Thu, Oct 16, 2014 at 10:52 AM,  <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > CHV adds a bunch of new registers for primary plane size/position and
>> > pipe blender setup. Initialize all those registers to avoid nasty
>> > surprises. PRIMSIZE is especially important as without programming it
>> > the outout will be garbled whenever the primary plane size would not
>> > match what the BIOS set up.
>> >
>> > Also program the sprite constant alpha register to disable the constant
>> > alpha blending factor. This applies to vlv as well as chv.
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/i915_reg.h      | 25 ++++++++++++++++++++++++-
>> >  drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
>> >  drivers/gpu/drm/i915/intel_sprite.c  |  2 ++
>> >  3 files changed, 39 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index 46cfbc7..c5c3b70 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -4270,9 +4270,11 @@ enum punit_power_well {
>> >  #define   DISPPLANE_NO_LINE_DOUBLE             0
>> >  #define   DISPPLANE_STEREO_POLARITY_FIRST      0
>> >  #define   DISPPLANE_STEREO_POLARITY_SECOND     (1<<18)
>> > -#define   DISPPLANE_ROTATE_180         (1<<15)
>> > +#define   DISPPLANE_ALPHA_PREMULTIPLY          (1<<16) /* CHV pipe B */
>> > +#define   DISPPLANE_ROTATE_180                 (1<<15)
>> >  #define   DISPPLANE_TRICKLE_FEED_DISABLE       (1<<14) /* Ironlake */
>> >  #define   DISPPLANE_TILED                      (1<<10)
>> > +#define   DISPPLANE_MIRROR                     (1<<8) /* CHV pipe B */
>> >  #define _DSPAADDR                              0x70184
>> >  #define _DSPASTRIDE                            0x70188
>> >  #define _DSPAPOS                               0x7018C /* reserved */
>> > @@ -4293,6 +4295,24 @@ enum punit_power_well {
>> >  #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
>> >  #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
>> >
>> > +/* CHV pipe B blender and primary plane */
>> > +#define _CHV_BLEND_A           0x60a00
>> > +#define   CHV_BLEND_LEGACY             (0<<30)
>> > +#define   CHV_BLEND_ANDROID            (1<<30)
>> > +#define   CHV_BLEND_MPO                        (2<<30)
>> > +#define   CHV_BLEND_MASK               (3<<30)
>> > +#define _CHV_CANVAS_A          0x60a04
>> > +#define _PRIMPOS_A             0x60a08
>> > +#define _PRIMSIZE_A            0x60a0c
>> > +#define _PRIMCNSTALPHA_A       0x60a10
>> > +#define   PRIM_CONST_ALPHA_ENABLE      (1<<31)
>> > +
>> > +#define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
>> > +#define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
>> > +#define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
>> > +#define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
>> > +#define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
>> > +
>> >  /* Display/Sprite base address macros */
>> >  #define DISP_BASEADDR_MASK     (0xfffff000)
>> >  #define I915_LO_DISPBASE(val)  (val & ~DISP_BASEADDR_MASK)
>> > @@ -4494,6 +4514,7 @@ enum punit_power_well {
>> >  #define   SP_FORMAT_RGBA1010102                (9<<26)
>> >  #define   SP_FORMAT_RGBX8888           (0xe<<26)
>> >  #define   SP_FORMAT_RGBA8888           (0xf<<26)
>> > +#define   SP_ALPHA_PREMULTIPLY         (1<<23) /* CHV pipe B */
>> >  #define   SP_SOURCE_KEY                        (1<<22)
>> >  #define   SP_YUV_BYTE_ORDER_MASK       (3<<16)
>> >  #define   SP_YUV_ORDER_YUYV            (0<<16)
>> > @@ -4502,6 +4523,7 @@ enum punit_power_well {
>> >  #define   SP_YUV_ORDER_VYUY            (3<<16)
>> >  #define   SP_ROTATE_180                        (1<<15)
>> >  #define   SP_TILED                     (1<<10)
>> > +#define   SP_MIRROR                    (1<<8) /* CHV pipe B */
>> >  #define _SPALINOFF             (VLV_DISPLAY_BASE + 0x72184)
>> >  #define _SPASTRIDE             (VLV_DISPLAY_BASE + 0x72188)
>> >  #define _SPAPOS                        (VLV_DISPLAY_BASE + 0x7218c)
>> > @@ -4512,6 +4534,7 @@ enum punit_power_well {
>> >  #define _SPAKEYMAXVAL          (VLV_DISPLAY_BASE + 0x721a0)
>> >  #define _SPATILEOFF            (VLV_DISPLAY_BASE + 0x721a4)
>> >  #define _SPACONSTALPHA         (VLV_DISPLAY_BASE + 0x721a8)
>> > +#define   SP_CONST_ALPHA_ENABLE                (1<<31)
>>
>> I don't believe this is on the right place...
>
> Where should it be?
>
I don't know. I couldn't find this bit definition there, but...

>>
>> >  #define _SPAGAMC               (VLV_DISPLAY_BASE + 0x721f4)
>> >
>> >  #define _SPBCNTR               (VLV_DISPLAY_BASE + 0x72280)
>> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> > index 18b493f..d901961 100644
>> > --- a/drivers/gpu/drm/i915/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > @@ -2443,6 +2443,12 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>> >                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
>> >                            (intel_crtc->config.pipe_src_w - 1));
>> >                 I915_WRITE(DSPPOS(plane), 0);
>> > +       } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
>> > +               I915_WRITE(PRIMSIZE(plane),
>> > +                          ((intel_crtc->config.pipe_src_h - 1) << 16) |
>> > +                          (intel_crtc->config.pipe_src_w - 1));
>> > +               I915_WRITE(PRIMPOS(plane), 0);
>> > +               I915_WRITE(PRIMCNSTALPHA(plane), 0);
>> >         }
>> >
>> >         switch (fb->pixel_format) {
>> > @@ -4848,6 +4854,13 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>> >
>> >         intel_set_pipe_timings(intel_crtc);
>> >
>> > +       if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
>> > +               struct drm_i915_private *dev_priv = dev->dev_private;
>> > +
>> > +               I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
>> > +               I915_WRITE(CHV_CANVAS(pipe), 0);
>> > +       }
>> > +
>> >         i9xx_set_pipeconf(intel_crtc);
>> >
>> >         intel_crtc->active = true;
>> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> > index 2c060ad..a452819 100644
>> > --- a/drivers/gpu/drm/i915/intel_sprite.c
>> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> > @@ -438,6 +438,8 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
>> >         else
>> >                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
>> >
>> > +       I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
>> > +
>>
>> Is this also valid for byt?
>
> Yes. As stated in the commit message ;)

... maybe I didn't see that for the same reason I missed the commit
message! hehe ;)
>
>>
>> >         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
>> >         I915_WRITE(SPCNTR(pipe, plane), sprctl);
>> >         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
>> > --
>> > 2.0.4
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> rest looks good so if those explained/fixed feel free to use:
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>
>> --
>> Rodrigo Vivi
>> Blog: http://blog.vivi.eng.br
>
> --
> Ville Syrjälä
> Intel OTC



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH 4/5] drm/i915: Do vlv cmnlane toggle w/a in more cases

[Daniel Vetter]

On Tue, Oct 28, 2014 at 08:12:30PM +0200, Ville Syrjälä wrote:
> On Tue, Oct 28, 2014 at 10:57:38AM -0700, Jesse Barnes wrote:
> > On Thu, 16 Oct 2014 20:52:33 +0300
> > ville.syrjala@linux.intel.com wrote:
> > 
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > In case the cmnlane power well is down but cmnreset isn't asserted we
> > > would currently skip the off+on toggle for the power well. That could
> > > leave cmnreset deasserted while cmnlane is powered down which might
> > > lead to problems with the PHY.
> > > 
> > > To avoid such issues skip the cmnlane toggle only if both cmnlane and
> > > disp2d wells are up and cmnreset is already deasserted. In all other
> > > cases power down the cmnlane well which will also make sure cmnreset
> > > gets asserted correctly while cmnlane is powered down.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ++-----
> > >  1 file changed, 2 insertions(+), 5 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c index 36749b9..f6b4e8d
> > > 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -1137,12 +1137,9 @@ static void vlv_cmnlane_wa(struct
> > > drm_i915_private *dev_priv) struct i915_power_well *disp2d =
> > >  		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
> > >  
> > > -	/* nothing to do if common lane is already off */
> > > -	if (!cmn->ops->is_enabled(dev_priv, cmn))
> > > -		return;
> > > -
> > >  	/* If the display might be already active skip this */
> > > -	if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
> > > +	if (cmn->ops->is_enabled(dev_priv, cmn) &&
> > > +	    disp2d->ops->is_enabled(dev_priv, disp2d) &&
> > >  	    I915_READ(DPIO_CTL) & DPIO_CMNRST)
> > >  		return;
> > >  
> > 
> > 
> > Yeah looks ok.  Do we have any bugs we know this fixes?
> 
> Not sure. I don't really know if I ever saw a machine that really
> needed this toggling. But I did simulate crappy BIOS for it once by
> turning on the cmn well but leaving everything else off, and after the
> toggle w/a nothing got stuck so it seemed to do the right thing at least :)
> 
> > I'm hoping the
> > remaining VLV DP training failures are fixed either by something like
> > this or your panel power sequencer fixes.
> 
> Me too. I think it should be pretty solid after those. Then we just need
> to figure out how to make it fast again if it really got much slower.
> But at least the massive init time increase might be fixed by the
> timestamp init patch I posted today.
> 
> > 
> > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Remaining two patches merged to dinq - we can always cherry-pick to -fixes
if this resolves a real issue.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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