[PATCH 0/7] Add clock and DT support for a few IPs on Exynos7

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* [PATCH 0/7] Add clock and DT support for a few IPs on Exynos7
@ 2014-10-17 16:11 ` Abhilash Kesavan
  0 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: linux-samsung-soc, catalin.marinas, robh, devicetree, tomasz.figa

This series adds clock support for I2C, MMC, RTC, Watchdog, TMU and PWM.
It also adds the device nodes for I2C, RTC, WDT, MMC and PMU.
The patchset has been tested on linux-next (20141017) on an Exynos7
Espresso board.

Following are the dependencies:
1) dts, kbuild: Implement support for dtb vendor subdirs" patchset 
http://comments.gmane.org/gmane.linux.kbuild.devel/12131
2) arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
3) Serial clean-up patches for Exynos7
http://www.spinics.net/lists/arm-kernel/msg367348.html
http://www.spinics.net/lists/arm-kernel/msg367349.html
4) Add initial support for pinctrl on Exynos7
http://www.spinics.net/lists/linux-samsung-soc/msg37708.html

For testing I have applied the following:
1) mmc: dw_mmc: Add IDMAC 64-bit address mode support
http://www.spinics.net/lists/kernel/msg1842300.html
2) mmc: dw_mmc: Reset DMA before enabling IDMAC
http://www.gossamer-threads.com/lists/linux/kernel/2021576?page=last
3) mmc: dw_mmc: exynos: Add support for exynos7
http://www.spinics.net/lists/linux-mmc/msg28294.html
4) mfd: sec: add S2MPS15 PMIC support
https://lkml.org/lkml/2014/10/14/50
5) drivers: rtc: fix s3c-rtc initialization failure without rtc source clock
https://lkml.org/lkml/2014/10/15/210
6) regulator: s2mps11: add support for S2MPS15 regulators
https://lkml.org/lkml/2014/10/14/52
7) Regulators dt nodes were added in the espresso dts file and I2C channel 4
which has the PMIC on it was tested.

Abhilash Kesavan (3):
  arm64: dts: Add PMU DT node for exynos7 SoC
  arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7
  arm64: exynos: Enable rtc and watchdog support for Exynos7

Naveen Krishna Ch (4):
  clk: samsung: exynos7: add clocks for I2C block
  clk: samsung: exynos7: add clocks for MMC block
  clk: samsung: exynos7: add clocks for RTC block
  clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks

 .../devicetree/bindings/arm/samsung/pmu.txt        |    1 +
 .../devicetree/bindings/clock/exynos7-clock.txt    |    4 +
 arch/arm64/Kconfig                                 |    3 +
 arch/arm64/boot/dts/exynos/exynos7-espresso.dts    |   41 +++
 arch/arm64/boot/dts/exynos/exynos7.dtsi            |  261 ++++++++++++++++
 drivers/clk/samsung/clk-exynos7.c                  |  316 ++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h            |   60 +++-
 7 files changed, 677 insertions(+), 9 deletions(-)

-- 
1.7.9.5

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH 0/7] Add clock and DT support for a few IPs on Exynos7
@ 2014-10-17 16:11 ` Abhilash Kesavan
  0 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel

This series adds clock support for I2C, MMC, RTC, Watchdog, TMU and PWM.
It also adds the device nodes for I2C, RTC, WDT, MMC and PMU.
The patchset has been tested on linux-next (20141017) on an Exynos7
Espresso board.

Following are the dependencies:
1) dts, kbuild: Implement support for dtb vendor subdirs" patchset 
http://comments.gmane.org/gmane.linux.kbuild.devel/12131
2) arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
3) Serial clean-up patches for Exynos7
http://www.spinics.net/lists/arm-kernel/msg367348.html
http://www.spinics.net/lists/arm-kernel/msg367349.html
4) Add initial support for pinctrl on Exynos7
http://www.spinics.net/lists/linux-samsung-soc/msg37708.html

For testing I have applied the following:
1) mmc: dw_mmc: Add IDMAC 64-bit address mode support
http://www.spinics.net/lists/kernel/msg1842300.html
2) mmc: dw_mmc: Reset DMA before enabling IDMAC
http://www.gossamer-threads.com/lists/linux/kernel/2021576?page=last
3) mmc: dw_mmc: exynos: Add support for exynos7
http://www.spinics.net/lists/linux-mmc/msg28294.html
4) mfd: sec: add S2MPS15 PMIC support
https://lkml.org/lkml/2014/10/14/50
5) drivers: rtc: fix s3c-rtc initialization failure without rtc source clock
https://lkml.org/lkml/2014/10/15/210
6) regulator: s2mps11: add support for S2MPS15 regulators
https://lkml.org/lkml/2014/10/14/52
7) Regulators dt nodes were added in the espresso dts file and I2C channel 4
which has the PMIC on it was tested.

Abhilash Kesavan (3):
  arm64: dts: Add PMU DT node for exynos7 SoC
  arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7
  arm64: exynos: Enable rtc and watchdog support for Exynos7

Naveen Krishna Ch (4):
  clk: samsung: exynos7: add clocks for I2C block
  clk: samsung: exynos7: add clocks for MMC block
  clk: samsung: exynos7: add clocks for RTC block
  clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks

 .../devicetree/bindings/arm/samsung/pmu.txt        |    1 +
 .../devicetree/bindings/clock/exynos7-clock.txt    |    4 +
 arch/arm64/Kconfig                                 |    3 +
 arch/arm64/boot/dts/exynos/exynos7-espresso.dts    |   41 +++
 arch/arm64/boot/dts/exynos/exynos7.dtsi            |  261 ++++++++++++++++
 drivers/clk/samsung/clk-exynos7.c                  |  316 ++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h            |   60 +++-
 7 files changed, 677 insertions(+), 9 deletions(-)

-- 
1.7.9.5

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH 1/7] clk: samsung: exynos7: add clocks for I2C block
  2014-10-17 16:11 ` Abhilash Kesavan
@ 2014-10-17 16:11   ` Abhilash Kesavan
  -1 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: linux-samsung-soc, catalin.marinas, robh, devicetree, tomasz.figa

From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>

Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |   24 ++++++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h |   16 ++++++++++++++--
 2 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 54206d4..c700f65 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -290,6 +290,20 @@ static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
 };
 
 static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+	GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 8, 0, 0),
+	GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 9, 0, 0),
+	GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 10, 0, 0),
+	GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 11, 0, 0),
+	GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 12, 0, 0),
+	GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 13, 0, 0),
+	GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 14, 0, 0),
 	GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
 		ENABLE_PCLK_PERIC0, 16, 0, 0),
 
@@ -347,6 +361,16 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
 };
 
 static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+	GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
+		ENABLE_PCLK_PERIC1, 4, 0, 0),
+	GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
+		ENABLE_PCLK_PERIC1, 5, 0, 0),
+	GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
+		ENABLE_PCLK_PERIC1, 6, 0, 0),
+	GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
+		ENABLE_PCLK_PERIC1, 7, 0, 0),
+	GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
+		ENABLE_PCLK_PERIC1, 8, 0, 0),
 	GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
 		ENABLE_PCLK_PERIC1, 9, 0, 0),
 	GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 00fd6de..6d07b6f 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -30,7 +30,14 @@
 /* PERIC0 */
 #define PCLK_UART0			1
 #define SCLK_UART0			2
-#define PERIC0_NR_CLK			3
+#define PCLK_HSI2C0			3
+#define PCLK_HSI2C1			4
+#define PCLK_HSI2C4			5
+#define PCLK_HSI2C5			6
+#define PCLK_HSI2C9			7
+#define PCLK_HSI2C10			8
+#define PCLK_HSI2C11			9
+#define PERIC0_NR_CLK			10
 
 /* PERIC1 */
 #define PCLK_UART1			1
@@ -39,7 +46,12 @@
 #define SCLK_UART1			4
 #define SCLK_UART2			5
 #define SCLK_UART3			6
-#define PERIC1_NR_CLK			7
+#define PCLK_HSI2C2			7
+#define PCLK_HSI2C3			8
+#define PCLK_HSI2C6			9
+#define PCLK_HSI2C7			10
+#define PCLK_HSI2C8			11
+#define PERIC1_NR_CLK			12
 
 /* PERIS */
 #define PCLK_CHIPID			1
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 1/7] clk: samsung: exynos7: add clocks for I2C block
@ 2014-10-17 16:11   ` Abhilash Kesavan
  0 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel

From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>

Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |   24 ++++++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h |   16 ++++++++++++++--
 2 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 54206d4..c700f65 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -290,6 +290,20 @@ static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
 };
 
 static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+	GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 8, 0, 0),
+	GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 9, 0, 0),
+	GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 10, 0, 0),
+	GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 11, 0, 0),
+	GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 12, 0, 0),
+	GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 13, 0, 0),
+	GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 14, 0, 0),
 	GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
 		ENABLE_PCLK_PERIC0, 16, 0, 0),
 
@@ -347,6 +361,16 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
 };
 
 static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+	GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
+		ENABLE_PCLK_PERIC1, 4, 0, 0),
+	GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
+		ENABLE_PCLK_PERIC1, 5, 0, 0),
+	GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
+		ENABLE_PCLK_PERIC1, 6, 0, 0),
+	GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
+		ENABLE_PCLK_PERIC1, 7, 0, 0),
+	GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
+		ENABLE_PCLK_PERIC1, 8, 0, 0),
 	GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
 		ENABLE_PCLK_PERIC1, 9, 0, 0),
 	GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 00fd6de..6d07b6f 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -30,7 +30,14 @@
 /* PERIC0 */
 #define PCLK_UART0			1
 #define SCLK_UART0			2
-#define PERIC0_NR_CLK			3
+#define PCLK_HSI2C0			3
+#define PCLK_HSI2C1			4
+#define PCLK_HSI2C4			5
+#define PCLK_HSI2C5			6
+#define PCLK_HSI2C9			7
+#define PCLK_HSI2C10			8
+#define PCLK_HSI2C11			9
+#define PERIC0_NR_CLK			10
 
 /* PERIC1 */
 #define PCLK_UART1			1
@@ -39,7 +46,12 @@
 #define SCLK_UART1			4
 #define SCLK_UART2			5
 #define SCLK_UART3			6
-#define PERIC1_NR_CLK			7
+#define PCLK_HSI2C2			7
+#define PCLK_HSI2C3			8
+#define PCLK_HSI2C6			9
+#define PCLK_HSI2C7			10
+#define PCLK_HSI2C8			11
+#define PERIC1_NR_CLK			12
 
 /* PERIS */
 #define PCLK_CHIPID			1
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block
  2014-10-17 16:11 ` Abhilash Kesavan
@ 2014-10-17 16:11   ` Abhilash Kesavan
  -1 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: linux-samsung-soc, catalin.marinas, robh, devicetree, tomasz.figa

From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>

Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 .../devicetree/bindings/clock/exynos7-clock.txt    |    3 +
 drivers/clk/samsung/clk-exynos7.c                  |  224 ++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h            |   20 ++
 3 files changed, 247 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..4c69b66 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
 
 	- "samsung,exynos7-clock-topc"
 	- "samsung,exynos7-clock-top0"
+	- "samsung,exynos7-clock-top1"
 	- "samsung,exynos7-clock-peric0"
 	- "samsung,exynos7-clock-peric1"
 	- "samsung,exynos7-clock-peris"
+	- "samsung,exynos7-clock-fsys0"
+	- "samsung,exynos7-clock-fsys1"
 
  - reg: physical base address of the controller and the length of
 	memory mapped region.
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index c700f65..f5e43fa 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct device_node *np)
 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
 	exynos7_clk_top0_init);
 
+/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
+#define MUX_SEL_TOP10			0x0200
+#define MUX_SEL_TOP11			0x0204
+#define MUX_SEL_TOP13			0x020C
+#define MUX_SEL_TOP1_FSYS0		0x0224
+#define MUX_SEL_TOP1_FSYS1		0x0228
+#define DIV_TOP13			0x060C
+#define DIV_TOP1_FSYS0			0x0624
+#define DIV_TOP1_FSYS1			0x0628
+#define ENABLE_ACLK_TOP13		0x080C
+#define ENABLE_SCLK_TOP1_FSYS0		0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1		0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)	= { "fin_pll", "dout_sclk_bus0_pll" };
+PNAME(mout_top1_bus1_pll_p)	= { "fin_pll", "dout_sclk_bus1_pll_b" };
+PNAME(mout_top1_cc_pll_p)	= { "fin_pll", "dout_sclk_cc_pll_b" };
+PNAME(mout_top1_mfc_pll_p)	= { "fin_pll", "dout_sclk_mfc_pll_b" };
+
+PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
+	"ffac_top1_bus0_pll_div2"};
+PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
+	"ffac_top1_bus1_pll_div2"};
+PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
+	"ffac_top1_cc_pll_div2"};
+PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
+	"ffac_top1_mfc_pll_div2"};
+
+PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
+	"mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
+	"mout_top1_half_mfc_pll"};
+
+static unsigned long top1_clk_regs[] __initdata = {
+	MUX_SEL_TOP10,
+	MUX_SEL_TOP11,
+	MUX_SEL_TOP13,
+	MUX_SEL_TOP1_FSYS0,
+	MUX_SEL_TOP1_FSYS1,
+	DIV_TOP13,
+	DIV_TOP1_FSYS0,
+	DIV_TOP1_FSYS1,
+	ENABLE_ACLK_TOP13,
+	ENABLE_SCLK_TOP1_FSYS0,
+	ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+	MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+	MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+	MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
+		MUX_SEL_TOP10, 12, 1),
+	MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
+		MUX_SEL_TOP10, 16, 1),
+
+	MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
+		MUX_SEL_TOP11, 4, 1),
+	MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
+		MUX_SEL_TOP11, 8, 1),
+	MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
+		MUX_SEL_TOP11, 12, 1),
+	MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
+		MUX_SEL_TOP11, 16, 1),
+
+	MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
+	MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
+
+	MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
+
+	MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
+	MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
+};
+
+static struct samsung_div_clock top1_div_clks[] __initdata = {
+	DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
+		DIV_TOP13, 24, 4),
+	DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
+		DIV_TOP13, 28, 4),
+
+	DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
+		DIV_TOP1_FSYS0, 24, 4),
+
+	DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
+		DIV_TOP1_FSYS1, 24, 4),
+	DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
+		DIV_TOP1_FSYS1, 28, 4),
+};
+
+static struct samsung_gate_clock top1_gate_clks[] __initdata = {
+	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
+		ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
+
+	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
+		ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
+		ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
+	FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
+};
+
+static struct samsung_cmu_info top1_cmu_info __initdata = {
+	.mux_clks		= top1_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(top1_mux_clks),
+	.div_clks		= top1_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(top1_div_clks),
+	.gate_clks		= top1_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(top1_gate_clks),
+	.fixed_factor_clks	= top1_fixed_factor_clks,
+	.nr_fixed_factor_clks	= ARRAY_SIZE(top1_fixed_factor_clks),
+	.nr_clk_ids		= TOP1_NR_CLK,
+	.clk_regs		= top1_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(top1_clk_regs),
+};
+
+static void __init exynos7_clk_top1_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &top1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
+	exynos7_clk_top1_init);
+
 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
 #define MUX_SEL_PERIC0			0x0200
 #define ENABLE_PCLK_PERIC0		0x0900
@@ -447,3 +573,101 @@ static void __init exynos7_clk_peris_init(struct device_node *np)
 
 CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
 	exynos7_clk_peris_init);
+
+/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
+#define MUX_SEL_FSYS00			0x0200
+#define MUX_SEL_FSYS01			0x0204
+#define ENABLE_ACLK_FSYS01		0x0804
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS0
+ */
+PNAME(mout_aclk_fsys0_200_p)	= { "fin_pll", "dout_aclk_fsys0_200" };
+PNAME(mout_sclk_mmc2_p)		= { "fin_pll", "sclk_mmc2" };
+
+static unsigned long fsys0_clk_regs[] __initdata = {
+	MUX_SEL_FSYS00,
+	MUX_SEL_FSYS01,
+	ENABLE_ACLK_FSYS01,
+};
+
+static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
+	MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
+		MUX_SEL_FSYS00, 24, 1),
+
+	MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
+};
+
+static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
+	GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
+		ENABLE_ACLK_FSYS01, 31, 0, 0),
+};
+
+static struct samsung_cmu_info fsys0_cmu_info __initdata = {
+	.mux_clks		= fsys0_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(fsys0_mux_clks),
+	.gate_clks		= fsys0_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(fsys0_gate_clks),
+	.nr_clk_ids		= TOP1_NR_CLK,
+	.clk_regs		= fsys0_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(fsys0_clk_regs),
+};
+
+static void __init exynos7_clk_fsys0_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &fsys0_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
+	exynos7_clk_fsys0_init);
+
+/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
+#define MUX_SEL_FSYS10			0x0200
+#define MUX_SEL_FSYS11			0x0204
+#define ENABLE_ACLK_FSYS1		0x0800
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS1
+ */
+PNAME(mout_aclk_fsys1_200_p)	= { "fin_pll",  "dout_aclk_fsys1_200" };
+PNAME(mout_sclk_mmc0_p)		= { "fin_pll", "sclk_mmc0" };
+PNAME(mout_sclk_mmc1_p)		= { "fin_pll", "sclk_mmc1" };
+
+static unsigned long fsys1_clk_regs[] __initdata = {
+	MUX_SEL_FSYS10,
+	MUX_SEL_FSYS11,
+	ENABLE_ACLK_FSYS1,
+};
+
+static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
+	MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
+		MUX_SEL_FSYS10, 28, 1),
+
+	MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
+	MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
+};
+
+static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
+	GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
+		ENABLE_ACLK_FSYS1, 29, 0, 0),
+	GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
+		ENABLE_ACLK_FSYS1, 30, 0, 0),
+};
+
+static struct samsung_cmu_info fsys1_cmu_info __initdata = {
+	.mux_clks		= fsys1_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(fsys1_mux_clks),
+	.gate_clks		= fsys1_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(fsys1_gate_clks),
+	.nr_clk_ids		= TOP1_NR_CLK,
+	.clk_regs		= fsys1_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(fsys1_clk_regs),
+};
+
+static void __init exynos7_clk_fsys1_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &fsys1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
+	exynos7_clk_fsys1_init);
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 6d07b6f..ff63c4e 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -27,6 +27,17 @@
 #define CLK_SCLK_UART3			6
 #define TOP0_NR_CLK			7
 
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200		1
+#define DOUT_ACLK_FSYS0_200		2
+#define DOUT_SCLK_MMC2			3
+#define DOUT_SCLK_MMC1			4
+#define DOUT_SCLK_MMC0			5
+#define CLK_SCLK_MMC2			6
+#define CLK_SCLK_MMC1			7
+#define CLK_SCLK_MMC0			8
+#define TOP1_NR_CLK			9
+
 /* PERIC0 */
 #define PCLK_UART0			1
 #define SCLK_UART0			2
@@ -58,4 +69,13 @@
 #define SCLK_CHIPID			2
 #define PERIS_NR_CLK			3
 
+/* FSYS0 */
+#define ACLK_MMC2			1
+#define FSYS0_NR_CLK			2
+
+/* FSYS1 */
+#define ACLK_MMC1			1
+#define ACLK_MMC0			2
+#define FSYS1_NR_CLK			3
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block
@ 2014-10-17 16:11   ` Abhilash Kesavan
  0 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel

From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>

Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 .../devicetree/bindings/clock/exynos7-clock.txt    |    3 +
 drivers/clk/samsung/clk-exynos7.c                  |  224 ++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h            |   20 ++
 3 files changed, 247 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..4c69b66 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
 
 	- "samsung,exynos7-clock-topc"
 	- "samsung,exynos7-clock-top0"
+	- "samsung,exynos7-clock-top1"
 	- "samsung,exynos7-clock-peric0"
 	- "samsung,exynos7-clock-peric1"
 	- "samsung,exynos7-clock-peris"
+	- "samsung,exynos7-clock-fsys0"
+	- "samsung,exynos7-clock-fsys1"
 
  - reg: physical base address of the controller and the length of
 	memory mapped region.
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index c700f65..f5e43fa 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct device_node *np)
 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
 	exynos7_clk_top0_init);
 
+/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
+#define MUX_SEL_TOP10			0x0200
+#define MUX_SEL_TOP11			0x0204
+#define MUX_SEL_TOP13			0x020C
+#define MUX_SEL_TOP1_FSYS0		0x0224
+#define MUX_SEL_TOP1_FSYS1		0x0228
+#define DIV_TOP13			0x060C
+#define DIV_TOP1_FSYS0			0x0624
+#define DIV_TOP1_FSYS1			0x0628
+#define ENABLE_ACLK_TOP13		0x080C
+#define ENABLE_SCLK_TOP1_FSYS0		0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1		0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)	= { "fin_pll", "dout_sclk_bus0_pll" };
+PNAME(mout_top1_bus1_pll_p)	= { "fin_pll", "dout_sclk_bus1_pll_b" };
+PNAME(mout_top1_cc_pll_p)	= { "fin_pll", "dout_sclk_cc_pll_b" };
+PNAME(mout_top1_mfc_pll_p)	= { "fin_pll", "dout_sclk_mfc_pll_b" };
+
+PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
+	"ffac_top1_bus0_pll_div2"};
+PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
+	"ffac_top1_bus1_pll_div2"};
+PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
+	"ffac_top1_cc_pll_div2"};
+PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
+	"ffac_top1_mfc_pll_div2"};
+
+PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
+	"mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
+	"mout_top1_half_mfc_pll"};
+
+static unsigned long top1_clk_regs[] __initdata = {
+	MUX_SEL_TOP10,
+	MUX_SEL_TOP11,
+	MUX_SEL_TOP13,
+	MUX_SEL_TOP1_FSYS0,
+	MUX_SEL_TOP1_FSYS1,
+	DIV_TOP13,
+	DIV_TOP1_FSYS0,
+	DIV_TOP1_FSYS1,
+	ENABLE_ACLK_TOP13,
+	ENABLE_SCLK_TOP1_FSYS0,
+	ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+	MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+	MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+	MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
+		MUX_SEL_TOP10, 12, 1),
+	MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
+		MUX_SEL_TOP10, 16, 1),
+
+	MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
+		MUX_SEL_TOP11, 4, 1),
+	MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
+		MUX_SEL_TOP11, 8, 1),
+	MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
+		MUX_SEL_TOP11, 12, 1),
+	MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
+		MUX_SEL_TOP11, 16, 1),
+
+	MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
+	MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
+
+	MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
+
+	MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
+	MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
+};
+
+static struct samsung_div_clock top1_div_clks[] __initdata = {
+	DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
+		DIV_TOP13, 24, 4),
+	DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
+		DIV_TOP13, 28, 4),
+
+	DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
+		DIV_TOP1_FSYS0, 24, 4),
+
+	DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
+		DIV_TOP1_FSYS1, 24, 4),
+	DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
+		DIV_TOP1_FSYS1, 28, 4),
+};
+
+static struct samsung_gate_clock top1_gate_clks[] __initdata = {
+	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
+		ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
+
+	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
+		ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
+		ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
+	FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
+};
+
+static struct samsung_cmu_info top1_cmu_info __initdata = {
+	.mux_clks		= top1_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(top1_mux_clks),
+	.div_clks		= top1_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(top1_div_clks),
+	.gate_clks		= top1_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(top1_gate_clks),
+	.fixed_factor_clks	= top1_fixed_factor_clks,
+	.nr_fixed_factor_clks	= ARRAY_SIZE(top1_fixed_factor_clks),
+	.nr_clk_ids		= TOP1_NR_CLK,
+	.clk_regs		= top1_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(top1_clk_regs),
+};
+
+static void __init exynos7_clk_top1_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &top1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
+	exynos7_clk_top1_init);
+
 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
 #define MUX_SEL_PERIC0			0x0200
 #define ENABLE_PCLK_PERIC0		0x0900
@@ -447,3 +573,101 @@ static void __init exynos7_clk_peris_init(struct device_node *np)
 
 CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
 	exynos7_clk_peris_init);
+
+/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
+#define MUX_SEL_FSYS00			0x0200
+#define MUX_SEL_FSYS01			0x0204
+#define ENABLE_ACLK_FSYS01		0x0804
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS0
+ */
+PNAME(mout_aclk_fsys0_200_p)	= { "fin_pll", "dout_aclk_fsys0_200" };
+PNAME(mout_sclk_mmc2_p)		= { "fin_pll", "sclk_mmc2" };
+
+static unsigned long fsys0_clk_regs[] __initdata = {
+	MUX_SEL_FSYS00,
+	MUX_SEL_FSYS01,
+	ENABLE_ACLK_FSYS01,
+};
+
+static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
+	MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
+		MUX_SEL_FSYS00, 24, 1),
+
+	MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
+};
+
+static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
+	GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
+		ENABLE_ACLK_FSYS01, 31, 0, 0),
+};
+
+static struct samsung_cmu_info fsys0_cmu_info __initdata = {
+	.mux_clks		= fsys0_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(fsys0_mux_clks),
+	.gate_clks		= fsys0_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(fsys0_gate_clks),
+	.nr_clk_ids		= TOP1_NR_CLK,
+	.clk_regs		= fsys0_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(fsys0_clk_regs),
+};
+
+static void __init exynos7_clk_fsys0_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &fsys0_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
+	exynos7_clk_fsys0_init);
+
+/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
+#define MUX_SEL_FSYS10			0x0200
+#define MUX_SEL_FSYS11			0x0204
+#define ENABLE_ACLK_FSYS1		0x0800
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS1
+ */
+PNAME(mout_aclk_fsys1_200_p)	= { "fin_pll",  "dout_aclk_fsys1_200" };
+PNAME(mout_sclk_mmc0_p)		= { "fin_pll", "sclk_mmc0" };
+PNAME(mout_sclk_mmc1_p)		= { "fin_pll", "sclk_mmc1" };
+
+static unsigned long fsys1_clk_regs[] __initdata = {
+	MUX_SEL_FSYS10,
+	MUX_SEL_FSYS11,
+	ENABLE_ACLK_FSYS1,
+};
+
+static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
+	MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
+		MUX_SEL_FSYS10, 28, 1),
+
+	MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
+	MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
+};
+
+static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
+	GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
+		ENABLE_ACLK_FSYS1, 29, 0, 0),
+	GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
+		ENABLE_ACLK_FSYS1, 30, 0, 0),
+};
+
+static struct samsung_cmu_info fsys1_cmu_info __initdata = {
+	.mux_clks		= fsys1_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(fsys1_mux_clks),
+	.gate_clks		= fsys1_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(fsys1_gate_clks),
+	.nr_clk_ids		= TOP1_NR_CLK,
+	.clk_regs		= fsys1_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(fsys1_clk_regs),
+};
+
+static void __init exynos7_clk_fsys1_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &fsys1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
+	exynos7_clk_fsys1_init);
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 6d07b6f..ff63c4e 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -27,6 +27,17 @@
 #define CLK_SCLK_UART3			6
 #define TOP0_NR_CLK			7
 
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200		1
+#define DOUT_ACLK_FSYS0_200		2
+#define DOUT_SCLK_MMC2			3
+#define DOUT_SCLK_MMC1			4
+#define DOUT_SCLK_MMC0			5
+#define CLK_SCLK_MMC2			6
+#define CLK_SCLK_MMC1			7
+#define CLK_SCLK_MMC0			8
+#define TOP1_NR_CLK			9
+
 /* PERIC0 */
 #define PCLK_UART0			1
 #define SCLK_UART0			2
@@ -58,4 +69,13 @@
 #define SCLK_CHIPID			2
 #define PERIS_NR_CLK			3
 
+/* FSYS0 */
+#define ACLK_MMC2			1
+#define FSYS0_NR_CLK			2
+
+/* FSYS1 */
+#define ACLK_MMC1			1
+#define ACLK_MMC0			2
+#define FSYS1_NR_CLK			3
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 3/7] clk: samsung: exynos7: add clocks for RTC block
  2014-10-17 16:11 ` Abhilash Kesavan
@ 2014-10-17 16:11     ` Abhilash Kesavan
  -1 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
  Cc: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	catalin.marinas-5wv7dgnIgG8, robh-DgEjT+Ai2ygdnm+yROfE0A,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w

From: Naveen Krishna Ch <naveenkrishna.ch-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Add clock support for the RTC block in Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Abhilash Kesavan <a.kesavan-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/clock/exynos7-clock.txt    |    1 +
 drivers/clk/samsung/clk-exynos7.c                  |   54 ++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h            |   17 +++---
 3 files changed, 66 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 4c69b66..aff6fd2 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -28,6 +28,7 @@ Required Properties for Clock Controller:
 	- "samsung,exynos7-clock-topc"
 	- "samsung,exynos7-clock-top0"
 	- "samsung,exynos7-clock-top1"
+	- "samsung,exynos7-clock-ccore"
 	- "samsung,exynos7-clock-peric0"
 	- "samsung,exynos7-clock-peric1"
 	- "samsung,exynos7-clock-peris"
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index f5e43fa..3a30f43 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -29,7 +29,9 @@
 #define AUD_PLL_CON0		0x0140
 #define MUX_SEL_TOPC0		0x0200
 #define MUX_SEL_TOPC1		0x0204
+#define MUX_SEL_TOPC2		0x0208
 #define MUX_SEL_TOPC3		0x020C
+#define DIV_TOPC0		0x0600
 #define DIV_TOPC1		0x0604
 #define DIV_TOPC3		0x060C
 
@@ -78,7 +80,9 @@ static unsigned long topc_clk_regs[] __initdata = {
 	AUD_PLL_CON0,
 	MUX_SEL_TOPC0,
 	MUX_SEL_TOPC1,
+	MUX_SEL_TOPC2,
 	MUX_SEL_TOPC3,
+	DIV_TOPC0,
 	DIV_TOPC1,
 	DIV_TOPC3,
 };
@@ -101,10 +105,15 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
 	MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
 		MUX_SEL_TOPC1, 16, 1),
 
+	MUX(0, "mout_aclk_ccore_133", mout_topc_group2,	MUX_SEL_TOPC2, 4, 2),
+
 	MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
 };
 
 static struct samsung_div_clock topc_div_clks[] __initdata = {
+	DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
+		DIV_TOPC0, 4, 4),
+
 	DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
 		DIV_TOPC1, 24, 4),
 
@@ -393,6 +402,51 @@ static void __init exynos7_clk_top1_init(struct device_node *np)
 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
 	exynos7_clk_top1_init);
 
+/* Register Offset definitions for CMU_CCORE (0x105B0000) */
+#define MUX_SEL_CCORE			0x0200
+#define DIV_CCORE			0x0600
+#define ENABLE_ACLK_CCORE0		0x0800
+#define ENABLE_ACLK_CCORE1		0x0804
+#define ENABLE_PCLK_CCORE		0x0900
+
+/*
+ * List of parent clocks for Muxes in CMU_CCORE
+ */
+PNAME(mout_aclk_ccore_133_p)	= { "fin_pll", "dout_aclk_ccore_133" };
+
+static unsigned long ccore_clk_regs[] __initdata = {
+	MUX_SEL_CCORE,
+	ENABLE_PCLK_CCORE,
+};
+
+static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
+	MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
+		MUX_SEL_CCORE, 1, 1),
+};
+
+static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
+	GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
+		ENABLE_PCLK_CCORE, 8, 0, 0),
+};
+
+static struct samsung_cmu_info ccore_cmu_info __initdata = {
+	.mux_clks		= ccore_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(ccore_mux_clks),
+	.gate_clks		= ccore_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(ccore_gate_clks),
+	.nr_clk_ids		= CCORE_NR_CLK,
+	.clk_regs		= ccore_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(ccore_clk_regs),
+};
+
+static void __init exynos7_clk_ccore_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &ccore_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
+	exynos7_clk_ccore_init);
+
 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
 #define MUX_SEL_PERIC0			0x0200
 #define ENABLE_PCLK_PERIC0		0x0900
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index ff63c4e..3227679 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -11,12 +11,13 @@
 #define _DT_BINDINGS_CLOCK_EXYNOS7_H
 
 /* TOPC */
-#define DOUT_ACLK_PERIS			1
-#define DOUT_SCLK_BUS0_PLL		2
-#define DOUT_SCLK_BUS1_PLL		3
-#define DOUT_SCLK_CC_PLL		4
-#define DOUT_SCLK_MFC_PLL		5
-#define TOPC_NR_CLK			6
+#define DOUT_ACLK_CCORE_133		1
+#define DOUT_ACLK_PERIS			2
+#define DOUT_SCLK_BUS0_PLL		3
+#define DOUT_SCLK_BUS1_PLL		4
+#define DOUT_SCLK_CC_PLL		5
+#define DOUT_SCLK_MFC_PLL		6
+#define TOPC_NR_CLK			7
 
 /* TOP0 */
 #define DOUT_ACLK_PERIC1		1
@@ -38,6 +39,10 @@
 #define CLK_SCLK_MMC0			8
 #define TOP1_NR_CLK			9
 
+/* CCORE */
+#define PCLK_RTC			1
+#define CCORE_NR_CLK			2
+
 /* PERIC0 */
 #define PCLK_UART0			1
 #define SCLK_UART0			2
-- 
1.7.9.5

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^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 3/7] clk: samsung: exynos7: add clocks for RTC block
@ 2014-10-17 16:11     ` Abhilash Kesavan
  0 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel

From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>

Add clock support for the RTC block in Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 .../devicetree/bindings/clock/exynos7-clock.txt    |    1 +
 drivers/clk/samsung/clk-exynos7.c                  |   54 ++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h            |   17 +++---
 3 files changed, 66 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 4c69b66..aff6fd2 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -28,6 +28,7 @@ Required Properties for Clock Controller:
 	- "samsung,exynos7-clock-topc"
 	- "samsung,exynos7-clock-top0"
 	- "samsung,exynos7-clock-top1"
+	- "samsung,exynos7-clock-ccore"
 	- "samsung,exynos7-clock-peric0"
 	- "samsung,exynos7-clock-peric1"
 	- "samsung,exynos7-clock-peris"
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index f5e43fa..3a30f43 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -29,7 +29,9 @@
 #define AUD_PLL_CON0		0x0140
 #define MUX_SEL_TOPC0		0x0200
 #define MUX_SEL_TOPC1		0x0204
+#define MUX_SEL_TOPC2		0x0208
 #define MUX_SEL_TOPC3		0x020C
+#define DIV_TOPC0		0x0600
 #define DIV_TOPC1		0x0604
 #define DIV_TOPC3		0x060C
 
@@ -78,7 +80,9 @@ static unsigned long topc_clk_regs[] __initdata = {
 	AUD_PLL_CON0,
 	MUX_SEL_TOPC0,
 	MUX_SEL_TOPC1,
+	MUX_SEL_TOPC2,
 	MUX_SEL_TOPC3,
+	DIV_TOPC0,
 	DIV_TOPC1,
 	DIV_TOPC3,
 };
@@ -101,10 +105,15 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
 	MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
 		MUX_SEL_TOPC1, 16, 1),
 
+	MUX(0, "mout_aclk_ccore_133", mout_topc_group2,	MUX_SEL_TOPC2, 4, 2),
+
 	MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
 };
 
 static struct samsung_div_clock topc_div_clks[] __initdata = {
+	DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
+		DIV_TOPC0, 4, 4),
+
 	DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
 		DIV_TOPC1, 24, 4),
 
@@ -393,6 +402,51 @@ static void __init exynos7_clk_top1_init(struct device_node *np)
 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
 	exynos7_clk_top1_init);
 
+/* Register Offset definitions for CMU_CCORE (0x105B0000) */
+#define MUX_SEL_CCORE			0x0200
+#define DIV_CCORE			0x0600
+#define ENABLE_ACLK_CCORE0		0x0800
+#define ENABLE_ACLK_CCORE1		0x0804
+#define ENABLE_PCLK_CCORE		0x0900
+
+/*
+ * List of parent clocks for Muxes in CMU_CCORE
+ */
+PNAME(mout_aclk_ccore_133_p)	= { "fin_pll", "dout_aclk_ccore_133" };
+
+static unsigned long ccore_clk_regs[] __initdata = {
+	MUX_SEL_CCORE,
+	ENABLE_PCLK_CCORE,
+};
+
+static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
+	MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
+		MUX_SEL_CCORE, 1, 1),
+};
+
+static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
+	GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
+		ENABLE_PCLK_CCORE, 8, 0, 0),
+};
+
+static struct samsung_cmu_info ccore_cmu_info __initdata = {
+	.mux_clks		= ccore_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(ccore_mux_clks),
+	.gate_clks		= ccore_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(ccore_gate_clks),
+	.nr_clk_ids		= CCORE_NR_CLK,
+	.clk_regs		= ccore_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(ccore_clk_regs),
+};
+
+static void __init exynos7_clk_ccore_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &ccore_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
+	exynos7_clk_ccore_init);
+
 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
 #define MUX_SEL_PERIC0			0x0200
 #define ENABLE_PCLK_PERIC0		0x0900
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index ff63c4e..3227679 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -11,12 +11,13 @@
 #define _DT_BINDINGS_CLOCK_EXYNOS7_H
 
 /* TOPC */
-#define DOUT_ACLK_PERIS			1
-#define DOUT_SCLK_BUS0_PLL		2
-#define DOUT_SCLK_BUS1_PLL		3
-#define DOUT_SCLK_CC_PLL		4
-#define DOUT_SCLK_MFC_PLL		5
-#define TOPC_NR_CLK			6
+#define DOUT_ACLK_CCORE_133		1
+#define DOUT_ACLK_PERIS			2
+#define DOUT_SCLK_BUS0_PLL		3
+#define DOUT_SCLK_BUS1_PLL		4
+#define DOUT_SCLK_CC_PLL		5
+#define DOUT_SCLK_MFC_PLL		6
+#define TOPC_NR_CLK			7
 
 /* TOP0 */
 #define DOUT_ACLK_PERIC1		1
@@ -38,6 +39,10 @@
 #define CLK_SCLK_MMC0			8
 #define TOP1_NR_CLK			9
 
+/* CCORE */
+#define PCLK_RTC			1
+#define CCORE_NR_CLK			2
+
 /* PERIC0 */
 #define PCLK_UART0			1
 #define SCLK_UART0			2
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 4/7] clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks
  2014-10-17 16:11 ` Abhilash Kesavan
@ 2014-10-17 16:11   ` Abhilash Kesavan
  -1 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: linux-samsung-soc, catalin.marinas, robh, devicetree, tomasz.figa

From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>

Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |   14 ++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h |    9 +++++++--
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 3a30f43..17e5cf4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -486,9 +486,12 @@ static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
 		ENABLE_PCLK_PERIC0, 14, 0, 0),
 	GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
 		ENABLE_PCLK_PERIC0, 16, 0, 0),
+	GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 21, 0, 0),
 
 	GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
 		ENABLE_SCLK_PERIC0, 16, 0, 0),
+	GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
 };
 
 static struct samsung_cmu_info peric0_cmu_info __initdata = {
@@ -586,7 +589,9 @@ CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
 
 /* Register Offset definitions for CMU_PERIS (0x10040000) */
 #define MUX_SEL_PERIS			0x0200
+#define ENABLE_PCLK_PERIS		0x0900
 #define ENABLE_PCLK_PERIS_SECURE_CHIPID	0x0910
+#define ENABLE_SCLK_PERIS		0x0A00
 #define ENABLE_SCLK_PERIS_SECURE_CHIPID	0x0A10
 
 /* List of parent clocks for Muxes in CMU_PERIS */
@@ -594,7 +599,9 @@ PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
 
 static unsigned long peris_clk_regs[] __initdata = {
 	MUX_SEL_PERIS,
+	ENABLE_PCLK_PERIS,
 	ENABLE_PCLK_PERIS_SECURE_CHIPID,
+	ENABLE_SCLK_PERIS,
 	ENABLE_SCLK_PERIS_SECURE_CHIPID,
 };
 
@@ -604,10 +611,17 @@ static struct samsung_mux_clock peris_mux_clks[] __initdata = {
 };
 
 static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+	GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
+		ENABLE_PCLK_PERIS, 6, 0, 0),
+	GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
+		ENABLE_PCLK_PERIS, 10, 0, 0),
+
 	GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
 		ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
 	GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
 		ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+	GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
 };
 
 static struct samsung_cmu_info peris_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 3227679..28c8aa7 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -53,7 +53,9 @@
 #define PCLK_HSI2C9			7
 #define PCLK_HSI2C10			8
 #define PCLK_HSI2C11			9
-#define PERIC0_NR_CLK			10
+#define PCLK_PWM			10
+#define SCLK_PWM			11
+#define PERIC0_NR_CLK			12
 
 /* PERIC1 */
 #define PCLK_UART1			1
@@ -72,7 +74,10 @@
 /* PERIS */
 #define PCLK_CHIPID			1
 #define SCLK_CHIPID			2
-#define PERIS_NR_CLK			3
+#define PCLK_WDT			3
+#define PCLK_TMU			4
+#define SCLK_TMU			5
+#define PERIS_NR_CLK			6
 
 /* FSYS0 */
 #define ACLK_MMC2			1
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 4/7] clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks
@ 2014-10-17 16:11   ` Abhilash Kesavan
  0 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel

From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>

Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |   14 ++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h |    9 +++++++--
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 3a30f43..17e5cf4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -486,9 +486,12 @@ static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
 		ENABLE_PCLK_PERIC0, 14, 0, 0),
 	GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
 		ENABLE_PCLK_PERIC0, 16, 0, 0),
+	GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
+		ENABLE_PCLK_PERIC0, 21, 0, 0),
 
 	GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
 		ENABLE_SCLK_PERIC0, 16, 0, 0),
+	GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
 };
 
 static struct samsung_cmu_info peric0_cmu_info __initdata = {
@@ -586,7 +589,9 @@ CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
 
 /* Register Offset definitions for CMU_PERIS (0x10040000) */
 #define MUX_SEL_PERIS			0x0200
+#define ENABLE_PCLK_PERIS		0x0900
 #define ENABLE_PCLK_PERIS_SECURE_CHIPID	0x0910
+#define ENABLE_SCLK_PERIS		0x0A00
 #define ENABLE_SCLK_PERIS_SECURE_CHIPID	0x0A10
 
 /* List of parent clocks for Muxes in CMU_PERIS */
@@ -594,7 +599,9 @@ PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
 
 static unsigned long peris_clk_regs[] __initdata = {
 	MUX_SEL_PERIS,
+	ENABLE_PCLK_PERIS,
 	ENABLE_PCLK_PERIS_SECURE_CHIPID,
+	ENABLE_SCLK_PERIS,
 	ENABLE_SCLK_PERIS_SECURE_CHIPID,
 };
 
@@ -604,10 +611,17 @@ static struct samsung_mux_clock peris_mux_clks[] __initdata = {
 };
 
 static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+	GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
+		ENABLE_PCLK_PERIS, 6, 0, 0),
+	GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
+		ENABLE_PCLK_PERIS, 10, 0, 0),
+
 	GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
 		ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
 	GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
 		ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+	GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
 };
 
 static struct samsung_cmu_info peris_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 3227679..28c8aa7 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -53,7 +53,9 @@
 #define PCLK_HSI2C9			7
 #define PCLK_HSI2C10			8
 #define PCLK_HSI2C11			9
-#define PERIC0_NR_CLK			10
+#define PCLK_PWM			10
+#define SCLK_PWM			11
+#define PERIC0_NR_CLK			12
 
 /* PERIC1 */
 #define PCLK_UART1			1
@@ -72,7 +74,10 @@
 /* PERIS */
 #define PCLK_CHIPID			1
 #define SCLK_CHIPID			2
-#define PERIS_NR_CLK			3
+#define PCLK_WDT			3
+#define PCLK_TMU			4
+#define SCLK_TMU			5
+#define PERIS_NR_CLK			6
 
 /* FSYS0 */
 #define ACLK_MMC2			1
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 5/7] arm64: dts: Add PMU DT node for exynos7 SoC
  2014-10-17 16:11 ` Abhilash Kesavan
@ 2014-10-17 16:11   ` Abhilash Kesavan
  -1 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: linux-samsung-soc, catalin.marinas, robh, devicetree, tomasz.figa

Adds PMU DT node for exynos7 SoC.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 .../devicetree/bindings/arm/samsung/pmu.txt        |    1 +
 arch/arm64/boot/dts/exynos/exynos7.dtsi            |    5 +++++
 2 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..67b2113 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -10,6 +10,7 @@ Properties:
 		   - "samsung,exynos5260-pmu" - for Exynos5260 SoC.
 		   - "samsung,exynos5410-pmu" - for Exynos5410 SoC,
 		   - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+		   - "samsung,exynos7-pmu" - for Exynos7 SoC.
 		second value must be always "syscon".
 
  - reg : offset and length of the register set.
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index ce221ac..6db8c78 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -243,6 +243,11 @@
 				     <1 11 0xff01>,
 				     <1 10 0xff01>;
 		};
+
+		pmu_system_controller: system-controller@105c0000 {
+			compatible = "samsung,exynos7-pmu", "syscon";
+			reg = <0x105c0000 0x5000>;
+		};
 	};
 };
 
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 5/7] arm64: dts: Add PMU DT node for exynos7 SoC
@ 2014-10-17 16:11   ` Abhilash Kesavan
  0 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel

Adds PMU DT node for exynos7 SoC.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 .../devicetree/bindings/arm/samsung/pmu.txt        |    1 +
 arch/arm64/boot/dts/exynos/exynos7.dtsi            |    5 +++++
 2 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..67b2113 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -10,6 +10,7 @@ Properties:
 		   - "samsung,exynos5260-pmu" - for Exynos5260 SoC.
 		   - "samsung,exynos5410-pmu" - for Exynos5410 SoC,
 		   - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+		   - "samsung,exynos7-pmu" - for Exynos7 SoC.
 		second value must be always "syscon".
 
  - reg : offset and length of the register set.
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index ce221ac..6db8c78 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -243,6 +243,11 @@
 				     <1 11 0xff01>,
 				     <1 10 0xff01>;
 		};
+
+		pmu_system_controller: system-controller at 105c0000 {
+			compatible = "samsung,exynos7-pmu", "syscon";
+			reg = <0x105c0000 0x5000>;
+		};
 	};
 };
 
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 6/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7
  2014-10-17 16:11 ` Abhilash Kesavan
@ 2014-10-17 16:11   ` Abhilash Kesavan
  -1 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: linux-samsung-soc, catalin.marinas, robh, devicetree, tomasz.figa

Add nodes for 3 mmc channels, 12 i2c channels, rtc, and watchdog
on Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos7-espresso.dts |   41 ++++
 arch/arm64/boot/dts/exynos/exynos7.dtsi         |  256 +++++++++++++++++++++++
 2 files changed, 297 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index e2c8283..d081c26 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -18,6 +18,8 @@
 
 	aliases {
 		serial0 = &serial_2;
+		mshc0 = &mmc_0;
+		mshc2 = &mmc_2;
 	};
 
 	chosen {
@@ -37,3 +39,42 @@
 &serial_2 {
 	status = "okay";
 };
+
+&rtc {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&mmc_0 {
+	status = "okay";
+	num-slots = <1>;
+	broken-cd;
+	caps2-mmc-hs200-1_8v;
+	supports-highspeed;
+	non-removable;
+	card-detect-delay = <200>;
+	clock-frequency = <800000000>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <0 4>;
+	samsung,dw-mshc-ddr-timing = <0 2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+	bus-width = <8>;
+};
+
+&mmc_2 {
+	status = "okay";
+	num-slots = <1>;
+	supports-highspeed;
+	card-detect-delay = <200>;
+	clock-frequency = <400000000>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <2 3>;
+	samsung,dw-mshc-ddr-timing = <1 2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+	bus-width = <4>;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 6db8c78..1300ded 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -113,6 +113,27 @@
 				      "dout_sclk_mfc_pll";
 		};
 
+		clock_top1: clock-controller@105e0000 {
+			compatible = "samsung,exynos7-clock-top1";
+			reg = <0x105e0000 0xb000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+				 <&clock_topc DOUT_SCLK_BUS1_PLL>,
+				 <&clock_topc DOUT_SCLK_CC_PLL>,
+				 <&clock_topc DOUT_SCLK_MFC_PLL>;
+			clock-names = "fin_pll", "dout_sclk_bus0_pll",
+				      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+				      "dout_sclk_mfc_pll";
+		};
+
+		clock_ccore: clock-controller@105b0000 {
+			compatible = "samsung,exynos7-clock-ccore";
+			reg = <0x105b0000 0xd00>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
+			clock-names = "fin_pll", "dout_aclk_ccore_133";
+		};
+
 		clock_peric0: clock-controller@13610000 {
 			compatible = "samsung,exynos7-clock-peric0";
 			reg = <0x13610000 0xd00>;
@@ -143,6 +164,27 @@
 			clock-names = "fin_pll", "dout_aclk_peris_66";
 		};
 
+		clock_fsys0: clock-controller@10e90000 {
+			compatible = "samsung,exynos7-clock-fsys0";
+			reg = <0x10e90000 0xd00>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
+				 <&clock_top1 DOUT_SCLK_MMC2>;
+			clock-names = "fin_pll", "dout_aclk_fsys0_200",
+				      "dout_sclk_mmc2";
+		};
+
+		clock_fsys1: clock-controller@156e0000 {
+			compatible = "samsung,exynos7-clock-fsys1";
+			reg = <0x156e0000 0xd00>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
+				 <&clock_top1 DOUT_SCLK_MMC0>,
+				 <&clock_top1 DOUT_SCLK_MMC1>;
+			clock-names = "fin_pll", "dout_aclk_fsys1_200",
+				      "dout_sclk_mmc0", "dout_sclk_mmc1";
+		};
+
 		serial_0: serial@13630000 {
 			compatible = "samsung,exynos4210-uart";
 			reg = <0x13630000 0x100>;
@@ -236,6 +278,162 @@
 			interrupts = <0 203 0>;
 		};
 
+		hsi2c_0: hsi2c@13640000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13640000 0x1000>;
+			interrupts = <0 441 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c0_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C0>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_1: hsi2c@13650000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13650000 0x1000>;
+			interrupts = <0 442 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c1_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C1>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_2: hsi2c@14e60000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x14e60000 0x1000>;
+			interrupts = <0 459 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c2_bus>;
+			clocks = <&clock_peric1 PCLK_HSI2C2>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_3: hsi2c@14e70000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x14e70000 0x1000>;
+			interrupts = <0 460 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c3_bus>;
+			clocks = <&clock_peric1 PCLK_HSI2C3>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_4: hsi2c@13660000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13660000 0x1000>;
+			interrupts = <0 443 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c4_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C4>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_5: hsi2c@13670000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13670000 0x1000>;
+			interrupts = <0 444 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c5_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C5>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_6: hsi2c@14e00000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x14e00000 0x1000>;
+			interrupts = <0 461 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c6_bus>;
+			clocks = <&clock_peric1 PCLK_HSI2C6>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_7: hsi2c@13e10000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13e10000 0x1000>;
+			interrupts = <0 462 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c7_bus>;
+			clocks = <&clock_peric1 PCLK_HSI2C7>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_8: hsi2c@14e20000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x14e20000 0x1000>;
+			interrupts = <0 463 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c8_bus>;
+			clocks = <&clock_peric1 PCLK_HSI2C8>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_9: hsi2c@13680000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13680000 0x1000>;
+			interrupts = <0 445 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c9_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C9>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_10: hsi2c@13690000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13690000 0x1000>;
+			interrupts = <0 446 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c10_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C10>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_11: hsi2c@136a0000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x136a0000 0x1000>;
+			interrupts = <0 447 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c11_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C11>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
 		timer {
 			compatible = "arm,armv8-timer";
 			interrupts = <1 13 0xff01>,
@@ -248,6 +446,64 @@
 			compatible = "samsung,exynos7-pmu", "syscon";
 			reg = <0x105c0000 0x5000>;
 		};
+
+		rtc: rtc@10590000 {
+			compatible = "samsung,s3c6410-rtc";
+			reg = <0x10590000 0x100>;
+			interrupts = <0 355 0>, <0 356 0>;
+			clocks = <&clock_ccore PCLK_RTC>;
+			clock-names = "rtc";
+			status = "disabled";
+		};
+
+		watchdog: watchdog@101d0000 {
+			compatible = "samsung,exynos7-wdt";
+			reg = <0x101d0000 0x100>;
+			interrupts = <0 110 0>;
+			clocks = <&clock_peris PCLK_WDT>;
+			clock-names = "watchdog";
+			samsung,syscon-phandle = <&pmu_system_controller>;
+			status = "disabled";
+		};
+
+		mmc_0: mmc@15740000 {
+			compatible = "samsung,exynos7-dw-mshc-smu";
+			interrupts = <0 201 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x15740000 0x2000>;
+			clocks = <&clock_fsys1 ACLK_MMC0>,
+				 <&clock_top1 CLK_SCLK_MMC0>;
+			clock-names = "biu", "ciu";
+			fifo-depth = <0x40>;
+			status = "disabled";
+		};
+
+		mmc_1: mmc@15750000 {
+			compatible = "samsung,exynos7-dw-mshc";
+			interrupts = <0 202 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x15750000 0x2000>;
+			clocks = <&clock_fsys1 ACLK_MMC1>,
+				 <&clock_top1 CLK_SCLK_MMC1>;
+			clock-names = "biu", "ciu";
+			fifo-depth = <0x40>;
+			status = "disabled";
+		};
+
+		mmc_2: mmc@15560000 {
+			compatible = "samsung,exynos7-dw-mshc-smu";
+			interrupts = <0 216 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x15560000 0x2000>;
+			clocks = <&clock_fsys0 ACLK_MMC2>,
+				 <&clock_top1 CLK_SCLK_MMC2>;
+			clock-names = "biu", "ciu";
+			fifo-depth = <0x40>;
+			status = "disabled";
+		};
 	};
 };
 
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 6/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7
@ 2014-10-17 16:11   ` Abhilash Kesavan
  0 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel

Add nodes for 3 mmc channels, 12 i2c channels, rtc, and watchdog
on Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos7-espresso.dts |   41 ++++
 arch/arm64/boot/dts/exynos/exynos7.dtsi         |  256 +++++++++++++++++++++++
 2 files changed, 297 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index e2c8283..d081c26 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -18,6 +18,8 @@
 
 	aliases {
 		serial0 = &serial_2;
+		mshc0 = &mmc_0;
+		mshc2 = &mmc_2;
 	};
 
 	chosen {
@@ -37,3 +39,42 @@
 &serial_2 {
 	status = "okay";
 };
+
+&rtc {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&mmc_0 {
+	status = "okay";
+	num-slots = <1>;
+	broken-cd;
+	caps2-mmc-hs200-1_8v;
+	supports-highspeed;
+	non-removable;
+	card-detect-delay = <200>;
+	clock-frequency = <800000000>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <0 4>;
+	samsung,dw-mshc-ddr-timing = <0 2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+	bus-width = <8>;
+};
+
+&mmc_2 {
+	status = "okay";
+	num-slots = <1>;
+	supports-highspeed;
+	card-detect-delay = <200>;
+	clock-frequency = <400000000>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <2 3>;
+	samsung,dw-mshc-ddr-timing = <1 2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+	bus-width = <4>;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 6db8c78..1300ded 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -113,6 +113,27 @@
 				      "dout_sclk_mfc_pll";
 		};
 
+		clock_top1: clock-controller at 105e0000 {
+			compatible = "samsung,exynos7-clock-top1";
+			reg = <0x105e0000 0xb000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+				 <&clock_topc DOUT_SCLK_BUS1_PLL>,
+				 <&clock_topc DOUT_SCLK_CC_PLL>,
+				 <&clock_topc DOUT_SCLK_MFC_PLL>;
+			clock-names = "fin_pll", "dout_sclk_bus0_pll",
+				      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+				      "dout_sclk_mfc_pll";
+		};
+
+		clock_ccore: clock-controller at 105b0000 {
+			compatible = "samsung,exynos7-clock-ccore";
+			reg = <0x105b0000 0xd00>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
+			clock-names = "fin_pll", "dout_aclk_ccore_133";
+		};
+
 		clock_peric0: clock-controller at 13610000 {
 			compatible = "samsung,exynos7-clock-peric0";
 			reg = <0x13610000 0xd00>;
@@ -143,6 +164,27 @@
 			clock-names = "fin_pll", "dout_aclk_peris_66";
 		};
 
+		clock_fsys0: clock-controller at 10e90000 {
+			compatible = "samsung,exynos7-clock-fsys0";
+			reg = <0x10e90000 0xd00>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
+				 <&clock_top1 DOUT_SCLK_MMC2>;
+			clock-names = "fin_pll", "dout_aclk_fsys0_200",
+				      "dout_sclk_mmc2";
+		};
+
+		clock_fsys1: clock-controller at 156e0000 {
+			compatible = "samsung,exynos7-clock-fsys1";
+			reg = <0x156e0000 0xd00>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
+				 <&clock_top1 DOUT_SCLK_MMC0>,
+				 <&clock_top1 DOUT_SCLK_MMC1>;
+			clock-names = "fin_pll", "dout_aclk_fsys1_200",
+				      "dout_sclk_mmc0", "dout_sclk_mmc1";
+		};
+
 		serial_0: serial at 13630000 {
 			compatible = "samsung,exynos4210-uart";
 			reg = <0x13630000 0x100>;
@@ -236,6 +278,162 @@
 			interrupts = <0 203 0>;
 		};
 
+		hsi2c_0: hsi2c at 13640000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13640000 0x1000>;
+			interrupts = <0 441 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c0_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C0>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_1: hsi2c at 13650000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13650000 0x1000>;
+			interrupts = <0 442 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c1_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C1>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_2: hsi2c at 14e60000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x14e60000 0x1000>;
+			interrupts = <0 459 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c2_bus>;
+			clocks = <&clock_peric1 PCLK_HSI2C2>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_3: hsi2c at 14e70000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x14e70000 0x1000>;
+			interrupts = <0 460 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c3_bus>;
+			clocks = <&clock_peric1 PCLK_HSI2C3>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_4: hsi2c at 13660000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13660000 0x1000>;
+			interrupts = <0 443 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c4_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C4>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_5: hsi2c at 13670000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13670000 0x1000>;
+			interrupts = <0 444 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c5_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C5>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_6: hsi2c at 14e00000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x14e00000 0x1000>;
+			interrupts = <0 461 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c6_bus>;
+			clocks = <&clock_peric1 PCLK_HSI2C6>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_7: hsi2c at 13e10000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13e10000 0x1000>;
+			interrupts = <0 462 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c7_bus>;
+			clocks = <&clock_peric1 PCLK_HSI2C7>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_8: hsi2c at 14e20000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x14e20000 0x1000>;
+			interrupts = <0 463 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c8_bus>;
+			clocks = <&clock_peric1 PCLK_HSI2C8>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_9: hsi2c at 13680000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13680000 0x1000>;
+			interrupts = <0 445 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c9_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C9>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_10: hsi2c at 13690000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x13690000 0x1000>;
+			interrupts = <0 446 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c10_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C10>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
+		hsi2c_11: hsi2c at 136a0000 {
+			compatible = "samsung,exynos7-hsi2c";
+			reg = <0x136a0000 0x1000>;
+			interrupts = <0 447 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hs_i2c11_bus>;
+			clocks = <&clock_peric0 PCLK_HSI2C11>;
+			clock-names = "hsi2c";
+			status = "disabled";
+		};
+
 		timer {
 			compatible = "arm,armv8-timer";
 			interrupts = <1 13 0xff01>,
@@ -248,6 +446,64 @@
 			compatible = "samsung,exynos7-pmu", "syscon";
 			reg = <0x105c0000 0x5000>;
 		};
+
+		rtc: rtc at 10590000 {
+			compatible = "samsung,s3c6410-rtc";
+			reg = <0x10590000 0x100>;
+			interrupts = <0 355 0>, <0 356 0>;
+			clocks = <&clock_ccore PCLK_RTC>;
+			clock-names = "rtc";
+			status = "disabled";
+		};
+
+		watchdog: watchdog at 101d0000 {
+			compatible = "samsung,exynos7-wdt";
+			reg = <0x101d0000 0x100>;
+			interrupts = <0 110 0>;
+			clocks = <&clock_peris PCLK_WDT>;
+			clock-names = "watchdog";
+			samsung,syscon-phandle = <&pmu_system_controller>;
+			status = "disabled";
+		};
+
+		mmc_0: mmc at 15740000 {
+			compatible = "samsung,exynos7-dw-mshc-smu";
+			interrupts = <0 201 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x15740000 0x2000>;
+			clocks = <&clock_fsys1 ACLK_MMC0>,
+				 <&clock_top1 CLK_SCLK_MMC0>;
+			clock-names = "biu", "ciu";
+			fifo-depth = <0x40>;
+			status = "disabled";
+		};
+
+		mmc_1: mmc at 15750000 {
+			compatible = "samsung,exynos7-dw-mshc";
+			interrupts = <0 202 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x15750000 0x2000>;
+			clocks = <&clock_fsys1 ACLK_MMC1>,
+				 <&clock_top1 CLK_SCLK_MMC1>;
+			clock-names = "biu", "ciu";
+			fifo-depth = <0x40>;
+			status = "disabled";
+		};
+
+		mmc_2: mmc at 15560000 {
+			compatible = "samsung,exynos7-dw-mshc-smu";
+			interrupts = <0 216 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x15560000 0x2000>;
+			clocks = <&clock_fsys0 ACLK_MMC2>,
+				 <&clock_top1 CLK_SCLK_MMC2>;
+			clock-names = "biu", "ciu";
+			fifo-depth = <0x40>;
+			status = "disabled";
+		};
 	};
 };
 
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 7/7] arm64: exynos: Enable rtc and watchdog support for Exynos7
  2014-10-17 16:11 ` Abhilash Kesavan
@ 2014-10-17 16:11   ` Abhilash Kesavan
  -1 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: linux-samsung-soc, catalin.marinas, robh, devicetree, tomasz.figa

Enable rtc and watchdog support for exynos7 SoCs.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm64/Kconfig |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 238acff..9bb4e02 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -158,6 +158,9 @@ config ARCH_EXYNOS7
 	select COMMON_CLK_SAMSUNG
 	select PINCTRL
 	select PINCTRL_EXYNOS
+	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select HAVE_S3C_RTC if RTC_CLASS
+
 	help
 	  This enables support for Samsung Exynos7 SoC family
 
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 7/7] arm64: exynos: Enable rtc and watchdog support for Exynos7
@ 2014-10-17 16:11   ` Abhilash Kesavan
  0 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-17 16:11 UTC (permalink / raw)
  To: linux-arm-kernel

Enable rtc and watchdog support for exynos7 SoCs.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm64/Kconfig |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 238acff..9bb4e02 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -158,6 +158,9 @@ config ARCH_EXYNOS7
 	select COMMON_CLK_SAMSUNG
 	select PINCTRL
 	select PINCTRL_EXYNOS
+	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select HAVE_S3C_RTC if RTC_CLASS
+
 	help
 	  This enables support for Samsung Exynos7 SoC family
 
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread

* Re: [PATCH 3/7] clk: samsung: exynos7: add clocks for RTC block
  2014-10-17 16:11     ` Abhilash Kesavan
@ 2014-10-20  9:48       ` Vivek Gautam
  -1 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2014-10-20  9:48 UTC (permalink / raw)
  To: Abhilash Kesavan
  Cc: linux-arm-kernel, linux-samsung-soc, catalin.marinas, robh,
	devicetree, Tomasz Figa

Hi Abhilash,


On Fri, Oct 17, 2014 at 9:41 PM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
> From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>
> Add clock support for the RTC block in Exynos7.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  .../devicetree/bindings/clock/exynos7-clock.txt    |    1 +
>  drivers/clk/samsung/clk-exynos7.c                  |   54 ++++++++++++++++++++
>  include/dt-bindings/clock/exynos7-clk.h            |   17 +++---
>  3 files changed, 66 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> index 4c69b66..aff6fd2 100644
> --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> @@ -28,6 +28,7 @@ Required Properties for Clock Controller:
>         - "samsung,exynos7-clock-topc"
>         - "samsung,exynos7-clock-top0"
>         - "samsung,exynos7-clock-top1"
> +       - "samsung,exynos7-clock-ccore"

just a nit.
you need to mention the clock sources for this block too, like it's
there for every other block in this Documentation ?

>         - "samsung,exynos7-clock-peric0"
>         - "samsung,exynos7-clock-peric1"
>         - "samsung,exynos7-clock-peris"
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index f5e43fa..3a30f43 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -29,7 +29,9 @@
>  #define AUD_PLL_CON0           0x0140
>  #define MUX_SEL_TOPC0          0x0200
>  #define MUX_SEL_TOPC1          0x0204
> +#define MUX_SEL_TOPC2          0x0208
>  #define MUX_SEL_TOPC3          0x020C
> +#define DIV_TOPC0              0x0600
>  #define DIV_TOPC1              0x0604
>  #define DIV_TOPC3              0x060C
>
> @@ -78,7 +80,9 @@ static unsigned long topc_clk_regs[] __initdata = {
>         AUD_PLL_CON0,
>         MUX_SEL_TOPC0,
>         MUX_SEL_TOPC1,
> +       MUX_SEL_TOPC2,
>         MUX_SEL_TOPC3,
> +       DIV_TOPC0,
>         DIV_TOPC1,
>         DIV_TOPC3,
>  };
> @@ -101,10 +105,15 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
>         MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
>                 MUX_SEL_TOPC1, 16, 1),
>
> +       MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
> +
>         MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
>  };
>
>  static struct samsung_div_clock topc_div_clks[] __initdata = {
> +       DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
> +               DIV_TOPC0, 4, 4),
> +
>         DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
>                 DIV_TOPC1, 24, 4),
>
> @@ -393,6 +402,51 @@ static void __init exynos7_clk_top1_init(struct device_node *np)
>  CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
>         exynos7_clk_top1_init);
>
> +/* Register Offset definitions for CMU_CCORE (0x105B0000) */
> +#define MUX_SEL_CCORE                  0x0200
> +#define DIV_CCORE                      0x0600
> +#define ENABLE_ACLK_CCORE0             0x0800
> +#define ENABLE_ACLK_CCORE1             0x0804
> +#define ENABLE_PCLK_CCORE              0x0900
> +
> +/*
> + * List of parent clocks for Muxes in CMU_CCORE
> + */
> +PNAME(mout_aclk_ccore_133_p)   = { "fin_pll", "dout_aclk_ccore_133" };
> +
> +static unsigned long ccore_clk_regs[] __initdata = {
> +       MUX_SEL_CCORE,
> +       ENABLE_PCLK_CCORE,
> +};
> +
> +static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
> +       MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
> +               MUX_SEL_CCORE, 1, 1),
> +};
> +
> +static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
> +       GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
> +               ENABLE_PCLK_CCORE, 8, 0, 0),
> +};
> +
> +static struct samsung_cmu_info ccore_cmu_info __initdata = {
> +       .mux_clks               = ccore_mux_clks,
> +       .nr_mux_clks            = ARRAY_SIZE(ccore_mux_clks),
> +       .gate_clks              = ccore_gate_clks,
> +       .nr_gate_clks           = ARRAY_SIZE(ccore_gate_clks),
> +       .nr_clk_ids             = CCORE_NR_CLK,
> +       .clk_regs               = ccore_clk_regs,
> +       .nr_clk_regs            = ARRAY_SIZE(ccore_clk_regs),
> +};
> +
> +static void __init exynos7_clk_ccore_init(struct device_node *np)
> +{
> +       samsung_cmu_register_one(np, &ccore_cmu_info);
> +}
> +
> +CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
> +       exynos7_clk_ccore_init);
> +
>  /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
>  #define MUX_SEL_PERIC0                 0x0200
>  #define ENABLE_PCLK_PERIC0             0x0900
> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
> index ff63c4e..3227679 100644
> --- a/include/dt-bindings/clock/exynos7-clk.h
> +++ b/include/dt-bindings/clock/exynos7-clk.h
> @@ -11,12 +11,13 @@
>  #define _DT_BINDINGS_CLOCK_EXYNOS7_H
>
>  /* TOPC */
> -#define DOUT_ACLK_PERIS                        1
> -#define DOUT_SCLK_BUS0_PLL             2
> -#define DOUT_SCLK_BUS1_PLL             3
> -#define DOUT_SCLK_CC_PLL               4
> -#define DOUT_SCLK_MFC_PLL              5
> -#define TOPC_NR_CLK                    6
> +#define DOUT_ACLK_CCORE_133            1
> +#define DOUT_ACLK_PERIS                        2
> +#define DOUT_SCLK_BUS0_PLL             3
> +#define DOUT_SCLK_BUS1_PLL             4
> +#define DOUT_SCLK_CC_PLL               5
> +#define DOUT_SCLK_MFC_PLL              6
> +#define TOPC_NR_CLK                    7
>
>  /* TOP0 */
>  #define DOUT_ACLK_PERIC1               1
> @@ -38,6 +39,10 @@
>  #define CLK_SCLK_MMC0                  8
>  #define TOP1_NR_CLK                    9
>
> +/* CCORE */
> +#define PCLK_RTC                       1
> +#define CCORE_NR_CLK                   2
> +
>  /* PERIC0 */
>  #define PCLK_UART0                     1
>  #define SCLK_UART0                     2
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH 3/7] clk: samsung: exynos7: add clocks for RTC block
@ 2014-10-20  9:48       ` Vivek Gautam
  0 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2014-10-20  9:48 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Abhilash,


On Fri, Oct 17, 2014 at 9:41 PM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
> From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>
> Add clock support for the RTC block in Exynos7.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  .../devicetree/bindings/clock/exynos7-clock.txt    |    1 +
>  drivers/clk/samsung/clk-exynos7.c                  |   54 ++++++++++++++++++++
>  include/dt-bindings/clock/exynos7-clk.h            |   17 +++---
>  3 files changed, 66 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> index 4c69b66..aff6fd2 100644
> --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> @@ -28,6 +28,7 @@ Required Properties for Clock Controller:
>         - "samsung,exynos7-clock-topc"
>         - "samsung,exynos7-clock-top0"
>         - "samsung,exynos7-clock-top1"
> +       - "samsung,exynos7-clock-ccore"

just a nit.
you need to mention the clock sources for this block too, like it's
there for every other block in this Documentation ?

>         - "samsung,exynos7-clock-peric0"
>         - "samsung,exynos7-clock-peric1"
>         - "samsung,exynos7-clock-peris"
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index f5e43fa..3a30f43 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -29,7 +29,9 @@
>  #define AUD_PLL_CON0           0x0140
>  #define MUX_SEL_TOPC0          0x0200
>  #define MUX_SEL_TOPC1          0x0204
> +#define MUX_SEL_TOPC2          0x0208
>  #define MUX_SEL_TOPC3          0x020C
> +#define DIV_TOPC0              0x0600
>  #define DIV_TOPC1              0x0604
>  #define DIV_TOPC3              0x060C
>
> @@ -78,7 +80,9 @@ static unsigned long topc_clk_regs[] __initdata = {
>         AUD_PLL_CON0,
>         MUX_SEL_TOPC0,
>         MUX_SEL_TOPC1,
> +       MUX_SEL_TOPC2,
>         MUX_SEL_TOPC3,
> +       DIV_TOPC0,
>         DIV_TOPC1,
>         DIV_TOPC3,
>  };
> @@ -101,10 +105,15 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
>         MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
>                 MUX_SEL_TOPC1, 16, 1),
>
> +       MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
> +
>         MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
>  };
>
>  static struct samsung_div_clock topc_div_clks[] __initdata = {
> +       DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
> +               DIV_TOPC0, 4, 4),
> +
>         DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
>                 DIV_TOPC1, 24, 4),
>
> @@ -393,6 +402,51 @@ static void __init exynos7_clk_top1_init(struct device_node *np)
>  CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
>         exynos7_clk_top1_init);
>
> +/* Register Offset definitions for CMU_CCORE (0x105B0000) */
> +#define MUX_SEL_CCORE                  0x0200
> +#define DIV_CCORE                      0x0600
> +#define ENABLE_ACLK_CCORE0             0x0800
> +#define ENABLE_ACLK_CCORE1             0x0804
> +#define ENABLE_PCLK_CCORE              0x0900
> +
> +/*
> + * List of parent clocks for Muxes in CMU_CCORE
> + */
> +PNAME(mout_aclk_ccore_133_p)   = { "fin_pll", "dout_aclk_ccore_133" };
> +
> +static unsigned long ccore_clk_regs[] __initdata = {
> +       MUX_SEL_CCORE,
> +       ENABLE_PCLK_CCORE,
> +};
> +
> +static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
> +       MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
> +               MUX_SEL_CCORE, 1, 1),
> +};
> +
> +static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
> +       GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
> +               ENABLE_PCLK_CCORE, 8, 0, 0),
> +};
> +
> +static struct samsung_cmu_info ccore_cmu_info __initdata = {
> +       .mux_clks               = ccore_mux_clks,
> +       .nr_mux_clks            = ARRAY_SIZE(ccore_mux_clks),
> +       .gate_clks              = ccore_gate_clks,
> +       .nr_gate_clks           = ARRAY_SIZE(ccore_gate_clks),
> +       .nr_clk_ids             = CCORE_NR_CLK,
> +       .clk_regs               = ccore_clk_regs,
> +       .nr_clk_regs            = ARRAY_SIZE(ccore_clk_regs),
> +};
> +
> +static void __init exynos7_clk_ccore_init(struct device_node *np)
> +{
> +       samsung_cmu_register_one(np, &ccore_cmu_info);
> +}
> +
> +CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
> +       exynos7_clk_ccore_init);
> +
>  /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
>  #define MUX_SEL_PERIC0                 0x0200
>  #define ENABLE_PCLK_PERIC0             0x0900
> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
> index ff63c4e..3227679 100644
> --- a/include/dt-bindings/clock/exynos7-clk.h
> +++ b/include/dt-bindings/clock/exynos7-clk.h
> @@ -11,12 +11,13 @@
>  #define _DT_BINDINGS_CLOCK_EXYNOS7_H
>
>  /* TOPC */
> -#define DOUT_ACLK_PERIS                        1
> -#define DOUT_SCLK_BUS0_PLL             2
> -#define DOUT_SCLK_BUS1_PLL             3
> -#define DOUT_SCLK_CC_PLL               4
> -#define DOUT_SCLK_MFC_PLL              5
> -#define TOPC_NR_CLK                    6
> +#define DOUT_ACLK_CCORE_133            1
> +#define DOUT_ACLK_PERIS                        2
> +#define DOUT_SCLK_BUS0_PLL             3
> +#define DOUT_SCLK_BUS1_PLL             4
> +#define DOUT_SCLK_CC_PLL               5
> +#define DOUT_SCLK_MFC_PLL              6
> +#define TOPC_NR_CLK                    7
>
>  /* TOP0 */
>  #define DOUT_ACLK_PERIC1               1
> @@ -38,6 +39,10 @@
>  #define CLK_SCLK_MMC0                  8
>  #define TOP1_NR_CLK                    9
>
> +/* CCORE */
> +#define PCLK_RTC                       1
> +#define CCORE_NR_CLK                   2
> +
>  /* PERIC0 */
>  #define PCLK_UART0                     1
>  #define SCLK_UART0                     2
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block
  2014-10-17 16:11   ` Abhilash Kesavan
@ 2014-10-20  9:49     ` Vivek Gautam
  -1 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2014-10-20  9:49 UTC (permalink / raw)
  To: Abhilash Kesavan
  Cc: linux-arm-kernel, linux-samsung-soc, catalin.marinas, robh,
	devicetree, Tomasz Figa

Hi Abhilash,


On Fri, Oct 17, 2014 at 9:41 PM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
> From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>
> Exynos7 supports 3 MMC channels, add the MMC gate clocks to
> support them.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  .../devicetree/bindings/clock/exynos7-clock.txt    |    3 +
>  drivers/clk/samsung/clk-exynos7.c                  |  224 ++++++++++++++++++++
>  include/dt-bindings/clock/exynos7-clk.h            |   20 ++
>  3 files changed, 247 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> index 789f761..4c69b66 100644
> --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> @@ -27,9 +27,12 @@ Required Properties for Clock Controller:
>
>         - "samsung,exynos7-clock-topc"
>         - "samsung,exynos7-clock-top0"
> +       - "samsung,exynos7-clock-top1"
>         - "samsung,exynos7-clock-peric0"
>         - "samsung,exynos7-clock-peric1"
>         - "samsung,exynos7-clock-peris"
> +       - "samsung,exynos7-clock-fsys0"
> +       - "samsung,exynos7-clock-fsys1"

same here, the input clocks for top1, fsys0 and fsys1 block need to be
mentioned in this doc.

>
>   - reg: physical base address of the controller and the length of
>         memory mapped region.
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index c700f65..f5e43fa 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct device_node *np)
>  CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
>         exynos7_clk_top0_init);
>
> +/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
> +#define MUX_SEL_TOP10                  0x0200
> +#define MUX_SEL_TOP11                  0x0204
> +#define MUX_SEL_TOP13                  0x020C
> +#define MUX_SEL_TOP1_FSYS0             0x0224
> +#define MUX_SEL_TOP1_FSYS1             0x0228
> +#define DIV_TOP13                      0x060C
> +#define DIV_TOP1_FSYS0                 0x0624
> +#define DIV_TOP1_FSYS1                 0x0628
> +#define ENABLE_ACLK_TOP13              0x080C
> +#define ENABLE_SCLK_TOP1_FSYS0         0x0A24
> +#define ENABLE_SCLK_TOP1_FSYS1         0x0A28
> +
> +/* List of parent clocks for Muxes in CMU_TOP1 */
> +PNAME(mout_top1_bus0_pll_p)    = { "fin_pll", "dout_sclk_bus0_pll" };
> +PNAME(mout_top1_bus1_pll_p)    = { "fin_pll", "dout_sclk_bus1_pll_b" };
> +PNAME(mout_top1_cc_pll_p)      = { "fin_pll", "dout_sclk_cc_pll_b" };
> +PNAME(mout_top1_mfc_pll_p)     = { "fin_pll", "dout_sclk_mfc_pll_b" };
> +
> +PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
> +       "ffac_top1_bus0_pll_div2"};
> +PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
> +       "ffac_top1_bus1_pll_div2"};
> +PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
> +       "ffac_top1_cc_pll_div2"};
> +PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
> +       "ffac_top1_mfc_pll_div2"};
> +
> +PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
> +       "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
> +       "mout_top1_half_mfc_pll"};
> +
> +static unsigned long top1_clk_regs[] __initdata = {
> +       MUX_SEL_TOP10,
> +       MUX_SEL_TOP11,
> +       MUX_SEL_TOP13,
> +       MUX_SEL_TOP1_FSYS0,
> +       MUX_SEL_TOP1_FSYS1,
> +       DIV_TOP13,
> +       DIV_TOP1_FSYS0,
> +       DIV_TOP1_FSYS1,
> +       ENABLE_ACLK_TOP13,
> +       ENABLE_SCLK_TOP1_FSYS0,
> +       ENABLE_SCLK_TOP1_FSYS1,
> +};
> +
> +static struct samsung_mux_clock top1_mux_clks[] __initdata = {
> +       MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
> +       MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
> +       MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
> +               MUX_SEL_TOP10, 12, 1),
> +       MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
> +               MUX_SEL_TOP10, 16, 1),
> +
> +       MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
> +               MUX_SEL_TOP11, 4, 1),
> +       MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
> +               MUX_SEL_TOP11, 8, 1),
> +       MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
> +               MUX_SEL_TOP11, 12, 1),
> +       MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
> +               MUX_SEL_TOP11, 16, 1),
> +
> +       MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
> +       MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
> +
> +       MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
> +
> +       MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
> +       MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
> +};
> +
> +static struct samsung_div_clock top1_div_clks[] __initdata = {
> +       DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
> +               DIV_TOP13, 24, 4),
> +       DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
> +               DIV_TOP13, 28, 4),
> +
> +       DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
> +               DIV_TOP1_FSYS0, 24, 4),
> +
> +       DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
> +               DIV_TOP1_FSYS1, 24, 4),
> +       DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
> +               DIV_TOP1_FSYS1, 28, 4),
> +};
> +
> +static struct samsung_gate_clock top1_gate_clks[] __initdata = {
> +       GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
> +               ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
> +
> +       GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
> +               ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
> +       GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
> +               ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
> +};
> +
> +static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
> +       FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
> +       FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
> +       FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
> +       FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
> +};
> +
> +static struct samsung_cmu_info top1_cmu_info __initdata = {
> +       .mux_clks               = top1_mux_clks,
> +       .nr_mux_clks            = ARRAY_SIZE(top1_mux_clks),
> +       .div_clks               = top1_div_clks,
> +       .nr_div_clks            = ARRAY_SIZE(top1_div_clks),
> +       .gate_clks              = top1_gate_clks,
> +       .nr_gate_clks           = ARRAY_SIZE(top1_gate_clks),
> +       .fixed_factor_clks      = top1_fixed_factor_clks,
> +       .nr_fixed_factor_clks   = ARRAY_SIZE(top1_fixed_factor_clks),
> +       .nr_clk_ids             = TOP1_NR_CLK,
> +       .clk_regs               = top1_clk_regs,
> +       .nr_clk_regs            = ARRAY_SIZE(top1_clk_regs),
> +};
> +
> +static void __init exynos7_clk_top1_init(struct device_node *np)
> +{
> +       samsung_cmu_register_one(np, &top1_cmu_info);
> +}
> +
> +CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
> +       exynos7_clk_top1_init);
> +
>  /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
>  #define MUX_SEL_PERIC0                 0x0200
>  #define ENABLE_PCLK_PERIC0             0x0900
> @@ -447,3 +573,101 @@ static void __init exynos7_clk_peris_init(struct device_node *np)
>
>  CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
>         exynos7_clk_peris_init);
> +
> +/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
> +#define MUX_SEL_FSYS00                 0x0200
> +#define MUX_SEL_FSYS01                 0x0204
> +#define ENABLE_ACLK_FSYS01             0x0804
> +
> +/*
> + * List of parent clocks for Muxes in CMU_FSYS0
> + */
> +PNAME(mout_aclk_fsys0_200_p)   = { "fin_pll", "dout_aclk_fsys0_200" };
> +PNAME(mout_sclk_mmc2_p)                = { "fin_pll", "sclk_mmc2" };
> +
> +static unsigned long fsys0_clk_regs[] __initdata = {
> +       MUX_SEL_FSYS00,
> +       MUX_SEL_FSYS01,
> +       ENABLE_ACLK_FSYS01,
> +};
> +
> +static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
> +       MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
> +               MUX_SEL_FSYS00, 24, 1),
> +
> +       MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
> +};
> +
> +static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
> +       GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
> +               ENABLE_ACLK_FSYS01, 31, 0, 0),
> +};
> +
> +static struct samsung_cmu_info fsys0_cmu_info __initdata = {
> +       .mux_clks               = fsys0_mux_clks,
> +       .nr_mux_clks            = ARRAY_SIZE(fsys0_mux_clks),
> +       .gate_clks              = fsys0_gate_clks,
> +       .nr_gate_clks           = ARRAY_SIZE(fsys0_gate_clks),
> +       .nr_clk_ids             = TOP1_NR_CLK,
> +       .clk_regs               = fsys0_clk_regs,
> +       .nr_clk_regs            = ARRAY_SIZE(fsys0_clk_regs),
> +};
> +
> +static void __init exynos7_clk_fsys0_init(struct device_node *np)
> +{
> +       samsung_cmu_register_one(np, &fsys0_cmu_info);
> +}
> +
> +CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
> +       exynos7_clk_fsys0_init);
> +
> +/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
> +#define MUX_SEL_FSYS10                 0x0200
> +#define MUX_SEL_FSYS11                 0x0204
> +#define ENABLE_ACLK_FSYS1              0x0800
> +
> +/*
> + * List of parent clocks for Muxes in CMU_FSYS1
> + */
> +PNAME(mout_aclk_fsys1_200_p)   = { "fin_pll",  "dout_aclk_fsys1_200" };
> +PNAME(mout_sclk_mmc0_p)                = { "fin_pll", "sclk_mmc0" };
> +PNAME(mout_sclk_mmc1_p)                = { "fin_pll", "sclk_mmc1" };
> +
> +static unsigned long fsys1_clk_regs[] __initdata = {
> +       MUX_SEL_FSYS10,
> +       MUX_SEL_FSYS11,
> +       ENABLE_ACLK_FSYS1,
> +};
> +
> +static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
> +       MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
> +               MUX_SEL_FSYS10, 28, 1),
> +
> +       MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
> +       MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
> +};
> +
> +static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
> +       GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
> +               ENABLE_ACLK_FSYS1, 29, 0, 0),
> +       GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
> +               ENABLE_ACLK_FSYS1, 30, 0, 0),
> +};
> +
> +static struct samsung_cmu_info fsys1_cmu_info __initdata = {
> +       .mux_clks               = fsys1_mux_clks,
> +       .nr_mux_clks            = ARRAY_SIZE(fsys1_mux_clks),
> +       .gate_clks              = fsys1_gate_clks,
> +       .nr_gate_clks           = ARRAY_SIZE(fsys1_gate_clks),
> +       .nr_clk_ids             = TOP1_NR_CLK,
> +       .clk_regs               = fsys1_clk_regs,
> +       .nr_clk_regs            = ARRAY_SIZE(fsys1_clk_regs),
> +};
> +
> +static void __init exynos7_clk_fsys1_init(struct device_node *np)
> +{
> +       samsung_cmu_register_one(np, &fsys1_cmu_info);
> +}
> +
> +CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
> +       exynos7_clk_fsys1_init);
> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
> index 6d07b6f..ff63c4e 100644
> --- a/include/dt-bindings/clock/exynos7-clk.h
> +++ b/include/dt-bindings/clock/exynos7-clk.h
> @@ -27,6 +27,17 @@
>  #define CLK_SCLK_UART3                 6
>  #define TOP0_NR_CLK                    7
>
> +/* TOP1 */
> +#define DOUT_ACLK_FSYS1_200            1
> +#define DOUT_ACLK_FSYS0_200            2
> +#define DOUT_SCLK_MMC2                 3
> +#define DOUT_SCLK_MMC1                 4
> +#define DOUT_SCLK_MMC0                 5
> +#define CLK_SCLK_MMC2                  6
> +#define CLK_SCLK_MMC1                  7
> +#define CLK_SCLK_MMC0                  8
> +#define TOP1_NR_CLK                    9
> +
>  /* PERIC0 */
>  #define PCLK_UART0                     1
>  #define SCLK_UART0                     2
> @@ -58,4 +69,13 @@
>  #define SCLK_CHIPID                    2
>  #define PERIS_NR_CLK                   3
>
> +/* FSYS0 */
> +#define ACLK_MMC2                      1
> +#define FSYS0_NR_CLK                   2
> +
> +/* FSYS1 */
> +#define ACLK_MMC1                      1
> +#define ACLK_MMC0                      2
> +#define FSYS1_NR_CLK                   3
> +
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block
@ 2014-10-20  9:49     ` Vivek Gautam
  0 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2014-10-20  9:49 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Abhilash,


On Fri, Oct 17, 2014 at 9:41 PM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
> From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>
> Exynos7 supports 3 MMC channels, add the MMC gate clocks to
> support them.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  .../devicetree/bindings/clock/exynos7-clock.txt    |    3 +
>  drivers/clk/samsung/clk-exynos7.c                  |  224 ++++++++++++++++++++
>  include/dt-bindings/clock/exynos7-clk.h            |   20 ++
>  3 files changed, 247 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> index 789f761..4c69b66 100644
> --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> @@ -27,9 +27,12 @@ Required Properties for Clock Controller:
>
>         - "samsung,exynos7-clock-topc"
>         - "samsung,exynos7-clock-top0"
> +       - "samsung,exynos7-clock-top1"
>         - "samsung,exynos7-clock-peric0"
>         - "samsung,exynos7-clock-peric1"
>         - "samsung,exynos7-clock-peris"
> +       - "samsung,exynos7-clock-fsys0"
> +       - "samsung,exynos7-clock-fsys1"

same here, the input clocks for top1, fsys0 and fsys1 block need to be
mentioned in this doc.

>
>   - reg: physical base address of the controller and the length of
>         memory mapped region.
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index c700f65..f5e43fa 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct device_node *np)
>  CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
>         exynos7_clk_top0_init);
>
> +/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
> +#define MUX_SEL_TOP10                  0x0200
> +#define MUX_SEL_TOP11                  0x0204
> +#define MUX_SEL_TOP13                  0x020C
> +#define MUX_SEL_TOP1_FSYS0             0x0224
> +#define MUX_SEL_TOP1_FSYS1             0x0228
> +#define DIV_TOP13                      0x060C
> +#define DIV_TOP1_FSYS0                 0x0624
> +#define DIV_TOP1_FSYS1                 0x0628
> +#define ENABLE_ACLK_TOP13              0x080C
> +#define ENABLE_SCLK_TOP1_FSYS0         0x0A24
> +#define ENABLE_SCLK_TOP1_FSYS1         0x0A28
> +
> +/* List of parent clocks for Muxes in CMU_TOP1 */
> +PNAME(mout_top1_bus0_pll_p)    = { "fin_pll", "dout_sclk_bus0_pll" };
> +PNAME(mout_top1_bus1_pll_p)    = { "fin_pll", "dout_sclk_bus1_pll_b" };
> +PNAME(mout_top1_cc_pll_p)      = { "fin_pll", "dout_sclk_cc_pll_b" };
> +PNAME(mout_top1_mfc_pll_p)     = { "fin_pll", "dout_sclk_mfc_pll_b" };
> +
> +PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
> +       "ffac_top1_bus0_pll_div2"};
> +PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
> +       "ffac_top1_bus1_pll_div2"};
> +PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
> +       "ffac_top1_cc_pll_div2"};
> +PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
> +       "ffac_top1_mfc_pll_div2"};
> +
> +PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
> +       "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
> +       "mout_top1_half_mfc_pll"};
> +
> +static unsigned long top1_clk_regs[] __initdata = {
> +       MUX_SEL_TOP10,
> +       MUX_SEL_TOP11,
> +       MUX_SEL_TOP13,
> +       MUX_SEL_TOP1_FSYS0,
> +       MUX_SEL_TOP1_FSYS1,
> +       DIV_TOP13,
> +       DIV_TOP1_FSYS0,
> +       DIV_TOP1_FSYS1,
> +       ENABLE_ACLK_TOP13,
> +       ENABLE_SCLK_TOP1_FSYS0,
> +       ENABLE_SCLK_TOP1_FSYS1,
> +};
> +
> +static struct samsung_mux_clock top1_mux_clks[] __initdata = {
> +       MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
> +       MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
> +       MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
> +               MUX_SEL_TOP10, 12, 1),
> +       MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
> +               MUX_SEL_TOP10, 16, 1),
> +
> +       MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
> +               MUX_SEL_TOP11, 4, 1),
> +       MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
> +               MUX_SEL_TOP11, 8, 1),
> +       MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
> +               MUX_SEL_TOP11, 12, 1),
> +       MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
> +               MUX_SEL_TOP11, 16, 1),
> +
> +       MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
> +       MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
> +
> +       MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
> +
> +       MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
> +       MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
> +};
> +
> +static struct samsung_div_clock top1_div_clks[] __initdata = {
> +       DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
> +               DIV_TOP13, 24, 4),
> +       DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
> +               DIV_TOP13, 28, 4),
> +
> +       DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
> +               DIV_TOP1_FSYS0, 24, 4),
> +
> +       DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
> +               DIV_TOP1_FSYS1, 24, 4),
> +       DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
> +               DIV_TOP1_FSYS1, 28, 4),
> +};
> +
> +static struct samsung_gate_clock top1_gate_clks[] __initdata = {
> +       GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
> +               ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
> +
> +       GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
> +               ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
> +       GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
> +               ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
> +};
> +
> +static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
> +       FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
> +       FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
> +       FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
> +       FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
> +};
> +
> +static struct samsung_cmu_info top1_cmu_info __initdata = {
> +       .mux_clks               = top1_mux_clks,
> +       .nr_mux_clks            = ARRAY_SIZE(top1_mux_clks),
> +       .div_clks               = top1_div_clks,
> +       .nr_div_clks            = ARRAY_SIZE(top1_div_clks),
> +       .gate_clks              = top1_gate_clks,
> +       .nr_gate_clks           = ARRAY_SIZE(top1_gate_clks),
> +       .fixed_factor_clks      = top1_fixed_factor_clks,
> +       .nr_fixed_factor_clks   = ARRAY_SIZE(top1_fixed_factor_clks),
> +       .nr_clk_ids             = TOP1_NR_CLK,
> +       .clk_regs               = top1_clk_regs,
> +       .nr_clk_regs            = ARRAY_SIZE(top1_clk_regs),
> +};
> +
> +static void __init exynos7_clk_top1_init(struct device_node *np)
> +{
> +       samsung_cmu_register_one(np, &top1_cmu_info);
> +}
> +
> +CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
> +       exynos7_clk_top1_init);
> +
>  /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
>  #define MUX_SEL_PERIC0                 0x0200
>  #define ENABLE_PCLK_PERIC0             0x0900
> @@ -447,3 +573,101 @@ static void __init exynos7_clk_peris_init(struct device_node *np)
>
>  CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
>         exynos7_clk_peris_init);
> +
> +/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
> +#define MUX_SEL_FSYS00                 0x0200
> +#define MUX_SEL_FSYS01                 0x0204
> +#define ENABLE_ACLK_FSYS01             0x0804
> +
> +/*
> + * List of parent clocks for Muxes in CMU_FSYS0
> + */
> +PNAME(mout_aclk_fsys0_200_p)   = { "fin_pll", "dout_aclk_fsys0_200" };
> +PNAME(mout_sclk_mmc2_p)                = { "fin_pll", "sclk_mmc2" };
> +
> +static unsigned long fsys0_clk_regs[] __initdata = {
> +       MUX_SEL_FSYS00,
> +       MUX_SEL_FSYS01,
> +       ENABLE_ACLK_FSYS01,
> +};
> +
> +static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
> +       MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
> +               MUX_SEL_FSYS00, 24, 1),
> +
> +       MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
> +};
> +
> +static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
> +       GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
> +               ENABLE_ACLK_FSYS01, 31, 0, 0),
> +};
> +
> +static struct samsung_cmu_info fsys0_cmu_info __initdata = {
> +       .mux_clks               = fsys0_mux_clks,
> +       .nr_mux_clks            = ARRAY_SIZE(fsys0_mux_clks),
> +       .gate_clks              = fsys0_gate_clks,
> +       .nr_gate_clks           = ARRAY_SIZE(fsys0_gate_clks),
> +       .nr_clk_ids             = TOP1_NR_CLK,
> +       .clk_regs               = fsys0_clk_regs,
> +       .nr_clk_regs            = ARRAY_SIZE(fsys0_clk_regs),
> +};
> +
> +static void __init exynos7_clk_fsys0_init(struct device_node *np)
> +{
> +       samsung_cmu_register_one(np, &fsys0_cmu_info);
> +}
> +
> +CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
> +       exynos7_clk_fsys0_init);
> +
> +/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
> +#define MUX_SEL_FSYS10                 0x0200
> +#define MUX_SEL_FSYS11                 0x0204
> +#define ENABLE_ACLK_FSYS1              0x0800
> +
> +/*
> + * List of parent clocks for Muxes in CMU_FSYS1
> + */
> +PNAME(mout_aclk_fsys1_200_p)   = { "fin_pll",  "dout_aclk_fsys1_200" };
> +PNAME(mout_sclk_mmc0_p)                = { "fin_pll", "sclk_mmc0" };
> +PNAME(mout_sclk_mmc1_p)                = { "fin_pll", "sclk_mmc1" };
> +
> +static unsigned long fsys1_clk_regs[] __initdata = {
> +       MUX_SEL_FSYS10,
> +       MUX_SEL_FSYS11,
> +       ENABLE_ACLK_FSYS1,
> +};
> +
> +static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
> +       MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
> +               MUX_SEL_FSYS10, 28, 1),
> +
> +       MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
> +       MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
> +};
> +
> +static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
> +       GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
> +               ENABLE_ACLK_FSYS1, 29, 0, 0),
> +       GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
> +               ENABLE_ACLK_FSYS1, 30, 0, 0),
> +};
> +
> +static struct samsung_cmu_info fsys1_cmu_info __initdata = {
> +       .mux_clks               = fsys1_mux_clks,
> +       .nr_mux_clks            = ARRAY_SIZE(fsys1_mux_clks),
> +       .gate_clks              = fsys1_gate_clks,
> +       .nr_gate_clks           = ARRAY_SIZE(fsys1_gate_clks),
> +       .nr_clk_ids             = TOP1_NR_CLK,
> +       .clk_regs               = fsys1_clk_regs,
> +       .nr_clk_regs            = ARRAY_SIZE(fsys1_clk_regs),
> +};
> +
> +static void __init exynos7_clk_fsys1_init(struct device_node *np)
> +{
> +       samsung_cmu_register_one(np, &fsys1_cmu_info);
> +}
> +
> +CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
> +       exynos7_clk_fsys1_init);
> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
> index 6d07b6f..ff63c4e 100644
> --- a/include/dt-bindings/clock/exynos7-clk.h
> +++ b/include/dt-bindings/clock/exynos7-clk.h
> @@ -27,6 +27,17 @@
>  #define CLK_SCLK_UART3                 6
>  #define TOP0_NR_CLK                    7
>
> +/* TOP1 */
> +#define DOUT_ACLK_FSYS1_200            1
> +#define DOUT_ACLK_FSYS0_200            2
> +#define DOUT_SCLK_MMC2                 3
> +#define DOUT_SCLK_MMC1                 4
> +#define DOUT_SCLK_MMC0                 5
> +#define CLK_SCLK_MMC2                  6
> +#define CLK_SCLK_MMC1                  7
> +#define CLK_SCLK_MMC0                  8
> +#define TOP1_NR_CLK                    9
> +
>  /* PERIC0 */
>  #define PCLK_UART0                     1
>  #define SCLK_UART0                     2
> @@ -58,4 +69,13 @@
>  #define SCLK_CHIPID                    2
>  #define PERIS_NR_CLK                   3
>
> +/* FSYS0 */
> +#define ACLK_MMC2                      1
> +#define FSYS0_NR_CLK                   2
> +
> +/* FSYS1 */
> +#define ACLK_MMC1                      1
> +#define ACLK_MMC0                      2
> +#define FSYS1_NR_CLK                   3
> +
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block
  2014-10-20  9:49     ` Vivek Gautam
@ 2014-10-20 13:58       ` Abhilash Kesavan
  -1 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-20 13:58 UTC (permalink / raw)
  To: Vivek Gautam
  Cc: devicetree, linux-samsung-soc, robh, Catalin Marinas,
	Tomasz Figa, linux-arm-kernel

Hi Vivek,

On Mon, Oct 20, 2014 at 3:19 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> Hi Abhilash,
>
>
> On Fri, Oct 17, 2014 at 9:41 PM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
>> From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>>
>> Exynos7 supports 3 MMC channels, add the MMC gate clocks to
>> support them.
>>
>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  .../devicetree/bindings/clock/exynos7-clock.txt    |    3 +
>>  drivers/clk/samsung/clk-exynos7.c                  |  224 ++++++++++++++++++++
>>  include/dt-bindings/clock/exynos7-clk.h            |   20 ++
>>  3 files changed, 247 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
>> index 789f761..4c69b66 100644
>> --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
>> +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
>> @@ -27,9 +27,12 @@ Required Properties for Clock Controller:
>>
>>         - "samsung,exynos7-clock-topc"
>>         - "samsung,exynos7-clock-top0"
>> +       - "samsung,exynos7-clock-top1"
>>         - "samsung,exynos7-clock-peric0"
>>         - "samsung,exynos7-clock-peric1"
>>         - "samsung,exynos7-clock-peris"
>> +       - "samsung,exynos7-clock-fsys0"
>> +       - "samsung,exynos7-clock-fsys1"
>
> same here, the input clocks for top1, fsys0 and fsys1 block need to be
> mentioned in this doc.

Thanks for the review. I missed adding these, will fix in the next version.

Regards,
Abhilash
>
>>
>>   - reg: physical base address of the controller and the length of
>>         memory mapped region.
>> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
>> index c700f65..f5e43fa 100644
>> --- a/drivers/clk/samsung/clk-exynos7.c
>> +++ b/drivers/clk/samsung/clk-exynos7.c
>> @@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct device_node *np)
>>  CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
>>         exynos7_clk_top0_init);
>>
>> +/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
>> +#define MUX_SEL_TOP10                  0x0200
>> +#define MUX_SEL_TOP11                  0x0204
>> +#define MUX_SEL_TOP13                  0x020C
>> +#define MUX_SEL_TOP1_FSYS0             0x0224
>> +#define MUX_SEL_TOP1_FSYS1             0x0228
>> +#define DIV_TOP13                      0x060C
>> +#define DIV_TOP1_FSYS0                 0x0624
>> +#define DIV_TOP1_FSYS1                 0x0628
>> +#define ENABLE_ACLK_TOP13              0x080C
>> +#define ENABLE_SCLK_TOP1_FSYS0         0x0A24
>> +#define ENABLE_SCLK_TOP1_FSYS1         0x0A28
>> +
>> +/* List of parent clocks for Muxes in CMU_TOP1 */
>> +PNAME(mout_top1_bus0_pll_p)    = { "fin_pll", "dout_sclk_bus0_pll" };
>> +PNAME(mout_top1_bus1_pll_p)    = { "fin_pll", "dout_sclk_bus1_pll_b" };
>> +PNAME(mout_top1_cc_pll_p)      = { "fin_pll", "dout_sclk_cc_pll_b" };
>> +PNAME(mout_top1_mfc_pll_p)     = { "fin_pll", "dout_sclk_mfc_pll_b" };
>> +
>> +PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
>> +       "ffac_top1_bus0_pll_div2"};
>> +PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
>> +       "ffac_top1_bus1_pll_div2"};
>> +PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
>> +       "ffac_top1_cc_pll_div2"};
>> +PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
>> +       "ffac_top1_mfc_pll_div2"};
>> +
>> +PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
>> +       "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
>> +       "mout_top1_half_mfc_pll"};
>> +
>> +static unsigned long top1_clk_regs[] __initdata = {
>> +       MUX_SEL_TOP10,
>> +       MUX_SEL_TOP11,
>> +       MUX_SEL_TOP13,
>> +       MUX_SEL_TOP1_FSYS0,
>> +       MUX_SEL_TOP1_FSYS1,
>> +       DIV_TOP13,
>> +       DIV_TOP1_FSYS0,
>> +       DIV_TOP1_FSYS1,
>> +       ENABLE_ACLK_TOP13,
>> +       ENABLE_SCLK_TOP1_FSYS0,
>> +       ENABLE_SCLK_TOP1_FSYS1,
>> +};
>> +
>> +static struct samsung_mux_clock top1_mux_clks[] __initdata = {
>> +       MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
>> +       MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
>> +       MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
>> +               MUX_SEL_TOP10, 12, 1),
>> +       MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
>> +               MUX_SEL_TOP10, 16, 1),
>> +
>> +       MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
>> +               MUX_SEL_TOP11, 4, 1),
>> +       MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
>> +               MUX_SEL_TOP11, 8, 1),
>> +       MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
>> +               MUX_SEL_TOP11, 12, 1),
>> +       MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
>> +               MUX_SEL_TOP11, 16, 1),
>> +
>> +       MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
>> +       MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
>> +
>> +       MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
>> +
>> +       MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
>> +       MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
>> +};
>> +
>> +static struct samsung_div_clock top1_div_clks[] __initdata = {
>> +       DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
>> +               DIV_TOP13, 24, 4),
>> +       DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
>> +               DIV_TOP13, 28, 4),
>> +
>> +       DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
>> +               DIV_TOP1_FSYS0, 24, 4),
>> +
>> +       DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
>> +               DIV_TOP1_FSYS1, 24, 4),
>> +       DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
>> +               DIV_TOP1_FSYS1, 28, 4),
>> +};
>> +
>> +static struct samsung_gate_clock top1_gate_clks[] __initdata = {
>> +       GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
>> +               ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
>> +
>> +       GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
>> +               ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
>> +       GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
>> +               ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
>> +};
>> +
>> +static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
>> +       FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
>> +       FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
>> +       FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
>> +       FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
>> +};
>> +
>> +static struct samsung_cmu_info top1_cmu_info __initdata = {
>> +       .mux_clks               = top1_mux_clks,
>> +       .nr_mux_clks            = ARRAY_SIZE(top1_mux_clks),
>> +       .div_clks               = top1_div_clks,
>> +       .nr_div_clks            = ARRAY_SIZE(top1_div_clks),
>> +       .gate_clks              = top1_gate_clks,
>> +       .nr_gate_clks           = ARRAY_SIZE(top1_gate_clks),
>> +       .fixed_factor_clks      = top1_fixed_factor_clks,
>> +       .nr_fixed_factor_clks   = ARRAY_SIZE(top1_fixed_factor_clks),
>> +       .nr_clk_ids             = TOP1_NR_CLK,
>> +       .clk_regs               = top1_clk_regs,
>> +       .nr_clk_regs            = ARRAY_SIZE(top1_clk_regs),
>> +};
>> +
>> +static void __init exynos7_clk_top1_init(struct device_node *np)
>> +{
>> +       samsung_cmu_register_one(np, &top1_cmu_info);
>> +}
>> +
>> +CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
>> +       exynos7_clk_top1_init);
>> +
>>  /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
>>  #define MUX_SEL_PERIC0                 0x0200
>>  #define ENABLE_PCLK_PERIC0             0x0900
>> @@ -447,3 +573,101 @@ static void __init exynos7_clk_peris_init(struct device_node *np)
>>
>>  CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
>>         exynos7_clk_peris_init);
>> +
>> +/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
>> +#define MUX_SEL_FSYS00                 0x0200
>> +#define MUX_SEL_FSYS01                 0x0204
>> +#define ENABLE_ACLK_FSYS01             0x0804
>> +
>> +/*
>> + * List of parent clocks for Muxes in CMU_FSYS0
>> + */
>> +PNAME(mout_aclk_fsys0_200_p)   = { "fin_pll", "dout_aclk_fsys0_200" };
>> +PNAME(mout_sclk_mmc2_p)                = { "fin_pll", "sclk_mmc2" };
>> +
>> +static unsigned long fsys0_clk_regs[] __initdata = {
>> +       MUX_SEL_FSYS00,
>> +       MUX_SEL_FSYS01,
>> +       ENABLE_ACLK_FSYS01,
>> +};
>> +
>> +static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
>> +       MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
>> +               MUX_SEL_FSYS00, 24, 1),
>> +
>> +       MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
>> +};
>> +
>> +static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
>> +       GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
>> +               ENABLE_ACLK_FSYS01, 31, 0, 0),
>> +};
>> +
>> +static struct samsung_cmu_info fsys0_cmu_info __initdata = {
>> +       .mux_clks               = fsys0_mux_clks,
>> +       .nr_mux_clks            = ARRAY_SIZE(fsys0_mux_clks),
>> +       .gate_clks              = fsys0_gate_clks,
>> +       .nr_gate_clks           = ARRAY_SIZE(fsys0_gate_clks),
>> +       .nr_clk_ids             = TOP1_NR_CLK,
>> +       .clk_regs               = fsys0_clk_regs,
>> +       .nr_clk_regs            = ARRAY_SIZE(fsys0_clk_regs),
>> +};
>> +
>> +static void __init exynos7_clk_fsys0_init(struct device_node *np)
>> +{
>> +       samsung_cmu_register_one(np, &fsys0_cmu_info);
>> +}
>> +
>> +CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
>> +       exynos7_clk_fsys0_init);
>> +
>> +/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
>> +#define MUX_SEL_FSYS10                 0x0200
>> +#define MUX_SEL_FSYS11                 0x0204
>> +#define ENABLE_ACLK_FSYS1              0x0800
>> +
>> +/*
>> + * List of parent clocks for Muxes in CMU_FSYS1
>> + */
>> +PNAME(mout_aclk_fsys1_200_p)   = { "fin_pll",  "dout_aclk_fsys1_200" };
>> +PNAME(mout_sclk_mmc0_p)                = { "fin_pll", "sclk_mmc0" };
>> +PNAME(mout_sclk_mmc1_p)                = { "fin_pll", "sclk_mmc1" };
>> +
>> +static unsigned long fsys1_clk_regs[] __initdata = {
>> +       MUX_SEL_FSYS10,
>> +       MUX_SEL_FSYS11,
>> +       ENABLE_ACLK_FSYS1,
>> +};
>> +
>> +static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
>> +       MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
>> +               MUX_SEL_FSYS10, 28, 1),
>> +
>> +       MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
>> +       MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
>> +};
>> +
>> +static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
>> +       GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
>> +               ENABLE_ACLK_FSYS1, 29, 0, 0),
>> +       GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
>> +               ENABLE_ACLK_FSYS1, 30, 0, 0),
>> +};
>> +
>> +static struct samsung_cmu_info fsys1_cmu_info __initdata = {
>> +       .mux_clks               = fsys1_mux_clks,
>> +       .nr_mux_clks            = ARRAY_SIZE(fsys1_mux_clks),
>> +       .gate_clks              = fsys1_gate_clks,
>> +       .nr_gate_clks           = ARRAY_SIZE(fsys1_gate_clks),
>> +       .nr_clk_ids             = TOP1_NR_CLK,
>> +       .clk_regs               = fsys1_clk_regs,
>> +       .nr_clk_regs            = ARRAY_SIZE(fsys1_clk_regs),
>> +};
>> +
>> +static void __init exynos7_clk_fsys1_init(struct device_node *np)
>> +{
>> +       samsung_cmu_register_one(np, &fsys1_cmu_info);
>> +}
>> +
>> +CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
>> +       exynos7_clk_fsys1_init);
>> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
>> index 6d07b6f..ff63c4e 100644
>> --- a/include/dt-bindings/clock/exynos7-clk.h
>> +++ b/include/dt-bindings/clock/exynos7-clk.h
>> @@ -27,6 +27,17 @@
>>  #define CLK_SCLK_UART3                 6
>>  #define TOP0_NR_CLK                    7
>>
>> +/* TOP1 */
>> +#define DOUT_ACLK_FSYS1_200            1
>> +#define DOUT_ACLK_FSYS0_200            2
>> +#define DOUT_SCLK_MMC2                 3
>> +#define DOUT_SCLK_MMC1                 4
>> +#define DOUT_SCLK_MMC0                 5
>> +#define CLK_SCLK_MMC2                  6
>> +#define CLK_SCLK_MMC1                  7
>> +#define CLK_SCLK_MMC0                  8
>> +#define TOP1_NR_CLK                    9
>> +
>>  /* PERIC0 */
>>  #define PCLK_UART0                     1
>>  #define SCLK_UART0                     2
>> @@ -58,4 +69,13 @@
>>  #define SCLK_CHIPID                    2
>>  #define PERIS_NR_CLK                   3
>>
>> +/* FSYS0 */
>> +#define ACLK_MMC2                      1
>> +#define FSYS0_NR_CLK                   2
>> +
>> +/* FSYS1 */
>> +#define ACLK_MMC1                      1
>> +#define ACLK_MMC0                      2
>> +#define FSYS1_NR_CLK                   3
>> +
>>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Best Regards
> Vivek Gautam
> Samsung R&D Institute, Bangalore
> India
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block
@ 2014-10-20 13:58       ` Abhilash Kesavan
  0 siblings, 0 replies; 22+ messages in thread
From: Abhilash Kesavan @ 2014-10-20 13:58 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Vivek,

On Mon, Oct 20, 2014 at 3:19 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> Hi Abhilash,
>
>
> On Fri, Oct 17, 2014 at 9:41 PM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
>> From: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>>
>> Exynos7 supports 3 MMC channels, add the MMC gate clocks to
>> support them.
>>
>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  .../devicetree/bindings/clock/exynos7-clock.txt    |    3 +
>>  drivers/clk/samsung/clk-exynos7.c                  |  224 ++++++++++++++++++++
>>  include/dt-bindings/clock/exynos7-clk.h            |   20 ++
>>  3 files changed, 247 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
>> index 789f761..4c69b66 100644
>> --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
>> +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
>> @@ -27,9 +27,12 @@ Required Properties for Clock Controller:
>>
>>         - "samsung,exynos7-clock-topc"
>>         - "samsung,exynos7-clock-top0"
>> +       - "samsung,exynos7-clock-top1"
>>         - "samsung,exynos7-clock-peric0"
>>         - "samsung,exynos7-clock-peric1"
>>         - "samsung,exynos7-clock-peris"
>> +       - "samsung,exynos7-clock-fsys0"
>> +       - "samsung,exynos7-clock-fsys1"
>
> same here, the input clocks for top1, fsys0 and fsys1 block need to be
> mentioned in this doc.

Thanks for the review. I missed adding these, will fix in the next version.

Regards,
Abhilash
>
>>
>>   - reg: physical base address of the controller and the length of
>>         memory mapped region.
>> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
>> index c700f65..f5e43fa 100644
>> --- a/drivers/clk/samsung/clk-exynos7.c
>> +++ b/drivers/clk/samsung/clk-exynos7.c
>> @@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct device_node *np)
>>  CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
>>         exynos7_clk_top0_init);
>>
>> +/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
>> +#define MUX_SEL_TOP10                  0x0200
>> +#define MUX_SEL_TOP11                  0x0204
>> +#define MUX_SEL_TOP13                  0x020C
>> +#define MUX_SEL_TOP1_FSYS0             0x0224
>> +#define MUX_SEL_TOP1_FSYS1             0x0228
>> +#define DIV_TOP13                      0x060C
>> +#define DIV_TOP1_FSYS0                 0x0624
>> +#define DIV_TOP1_FSYS1                 0x0628
>> +#define ENABLE_ACLK_TOP13              0x080C
>> +#define ENABLE_SCLK_TOP1_FSYS0         0x0A24
>> +#define ENABLE_SCLK_TOP1_FSYS1         0x0A28
>> +
>> +/* List of parent clocks for Muxes in CMU_TOP1 */
>> +PNAME(mout_top1_bus0_pll_p)    = { "fin_pll", "dout_sclk_bus0_pll" };
>> +PNAME(mout_top1_bus1_pll_p)    = { "fin_pll", "dout_sclk_bus1_pll_b" };
>> +PNAME(mout_top1_cc_pll_p)      = { "fin_pll", "dout_sclk_cc_pll_b" };
>> +PNAME(mout_top1_mfc_pll_p)     = { "fin_pll", "dout_sclk_mfc_pll_b" };
>> +
>> +PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
>> +       "ffac_top1_bus0_pll_div2"};
>> +PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
>> +       "ffac_top1_bus1_pll_div2"};
>> +PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
>> +       "ffac_top1_cc_pll_div2"};
>> +PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
>> +       "ffac_top1_mfc_pll_div2"};
>> +
>> +PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
>> +       "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
>> +       "mout_top1_half_mfc_pll"};
>> +
>> +static unsigned long top1_clk_regs[] __initdata = {
>> +       MUX_SEL_TOP10,
>> +       MUX_SEL_TOP11,
>> +       MUX_SEL_TOP13,
>> +       MUX_SEL_TOP1_FSYS0,
>> +       MUX_SEL_TOP1_FSYS1,
>> +       DIV_TOP13,
>> +       DIV_TOP1_FSYS0,
>> +       DIV_TOP1_FSYS1,
>> +       ENABLE_ACLK_TOP13,
>> +       ENABLE_SCLK_TOP1_FSYS0,
>> +       ENABLE_SCLK_TOP1_FSYS1,
>> +};
>> +
>> +static struct samsung_mux_clock top1_mux_clks[] __initdata = {
>> +       MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
>> +       MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
>> +       MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
>> +               MUX_SEL_TOP10, 12, 1),
>> +       MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
>> +               MUX_SEL_TOP10, 16, 1),
>> +
>> +       MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
>> +               MUX_SEL_TOP11, 4, 1),
>> +       MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
>> +               MUX_SEL_TOP11, 8, 1),
>> +       MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
>> +               MUX_SEL_TOP11, 12, 1),
>> +       MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
>> +               MUX_SEL_TOP11, 16, 1),
>> +
>> +       MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
>> +       MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
>> +
>> +       MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
>> +
>> +       MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
>> +       MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
>> +};
>> +
>> +static struct samsung_div_clock top1_div_clks[] __initdata = {
>> +       DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
>> +               DIV_TOP13, 24, 4),
>> +       DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
>> +               DIV_TOP13, 28, 4),
>> +
>> +       DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
>> +               DIV_TOP1_FSYS0, 24, 4),
>> +
>> +       DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
>> +               DIV_TOP1_FSYS1, 24, 4),
>> +       DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
>> +               DIV_TOP1_FSYS1, 28, 4),
>> +};
>> +
>> +static struct samsung_gate_clock top1_gate_clks[] __initdata = {
>> +       GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
>> +               ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
>> +
>> +       GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
>> +               ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
>> +       GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
>> +               ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
>> +};
>> +
>> +static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
>> +       FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
>> +       FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
>> +       FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
>> +       FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
>> +};
>> +
>> +static struct samsung_cmu_info top1_cmu_info __initdata = {
>> +       .mux_clks               = top1_mux_clks,
>> +       .nr_mux_clks            = ARRAY_SIZE(top1_mux_clks),
>> +       .div_clks               = top1_div_clks,
>> +       .nr_div_clks            = ARRAY_SIZE(top1_div_clks),
>> +       .gate_clks              = top1_gate_clks,
>> +       .nr_gate_clks           = ARRAY_SIZE(top1_gate_clks),
>> +       .fixed_factor_clks      = top1_fixed_factor_clks,
>> +       .nr_fixed_factor_clks   = ARRAY_SIZE(top1_fixed_factor_clks),
>> +       .nr_clk_ids             = TOP1_NR_CLK,
>> +       .clk_regs               = top1_clk_regs,
>> +       .nr_clk_regs            = ARRAY_SIZE(top1_clk_regs),
>> +};
>> +
>> +static void __init exynos7_clk_top1_init(struct device_node *np)
>> +{
>> +       samsung_cmu_register_one(np, &top1_cmu_info);
>> +}
>> +
>> +CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
>> +       exynos7_clk_top1_init);
>> +
>>  /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
>>  #define MUX_SEL_PERIC0                 0x0200
>>  #define ENABLE_PCLK_PERIC0             0x0900
>> @@ -447,3 +573,101 @@ static void __init exynos7_clk_peris_init(struct device_node *np)
>>
>>  CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
>>         exynos7_clk_peris_init);
>> +
>> +/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
>> +#define MUX_SEL_FSYS00                 0x0200
>> +#define MUX_SEL_FSYS01                 0x0204
>> +#define ENABLE_ACLK_FSYS01             0x0804
>> +
>> +/*
>> + * List of parent clocks for Muxes in CMU_FSYS0
>> + */
>> +PNAME(mout_aclk_fsys0_200_p)   = { "fin_pll", "dout_aclk_fsys0_200" };
>> +PNAME(mout_sclk_mmc2_p)                = { "fin_pll", "sclk_mmc2" };
>> +
>> +static unsigned long fsys0_clk_regs[] __initdata = {
>> +       MUX_SEL_FSYS00,
>> +       MUX_SEL_FSYS01,
>> +       ENABLE_ACLK_FSYS01,
>> +};
>> +
>> +static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
>> +       MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
>> +               MUX_SEL_FSYS00, 24, 1),
>> +
>> +       MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
>> +};
>> +
>> +static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
>> +       GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
>> +               ENABLE_ACLK_FSYS01, 31, 0, 0),
>> +};
>> +
>> +static struct samsung_cmu_info fsys0_cmu_info __initdata = {
>> +       .mux_clks               = fsys0_mux_clks,
>> +       .nr_mux_clks            = ARRAY_SIZE(fsys0_mux_clks),
>> +       .gate_clks              = fsys0_gate_clks,
>> +       .nr_gate_clks           = ARRAY_SIZE(fsys0_gate_clks),
>> +       .nr_clk_ids             = TOP1_NR_CLK,
>> +       .clk_regs               = fsys0_clk_regs,
>> +       .nr_clk_regs            = ARRAY_SIZE(fsys0_clk_regs),
>> +};
>> +
>> +static void __init exynos7_clk_fsys0_init(struct device_node *np)
>> +{
>> +       samsung_cmu_register_one(np, &fsys0_cmu_info);
>> +}
>> +
>> +CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
>> +       exynos7_clk_fsys0_init);
>> +
>> +/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
>> +#define MUX_SEL_FSYS10                 0x0200
>> +#define MUX_SEL_FSYS11                 0x0204
>> +#define ENABLE_ACLK_FSYS1              0x0800
>> +
>> +/*
>> + * List of parent clocks for Muxes in CMU_FSYS1
>> + */
>> +PNAME(mout_aclk_fsys1_200_p)   = { "fin_pll",  "dout_aclk_fsys1_200" };
>> +PNAME(mout_sclk_mmc0_p)                = { "fin_pll", "sclk_mmc0" };
>> +PNAME(mout_sclk_mmc1_p)                = { "fin_pll", "sclk_mmc1" };
>> +
>> +static unsigned long fsys1_clk_regs[] __initdata = {
>> +       MUX_SEL_FSYS10,
>> +       MUX_SEL_FSYS11,
>> +       ENABLE_ACLK_FSYS1,
>> +};
>> +
>> +static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
>> +       MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
>> +               MUX_SEL_FSYS10, 28, 1),
>> +
>> +       MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
>> +       MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
>> +};
>> +
>> +static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
>> +       GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
>> +               ENABLE_ACLK_FSYS1, 29, 0, 0),
>> +       GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
>> +               ENABLE_ACLK_FSYS1, 30, 0, 0),
>> +};
>> +
>> +static struct samsung_cmu_info fsys1_cmu_info __initdata = {
>> +       .mux_clks               = fsys1_mux_clks,
>> +       .nr_mux_clks            = ARRAY_SIZE(fsys1_mux_clks),
>> +       .gate_clks              = fsys1_gate_clks,
>> +       .nr_gate_clks           = ARRAY_SIZE(fsys1_gate_clks),
>> +       .nr_clk_ids             = TOP1_NR_CLK,
>> +       .clk_regs               = fsys1_clk_regs,
>> +       .nr_clk_regs            = ARRAY_SIZE(fsys1_clk_regs),
>> +};
>> +
>> +static void __init exynos7_clk_fsys1_init(struct device_node *np)
>> +{
>> +       samsung_cmu_register_one(np, &fsys1_cmu_info);
>> +}
>> +
>> +CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
>> +       exynos7_clk_fsys1_init);
>> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
>> index 6d07b6f..ff63c4e 100644
>> --- a/include/dt-bindings/clock/exynos7-clk.h
>> +++ b/include/dt-bindings/clock/exynos7-clk.h
>> @@ -27,6 +27,17 @@
>>  #define CLK_SCLK_UART3                 6
>>  #define TOP0_NR_CLK                    7
>>
>> +/* TOP1 */
>> +#define DOUT_ACLK_FSYS1_200            1
>> +#define DOUT_ACLK_FSYS0_200            2
>> +#define DOUT_SCLK_MMC2                 3
>> +#define DOUT_SCLK_MMC1                 4
>> +#define DOUT_SCLK_MMC0                 5
>> +#define CLK_SCLK_MMC2                  6
>> +#define CLK_SCLK_MMC1                  7
>> +#define CLK_SCLK_MMC0                  8
>> +#define TOP1_NR_CLK                    9
>> +
>>  /* PERIC0 */
>>  #define PCLK_UART0                     1
>>  #define SCLK_UART0                     2
>> @@ -58,4 +69,13 @@
>>  #define SCLK_CHIPID                    2
>>  #define PERIS_NR_CLK                   3
>>
>> +/* FSYS0 */
>> +#define ACLK_MMC2                      1
>> +#define FSYS0_NR_CLK                   2
>> +
>> +/* FSYS1 */
>> +#define ACLK_MMC1                      1
>> +#define ACLK_MMC0                      2
>> +#define FSYS1_NR_CLK                   3
>> +
>>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Best Regards
> Vivek Gautam
> Samsung R&D Institute, Bangalore
> India
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 22+ messages in thread

end of thread, other threads:[~2014-10-20 13:58 UTC | newest]

Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-10-17 16:11 [PATCH 0/7] Add clock and DT support for a few IPs on Exynos7 Abhilash Kesavan
2014-10-17 16:11 ` Abhilash Kesavan
2014-10-17 16:11 ` [PATCH 1/7] clk: samsung: exynos7: add clocks for I2C block Abhilash Kesavan
2014-10-17 16:11   ` Abhilash Kesavan
2014-10-17 16:11 ` [PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block Abhilash Kesavan
2014-10-17 16:11   ` Abhilash Kesavan
2014-10-20  9:49   ` Vivek Gautam
2014-10-20  9:49     ` Vivek Gautam
2014-10-20 13:58     ` Abhilash Kesavan
2014-10-20 13:58       ` Abhilash Kesavan
     [not found] ` <1413562315-12283-1-git-send-email-a.kesavan-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2014-10-17 16:11   ` [PATCH 3/7] clk: samsung: exynos7: add clocks for RTC block Abhilash Kesavan
2014-10-17 16:11     ` Abhilash Kesavan
2014-10-20  9:48     ` Vivek Gautam
2014-10-20  9:48       ` Vivek Gautam
2014-10-17 16:11 ` [PATCH 4/7] clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks Abhilash Kesavan
2014-10-17 16:11   ` Abhilash Kesavan
2014-10-17 16:11 ` [PATCH 5/7] arm64: dts: Add PMU DT node for exynos7 SoC Abhilash Kesavan
2014-10-17 16:11   ` Abhilash Kesavan
2014-10-17 16:11 ` [PATCH 6/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7 Abhilash Kesavan
2014-10-17 16:11   ` Abhilash Kesavan
2014-10-17 16:11 ` [PATCH 7/7] arm64: exynos: Enable rtc and watchdog support for Exynos7 Abhilash Kesavan
2014-10-17 16:11   ` Abhilash Kesavan

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