* [U-Boot] [PATCH v3 0/5] ls102xa: HYP/non-sec: for ls102xa.
@ 2014-10-20 9:00 Xiubo Li
2014-10-20 9:00 ` [U-Boot] [PATCH v3 1/5] ARM: HYP/non-sec: add the pen address BE mode support Xiubo Li
` (5 more replies)
0 siblings, 6 replies; 22+ messages in thread
From: Xiubo Li @ 2014-10-20 9:00 UTC (permalink / raw)
To: u-boot
Change for V3:
- Fix the language in commit message.
Change for V2:
- All the registers are defined as a struct, here use it.
- Use CONFIG_PEN_ADDR_BIG_ENDIAN instead of CONFIG_SOC_BIG_ENDIAN.
Xiubo Li (5):
ARM: HYP/non-sec: add the pen address BE mode support.
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
ls102xa: HYP/non-sec: support for ls102xa boards
ARM: ls102xa: allow all the peripheral access permissions as R/W.
ARM: ls102xa: Setting device's stream id for SMMUs.
arch/arm/cpu/armv7/ls102xa/cpu.c | 15 +++
arch/arm/cpu/armv7/nonsec_virt.S | 7 +-
arch/arm/include/asm/arch-ls102xa/config.h | 3 +
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +
.../include/asm/arch-ls102xa/ls102xa_stream_id.h | 17 +++
arch/arm/include/asm/arch-ls102xa/ns_access.h | 118 +++++++++++++++++++++
board/freescale/common/Makefile | 4 +
board/freescale/common/ls102xa_stream_id.c | 18 ++++
board/freescale/common/ns_access.c | 30 ++++++
board/freescale/ls1021aqds/ls1021aqds.c | 113 ++++++++++++++++++++
board/freescale/ls1021atwr/ls1021atwr.c | 112 +++++++++++++++++++
include/configs/ls1021aqds.h | 10 ++
include/configs/ls1021atwr.h | 10 ++
include/configs/sun7i.h | 1 +
14 files changed, 459 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/ns_access.h
create mode 100644 board/freescale/common/ls102xa_stream_id.c
create mode 100644 board/freescale/common/ns_access.c
--
2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 1/5] ARM: HYP/non-sec: add the pen address BE mode support.
2014-10-20 9:00 [U-Boot] [PATCH v3 0/5] ls102xa: HYP/non-sec: for ls102xa Xiubo Li
@ 2014-10-20 9:00 ` Xiubo Li
2014-11-13 16:44 ` York Sun
2014-10-20 9:00 ` [U-Boot] [PATCH v3 2/5] ARM: HYP/non-sec: Fix the ARCH Timer frequency setting Xiubo Li
` (4 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Xiubo Li @ 2014-10-20 9:00 UTC (permalink / raw)
To: u-boot
For some SoCs, the pen address register maybe in BE mode and the
CPUs are in LE mode.
This patch adds BE mode support for smp pen address.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
arch/arm/cpu/armv7/nonsec_virt.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 745670e..1ab5d54 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -191,6 +191,9 @@ ENTRY(smp_waitloop)
wfi
ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
ldr r1, [r1]
+#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
+ rev r1, r1
+#endif
cmp r0, r1 @ make sure we dont execute this code
beq smp_waitloop @ again (due to a spurious wakeup)
mov r0, r1
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 2/5] ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
2014-10-20 9:00 [U-Boot] [PATCH v3 0/5] ls102xa: HYP/non-sec: for ls102xa Xiubo Li
2014-10-20 9:00 ` [U-Boot] [PATCH v3 1/5] ARM: HYP/non-sec: add the pen address BE mode support Xiubo Li
@ 2014-10-20 9:00 ` Xiubo Li
2014-11-13 16:44 ` York Sun
2014-10-20 9:00 ` [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards Xiubo Li
` (3 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Xiubo Li @ 2014-10-20 9:00 UTC (permalink / raw)
To: u-boot
For some SoCs, the system clock frequency may not equal to the
ARCH Timer's frequency.
This patch uses the CONFIG_TIMER_CLK_FREQ instead of
CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
macor could be set separately and without interfering each other.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
arch/arm/cpu/armv7/nonsec_virt.S | 4 ++--
include/configs/sun7i.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 1ab5d54..30d81db 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -169,11 +169,11 @@ ENTRY(_nonsec_init)
* we do this here instead.
* But first check if we have the generic timer.
*/
-#ifdef CONFIG_SYS_CLK_FREQ
+#ifdef CONFIG_TIMER_CLK_FREQ
mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
- ldreq r1, =CONFIG_SYS_CLK_FREQ
+ ldreq r1, =CONFIG_TIMER_CLK_FREQ
mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
#endif
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index a902b84..6e201f2f 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -35,6 +35,7 @@
#define CONFIG_ARMV7_PSCI_NR_CPUS 2
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_SYS_CLK_FREQ 24000000
+#define CONFIG_SYS_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ
/*
* Include common sunxi configuration where most the settings are
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
2014-10-20 9:00 [U-Boot] [PATCH v3 0/5] ls102xa: HYP/non-sec: for ls102xa Xiubo Li
2014-10-20 9:00 ` [U-Boot] [PATCH v3 1/5] ARM: HYP/non-sec: add the pen address BE mode support Xiubo Li
2014-10-20 9:00 ` [U-Boot] [PATCH v3 2/5] ARM: HYP/non-sec: Fix the ARCH Timer frequency setting Xiubo Li
@ 2014-10-20 9:00 ` Xiubo Li
2014-11-13 16:44 ` York Sun
2014-11-14 7:49 ` Albert ARIBAUD
2014-10-20 9:00 ` [U-Boot] [PATCH v3 4/5] ARM: ls102xa: allow all the peripheral access permissions as R/W Xiubo Li
` (2 subsequent siblings)
5 siblings, 2 replies; 22+ messages in thread
From: Xiubo Li @ 2014-10-20 9:00 UTC (permalink / raw)
To: u-boot
Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function
to set the start address for secondary cores in the LS1021A specific
manner.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 15 +++++++++++++++
arch/arm/include/asm/arch-ls102xa/config.h | 2 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++
include/configs/ls1021aqds.h | 7 +++++++
include/configs/ls1021atwr.h | 7 +++++++
5 files changed, 34 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index b7dde45..69d1801 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -101,3 +101,18 @@ int cpu_eth_init(bd_t *bis)
return 0;
}
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+/* Setting the address at which secondary cores start from.*/
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ /*
+ * After setting the secondary cores start address,
+ * just release them to boot.
+ */
+ out_be32(&gur->scratchrw[0], addr);
+ out_be32(&gur->brrl, 0x2);
+}
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index ed78c33..4856388 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -11,6 +11,8 @@
#define OCRAM_BASE_ADDR 0x10000000
#define OCRAM_SIZE 0x00020000
+#define OCRAM_BASE_S_ADDR 0x10010000
+#define OCRAM_S_SIZE 0x00010000
#define CONFIG_SYS_IMMR 0x01000000
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..0bac353 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -17,6 +17,9 @@
#define SOC_VER_LS1021 0x11
#define SOC_VER_LS1022 0x12
+#define CCSR_BRR_OFFSET 0xe4
+#define CCSR_SCRATCHRW1_OFFSET 0x200
+
#define RCWSR0_SYS_PLL_RAT_SHIFT 25
#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
#define RCWSR0_MEM_PLL_RAT_SHIFT 16
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 657e3b6..6976cfa 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -324,6 +324,13 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CMDLINE_EDITING
#define CONFIG_CMD_IMLS
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_SMP_PEN_ADDR 0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ 12500000
+#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
+
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 45b2272..655b39a 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -227,6 +227,13 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_CMD_IMLS
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_SMP_PEN_ADDR 0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ 12500000
+#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
+
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 4/5] ARM: ls102xa: allow all the peripheral access permissions as R/W.
2014-10-20 9:00 [U-Boot] [PATCH v3 0/5] ls102xa: HYP/non-sec: for ls102xa Xiubo Li
` (2 preceding siblings ...)
2014-10-20 9:00 ` [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards Xiubo Li
@ 2014-10-20 9:00 ` Xiubo Li
2014-11-13 16:45 ` York Sun
2014-10-20 9:00 ` [U-Boot] [PATCH v3 5/5] ARM: ls102xa: Setting device's stream id for SMMUs Xiubo Li
2014-11-13 6:15 ` [U-Boot] [PATCH v3 0/5] ls102xa: HYP/non-sec: for ls102xa Albert ARIBAUD
5 siblings, 1 reply; 22+ messages in thread
From: Xiubo Li @ 2014-10-20 9:00 UTC (permalink / raw)
To: u-boot
The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.
For now we configure all the peripheral access permissions as R/W.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
arch/arm/include/asm/arch-ls102xa/ns_access.h | 118 ++++++++++++++++++++++++++
board/freescale/common/Makefile | 2 +
board/freescale/common/ns_access.c | 30 +++++++
board/freescale/ls1021aqds/ls1021aqds.c | 92 ++++++++++++++++++++
board/freescale/ls1021atwr/ls1021atwr.c | 91 ++++++++++++++++++++
include/configs/ls1021aqds.h | 1 +
include/configs/ls1021atwr.h | 1 +
8 files changed, 336 insertions(+)
create mode 100644 arch/arm/include/asm/arch-ls102xa/ns_access.h
create mode 100644 board/freescale/common/ns_access.c
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 4856388..0754296 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -18,6 +18,7 @@
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
+#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h
new file mode 100644
index 0000000..b53f699
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_NS_ACCESS_H_
+#define __FSL_NS_ACCESS_H_
+
+enum csu_cslx_access {
+ CSU_NS_SUP_R = 0x08,
+ CSU_NS_SUP_W = 0x80,
+ CSU_NS_SUP_RW = 0x88,
+ CSU_NS_USER_R = 0x04,
+ CSU_NS_USER_W = 0x40,
+ CSU_NS_USER_RW = 0x44,
+ CSU_S_SUP_R = 0x02,
+ CSU_S_SUP_W = 0x20,
+ CSU_S_SUP_RW = 0x22,
+ CSU_S_USER_R = 0x01,
+ CSU_S_USER_W = 0x10,
+ CSU_S_USER_RW = 0x11,
+ CSU_ALL_RW = 0xff,
+};
+
+enum csu_cslx_ind {
+ CSU_CSLX_PCIE2_IO = 0,
+ CSU_CSLX_PCIE1_IO,
+ CSU_CSLX_MG2TPR_IP,
+ CSU_CSLX_IFC_MEM,
+ CSU_CSLX_OCRAM,
+ CSU_CSLX_GIC,
+ CSU_CSLX_PCIE1,
+ CSU_CSLX_OCRAM2,
+ CSU_CSLX_QSPI_MEM,
+ CSU_CSLX_PCIE2,
+ CSU_CSLX_SATA,
+ CSU_CSLX_USB3,
+ CSU_CSLX_SERDES = 32,
+ CSU_CSLX_QDMA,
+ CSU_CSLX_LPUART2,
+ CSU_CSLX_LPUART1,
+ CSU_CSLX_LPUART4,
+ CSU_CSLX_LPUART3,
+ CSU_CSLX_LPUART6,
+ CSU_CSLX_LPUART5,
+ CSU_CSLX_DSPI2 = 40,
+ CSU_CSLX_DSPI1,
+ CSU_CSLX_QSPI,
+ CSU_CSLX_ESDHC,
+ CSU_CSLX_2D_ACE,
+ CSU_CSLX_IFC,
+ CSU_CSLX_I2C1,
+ CSU_CSLX_USB2,
+ CSU_CSLX_I2C3,
+ CSU_CSLX_I2C2,
+ CSU_CSLX_DUART2 = 50,
+ CSU_CSLX_DUART1,
+ CSU_CSLX_WDT2,
+ CSU_CSLX_WDT1,
+ CSU_CSLX_EDMA,
+ CSU_CSLX_SYS_CNT,
+ CSU_CSLX_DMA_MUX2,
+ CSU_CSLX_DMA_MUX1,
+ CSU_CSLX_DDR,
+ CSU_CSLX_QUICC,
+ CSU_CSLX_DCFG_CCU_RCPM = 60,
+ CSU_CSLX_SECURE_BOOTROM,
+ CSU_CSLX_SFP,
+ CSU_CSLX_TMU,
+ CSU_CSLX_SECURE_MONITOR,
+ CSU_CSLX_RESERVED0,
+ CSU_CSLX_ETSEC1,
+ CSU_CSLX_SEC5_5,
+ CSU_CSLX_ETSEC3,
+ CSU_CSLX_ETSEC2,
+ CSU_CSLX_GPIO2 = 70,
+ CSU_CSLX_GPIO1,
+ CSU_CSLX_GPIO4,
+ CSU_CSLX_GPIO3,
+ CSU_CSLX_PLATFORM_CONT,
+ CSU_CSLX_CSU,
+ CSU_CSLX_ASRC,
+ CSU_CSLX_SPDIF,
+ CSU_CSLX_FLEXCAN2,
+ CSU_CSLX_FLEXCAN1,
+ CSU_CSLX_FLEXCAN4 = 80,
+ CSU_CSLX_FLEXCAN3,
+ CSU_CSLX_SAI2,
+ CSU_CSLX_SAI1,
+ CSU_CSLX_SAI4,
+ CSU_CSLX_SAI3,
+ CSU_CSLX_FTM2,
+ CSU_CSLX_FTM1,
+ CSU_CSLX_FTM4,
+ CSU_CSLX_FTM3,
+ CSU_CSLX_FTM6 = 90,
+ CSU_CSLX_FTM5,
+ CSU_CSLX_FTM8,
+ CSU_CSLX_FTM7,
+ CSU_CSLX_COP_DCSR,
+ CSU_CSLX_EPU,
+ CSU_CSLX_GDI,
+ CSU_CSLX_DDI,
+ CSU_CSLX_RESERVED1,
+ CSU_CSLX_USB3_PHY = 117,
+ CSU_CSLX_RESERVED2,
+ CSU_CSLX_MAX,
+};
+
+struct csu_ns_dev {
+ unsigned long ind;
+ uint32_t val;
+};
+
+void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
+
+#endif
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 32b5a3b..e5aad2d 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -60,4 +60,6 @@ obj-$(CONFIG_P3041DS) += p_corenet/
obj-$(CONFIG_P4080DS) += p_corenet/
obj-$(CONFIG_P5020DS) += p_corenet/
obj-$(CONFIG_P5040DS) += p_corenet/
+
+obj-$(CONFIG_LS102XA_NS_ACESSC) += ns_access.o
endif
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
new file mode 100644
index 0000000..d7de982
--- /dev/null
+++ b/board/freescale/common/ns_access.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ns_access.h>
+
+void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+{
+ u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
+ u32 *reg;
+ uint32_t val;
+ int i;
+
+ for (i = 0; i < num; i++) {
+ reg = base + ns_dev[i].ind / 2;
+ val = in_be32(reg);
+ if (ns_dev[i].ind % 2 == 0) {
+ val &= 0x0000ffff;
+ val |= ns_dev[i].val << 16;
+ } else {
+ val &= 0xffff0000;
+ val |= ns_dev[i].val;
+ }
+ out_be32(reg, val);
+ }
+}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 12e83f7..07df7d2 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -8,6 +8,7 @@
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ns_access.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <mmc.h>
@@ -213,6 +214,92 @@ int config_serdes_mux(void)
return 0;
}
+#ifdef CONFIG_SYS_FSL_CSU_ADDR
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_ALL_RW },
+ { CSU_CSLX_GDI, CSU_ALL_RW },
+ { CSU_CSLX_DDI, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+ { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+#endif
+
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -227,6 +314,11 @@ int board_init(void)
fsl_serdes_init();
config_serdes_mux();
#endif
+
+#ifdef CONFIG_SYS_FSL_CSU_ADDR
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+
return 0;
}
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index b522ff2..c4d3600 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -8,6 +8,7 @@
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ns_access.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <mmc.h>
@@ -270,6 +271,92 @@ int board_early_init_f(void)
return 0;
}
+#ifdef CONFIG_SYS_FSL_CSU_ADDR
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_ALL_RW },
+ { CSU_CSLX_GDI, CSU_ALL_RW },
+ { CSU_CSLX_DDI, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+ { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+#endif
+
int board_init(void)
{
#ifndef CONFIG_SYS_FSL_NO_SERDES
@@ -277,6 +364,10 @@ int board_init(void)
config_serdes_mux();
#endif
+#ifdef CONFIG_SYS_FSL_CSU_ADDR
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+
return 0;
}
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 6976cfa..4067be9 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -327,6 +327,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ARMV7_NONSEC
#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LS102XA_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define CONFIG_TIMER_CLK_FREQ 12500000
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 655b39a..2a40d6a 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -230,6 +230,7 @@
#define CONFIG_ARMV7_NONSEC
#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LS102XA_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define CONFIG_TIMER_CLK_FREQ 12500000
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 5/5] ARM: ls102xa: Setting device's stream id for SMMUs.
2014-10-20 9:00 [U-Boot] [PATCH v3 0/5] ls102xa: HYP/non-sec: for ls102xa Xiubo Li
` (3 preceding siblings ...)
2014-10-20 9:00 ` [U-Boot] [PATCH v3 4/5] ARM: ls102xa: allow all the peripheral access permissions as R/W Xiubo Li
@ 2014-10-20 9:00 ` Xiubo Li
2014-11-13 16:45 ` York Sun
2014-11-13 6:15 ` [U-Boot] [PATCH v3 0/5] ls102xa: HYP/non-sec: for ls102xa Albert ARIBAUD
5 siblings, 1 reply; 22+ messages in thread
From: Xiubo Li @ 2014-10-20 9:00 UTC (permalink / raw)
To: u-boot
LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
.../include/asm/arch-ls102xa/ls102xa_stream_id.h | 17 +++++++++++++++++
board/freescale/common/Makefile | 2 ++
board/freescale/common/ls102xa_stream_id.c | 18 ++++++++++++++++++
board/freescale/ls1021aqds/ls1021aqds.c | 21 +++++++++++++++++++++
board/freescale/ls1021atwr/ls1021atwr.c | 21 +++++++++++++++++++++
include/configs/ls1021aqds.h | 2 ++
include/configs/ls1021atwr.h | 2 ++
7 files changed, 83 insertions(+)
create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
create mode 100644 board/freescale/common/ls102xa_stream_id.c
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
new file mode 100644
index 0000000..abd70fc
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_STREAM_ID_H_
+#define __FSL_LS102XA_STREAM_ID_H_
+
+struct smmu_stream_id {
+ uint16_t offset;
+ uint16_t stream_id;
+ char dev_name[32];
+};
+
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+#endif
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index e5aad2d..2cf3963 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -54,6 +54,8 @@ obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
obj-$(CONFIG_ZM7300) += zm7300.o
+obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
+
# deal with common files for P-series corenet based devices
obj-$(CONFIG_P2041RDB) += p_corenet/
obj-$(CONFIG_P3041DS) += p_corenet/
diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
new file mode 100644
index 0000000..6154c9c
--- /dev/null
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ls102xa_stream_id.h>
+
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
+{
+ uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
+ int i;
+
+ for (i = 0; i < num; i++)
+ out_be32(scfg + id[i].offset, id[i].stream_id);
+}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 07df7d2..dba0190 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -11,6 +11,7 @@
#include <asm/arch/ns_access.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
@@ -300,6 +301,23 @@ static struct csu_ns_dev ns_dev[] = {
};
#endif
+struct smmu_stream_id dev_stream_id[] = {
+ { 0x100, 0x01, "ETSEC MAC1" },
+ { 0x104, 0x02, "ETSEC MAC2" },
+ { 0x108, 0x03, "ETSEC MAC3" },
+ { 0x10c, 0x04, "PEX1" },
+ { 0x110, 0x05, "PEX2" },
+ { 0x114, 0x06, "qDMA" },
+ { 0x118, 0x07, "SATA" },
+ { 0x11c, 0x08, "USB3" },
+ { 0x120, 0x09, "QE" },
+ { 0x124, 0x0a, "eSDHC" },
+ { 0x128, 0x0b, "eMA" },
+ { 0x14c, 0x0c, "2D-ACE" },
+ { 0x150, 0x0d, "USB2" },
+ { 0x18c, 0x0e, "DEBUG" },
+};
+
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -315,6 +333,9 @@ int board_init(void)
config_serdes_mux();
#endif
+ ls102xa_config_smmu_stream_id(dev_stream_id,
+ ARRAY_SIZE(dev_stream_id));
+
#ifdef CONFIG_SYS_FSL_CSU_ADDR
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
#endif
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index c4d3600..a1978e8 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -11,6 +11,7 @@
#include <asm/arch/ns_access.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
@@ -357,6 +358,23 @@ static struct csu_ns_dev ns_dev[] = {
};
#endif
+struct smmu_stream_id dev_stream_id[] = {
+ { 0x100, 0x01, "ETSEC MAC1" },
+ { 0x104, 0x02, "ETSEC MAC2" },
+ { 0x108, 0x03, "ETSEC MAC3" },
+ { 0x10c, 0x04, "PEX1" },
+ { 0x110, 0x05, "PEX2" },
+ { 0x114, 0x06, "qDMA" },
+ { 0x118, 0x07, "SATA" },
+ { 0x11c, 0x08, "USB3" },
+ { 0x120, 0x09, "QE" },
+ { 0x124, 0x0a, "eSDHC" },
+ { 0x128, 0x0b, "eMA" },
+ { 0x14c, 0x0c, "2D-ACE" },
+ { 0x150, 0x0d, "USB2" },
+ { 0x18c, 0x0e, "DEBUG" },
+};
+
int board_init(void)
{
#ifndef CONFIG_SYS_FSL_NO_SERDES
@@ -364,6 +382,9 @@ int board_init(void)
config_serdes_mux();
#endif
+ ls102xa_config_smmu_stream_id(dev_stream_id,
+ ARRAY_SIZE(dev_stream_id));
+
#ifdef CONFIG_SYS_FSL_CSU_ADDR
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
#endif
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 4067be9..480e129 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -367,6 +367,8 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_SYS_HZ 1000
+#define CONFIG_LS102XA_STREAM_ID
+
/*
* Stack sizes
* The stack sizes are set up in start.S using the settings below
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 2a40d6a..7f480bd 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -269,6 +269,8 @@
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_SYS_HZ 1000
+#define CONFIG_LS102XA_STREAM_ID
+
/*
* Stack sizes
* The stack sizes are set up in start.S using the settings below
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 0/5] ls102xa: HYP/non-sec: for ls102xa.
2014-10-20 9:00 [U-Boot] [PATCH v3 0/5] ls102xa: HYP/non-sec: for ls102xa Xiubo Li
` (4 preceding siblings ...)
2014-10-20 9:00 ` [U-Boot] [PATCH v3 5/5] ARM: ls102xa: Setting device's stream id for SMMUs Xiubo Li
@ 2014-11-13 6:15 ` Albert ARIBAUD
5 siblings, 0 replies; 22+ messages in thread
From: Albert ARIBAUD @ 2014-11-13 6:15 UTC (permalink / raw)
To: u-boot
Hello York,
On Mon, 20 Oct 2014 17:00:45 +0800, Xiubo Li <Li.Xiubo@freescale.com>
wrote:
> Change for V3:
> - Fix the language in commit message.
>
> Change for V2:
> - All the registers are defined as a struct, here use it.
> - Use CONFIG_PEN_ADDR_BIG_ENDIAN instead of CONFIG_SOC_BIG_ENDIAN.
>
>
> Xiubo Li (5):
> ARM: HYP/non-sec: add the pen address BE mode support.
> ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
> ls102xa: HYP/non-sec: support for ls102xa boards
> ARM: ls102xa: allow all the peripheral access permissions as R/W.
> ARM: ls102xa: Setting device's stream id for SMMUs.
York,
Delegation of this patch is split among us. Again, one of us could
give his acked-by and the other could apply the whole patch in a row. I'm ok
with applying. :)
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 1/5] ARM: HYP/non-sec: add the pen address BE mode support.
2014-10-20 9:00 ` [U-Boot] [PATCH v3 1/5] ARM: HYP/non-sec: add the pen address BE mode support Xiubo Li
@ 2014-11-13 16:44 ` York Sun
0 siblings, 0 replies; 22+ messages in thread
From: York Sun @ 2014-11-13 16:44 UTC (permalink / raw)
To: u-boot
On 10/20/2014 02:00 AM, Xiubo Li wrote:
> For some SoCs, the pen address register maybe in BE mode and the
> CPUs are in LE mode.
>
> This patch adds BE mode support for smp pen address.
>
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> ---
Acked-by: York Sun <yorksun@freescale.com>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 2/5] ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
2014-10-20 9:00 ` [U-Boot] [PATCH v3 2/5] ARM: HYP/non-sec: Fix the ARCH Timer frequency setting Xiubo Li
@ 2014-11-13 16:44 ` York Sun
0 siblings, 0 replies; 22+ messages in thread
From: York Sun @ 2014-11-13 16:44 UTC (permalink / raw)
To: u-boot
On 10/20/2014 02:00 AM, Xiubo Li wrote:
> For some SoCs, the system clock frequency may not equal to the
> ARCH Timer's frequency.
>
> This patch uses the CONFIG_TIMER_CLK_FREQ instead of
> CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
> macor could be set separately and without interfering each other.
>
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> ---
Acked-by: York Sun <yorksun@freescale.com>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
2014-10-20 9:00 ` [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards Xiubo Li
@ 2014-11-13 16:44 ` York Sun
2014-11-14 7:49 ` Albert ARIBAUD
1 sibling, 0 replies; 22+ messages in thread
From: York Sun @ 2014-11-13 16:44 UTC (permalink / raw)
To: u-boot
On 10/20/2014 02:00 AM, Xiubo Li wrote:
> Enable hypervisors utilizing the ARMv7 virtualization extension
> on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
> required configuration variable.
> Also we define the board specific smp_set_cpu_boot_addr() function
> to set the start address for secondary cores in the LS1021A specific
> manner.
>
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> ---
Acked-by: York Sun <yorksun@freescale.com>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 4/5] ARM: ls102xa: allow all the peripheral access permissions as R/W.
2014-10-20 9:00 ` [U-Boot] [PATCH v3 4/5] ARM: ls102xa: allow all the peripheral access permissions as R/W Xiubo Li
@ 2014-11-13 16:45 ` York Sun
0 siblings, 0 replies; 22+ messages in thread
From: York Sun @ 2014-11-13 16:45 UTC (permalink / raw)
To: u-boot
On 10/20/2014 02:00 AM, Xiubo Li wrote:
> The Central Security Unit (CSU) allows secure world software to
> change the default access control policies of peripherals/bus
> slaves, determining which bus masters may access them. This
> allows peripherals to be separated into distinct security domains.
> Combined with SMMU configuration of the system masters privileges,
> these features provide protection against indirect unauthorized
> access to data.
>
> For now we configure all the peripheral access permissions as R/W.
>
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> ---
Acked-by: York Sun <yorksun@freescale.com>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 5/5] ARM: ls102xa: Setting device's stream id for SMMUs.
2014-10-20 9:00 ` [U-Boot] [PATCH v3 5/5] ARM: ls102xa: Setting device's stream id for SMMUs Xiubo Li
@ 2014-11-13 16:45 ` York Sun
0 siblings, 0 replies; 22+ messages in thread
From: York Sun @ 2014-11-13 16:45 UTC (permalink / raw)
To: u-boot
On 10/20/2014 02:00 AM, Xiubo Li wrote:
> LS1 has 4 SMMUs for address translation of the masters. All the
> SMMUs' stream IDs are 8-bit. The address translation depends on the
> stream ID of the incoming transaction.
> Each master has unique stream ID assigned to it and is configurable
> through SCFG registers. The stream ID for the masters is identical
> and share the same register field of STREAM ID registers.
>
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> ---
Acked-by: York Sun <yorksun@freescale.com>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
2014-10-20 9:00 ` [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards Xiubo Li
2014-11-13 16:44 ` York Sun
@ 2014-11-14 7:49 ` Albert ARIBAUD
2014-11-14 9:06 ` Li.Xiubo at freescale.com
1 sibling, 1 reply; 22+ messages in thread
From: Albert ARIBAUD @ 2014-11-14 7:49 UTC (permalink / raw)
To: u-boot
Hello Xiubo,
On Mon, 20 Oct 2014 17:00:48 +0800, Xiubo Li <Li.Xiubo@freescale.com>
wrote:
> Enable hypervisors utilizing the ARMv7 virtualization extension
> on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
> required configuration variable.
> Also we define the board specific smp_set_cpu_boot_addr() function
> to set the start address for secondary cores in the LS1021A specific
> manner.
Seems like there are two different logical changes here:
- adding a secondary core boot address function;
- changing a few targets' configurations.
Please split this patch in two.
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> ---
> arch/arm/cpu/armv7/ls102xa/cpu.c | 15 +++++++++++++++
> arch/arm/include/asm/arch-ls102xa/config.h | 2 ++
> arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++
> include/configs/ls1021aqds.h | 7 +++++++
> include/configs/ls1021atwr.h | 7 +++++++
> 5 files changed, 34 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
> index b7dde45..69d1801 100644
> --- a/arch/arm/cpu/armv7/ls102xa/cpu.c
> +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
> @@ -101,3 +101,18 @@ int cpu_eth_init(bd_t *bis)
>
> return 0;
> }
> +
> +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> +/* Setting the address at which secondary cores start from.*/
> +void smp_set_core_boot_addr(unsigned long addr, int corenr)
> +{
> + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> +
> + /*
> + * After setting the secondary cores start address,
> + * just release them to boot.
> + */
> + out_be32(&gur->scratchrw[0], addr);
> + out_be32(&gur->brrl, 0x2);
> +}
This function does not exactly "[set] the address at which secondary
cores start from"; it sets *a* secondary core's boot address, and then
it *boots* it.
Why does this version of smp_set_core_boot_addr() need to boot the core
in addition to setting the address, whereas the existing ones in
virt_v7, vexpress_common and arndale don't boot the cores?
> +#endif
> diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
> index ed78c33..4856388 100644
> --- a/arch/arm/include/asm/arch-ls102xa/config.h
> +++ b/arch/arm/include/asm/arch-ls102xa/config.h
> @@ -11,6 +11,8 @@
>
> #define OCRAM_BASE_ADDR 0x10000000
> #define OCRAM_SIZE 0x00020000
> +#define OCRAM_BASE_S_ADDR 0x10010000
> +#define OCRAM_S_SIZE 0x00010000
>
> #define CONFIG_SYS_IMMR 0x01000000
>
> diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
> index 7995fe2..0bac353 100644
> --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
> +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
> @@ -17,6 +17,9 @@
> #define SOC_VER_LS1021 0x11
> #define SOC_VER_LS1022 0x12
>
> +#define CCSR_BRR_OFFSET 0xe4
> +#define CCSR_SCRATCHRW1_OFFSET 0x200
> +
> #define RCWSR0_SYS_PLL_RAT_SHIFT 25
> #define RCWSR0_SYS_PLL_RAT_MASK 0x1f
> #define RCWSR0_MEM_PLL_RAT_SHIFT 16
> diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
> index 657e3b6..6976cfa 100644
> --- a/include/configs/ls1021aqds.h
> +++ b/include/configs/ls1021aqds.h
> @@ -324,6 +324,13 @@ unsigned long get_board_ddr_clk(void);
> #define CONFIG_CMDLINE_EDITING
> #define CONFIG_CMD_IMLS
>
> +#define CONFIG_ARMV7_NONSEC
> +#define CONFIG_ARMV7_VIRT
> +#define CONFIG_PEN_ADDR_BIG_ENDIAN
> +#define CONFIG_SMP_PEN_ADDR 0x01ee0200
> +#define CONFIG_TIMER_CLK_FREQ 12500000
> +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
> +
> #define CONFIG_HWCONFIG
> #define HWCONFIG_BUFFER_SIZE 128
>
> diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
> index 45b2272..655b39a 100644
> --- a/include/configs/ls1021atwr.h
> +++ b/include/configs/ls1021atwr.h
> @@ -227,6 +227,13 @@
> #define CONFIG_CMDLINE_EDITING
> #define CONFIG_CMD_IMLS
>
> +#define CONFIG_ARMV7_NONSEC
> +#define CONFIG_ARMV7_VIRT
> +#define CONFIG_PEN_ADDR_BIG_ENDIAN
> +#define CONFIG_SMP_PEN_ADDR 0x01ee0200
> +#define CONFIG_TIMER_CLK_FREQ 12500000
> +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
> +
> #define CONFIG_HWCONFIG
> #define HWCONFIG_BUFFER_SIZE 128
>
> --
> 2.1.0.27.g96db324
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
2014-11-14 7:49 ` Albert ARIBAUD
@ 2014-11-14 9:06 ` Li.Xiubo at freescale.com
2014-11-14 11:44 ` Albert ARIBAUD
0 siblings, 1 reply; 22+ messages in thread
From: Li.Xiubo at freescale.com @ 2014-11-14 9:06 UTC (permalink / raw)
To: u-boot
Hi Albert,
> > +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> > +/* Setting the address at which secondary cores start from.*/
> > +void smp_set_core_boot_addr(unsigned long addr, int corenr)
> > +{
> > + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > +
> > + /*
> > + * After setting the secondary cores start address,
> > + * just release them to boot.
> > + */
> > + out_be32(&gur->scratchrw[0], addr);
> > + out_be32(&gur->brrl, 0x2);
> > +}
>
> This function does not exactly "[set] the address at which secondary
> cores start from"; it sets *a* secondary core's boot address, and then
> it *boots* it.
>
Okay, I will fix it later.
> Why does this version of smp_set_core_boot_addr() need to boot the core
> in addition to setting the address, whereas the existing ones in
> virt_v7, vexpress_common and arndale don't boot the cores?
>
Yes, they don't doing the release operation.
For Low Power Management requirement, maybe only one core will be used, and then
We also make sure that the secondary core must be in low power and deep sleep
mode(using wfi). So I just release it here, to make sure that the wfi instruction
will be executed as early as possible.
Thanks,
BRs,
Xiubo
> > +#endif
> > diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
> b/arch/arm/include/asm/arch-ls102xa/config.h
> > index ed78c33..4856388 100644
> > --- a/arch/arm/include/asm/arch-ls102xa/config.h
> > +++ b/arch/arm/include/asm/arch-ls102xa/config.h
> > @@ -11,6 +11,8 @@
> >
> > #define OCRAM_BASE_ADDR 0x10000000
> > #define OCRAM_SIZE 0x00020000
> > +#define OCRAM_BASE_S_ADDR 0x10010000
> > +#define OCRAM_S_SIZE 0x00010000
> >
> > #define CONFIG_SYS_IMMR 0x01000000
> >
> > diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
> b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
> > index 7995fe2..0bac353 100644
> > --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
> > +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
> > @@ -17,6 +17,9 @@
> > #define SOC_VER_LS1021 0x11
> > #define SOC_VER_LS1022 0x12
> >
> > +#define CCSR_BRR_OFFSET 0xe4
> > +#define CCSR_SCRATCHRW1_OFFSET 0x200
> > +
> > #define RCWSR0_SYS_PLL_RAT_SHIFT 25
> > #define RCWSR0_SYS_PLL_RAT_MASK 0x1f
> > #define RCWSR0_MEM_PLL_RAT_SHIFT 16
> > diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
> > index 657e3b6..6976cfa 100644
> > --- a/include/configs/ls1021aqds.h
> > +++ b/include/configs/ls1021aqds.h
> > @@ -324,6 +324,13 @@ unsigned long get_board_ddr_clk(void);
> > #define CONFIG_CMDLINE_EDITING
> > #define CONFIG_CMD_IMLS
> >
> > +#define CONFIG_ARMV7_NONSEC
> > +#define CONFIG_ARMV7_VIRT
> > +#define CONFIG_PEN_ADDR_BIG_ENDIAN
> > +#define CONFIG_SMP_PEN_ADDR 0x01ee0200
> > +#define CONFIG_TIMER_CLK_FREQ 12500000
> > +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
> > +
> > #define CONFIG_HWCONFIG
> > #define HWCONFIG_BUFFER_SIZE 128
> >
> > diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
> > index 45b2272..655b39a 100644
> > --- a/include/configs/ls1021atwr.h
> > +++ b/include/configs/ls1021atwr.h
> > @@ -227,6 +227,13 @@
> > #define CONFIG_CMDLINE_EDITING
> > #define CONFIG_CMD_IMLS
> >
> > +#define CONFIG_ARMV7_NONSEC
> > +#define CONFIG_ARMV7_VIRT
> > +#define CONFIG_PEN_ADDR_BIG_ENDIAN
> > +#define CONFIG_SMP_PEN_ADDR 0x01ee0200
> > +#define CONFIG_TIMER_CLK_FREQ 12500000
> > +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
> > +
> > #define CONFIG_HWCONFIG
> > #define HWCONFIG_BUFFER_SIZE 128
> >
> > --
> > 2.1.0.27.g96db324
>
>
>
> Amicalement,
> --
> Albert.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
2014-11-14 9:06 ` Li.Xiubo at freescale.com
@ 2014-11-14 11:44 ` Albert ARIBAUD
2014-11-17 2:16 ` Li.Xiubo at freescale.com
0 siblings, 1 reply; 22+ messages in thread
From: Albert ARIBAUD @ 2014-11-14 11:44 UTC (permalink / raw)
To: u-boot
Hello Li.Xiubo at freescale.com,
On Fri, 14 Nov 2014 09:06:13 +0000, Li.Xiubo at freescale.com
<Li.Xiubo@freescale.com> wrote:
> Hi Albert,
>
> > > +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> > > +/* Setting the address at which secondary cores start from.*/
> > > +void smp_set_core_boot_addr(unsigned long addr, int corenr)
> > > +{
> > > + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > > +
> > > + /*
> > > + * After setting the secondary cores start address,
> > > + * just release them to boot.
> > > + */
> > > + out_be32(&gur->scratchrw[0], addr);
> > > + out_be32(&gur->brrl, 0x2);
> > > +}
> >
> > This function does not exactly "[set] the address at which secondary
> > cores start from"; it sets *a* secondary core's boot address, and then
> > it *boots* it.
> >
>
> Okay, I will fix it later.
>
> > Why does this version of smp_set_core_boot_addr() need to boot the core
> > in addition to setting the address, whereas the existing ones in
> > virt_v7, vexpress_common and arndale don't boot the cores?
> >
>
> Yes, they don't doing the release operation.
>
> For Low Power Management requirement, maybe only one core will be used, and then
> We also make sure that the secondary core must be in low power and deep sleep
> mode(using wfi). So I just release it here, to make sure that the wfi instruction
> will be executed as early as possible.
Right after smp_set_core_boot_addr() is called, kick_all_cpus() isgoing
to be called. Wouldn't that boot your CPUs just as well?
> Thanks,
>
> BRs,
> Xiubo
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
2014-11-14 11:44 ` Albert ARIBAUD
@ 2014-11-17 2:16 ` Li.Xiubo at freescale.com
2014-11-17 13:04 ` Albert ARIBAUD
0 siblings, 1 reply; 22+ messages in thread
From: Li.Xiubo at freescale.com @ 2014-11-17 2:16 UTC (permalink / raw)
To: u-boot
Hi Albert,
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.u.boot at aribaud.net]
> Sent: Friday, November 14, 2014 7:45 PM
> To: Xiubo Li-B47053
> Cc: Sun York-R58495; Jin Zhengxiong-R64188; u-boot at lists.denx.de
> Subject: Re: [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
>
> Hello Li.Xiubo at freescale.com,
>
> On Fri, 14 Nov 2014 09:06:13 +0000, Li.Xiubo at freescale.com
> <Li.Xiubo@freescale.com> wrote:
> > Hi Albert,
> >
> > > > +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> > > > +/* Setting the address at which secondary cores start from.*/
> > > > +void smp_set_core_boot_addr(unsigned long addr, int corenr)
> > > > +{
> > > > + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > > > +
> > > > + /*
> > > > + * After setting the secondary cores start address,
> > > > + * just release them to boot.
> > > > + */
> > > > + out_be32(&gur->scratchrw[0], addr);
> > > > + out_be32(&gur->brrl, 0x2);
> > > > +}
> > >
> > > This function does not exactly "[set] the address at which secondary
> > > cores start from"; it sets *a* secondary core's boot address, and then
> > > it *boots* it.
> > >
> >
> > Okay, I will fix it later.
> >
> > > Why does this version of smp_set_core_boot_addr() need to boot the core
> > > in addition to setting the address, whereas the existing ones in
> > > virt_v7, vexpress_common and arndale don't boot the cores?
> > >
> >
> > Yes, they don't doing the release operation.
> >
> > For Low Power Management requirement, maybe only one core will be used, and
> then
> > We also make sure that the secondary core must be in low power and deep
> sleep
> > mode(using wfi). So I just release it here, to make sure that the wfi
> instruction
> > will be executed as early as possible.
>
> Right after smp_set_core_boot_addr() is called, kick_all_cpus() isgoing
> to be called. Wouldn't that boot your CPUs just as well?
>
Yes, it will.
But before that we must do the holdoff bit set operation as the SoC's requirement.
The BRR contains control bits for enabling boot for each core. On exiting HRESET or
PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released
for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their
corresponding bit is set.
Maybe the comment is not very clear and a bit confusing.
Thanks,
BRs
Xiubo
> > Thanks,
> >
> > BRs,
> > Xiubo
>
> Amicalement,
> --
> Albert.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
2014-11-17 2:16 ` Li.Xiubo at freescale.com
@ 2014-11-17 13:04 ` Albert ARIBAUD
2014-11-18 2:01 ` Li.Xiubo at freescale.com
0 siblings, 1 reply; 22+ messages in thread
From: Albert ARIBAUD @ 2014-11-17 13:04 UTC (permalink / raw)
To: u-boot
Hello Li.Xiubo at freescale.com,
On Mon, 17 Nov 2014 02:16:11 +0000, Li.Xiubo at freescale.com
<Li.Xiubo@freescale.com> wrote:
> Hi Albert,
>
>
> > -----Original Message-----
> > From: Albert ARIBAUD [mailto:albert.u.boot at aribaud.net]
> > Sent: Friday, November 14, 2014 7:45 PM
> > To: Xiubo Li-B47053
> > Cc: Sun York-R58495; Jin Zhengxiong-R64188; u-boot at lists.denx.de
> > Subject: Re: [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
> >
> > Hello Li.Xiubo at freescale.com,
> >
> > On Fri, 14 Nov 2014 09:06:13 +0000, Li.Xiubo at freescale.com
> > <Li.Xiubo@freescale.com> wrote:
> > > Hi Albert,
> > >
> > > > > +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> > > > > +/* Setting the address at which secondary cores start from.*/
> > > > > +void smp_set_core_boot_addr(unsigned long addr, int corenr)
> > > > > +{
> > > > > + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > > > > +
> > > > > + /*
> > > > > + * After setting the secondary cores start address,
> > > > > + * just release them to boot.
> > > > > + */
> > > > > + out_be32(&gur->scratchrw[0], addr);
> > > > > + out_be32(&gur->brrl, 0x2);
> > > > > +}
> > > >
> > > > This function does not exactly "[set] the address at which secondary
> > > > cores start from"; it sets *a* secondary core's boot address, and then
> > > > it *boots* it.
> > > >
> > >
> > > Okay, I will fix it later.
> > >
> > > > Why does this version of smp_set_core_boot_addr() need to boot the core
> > > > in addition to setting the address, whereas the existing ones in
> > > > virt_v7, vexpress_common and arndale don't boot the cores?
> > > >
> > >
> > > Yes, they don't doing the release operation.
> > >
> > > For Low Power Management requirement, maybe only one core will be used, and
> > then
> > > We also make sure that the secondary core must be in low power and deep
> > sleep
> > > mode(using wfi). So I just release it here, to make sure that the wfi
> > instruction
> > > will be executed as early as possible.
> >
> > Right after smp_set_core_boot_addr() is called, kick_all_cpus() isgoing
> > to be called. Wouldn't that boot your CPUs just as well?
> >
>
> Yes, it will.
>
> But before that we must do the holdoff bit set operation as the SoC's requirement.
>
> The BRR contains control bits for enabling boot for each core. On exiting HRESET or
> PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released
> for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their
> corresponding bit is set.
>
> Maybe the comment is not very clear and a bit confusing.
Before I'm lost entirely, do you mean that the comment:
> > > > > + /*
> > > > > + * After setting the secondary cores start address,
> > > > > + * just release them to boot.
> > > > > + */
Is actually wrong, and the instructions that follow it do not actually
boot the secondary core(s)?
> Thanks,
>
> BRs
> Xiubo
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
2014-11-17 13:04 ` Albert ARIBAUD
@ 2014-11-18 2:01 ` Li.Xiubo at freescale.com
2014-11-18 7:18 ` Albert ARIBAUD
0 siblings, 1 reply; 22+ messages in thread
From: Li.Xiubo at freescale.com @ 2014-11-18 2:01 UTC (permalink / raw)
To: u-boot
Hi Albert,
> > > > > > +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> > > > > > +/* Setting the address at which secondary cores start from.*/
> > > > > > +void smp_set_core_boot_addr(unsigned long addr, int corenr)
> > > > > > +{
> > > > > > + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > > > > > +
> > > > > > + /*
> > > > > > + * After setting the secondary cores start address,
> > > > > > + * just release them to boot.
> > > > > > + */
> > > > > > + out_be32(&gur->scratchrw[0], addr);
> > > > > > + out_be32(&gur->brrl, 0x2);
> > > > > > +}
> > > > >
> > > > > This function does not exactly "[set] the address at which secondary
> > > > > cores start from"; it sets *a* secondary core's boot address, and then
> > > > > it *boots* it.
> > > > >
> > > >
> > > > Okay, I will fix it later.
> > > >
> > > > > Why does this version of smp_set_core_boot_addr() need to boot the
> core
> > > > > in addition to setting the address, whereas the existing ones in
> > > > > virt_v7, vexpress_common and arndale don't boot the cores?
> > > > >
> > > >
> > > > Yes, they don't doing the release operation.
> > > >
> > > > For Low Power Management requirement, maybe only one core will be used,
> and
> > > then
> > > > We also make sure that the secondary core must be in low power and deep
> > > sleep
> > > > mode(using wfi). So I just release it here, to make sure that the wfi
> > > instruction
> > > > will be executed as early as possible.
> > >
> > > Right after smp_set_core_boot_addr() is called, kick_all_cpus() isgoing
> > > to be called. Wouldn't that boot your CPUs just as well?
> > >
> >
> > Yes, it will.
> >
> > But before that we must do the holdoff bit set operation as the SoC's
> requirement.
> >
> > The BRR contains control bits for enabling boot for each core. On exiting
> HRESET or
> > PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be
> released
> > for booting or to remain in boot holdoff. All other cores remain in boot
> holdoff until their
> > corresponding bit is set.
> >
> > Maybe the comment is not very clear and a bit confusing.
>
> Before I'm lost entirely, do you mean that the comment:
>
> > > > > > + /*
> > > > > > + * After setting the secondary cores start address,
> > > > > > + * just release them to boot.
> > > > > > + */
>
> Is actually wrong, and the instructions that follow it do not actually
> boot the secondary core(s)?
>
The comment should be:
/*
* After setting the secondary core's start address,
* just release it from holdoff.
*/
From my tests, for most time the release instructions will boot the secondary
core(s) without smp_kick_all_cpus(). One time has failed.
So I think the release can not make sure that it will boot the secondary core(s).
Thanks,
BRs
Xiubo
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
2014-11-18 2:01 ` Li.Xiubo at freescale.com
@ 2014-11-18 7:18 ` Albert ARIBAUD
2014-11-19 7:21 ` Li.Xiubo at freescale.com
0 siblings, 1 reply; 22+ messages in thread
From: Albert ARIBAUD @ 2014-11-18 7:18 UTC (permalink / raw)
To: u-boot
Hello Li.Xiubo at freescale.com,
On Tue, 18 Nov 2014 02:01:02 +0000, Li.Xiubo at freescale.com
<Li.Xiubo@freescale.com> wrote:
> Hi Albert,
>
>
> > > > > > > +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> > > > > > > +/* Setting the address at which secondary cores start from.*/
> > > > > > > +void smp_set_core_boot_addr(unsigned long addr, int corenr)
> > > > > > > +{
> > > > > > > + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > > > > > > +
> > > > > > > + /*
> > > > > > > + * After setting the secondary cores start address,
> > > > > > > + * just release them to boot.
> > > > > > > + */
> > > > > > > + out_be32(&gur->scratchrw[0], addr);
> > > > > > > + out_be32(&gur->brrl, 0x2);
> > > > > > > +}
> > > > > >
> > > > > > This function does not exactly "[set] the address at which secondary
> > > > > > cores start from"; it sets *a* secondary core's boot address, and then
> > > > > > it *boots* it.
> > > > > >
> > > > >
> > > > > Okay, I will fix it later.
> > > > >
> > > > > > Why does this version of smp_set_core_boot_addr() need to boot the
> > core
> > > > > > in addition to setting the address, whereas the existing ones in
> > > > > > virt_v7, vexpress_common and arndale don't boot the cores?
> > > > > >
> > > > >
> > > > > Yes, they don't doing the release operation.
> > > > >
> > > > > For Low Power Management requirement, maybe only one core will be used,
> > and
> > > > then
> > > > > We also make sure that the secondary core must be in low power and deep
> > > > sleep
> > > > > mode(using wfi). So I just release it here, to make sure that the wfi
> > > > instruction
> > > > > will be executed as early as possible.
> > > >
> > > > Right after smp_set_core_boot_addr() is called, kick_all_cpus() isgoing
> > > > to be called. Wouldn't that boot your CPUs just as well?
> > > >
> > >
> > > Yes, it will.
> > >
> > > But before that we must do the holdoff bit set operation as the SoC's
> > requirement.
> > >
> > > The BRR contains control bits for enabling boot for each core. On exiting
> > HRESET or
> > > PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be
> > released
> > > for booting or to remain in boot holdoff. All other cores remain in boot
> > holdoff until their
> > > corresponding bit is set.
> > >
> > > Maybe the comment is not very clear and a bit confusing.
> >
> > Before I'm lost entirely, do you mean that the comment:
> >
> > > > > > > + /*
> > > > > > > + * After setting the secondary cores start address,
> > > > > > > + * just release them to boot.
> > > > > > > + */
> >
> > Is actually wrong, and the instructions that follow it do not actually
> > boot the secondary core(s)?
> >
>
> The comment should be:
> /*
> * After setting the secondary core's start address,
> * just release it from holdoff.
> */
> From my tests, for most time the release instructions will boot the secondary
> core(s) without smp_kick_all_cpus(). One time has failed.
>
> So I think the release can not make sure that it will boot the secondary core(s).
Thanks for clarifying.
If a holdoff release is the right way to boot a secondary core for you,
then I think the right place to do it is not smp_set_core_boot_addr()
but smp_kick_all_cpus(), of which you could make a strong version which
would do the holdoff release instead of whatever the weak version does.
That is, unless you also need the weak version to run, in which case
I /still/ think you should find a way for all of this to happen at the
'kick" stage (maybe with a .weakref in arch/arm/cpu/armv8/start.S, to
give the weak smp_kick_all_cpus symbol another name that could be
referred to by the strong version).
> Thanks,
>
> BRs
> Xiubo
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
2014-11-18 7:18 ` Albert ARIBAUD
@ 2014-11-19 7:21 ` Li.Xiubo at freescale.com
2014-11-20 12:06 ` Albert ARIBAUD
0 siblings, 1 reply; 22+ messages in thread
From: Li.Xiubo at freescale.com @ 2014-11-19 7:21 UTC (permalink / raw)
To: u-boot
Hi Albert,
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.u.boot at aribaud.net]
> Sent: Tuesday, November 18, 2014 3:18 PM
> To: Xiubo Li-B47053
> Cc: Sun York-R58495; Jin Zhengxiong-R64188; u-boot at lists.denx.de
> Subject: Re: [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
>
> Hello Li.Xiubo at freescale.com,
>
> On Tue, 18 Nov 2014 02:01:02 +0000, Li.Xiubo at freescale.com
> <Li.Xiubo@freescale.com> wrote:
> > Hi Albert,
> >
> >
> > > > > > > > +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> > > > > > > > +/* Setting the address at which secondary cores start from.*/
> > > > > > > > +void smp_set_core_boot_addr(unsigned long addr, int corenr)
> > > > > > > > +{
> > > > > > > > + struct ccsr_gur __iomem *gur = (void
> *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > > > > > > > +
> > > > > > > > + /*
> > > > > > > > + * After setting the secondary cores start address,
> > > > > > > > + * just release them to boot.
> > > > > > > > + */
> > > > > > > > + out_be32(&gur->scratchrw[0], addr);
> > > > > > > > + out_be32(&gur->brrl, 0x2);
> > > > > > > > +}
> > > > > > >
> > > > > > > This function does not exactly "[set] the address at which
> secondary
> > > > > > > cores start from"; it sets *a* secondary core's boot address, and
> then
> > > > > > > it *boots* it.
> > > > > > >
> > > > > >
> > > > > > Okay, I will fix it later.
> > > > > >
> > > > > > > Why does this version of smp_set_core_boot_addr() need to boot the
> > > core
> > > > > > > in addition to setting the address, whereas the existing ones in
> > > > > > > virt_v7, vexpress_common and arndale don't boot the cores?
> > > > > > >
> > > > > >
> > > > > > Yes, they don't doing the release operation.
> > > > > >
> > > > > > For Low Power Management requirement, maybe only one core will be
> used,
> > > and
> > > > > then
> > > > > > We also make sure that the secondary core must be in low power and
> deep
> > > > > sleep
> > > > > > mode(using wfi). So I just release it here, to make sure that the
> wfi
> > > > > instruction
> > > > > > will be executed as early as possible.
> > > > >
> > > > > Right after smp_set_core_boot_addr() is called, kick_all_cpus()
> isgoing
> > > > > to be called. Wouldn't that boot your CPUs just as well?
> > > > >
> > > >
> > > > Yes, it will.
> > > >
> > > > But before that we must do the holdoff bit set operation as the SoC's
> > > requirement.
> > > >
> > > > The BRR contains control bits for enabling boot for each core. On
> exiting
> > > HRESET or
> > > > PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to
> be
> > > released
> > > > for booting or to remain in boot holdoff. All other cores remain in boot
> > > holdoff until their
> > > > corresponding bit is set.
> > > >
> > > > Maybe the comment is not very clear and a bit confusing.
> > >
> > > Before I'm lost entirely, do you mean that the comment:
> > >
> > > > > > > > + /*
> > > > > > > > + * After setting the secondary cores start address,
> > > > > > > > + * just release them to boot.
> > > > > > > > + */
> > >
> > > Is actually wrong, and the instructions that follow it do not actually
> > > boot the secondary core(s)?
> > >
> >
> > The comment should be:
> > /*
> > * After setting the secondary core's start address,
> > * just release it from holdoff.
> > */
> > From my tests, for most time the release instructions will boot the
> secondary
> > core(s) without smp_kick_all_cpus(). One time has failed.
> >
> > So I think the release can not make sure that it will boot the secondary
> core(s).
>
> Thanks for clarifying.
>
> If a holdoff release is the right way to boot a secondary core for you,
> then I think the right place to do it is not smp_set_core_boot_addr()
> but smp_kick_all_cpus(), of which you could make a strong version which
> would do the holdoff release instead of whatever the weak version does.
>
Yes, I do think a strong version will be okay.
In file arch/arm/cpu/armv7/ls102xa/cpu.c, add the strong version:
+/* Release the secondary core from holdoff state and boot it */
+void smp_kick_all_cpus(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ out_be32(&gur->brrl, 0x2);
+}
+
Is this okay ?
I have test the holdoff release in two boards(including the old one before
I used) for 37 times and all has passed. I have a check the before failed logs,
It is another issue led to the failure. And also get confirmation that the
Holdoff release will do reset and then boot the secondary core.
Thanks,
BRs
Xiubo
> That is, unless you also need the weak version to run, in which case
> I /still/ think you should find a way for all of this to happen at the
> 'kick" stage (maybe with a .weakref in arch/arm/cpu/armv8/start.S, to
> give the weak smp_kick_all_cpus symbol another name that could be
> referred to by the strong version).
>
> > Thanks,
> >
> > BRs
> > Xiubo
>
> Amicalement,
> --
> Albert.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
2014-11-19 7:21 ` Li.Xiubo at freescale.com
@ 2014-11-20 12:06 ` Albert ARIBAUD
2014-11-21 1:55 ` Li.Xiubo at freescale.com
0 siblings, 1 reply; 22+ messages in thread
From: Albert ARIBAUD @ 2014-11-20 12:06 UTC (permalink / raw)
To: u-boot
Hello Li.Xiubo at freescale.com,
On Wed, 19 Nov 2014 07:21:26 +0000, Li.Xiubo at freescale.com
<Li.Xiubo@freescale.com> wrote:
> Hi Albert,
>
> > -----Original Message-----
> > From: Albert ARIBAUD [mailto:albert.u.boot at aribaud.net]
> > Sent: Tuesday, November 18, 2014 3:18 PM
> > To: Xiubo Li-B47053
> > Cc: Sun York-R58495; Jin Zhengxiong-R64188; u-boot at lists.denx.de
> > Subject: Re: [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
> >
> > Hello Li.Xiubo at freescale.com,
> >
> > On Tue, 18 Nov 2014 02:01:02 +0000, Li.Xiubo at freescale.com
> > <Li.Xiubo@freescale.com> wrote:
> > > Hi Albert,
> > >
> > >
> > > > > > > > > +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> > > > > > > > > +/* Setting the address at which secondary cores start from.*/
> > > > > > > > > +void smp_set_core_boot_addr(unsigned long addr, int corenr)
> > > > > > > > > +{
> > > > > > > > > + struct ccsr_gur __iomem *gur = (void
> > *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > > > > > > > > +
> > > > > > > > > + /*
> > > > > > > > > + * After setting the secondary cores start address,
> > > > > > > > > + * just release them to boot.
> > > > > > > > > + */
> > > > > > > > > + out_be32(&gur->scratchrw[0], addr);
> > > > > > > > > + out_be32(&gur->brrl, 0x2);
> > > > > > > > > +}
> > > > > > > >
> > > > > > > > This function does not exactly "[set] the address at which
> > secondary
> > > > > > > > cores start from"; it sets *a* secondary core's boot address, and
> > then
> > > > > > > > it *boots* it.
> > > > > > > >
> > > > > > >
> > > > > > > Okay, I will fix it later.
> > > > > > >
> > > > > > > > Why does this version of smp_set_core_boot_addr() need to boot the
> > > > core
> > > > > > > > in addition to setting the address, whereas the existing ones in
> > > > > > > > virt_v7, vexpress_common and arndale don't boot the cores?
> > > > > > > >
> > > > > > >
> > > > > > > Yes, they don't doing the release operation.
> > > > > > >
> > > > > > > For Low Power Management requirement, maybe only one core will be
> > used,
> > > > and
> > > > > > then
> > > > > > > We also make sure that the secondary core must be in low power and
> > deep
> > > > > > sleep
> > > > > > > mode(using wfi). So I just release it here, to make sure that the
> > wfi
> > > > > > instruction
> > > > > > > will be executed as early as possible.
> > > > > >
> > > > > > Right after smp_set_core_boot_addr() is called, kick_all_cpus()
> > isgoing
> > > > > > to be called. Wouldn't that boot your CPUs just as well?
> > > > > >
> > > > >
> > > > > Yes, it will.
> > > > >
> > > > > But before that we must do the holdoff bit set operation as the SoC's
> > > > requirement.
> > > > >
> > > > > The BRR contains control bits for enabling boot for each core. On
> > exiting
> > > > HRESET or
> > > > > PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to
> > be
> > > > released
> > > > > for booting or to remain in boot holdoff. All other cores remain in boot
> > > > holdoff until their
> > > > > corresponding bit is set.
> > > > >
> > > > > Maybe the comment is not very clear and a bit confusing.
> > > >
> > > > Before I'm lost entirely, do you mean that the comment:
> > > >
> > > > > > > > > + /*
> > > > > > > > > + * After setting the secondary cores start address,
> > > > > > > > > + * just release them to boot.
> > > > > > > > > + */
> > > >
> > > > Is actually wrong, and the instructions that follow it do not actually
> > > > boot the secondary core(s)?
> > > >
> > >
> > > The comment should be:
> > > /*
> > > * After setting the secondary core's start address,
> > > * just release it from holdoff.
> > > */
> > > From my tests, for most time the release instructions will boot the
> > secondary
> > > core(s) without smp_kick_all_cpus(). One time has failed.
> > >
> > > So I think the release can not make sure that it will boot the secondary
> > core(s).
> >
> > Thanks for clarifying.
> >
> > If a holdoff release is the right way to boot a secondary core for you,
> > then I think the right place to do it is not smp_set_core_boot_addr()
> > but smp_kick_all_cpus(), of which you could make a strong version which
> > would do the holdoff release instead of whatever the weak version does.
> >
>
> Yes, I do think a strong version will be okay.
>
> In file arch/arm/cpu/armv7/ls102xa/cpu.c, add the strong version:
>
> +/* Release the secondary core from holdoff state and boot it */
> +void smp_kick_all_cpus(void)
> +{
> + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> +
> + out_be32(&gur->brrl, 0x2);
> +}
> +
> Is this okay ?
Yes, thanks!
> I have test the holdoff release in two boards(including the old one before
> I used) for 37 times and all has passed. I have a check the before failed logs,
> It is another issue led to the failure. And also get confirmation that the
> Holdoff release will do reset and then boot the secondary core.
Good -- this makes smp_kick_all_cpus() the right home for holdoff
releast.
> Thanks,
Thank you for your patience. :)
> BRs
> Xiubo
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
2014-11-20 12:06 ` Albert ARIBAUD
@ 2014-11-21 1:55 ` Li.Xiubo at freescale.com
0 siblings, 0 replies; 22+ messages in thread
From: Li.Xiubo at freescale.com @ 2014-11-21 1:55 UTC (permalink / raw)
To: u-boot
Hi Albert,
If there hasn't any other problem, I will send out the V4 series.
Thanks very much,
BRs
Xiubo
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.u.boot at aribaud.net]
> Sent: Thursday, November 20, 2014 8:07 PM
> To: Xiubo Li-B47053
> Cc: Sun York-R58495; Jin Zhengxiong-R64188; u-boot at lists.denx.de
> Subject: Re: [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards
>
> Hello Li.Xiubo at freescale.com,
>
> On Wed, 19 Nov 2014 07:21:26 +0000, Li.Xiubo at freescale.com
> <Li.Xiubo@freescale.com> wrote:
> > Hi Albert,
> >
> > > -----Original Message-----
> > > From: Albert ARIBAUD [mailto:albert.u.boot at aribaud.net]
> > > Sent: Tuesday, November 18, 2014 3:18 PM
> > > To: Xiubo Li-B47053
> > > Cc: Sun York-R58495; Jin Zhengxiong-R64188; u-boot at lists.denx.de
> > > Subject: Re: [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa
> boards
> > >
> > > Hello Li.Xiubo at freescale.com,
> > >
> > > On Tue, 18 Nov 2014 02:01:02 +0000, Li.Xiubo at freescale.com
> > > <Li.Xiubo@freescale.com> wrote:
> > > > Hi Albert,
> > > >
> > > >
> > > > > > > > > > +#if defined(CONFIG_ARMV7_NONSEC) ||
> defined(CONFIG_ARMV7_VIRT)
> > > > > > > > > > +/* Setting the address at which secondary cores start
> from.*/
> > > > > > > > > > +void smp_set_core_boot_addr(unsigned long addr, int corenr)
> > > > > > > > > > +{
> > > > > > > > > > + struct ccsr_gur __iomem *gur = (void
> > > *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > > > > > > > > > +
> > > > > > > > > > + /*
> > > > > > > > > > + * After setting the secondary cores start address,
> > > > > > > > > > + * just release them to boot.
> > > > > > > > > > + */
> > > > > > > > > > + out_be32(&gur->scratchrw[0], addr);
> > > > > > > > > > + out_be32(&gur->brrl, 0x2);
> > > > > > > > > > +}
> > > > > > > > >
> > > > > > > > > This function does not exactly "[set] the address at which
> > > secondary
> > > > > > > > > cores start from"; it sets *a* secondary core's boot address,
> and
> > > then
> > > > > > > > > it *boots* it.
> > > > > > > > >
> > > > > > > >
> > > > > > > > Okay, I will fix it later.
> > > > > > > >
> > > > > > > > > Why does this version of smp_set_core_boot_addr() need to boot
> the
> > > > > core
> > > > > > > > > in addition to setting the address, whereas the existing ones
> in
> > > > > > > > > virt_v7, vexpress_common and arndale don't boot the cores?
> > > > > > > > >
> > > > > > > >
> > > > > > > > Yes, they don't doing the release operation.
> > > > > > > >
> > > > > > > > For Low Power Management requirement, maybe only one core will
> be
> > > used,
> > > > > and
> > > > > > > then
> > > > > > > > We also make sure that the secondary core must be in low power
> and
> > > deep
> > > > > > > sleep
> > > > > > > > mode(using wfi). So I just release it here, to make sure that
> the
> > > wfi
> > > > > > > instruction
> > > > > > > > will be executed as early as possible.
> > > > > > >
> > > > > > > Right after smp_set_core_boot_addr() is called, kick_all_cpus()
> > > isgoing
> > > > > > > to be called. Wouldn't that boot your CPUs just as well?
> > > > > > >
> > > > > >
> > > > > > Yes, it will.
> > > > > >
> > > > > > But before that we must do the holdoff bit set operation as the
> SoC's
> > > > > requirement.
> > > > > >
> > > > > > The BRR contains control bits for enabling boot for each core. On
> > > exiting
> > > > > HRESET or
> > > > > > PORESET, the RCW BOOT_HO field optionally allows for logical core 0
> to
> > > be
> > > > > released
> > > > > > for booting or to remain in boot holdoff. All other cores remain in
> boot
> > > > > holdoff until their
> > > > > > corresponding bit is set.
> > > > > >
> > > > > > Maybe the comment is not very clear and a bit confusing.
> > > > >
> > > > > Before I'm lost entirely, do you mean that the comment:
> > > > >
> > > > > > > > > > + /*
> > > > > > > > > > + * After setting the secondary cores start address,
> > > > > > > > > > + * just release them to boot.
> > > > > > > > > > + */
> > > > >
> > > > > Is actually wrong, and the instructions that follow it do not actually
> > > > > boot the secondary core(s)?
> > > > >
> > > >
> > > > The comment should be:
> > > > /*
> > > > * After setting the secondary core's start address,
> > > > * just release it from holdoff.
> > > > */
> > > > From my tests, for most time the release instructions will boot the
> > > secondary
> > > > core(s) without smp_kick_all_cpus(). One time has failed.
> > > >
> > > > So I think the release can not make sure that it will boot the secondary
> > > core(s).
> > >
> > > Thanks for clarifying.
> > >
> > > If a holdoff release is the right way to boot a secondary core for you,
> > > then I think the right place to do it is not smp_set_core_boot_addr()
> > > but smp_kick_all_cpus(), of which you could make a strong version which
> > > would do the holdoff release instead of whatever the weak version does.
> > >
> >
> > Yes, I do think a strong version will be okay.
> >
> > In file arch/arm/cpu/armv7/ls102xa/cpu.c, add the strong version:
> >
> > +/* Release the secondary core from holdoff state and boot it */
> > +void smp_kick_all_cpus(void)
> > +{
> > + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > +
> > + out_be32(&gur->brrl, 0x2);
> > +}
> > +
> > Is this okay ?
>
> Yes, thanks!
>
> > I have test the holdoff release in two boards(including the old one before
> > I used) for 37 times and all has passed. I have a check the before failed
> logs,
> > It is another issue led to the failure. And also get confirmation that the
> > Holdoff release will do reset and then boot the secondary core.
>
> Good -- this makes smp_kick_all_cpus() the right home for holdoff
> releast.
>
> > Thanks,
>
> Thank you for your patience. :)
>
> > BRs
> > Xiubo
>
> Amicalement,
> --
> Albert.
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2014-11-21 1:55 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-10-20 9:00 [U-Boot] [PATCH v3 0/5] ls102xa: HYP/non-sec: for ls102xa Xiubo Li
2014-10-20 9:00 ` [U-Boot] [PATCH v3 1/5] ARM: HYP/non-sec: add the pen address BE mode support Xiubo Li
2014-11-13 16:44 ` York Sun
2014-10-20 9:00 ` [U-Boot] [PATCH v3 2/5] ARM: HYP/non-sec: Fix the ARCH Timer frequency setting Xiubo Li
2014-11-13 16:44 ` York Sun
2014-10-20 9:00 ` [U-Boot] [PATCH v3 3/5] ls102xa: HYP/non-sec: support for ls102xa boards Xiubo Li
2014-11-13 16:44 ` York Sun
2014-11-14 7:49 ` Albert ARIBAUD
2014-11-14 9:06 ` Li.Xiubo at freescale.com
2014-11-14 11:44 ` Albert ARIBAUD
2014-11-17 2:16 ` Li.Xiubo at freescale.com
2014-11-17 13:04 ` Albert ARIBAUD
2014-11-18 2:01 ` Li.Xiubo at freescale.com
2014-11-18 7:18 ` Albert ARIBAUD
2014-11-19 7:21 ` Li.Xiubo at freescale.com
2014-11-20 12:06 ` Albert ARIBAUD
2014-11-21 1:55 ` Li.Xiubo at freescale.com
2014-10-20 9:00 ` [U-Boot] [PATCH v3 4/5] ARM: ls102xa: allow all the peripheral access permissions as R/W Xiubo Li
2014-11-13 16:45 ` York Sun
2014-10-20 9:00 ` [U-Boot] [PATCH v3 5/5] ARM: ls102xa: Setting device's stream id for SMMUs Xiubo Li
2014-11-13 16:45 ` York Sun
2014-11-13 6:15 ` [U-Boot] [PATCH v3 0/5] ls102xa: HYP/non-sec: for ls102xa Albert ARIBAUD
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