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* [U-Boot] [PATCH v2 0/6] dm: Introduce driver model for sunxi
@ 2014-10-23  4:02 Simon Glass
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 1/6] dm: sunxi: dts: Add sun7i device tree files Simon Glass
                   ` (5 more replies)
  0 siblings, 6 replies; 37+ messages in thread
From: Simon Glass @ 2014-10-23  4:02 UTC (permalink / raw)
  To: u-boot

This series adds driver model support for serial and GPIO for sunxi. Since
I only have a sun7i board to test with, I have added a new config for the
pcDuino3, which uses device tree and driver model. This should make it
fairly easy to enable for the other boards at some point.

This series is available at u-boot-dm/sunix-working. Note that it depends
on the patches which move GPIO request/free to the GPIO uclass.

Changes in v2:
- Remove references to exynos and tegra
- Use the word 'bank' instead of 'port'
- Split non-sunxi patches into a separate dependent series

Simon Glass (6):
  dm: sunxi: dts: Add sun7i device tree files
  dm: sunxi: Add a new config for an FDT-based pcDuino3
  dm: sunxi: Add pinmux functions which take a bank parameter
  dm: sunxi: Make sure that GPIOs are requested
  dm: sunxi: Modify the GPIO driver to support driver model
  dm: sunxi: Add support for serial using driver model

 Makefile                                  |   3 +-
 arch/arm/cpu/armv7/sunxi/pinmux.c         |  32 +-
 arch/arm/dts/Makefile                     |   1 +
 arch/arm/dts/sun7i-a20-pcduino3.dts       | 177 ++++++
 arch/arm/dts/sun7i-a20.dtsi               | 988 ++++++++++++++++++++++++++++++
 arch/arm/dts/sunxi-common-regulators.dtsi |  89 +++
 arch/arm/include/asm/arch-sunxi/gpio.h    |   4 +-
 board/sunxi/MAINTAINERS                   |   1 +
 board/sunxi/ahci.c                        |   1 +
 configs/Linksprite_pcDuino3_fdt_defconfig |   8 +
 drivers/gpio/sunxi_gpio.c                 | 170 +++++
 drivers/serial/Makefile                   |   1 +
 drivers/serial/serial_dw.c                |  39 ++
 include/configs/sun7i.h                   |   8 +
 include/configs/sunxi-common.h            |  12 +-
 include/dt-bindings/input/input.h         | 525 ++++++++++++++++
 16 files changed, 2041 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm/dts/sun7i-a20-pcduino3.dts
 create mode 100644 arch/arm/dts/sun7i-a20.dtsi
 create mode 100644 arch/arm/dts/sunxi-common-regulators.dtsi
 create mode 100644 configs/Linksprite_pcDuino3_fdt_defconfig
 create mode 100644 drivers/serial/serial_dw.c
 create mode 100644 include/dt-bindings/input/input.h

-- 
2.1.0.rc2.206.gedb03e5

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 1/6] dm: sunxi: dts: Add sun7i device tree files
  2014-10-23  4:02 [U-Boot] [PATCH v2 0/6] dm: Introduce driver model for sunxi Simon Glass
@ 2014-10-23  4:02 ` Simon Glass
  2014-10-24  8:32   ` [U-Boot] [U-Boot, v2, " Hans de Goede
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 2/6] dm: sunxi: Add a new config for an FDT-based pcDuino3 Simon Glass
                   ` (4 subsequent siblings)
  5 siblings, 1 reply; 37+ messages in thread
From: Simon Glass @ 2014-10-23  4:02 UTC (permalink / raw)
  To: u-boot

These are from Linux 3.17-rc7 (commit fe82dcec). U-Boot only uses a small
portion of these, but we may as well have something to look forward to.

The total compiled size is about 25KB.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/arm/dts/sun7i-a20-pcduino3.dts       | 173 ++++++
 arch/arm/dts/sun7i-a20.dtsi               | 988 ++++++++++++++++++++++++++++++
 arch/arm/dts/sunxi-common-regulators.dtsi |  89 +++
 include/dt-bindings/input/input.h         | 525 ++++++++++++++++
 4 files changed, 1775 insertions(+)
 create mode 100644 arch/arm/dts/sun7i-a20-pcduino3.dts
 create mode 100644 arch/arm/dts/sun7i-a20.dtsi
 create mode 100644 arch/arm/dts/sunxi-common-regulators.dtsi
 create mode 100644 include/dt-bindings/input/input.h

diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts
new file mode 100644
index 0000000..046dfc0
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-pcduino3.dts
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2014 Zoltan HERPAI
+ * Zoltan HERPAI <wigyori@uid0.hu>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "LinkSprite pcDuino3";
+	compatible = "linksprite,pcduino3", "allwinner,sun7i-a20";
+
+	soc at 01c00000 {
+		mmc0: mmc at 01c0f000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+			vmmc-supply = <&reg_vcc3v3>;
+			bus-width = <4>;
+			cd-gpios = <&pio 7 1 0>; /* PH1 */
+			cd-inverted;
+			status = "okay";
+		};
+
+		usbphy: phy at 01c13400 {
+			usb1_vbus-supply = <&reg_usb1_vbus>;
+			usb2_vbus-supply = <&reg_usb2_vbus>;
+			status = "okay";
+		};
+
+		ehci0: usb at 01c14000 {
+			status = "okay";
+		};
+
+		ohci0: usb at 01c14400 {
+			status = "okay";
+		};
+
+		ahci: sata at 01c18000 {
+			target-supply = <&reg_ahci_5v>;
+			status = "okay";
+		};
+
+		ehci1: usb at 01c1c000 {
+			status = "okay";
+		};
+
+		ohci1: usb at 01c1c400 {
+			status = "okay";
+		};
+
+		pinctrl at 01c20800 {
+			ahci_pwr_pin_a: ahci_pwr_pin at 0 {
+				allwinner,pins = "PH2";
+			};
+
+			led_pins_pcduino3: led_pins at 0 {
+				allwinner,pins = "PH15", "PH16";
+				allwinner,function = "gpio_out";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			key_pins_pcduino3: key_pins at 0 {
+				allwinner,pins = "PH17", "PH18", "PH19";
+				allwinner,function = "gpio_in";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+		};
+
+		ir0: ir at 01c21800 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&ir0_pins_a>;
+			status = "okay";
+		};
+
+		uart0: serial at 01c28000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_pins_a>;
+			status = "okay";
+		};
+
+		i2c0: i2c at 01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			status = "okay";
+
+			axp209: pmic at 34 {
+				compatible = "x-powers,axp209";
+				reg = <0x34>;
+				interrupt-parent = <&nmi_intc>;
+				interrupts = <0 8>;
+
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		gmac: ethernet at 01c50000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&gmac_pins_mii_a>;
+			phy = <&phy1>;
+			phy-mode = "mii";
+			status = "okay";
+
+			phy1: ethernet-phy at 1 {
+				reg = <1>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins_pcduino3>;
+
+		tx {
+			label = "pcduino3:green:tx";
+			gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
+		};
+
+		rx {
+			label = "pcduino3:green:rx";
+			gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_pins_pcduino3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		button at 0 {
+			label = "Key Back";
+			linux,code = <KEY_BACK>;
+			gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
+		};
+		button at 1 {
+			label = "Key Home";
+			linux,code = <KEY_HOME>;
+			gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
+		};
+		button at 2 {
+			label = "Key Menu";
+			linux,code = <KEY_MENU>;
+			gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	reg_usb1_vbus: usb1-vbus {
+		status = "okay";
+	};
+
+	reg_usb2_vbus: usb2-vbus {
+		status = "okay";
+	};
+
+	reg_ahci_5v: ahci-5v {
+		gpio = <&pio 7 2 0>;
+		status = "okay";
+	};
+};
diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi
new file mode 100644
index 0000000..4011628
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20.dtsi
@@ -0,0 +1,988 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&gic>;
+
+	aliases {
+		ethernet0 = &gmac;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		serial6 = &uart6;
+		serial7 = &uart7;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu at 1 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+
+	memory {
+		reg = <0x40000000 0x80000000>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <1 13 0xf08>,
+			     <1 14 0xf08>,
+			     <1 11 0xf08>,
+			     <1 10 0xf08>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+		interrupts = <0 120 4>,
+			     <0 121 4>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc24M: clk at 01c20050 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-osc-clk";
+			reg = <0x01c20050 0x4>;
+			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
+		};
+
+		osc32k: clk at 0 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
+		};
+
+		pll1: clk at 01c20000 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-pll1-clk";
+			reg = <0x01c20000 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll1";
+		};
+
+		pll4: clk at 01c20018 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-pll4-clk";
+			reg = <0x01c20018 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll4";
+		};
+
+		pll5: clk at 01c20020 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-pll5-clk";
+			reg = <0x01c20020 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll5_ddr", "pll5_other";
+		};
+
+		pll6: clk at 01c20028 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-pll6-clk";
+			reg = <0x01c20028 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll6_sata", "pll6_other", "pll6";
+		};
+
+		pll8: clk at 01c20040 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-pll4-clk";
+			reg = <0x01c20040 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll8";
+		};
+
+		cpu: cpu at 01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-cpu-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
+			clock-output-names = "cpu";
+		};
+
+		axi: axi at 01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-axi-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&cpu>;
+			clock-output-names = "axi";
+		};
+
+		ahb: ahb at 01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-ahb-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&axi>;
+			clock-output-names = "ahb";
+		};
+
+		ahb_gates: clk at 01c20060 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun7i-a20-ahb-gates-clk";
+			reg = <0x01c20060 0x8>;
+			clocks = <&ahb>;
+			clock-output-names = "ahb_usb0", "ahb_ehci0",
+				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
+				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+				"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+				"ahb_nand", "ahb_sdram", "ahb_ace",
+				"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+				"ahb_spi2", "ahb_spi3", "ahb_sata",
+				"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
+				"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
+				"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
+				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+				"ahb_de_fe1", "ahb_gmac", "ahb_mp",
+				"ahb_mali";
+		};
+
+		apb0: apb0 at 01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb0-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&ahb>;
+			clock-output-names = "apb0";
+		};
+
+		apb0_gates: clk at 01c20068 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun7i-a20-apb0-gates-clk";
+			reg = <0x01c20068 0x4>;
+			clocks = <&apb0>;
+			clock-output-names = "apb0_codec", "apb0_spdif",
+				"apb0_ac97", "apb0_iis0", "apb0_iis1",
+				"apb0_pio", "apb0_ir0", "apb0_ir1",
+				"apb0_iis2", "apb0_keypad";
+		};
+
+		apb1_mux: apb1_mux at 01c20058 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb1-mux-clk";
+			reg = <0x01c20058 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+			clock-output-names = "apb1_mux";
+		};
+
+		apb1: apb1 at 01c20058 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb1-clk";
+			reg = <0x01c20058 0x4>;
+			clocks = <&apb1_mux>;
+			clock-output-names = "apb1";
+		};
+
+		apb1_gates: clk at 01c2006c {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun7i-a20-apb1-gates-clk";
+			reg = <0x01c2006c 0x4>;
+			clocks = <&apb1>;
+			clock-output-names = "apb1_i2c0", "apb1_i2c1",
+				"apb1_i2c2", "apb1_i2c3", "apb1_can",
+				"apb1_scr", "apb1_ps20", "apb1_ps21",
+				"apb1_i2c4", "apb1_uart0", "apb1_uart1",
+				"apb1_uart2", "apb1_uart3", "apb1_uart4",
+				"apb1_uart5", "apb1_uart6", "apb1_uart7";
+		};
+
+		nand_clk: clk at 01c20080 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20080 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "nand";
+		};
+
+		ms_clk: clk at 01c20084 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20084 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ms";
+		};
+
+		mmc0_clk: clk at 01c20088 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20088 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "mmc0";
+		};
+
+		mmc1_clk: clk at 01c2008c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c2008c 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "mmc1";
+		};
+
+		mmc2_clk: clk at 01c20090 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20090 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "mmc2";
+		};
+
+		mmc3_clk: clk at 01c20094 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20094 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "mmc3";
+		};
+
+		ts_clk: clk at 01c20098 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20098 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ts";
+		};
+
+		ss_clk: clk at 01c2009c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c2009c 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ss";
+		};
+
+		spi0_clk: clk at 01c200a0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200a0 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "spi0";
+		};
+
+		spi1_clk: clk at 01c200a4 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200a4 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "spi1";
+		};
+
+		spi2_clk: clk at 01c200a8 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200a8 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "spi2";
+		};
+
+		pata_clk: clk at 01c200ac {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200ac 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "pata";
+		};
+
+		ir0_clk: clk at 01c200b0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200b0 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ir0";
+		};
+
+		ir1_clk: clk at 01c200b4 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200b4 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ir1";
+		};
+
+		usb_clk: clk at 01c200cc {
+			#clock-cells = <1>;
+		        #reset-cells = <1>;
+			compatible = "allwinner,sun4i-a10-usb-clk";
+			reg = <0x01c200cc 0x4>;
+			clocks = <&pll6 1>;
+			clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
+		};
+
+		spi3_clk: clk at 01c200d4 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200d4 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "spi3";
+		};
+
+		mbus_clk: clk at 01c2015c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c2015c 0x4>;
+			clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
+			clock-output-names = "mbus";
+		};
+
+		/*
+		 * The following two are dummy clocks, placeholders used in the gmac_tx
+		 * clock. The gmac driver will choose one parent depending on the PHY
+		 * interface mode, using clk_set_rate auto-reparenting.
+		 * The actual TX clock rate is not controlled by the gmac_tx clock.
+		 */
+		mii_phy_tx_clk: clk at 2 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+			clock-output-names = "mii_phy_tx";
+		};
+
+		gmac_int_tx_clk: clk at 3 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <125000000>;
+			clock-output-names = "gmac_int_tx";
+		};
+
+		gmac_tx_clk: clk at 01c20164 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-gmac-clk";
+			reg = <0x01c20164 0x4>;
+			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+			clock-output-names = "gmac_tx";
+		};
+
+		/*
+		 * Dummy clock used by output clocks
+		 */
+		osc24M_32k: clk at 1 {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <750>;
+			clock-mult = <1>;
+			clocks = <&osc24M>;
+			clock-output-names = "osc24M_32k";
+		};
+
+		clk_out_a: clk at 01c201f0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-out-clk";
+			reg = <0x01c201f0 0x4>;
+			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+			clock-output-names = "clk_out_a";
+		};
+
+		clk_out_b: clk at 01c201f4 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-out-clk";
+			reg = <0x01c201f4 0x4>;
+			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+			clock-output-names = "clk_out_b";
+		};
+	};
+
+	soc at 01c00000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		nmi_intc: interrupt-controller at 01c00030 {
+			compatible = "allwinner,sun7i-a20-sc-nmi";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01c00030 0x0c>;
+			interrupts = <0 0 4>;
+		};
+
+		spi0: spi at 01c05000 {
+			compatible = "allwinner,sun4i-a10-spi";
+			reg = <0x01c05000 0x1000>;
+			interrupts = <0 10 4>;
+			clocks = <&ahb_gates 20>, <&spi0_clk>;
+			clock-names = "ahb", "mod";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi at 01c06000 {
+			compatible = "allwinner,sun4i-a10-spi";
+			reg = <0x01c06000 0x1000>;
+			interrupts = <0 11 4>;
+			clocks = <&ahb_gates 21>, <&spi1_clk>;
+			clock-names = "ahb", "mod";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		emac: ethernet at 01c0b000 {
+			compatible = "allwinner,sun4i-a10-emac";
+			reg = <0x01c0b000 0x1000>;
+			interrupts = <0 55 4>;
+			clocks = <&ahb_gates 17>;
+			status = "disabled";
+		};
+
+		mdio at 01c0b080 {
+			compatible = "allwinner,sun4i-a10-mdio";
+			reg = <0x01c0b080 0x14>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc0: mmc at 01c0f000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&ahb_gates 8>, <&mmc0_clk>;
+			clock-names = "ahb", "mmc";
+			interrupts = <0 32 4>;
+			status = "disabled";
+		};
+
+		mmc1: mmc at 01c10000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c10000 0x1000>;
+			clocks = <&ahb_gates 9>, <&mmc1_clk>;
+			clock-names = "ahb", "mmc";
+			interrupts = <0 33 4>;
+			status = "disabled";
+		};
+
+		mmc2: mmc at 01c11000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c11000 0x1000>;
+			clocks = <&ahb_gates 10>, <&mmc2_clk>;
+			clock-names = "ahb", "mmc";
+			interrupts = <0 34 4>;
+			status = "disabled";
+		};
+
+		mmc3: mmc at 01c12000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c12000 0x1000>;
+			clocks = <&ahb_gates 11>, <&mmc3_clk>;
+			clock-names = "ahb", "mmc";
+			interrupts = <0 35 4>;
+			status = "disabled";
+		};
+
+		usbphy: phy at 01c13400 {
+			#phy-cells = <1>;
+			compatible = "allwinner,sun7i-a20-usb-phy";
+			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+			reg-names = "phy_ctrl", "pmu1", "pmu2";
+			clocks = <&usb_clk 8>;
+			clock-names = "usb_phy";
+			resets = <&usb_clk 1>, <&usb_clk 2>;
+			reset-names = "usb1_reset", "usb2_reset";
+			status = "disabled";
+		};
+
+		ehci0: usb at 01c14000 {
+			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
+			reg = <0x01c14000 0x100>;
+			interrupts = <0 39 4>;
+			clocks = <&ahb_gates 1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci0: usb at 01c14400 {
+			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
+			reg = <0x01c14400 0x100>;
+			interrupts = <0 64 4>;
+			clocks = <&usb_clk 6>, <&ahb_gates 2>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		spi2: spi at 01c17000 {
+			compatible = "allwinner,sun4i-a10-spi";
+			reg = <0x01c17000 0x1000>;
+			interrupts = <0 12 4>;
+			clocks = <&ahb_gates 22>, <&spi2_clk>;
+			clock-names = "ahb", "mod";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		ahci: sata at 01c18000 {
+			compatible = "allwinner,sun4i-a10-ahci";
+			reg = <0x01c18000 0x1000>;
+			interrupts = <0 56 4>;
+			clocks = <&pll6 0>, <&ahb_gates 25>;
+			status = "disabled";
+		};
+
+		ehci1: usb at 01c1c000 {
+			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
+			reg = <0x01c1c000 0x100>;
+			interrupts = <0 40 4>;
+			clocks = <&ahb_gates 3>;
+			phys = <&usbphy 2>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci1: usb at 01c1c400 {
+			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
+			reg = <0x01c1c400 0x100>;
+			interrupts = <0 65 4>;
+			clocks = <&usb_clk 7>, <&ahb_gates 4>;
+			phys = <&usbphy 2>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		spi3: spi at 01c1f000 {
+			compatible = "allwinner,sun4i-a10-spi";
+			reg = <0x01c1f000 0x1000>;
+			interrupts = <0 50 4>;
+			clocks = <&ahb_gates 23>, <&spi3_clk>;
+			clock-names = "ahb", "mod";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		pio: pinctrl at 01c20800 {
+			compatible = "allwinner,sun7i-a20-pinctrl";
+			reg = <0x01c20800 0x400>;
+			interrupts = <0 28 4>;
+			clocks = <&apb0_gates 5>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			#size-cells = <0>;
+			#gpio-cells = <3>;
+
+			pwm0_pins_a: pwm0 at 0 {
+				allwinner,pins = "PB2";
+				allwinner,function = "pwm";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			pwm1_pins_a: pwm1 at 0 {
+				allwinner,pins = "PI3";
+				allwinner,function = "pwm";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			uart0_pins_a: uart0 at 0 {
+				allwinner,pins = "PB22", "PB23";
+				allwinner,function = "uart0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			uart2_pins_a: uart2 at 0 {
+				allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+				allwinner,function = "uart2";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			uart6_pins_a: uart6 at 0 {
+				allwinner,pins = "PI12", "PI13";
+				allwinner,function = "uart6";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			uart7_pins_a: uart7 at 0 {
+				allwinner,pins = "PI20", "PI21";
+				allwinner,function = "uart7";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			i2c0_pins_a: i2c0 at 0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			i2c1_pins_a: i2c1 at 0 {
+				allwinner,pins = "PB18", "PB19";
+				allwinner,function = "i2c1";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			i2c2_pins_a: i2c2 at 0 {
+				allwinner,pins = "PB20", "PB21";
+				allwinner,function = "i2c2";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			emac_pins_a: emac0 at 0 {
+				allwinner,pins = "PA0", "PA1", "PA2",
+						"PA3", "PA4", "PA5", "PA6",
+						"PA7", "PA8", "PA9", "PA10",
+						"PA11", "PA12", "PA13", "PA14",
+						"PA15", "PA16";
+				allwinner,function = "emac";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			clk_out_a_pins_a: clk_out_a at 0 {
+				allwinner,pins = "PI12";
+				allwinner,function = "clk_out_a";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			clk_out_b_pins_a: clk_out_b at 0 {
+				allwinner,pins = "PI13";
+				allwinner,function = "clk_out_b";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			gmac_pins_mii_a: gmac_mii at 0 {
+				allwinner,pins = "PA0", "PA1", "PA2",
+						"PA3", "PA4", "PA5", "PA6",
+						"PA7", "PA8", "PA9", "PA10",
+						"PA11", "PA12", "PA13", "PA14",
+						"PA15", "PA16";
+				allwinner,function = "gmac";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			gmac_pins_rgmii_a: gmac_rgmii at 0 {
+				allwinner,pins = "PA0", "PA1", "PA2",
+						"PA3", "PA4", "PA5", "PA6",
+						"PA7", "PA8", "PA10",
+						"PA11", "PA12", "PA13",
+						"PA15", "PA16";
+				allwinner,function = "gmac";
+				/*
+				 * data lines in RGMII mode use DDR mode
+				 * and need a higher signal drive strength
+				 */
+				allwinner,drive = <3>;
+				allwinner,pull = <0>;
+			};
+
+			spi1_pins_a: spi1 at 0 {
+				allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+				allwinner,function = "spi1";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			spi2_pins_a: spi2 at 0 {
+				allwinner,pins = "PC19", "PC20", "PC21", "PC22";
+				allwinner,function = "spi2";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			mmc0_pins_a: mmc0 at 0 {
+				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+				allwinner,function = "mmc0";
+				allwinner,drive = <2>;
+				allwinner,pull = <0>;
+			};
+
+			mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
+				allwinner,pins = "PH1";
+				allwinner,function = "gpio_in";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			mmc3_pins_a: mmc3 at 0 {
+				allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
+				allwinner,function = "mmc3";
+				allwinner,drive = <2>;
+				allwinner,pull = <0>;
+			};
+
+			ir0_pins_a: ir0 at 0 {
+				    allwinner,pins = "PB3","PB4";
+				    allwinner,function = "ir0";
+				    allwinner,drive = <0>;
+				    allwinner,pull = <0>;
+			};
+
+			ir1_pins_a: ir1 at 0 {
+				    allwinner,pins = "PB22","PB23";
+				    allwinner,function = "ir1";
+				    allwinner,drive = <0>;
+				    allwinner,pull = <0>;
+			};
+		};
+
+		timer at 01c20c00 {
+			compatible = "allwinner,sun4i-a10-timer";
+			reg = <0x01c20c00 0x90>;
+			interrupts = <0 22 4>,
+				     <0 23 4>,
+				     <0 24 4>,
+				     <0 25 4>,
+				     <0 67 4>,
+				     <0 68 4>;
+			clocks = <&osc24M>;
+		};
+
+		wdt: watchdog at 01c20c90 {
+			compatible = "allwinner,sun4i-a10-wdt";
+			reg = <0x01c20c90 0x10>;
+		};
+
+		rtc: rtc at 01c20d00 {
+			compatible = "allwinner,sun7i-a20-rtc";
+			reg = <0x01c20d00 0x20>;
+			interrupts = <0 24 4>;
+		};
+
+		pwm: pwm at 01c20e00 {
+			compatible = "allwinner,sun7i-a20-pwm";
+			reg = <0x01c20e00 0xc>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		ir0: ir at 01c21800 {
+			compatible = "allwinner,sun4i-a10-ir";
+			clocks = <&apb0_gates 6>, <&ir0_clk>;
+			clock-names = "apb", "ir";
+			interrupts = <0 5 4>;
+			reg = <0x01c21800 0x40>;
+			status = "disabled";
+		};
+
+		ir1: ir at 01c21c00 {
+			compatible = "allwinner,sun4i-a10-ir";
+			clocks = <&apb0_gates 7>, <&ir1_clk>;
+			clock-names = "apb", "ir";
+			interrupts = <0 6 4>;
+			reg = <0x01c21c00 0x40>;
+			status = "disabled";
+		};
+
+		sid: eeprom at 01c23800 {
+			compatible = "allwinner,sun7i-a20-sid";
+			reg = <0x01c23800 0x200>;
+		};
+
+		rtp: rtp at 01c25000 {
+			compatible = "allwinner,sun4i-a10-ts";
+			reg = <0x01c25000 0x100>;
+			interrupts = <0 29 4>;
+		};
+
+		uart0: serial at 01c28000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28000 0x400>;
+			interrupts = <0 1 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 16>;
+			status = "disabled";
+		};
+
+		uart1: serial at 01c28400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28400 0x400>;
+			interrupts = <0 2 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 17>;
+			status = "disabled";
+		};
+
+		uart2: serial at 01c28800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28800 0x400>;
+			interrupts = <0 3 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 18>;
+			status = "disabled";
+		};
+
+		uart3: serial at 01c28c00 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28c00 0x400>;
+			interrupts = <0 4 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 19>;
+			status = "disabled";
+		};
+
+		uart4: serial at 01c29000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29000 0x400>;
+			interrupts = <0 17 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 20>;
+			status = "disabled";
+		};
+
+		uart5: serial at 01c29400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29400 0x400>;
+			interrupts = <0 18 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 21>;
+			status = "disabled";
+		};
+
+		uart6: serial at 01c29800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29800 0x400>;
+			interrupts = <0 19 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 22>;
+			status = "disabled";
+		};
+
+		uart7: serial at 01c29c00 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29c00 0x400>;
+			interrupts = <0 20 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 23>;
+			status = "disabled";
+		};
+
+		i2c0: i2c at 01c2ac00 {
+			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <0 7 4>;
+			clocks = <&apb1_gates 0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c at 01c2b000 {
+			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <0 8 4>;
+			clocks = <&apb1_gates 1>;
+			clock-frequency = <100000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c at 01c2b400 {
+			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <0 9 4>;
+			clocks = <&apb1_gates 2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c at 01c2b800 {
+			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2b800 0x400>;
+			interrupts = <0 88 4>;
+			clocks = <&apb1_gates 3>;
+			clock-frequency = <100000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c at 01c2c000 {
+			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2c000 0x400>;
+			interrupts = <0 89 4>;
+			clocks = <&apb1_gates 15>;
+			clock-frequency = <100000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		gmac: ethernet at 01c50000 {
+			compatible = "allwinner,sun7i-a20-gmac";
+			reg = <0x01c50000 0x10000>;
+			interrupts = <0 85 4>;
+			interrupt-names = "macirq";
+			clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
+			clock-names = "stmmaceth", "allwinner_gmac_tx";
+			snps,pbl = <2>;
+			snps,fixed-burst;
+			snps,force_sf_dma_mode;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		hstimer at 01c60000 {
+			compatible = "allwinner,sun7i-a20-hstimer";
+			reg = <0x01c60000 0x1000>;
+			interrupts = <0 81 4>,
+				     <0 82 4>,
+				     <0 83 4>,
+				     <0 84 4>;
+			clocks = <&ahb_gates 28>;
+		};
+
+		gic: interrupt-controller at 01c81000 {
+			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+			reg = <0x01c81000 0x1000>,
+			      <0x01c82000 0x1000>,
+			      <0x01c84000 0x2000>,
+			      <0x01c86000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <1 9 0xf04>;
+		};
+	};
+};
diff --git a/arch/arm/dts/sunxi-common-regulators.dtsi b/arch/arm/dts/sunxi-common-regulators.dtsi
new file mode 100644
index 0000000..3d021ef
--- /dev/null
+++ b/arch/arm/dts/sunxi-common-regulators.dtsi
@@ -0,0 +1,89 @@
+/*
+ * sunxi boards common regulator (ahci target power supply, usb-vbus) code
+ *
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+	soc at 01c00000 {
+		pio: pinctrl at 01c20800 {
+			ahci_pwr_pin_a: ahci_pwr_pin at 0 {
+				allwinner,pins = "PB8";
+				allwinner,function = "gpio_out";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			usb1_vbus_pin_a: usb1_vbus_pin at 0 {
+				allwinner,pins = "PH6";
+				allwinner,function = "gpio_out";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			usb2_vbus_pin_a: usb2_vbus_pin at 0 {
+				allwinner,pins = "PH3";
+				allwinner,function = "gpio_out";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+		};
+	};
+
+	reg_ahci_5v: ahci-5v {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&ahci_pwr_pin_a>;
+		regulator-name = "ahci-5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&pio 1 8 0>;
+		status = "disabled";
+	};
+
+	reg_usb1_vbus: usb1-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb1_vbus_pin_a>;
+		regulator-name = "usb1-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&pio 7 6 0>;
+		status = "disabled";
+	};
+
+	reg_usb2_vbus: usb2-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb2_vbus_pin_a>;
+		regulator-name = "usb2-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&pio 7 3 0>;
+		status = "disabled";
+	};
+
+	reg_vcc3v0: vcc3v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v0";
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
diff --git a/include/dt-bindings/input/input.h b/include/dt-bindings/input/input.h
new file mode 100644
index 0000000..042e7b3
--- /dev/null
+++ b/include/dt-bindings/input/input.h
@@ -0,0 +1,525 @@
+/*
+ * This header provides constants for most input bindings.
+ *
+ * Most input bindings include key code, matrix key code format.
+ * In most cases, key code and matrix key code format uses
+ * the standard values/macro defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INPUT_INPUT_H
+#define _DT_BINDINGS_INPUT_INPUT_H
+
+#define KEY_RESERVED		0
+#define KEY_ESC			1
+#define KEY_1			2
+#define KEY_2			3
+#define KEY_3			4
+#define KEY_4			5
+#define KEY_5			6
+#define KEY_6			7
+#define KEY_7			8
+#define KEY_8			9
+#define KEY_9			10
+#define KEY_0			11
+#define KEY_MINUS		12
+#define KEY_EQUAL		13
+#define KEY_BACKSPACE		14
+#define KEY_TAB			15
+#define KEY_Q			16
+#define KEY_W			17
+#define KEY_E			18
+#define KEY_R			19
+#define KEY_T			20
+#define KEY_Y			21
+#define KEY_U			22
+#define KEY_I			23
+#define KEY_O			24
+#define KEY_P			25
+#define KEY_LEFTBRACE		26
+#define KEY_RIGHTBRACE		27
+#define KEY_ENTER		28
+#define KEY_LEFTCTRL		29
+#define KEY_A			30
+#define KEY_S			31
+#define KEY_D			32
+#define KEY_F			33
+#define KEY_G			34
+#define KEY_H			35
+#define KEY_J			36
+#define KEY_K			37
+#define KEY_L			38
+#define KEY_SEMICOLON		39
+#define KEY_APOSTROPHE		40
+#define KEY_GRAVE		41
+#define KEY_LEFTSHIFT		42
+#define KEY_BACKSLASH		43
+#define KEY_Z			44
+#define KEY_X			45
+#define KEY_C			46
+#define KEY_V			47
+#define KEY_B			48
+#define KEY_N			49
+#define KEY_M			50
+#define KEY_COMMA		51
+#define KEY_DOT			52
+#define KEY_SLASH		53
+#define KEY_RIGHTSHIFT		54
+#define KEY_KPASTERISK		55
+#define KEY_LEFTALT		56
+#define KEY_SPACE		57
+#define KEY_CAPSLOCK		58
+#define KEY_F1			59
+#define KEY_F2			60
+#define KEY_F3			61
+#define KEY_F4			62
+#define KEY_F5			63
+#define KEY_F6			64
+#define KEY_F7			65
+#define KEY_F8			66
+#define KEY_F9			67
+#define KEY_F10			68
+#define KEY_NUMLOCK		69
+#define KEY_SCROLLLOCK		70
+#define KEY_KP7			71
+#define KEY_KP8			72
+#define KEY_KP9			73
+#define KEY_KPMINUS		74
+#define KEY_KP4			75
+#define KEY_KP5			76
+#define KEY_KP6			77
+#define KEY_KPPLUS		78
+#define KEY_KP1			79
+#define KEY_KP2			80
+#define KEY_KP3			81
+#define KEY_KP0			82
+#define KEY_KPDOT		83
+
+#define KEY_ZENKAKUHANKAKU	85
+#define KEY_102ND		86
+#define KEY_F11			87
+#define KEY_F12			88
+#define KEY_RO			89
+#define KEY_KATAKANA		90
+#define KEY_HIRAGANA		91
+#define KEY_HENKAN		92
+#define KEY_KATAKANAHIRAGANA	93
+#define KEY_MUHENKAN		94
+#define KEY_KPJPCOMMA		95
+#define KEY_KPENTER		96
+#define KEY_RIGHTCTRL		97
+#define KEY_KPSLASH		98
+#define KEY_SYSRQ		99
+#define KEY_RIGHTALT		100
+#define KEY_LINEFEED		101
+#define KEY_HOME		102
+#define KEY_UP			103
+#define KEY_PAGEUP		104
+#define KEY_LEFT		105
+#define KEY_RIGHT		106
+#define KEY_END			107
+#define KEY_DOWN		108
+#define KEY_PAGEDOWN		109
+#define KEY_INSERT		110
+#define KEY_DELETE		111
+#define KEY_MACRO		112
+#define KEY_MUTE		113
+#define KEY_VOLUMEDOWN		114
+#define KEY_VOLUMEUP		115
+#define KEY_POWER		116	/* SC System Power Down */
+#define KEY_KPEQUAL		117
+#define KEY_KPPLUSMINUS		118
+#define KEY_PAUSE		119
+#define KEY_SCALE		120	/* AL Compiz Scale (Expose) */
+
+#define KEY_KPCOMMA		121
+#define KEY_HANGEUL		122
+#define KEY_HANGUEL		KEY_HANGEUL
+#define KEY_HANJA		123
+#define KEY_YEN			124
+#define KEY_LEFTMETA		125
+#define KEY_RIGHTMETA		126
+#define KEY_COMPOSE		127
+
+#define KEY_STOP		128	/* AC Stop */
+#define KEY_AGAIN		129
+#define KEY_PROPS		130	/* AC Properties */
+#define KEY_UNDO		131	/* AC Undo */
+#define KEY_FRONT		132
+#define KEY_COPY		133	/* AC Copy */
+#define KEY_OPEN		134	/* AC Open */
+#define KEY_PASTE		135	/* AC Paste */
+#define KEY_FIND		136	/* AC Search */
+#define KEY_CUT			137	/* AC Cut */
+#define KEY_HELP		138	/* AL Integrated Help Center */
+#define KEY_MENU		139	/* Menu (show menu) */
+#define KEY_CALC		140	/* AL Calculator */
+#define KEY_SETUP		141
+#define KEY_SLEEP		142	/* SC System Sleep */
+#define KEY_WAKEUP		143	/* System Wake Up */
+#define KEY_FILE		144	/* AL Local Machine Browser */
+#define KEY_SENDFILE		145
+#define KEY_DELETEFILE		146
+#define KEY_XFER		147
+#define KEY_PROG1		148
+#define KEY_PROG2		149
+#define KEY_WWW			150	/* AL Internet Browser */
+#define KEY_MSDOS		151
+#define KEY_COFFEE		152	/* AL Terminal Lock/Screensaver */
+#define KEY_SCREENLOCK		KEY_COFFEE
+#define KEY_DIRECTION		153
+#define KEY_CYCLEWINDOWS	154
+#define KEY_MAIL		155
+#define KEY_BOOKMARKS		156	/* AC Bookmarks */
+#define KEY_COMPUTER		157
+#define KEY_BACK		158	/* AC Back */
+#define KEY_FORWARD		159	/* AC Forward */
+#define KEY_CLOSECD		160
+#define KEY_EJECTCD		161
+#define KEY_EJECTCLOSECD	162
+#define KEY_NEXTSONG		163
+#define KEY_PLAYPAUSE		164
+#define KEY_PREVIOUSSONG	165
+#define KEY_STOPCD		166
+#define KEY_RECORD		167
+#define KEY_REWIND		168
+#define KEY_PHONE		169	/* Media Select Telephone */
+#define KEY_ISO			170
+#define KEY_CONFIG		171	/* AL Consumer Control Configuration */
+#define KEY_HOMEPAGE		172	/* AC Home */
+#define KEY_REFRESH		173	/* AC Refresh */
+#define KEY_EXIT		174	/* AC Exit */
+#define KEY_MOVE		175
+#define KEY_EDIT		176
+#define KEY_SCROLLUP		177
+#define KEY_SCROLLDOWN		178
+#define KEY_KPLEFTPAREN		179
+#define KEY_KPRIGHTPAREN	180
+#define KEY_NEW			181	/* AC New */
+#define KEY_REDO		182	/* AC Redo/Repeat */
+
+#define KEY_F13			183
+#define KEY_F14			184
+#define KEY_F15			185
+#define KEY_F16			186
+#define KEY_F17			187
+#define KEY_F18			188
+#define KEY_F19			189
+#define KEY_F20			190
+#define KEY_F21			191
+#define KEY_F22			192
+#define KEY_F23			193
+#define KEY_F24			194
+
+#define KEY_PLAYCD		200
+#define KEY_PAUSECD		201
+#define KEY_PROG3		202
+#define KEY_PROG4		203
+#define KEY_DASHBOARD		204	/* AL Dashboard */
+#define KEY_SUSPEND		205
+#define KEY_CLOSE		206	/* AC Close */
+#define KEY_PLAY		207
+#define KEY_FASTFORWARD		208
+#define KEY_BASSBOOST		209
+#define KEY_PRINT		210	/* AC Print */
+#define KEY_HP			211
+#define KEY_CAMERA		212
+#define KEY_SOUND		213
+#define KEY_QUESTION		214
+#define KEY_EMAIL		215
+#define KEY_CHAT		216
+#define KEY_SEARCH		217
+#define KEY_CONNECT		218
+#define KEY_FINANCE		219	/* AL Checkbook/Finance */
+#define KEY_SPORT		220
+#define KEY_SHOP		221
+#define KEY_ALTERASE		222
+#define KEY_CANCEL		223	/* AC Cancel */
+#define KEY_BRIGHTNESSDOWN	224
+#define KEY_BRIGHTNESSUP	225
+#define KEY_MEDIA		226
+
+#define KEY_SWITCHVIDEOMODE	227	/* Cycle between available video
+					   outputs (Monitor/LCD/TV-out/etc) */
+#define KEY_KBDILLUMTOGGLE	228
+#define KEY_KBDILLUMDOWN	229
+#define KEY_KBDILLUMUP		230
+
+#define KEY_SEND		231	/* AC Send */
+#define KEY_REPLY		232	/* AC Reply */
+#define KEY_FORWARDMAIL		233	/* AC Forward Msg */
+#define KEY_SAVE		234	/* AC Save */
+#define KEY_DOCUMENTS		235
+
+#define KEY_BATTERY		236
+
+#define KEY_BLUETOOTH		237
+#define KEY_WLAN		238
+#define KEY_UWB			239
+
+#define KEY_UNKNOWN		240
+
+#define KEY_VIDEO_NEXT		241	/* drive next video source */
+#define KEY_VIDEO_PREV		242	/* drive previous video source */
+#define KEY_BRIGHTNESS_CYCLE	243	/* brightness up, after max is min */
+#define KEY_BRIGHTNESS_ZERO	244	/* brightness off, use ambient */
+#define KEY_DISPLAY_OFF		245	/* display device to off state */
+
+#define KEY_WIMAX		246
+#define KEY_RFKILL		247	/* Key that controls all radios */
+
+#define KEY_MICMUTE		248	/* Mute / unmute the microphone */
+
+/* Code 255 is reserved for special needs of AT keyboard driver */
+
+#define BTN_MISC		0x100
+#define BTN_0			0x100
+#define BTN_1			0x101
+#define BTN_2			0x102
+#define BTN_3			0x103
+#define BTN_4			0x104
+#define BTN_5			0x105
+#define BTN_6			0x106
+#define BTN_7			0x107
+#define BTN_8			0x108
+#define BTN_9			0x109
+
+#define BTN_MOUSE		0x110
+#define BTN_LEFT		0x110
+#define BTN_RIGHT		0x111
+#define BTN_MIDDLE		0x112
+#define BTN_SIDE		0x113
+#define BTN_EXTRA		0x114
+#define BTN_FORWARD		0x115
+#define BTN_BACK		0x116
+#define BTN_TASK		0x117
+
+#define BTN_JOYSTICK		0x120
+#define BTN_TRIGGER		0x120
+#define BTN_THUMB		0x121
+#define BTN_THUMB2		0x122
+#define BTN_TOP			0x123
+#define BTN_TOP2		0x124
+#define BTN_PINKIE		0x125
+#define BTN_BASE		0x126
+#define BTN_BASE2		0x127
+#define BTN_BASE3		0x128
+#define BTN_BASE4		0x129
+#define BTN_BASE5		0x12a
+#define BTN_BASE6		0x12b
+#define BTN_DEAD		0x12f
+
+#define BTN_GAMEPAD		0x130
+#define BTN_SOUTH		0x130
+#define BTN_A			BTN_SOUTH
+#define BTN_EAST		0x131
+#define BTN_B			BTN_EAST
+#define BTN_C			0x132
+#define BTN_NORTH		0x133
+#define BTN_X			BTN_NORTH
+#define BTN_WEST		0x134
+#define BTN_Y			BTN_WEST
+#define BTN_Z			0x135
+#define BTN_TL			0x136
+#define BTN_TR			0x137
+#define BTN_TL2			0x138
+#define BTN_TR2			0x139
+#define BTN_SELECT		0x13a
+#define BTN_START		0x13b
+#define BTN_MODE		0x13c
+#define BTN_THUMBL		0x13d
+#define BTN_THUMBR		0x13e
+
+#define BTN_DIGI		0x140
+#define BTN_TOOL_PEN		0x140
+#define BTN_TOOL_RUBBER		0x141
+#define BTN_TOOL_BRUSH		0x142
+#define BTN_TOOL_PENCIL		0x143
+#define BTN_TOOL_AIRBRUSH	0x144
+#define BTN_TOOL_FINGER		0x145
+#define BTN_TOOL_MOUSE		0x146
+#define BTN_TOOL_LENS		0x147
+#define BTN_TOOL_QUINTTAP	0x148	/* Five fingers on trackpad */
+#define BTN_TOUCH		0x14a
+#define BTN_STYLUS		0x14b
+#define BTN_STYLUS2		0x14c
+#define BTN_TOOL_DOUBLETAP	0x14d
+#define BTN_TOOL_TRIPLETAP	0x14e
+#define BTN_TOOL_QUADTAP	0x14f	/* Four fingers on trackpad */
+
+#define BTN_WHEEL		0x150
+#define BTN_GEAR_DOWN		0x150
+#define BTN_GEAR_UP		0x151
+
+#define KEY_OK			0x160
+#define KEY_SELECT		0x161
+#define KEY_GOTO		0x162
+#define KEY_CLEAR		0x163
+#define KEY_POWER2		0x164
+#define KEY_OPTION		0x165
+#define KEY_INFO		0x166	/* AL OEM Features/Tips/Tutorial */
+#define KEY_TIME		0x167
+#define KEY_VENDOR		0x168
+#define KEY_ARCHIVE		0x169
+#define KEY_PROGRAM		0x16a	/* Media Select Program Guide */
+#define KEY_CHANNEL		0x16b
+#define KEY_FAVORITES		0x16c
+#define KEY_EPG			0x16d
+#define KEY_PVR			0x16e	/* Media Select Home */
+#define KEY_MHP			0x16f
+#define KEY_LANGUAGE		0x170
+#define KEY_TITLE		0x171
+#define KEY_SUBTITLE		0x172
+#define KEY_ANGLE		0x173
+#define KEY_ZOOM		0x174
+#define KEY_MODE		0x175
+#define KEY_KEYBOARD		0x176
+#define KEY_SCREEN		0x177
+#define KEY_PC			0x178	/* Media Select Computer */
+#define KEY_TV			0x179	/* Media Select TV */
+#define KEY_TV2			0x17a	/* Media Select Cable */
+#define KEY_VCR			0x17b	/* Media Select VCR */
+#define KEY_VCR2		0x17c	/* VCR Plus */
+#define KEY_SAT			0x17d	/* Media Select Satellite */
+#define KEY_SAT2		0x17e
+#define KEY_CD			0x17f	/* Media Select CD */
+#define KEY_TAPE		0x180	/* Media Select Tape */
+#define KEY_RADIO		0x181
+#define KEY_TUNER		0x182	/* Media Select Tuner */
+#define KEY_PLAYER		0x183
+#define KEY_TEXT		0x184
+#define KEY_DVD			0x185	/* Media Select DVD */
+#define KEY_AUX			0x186
+#define KEY_MP3			0x187
+#define KEY_AUDIO		0x188	/* AL Audio Browser */
+#define KEY_VIDEO		0x189	/* AL Movie Browser */
+#define KEY_DIRECTORY		0x18a
+#define KEY_LIST		0x18b
+#define KEY_MEMO		0x18c	/* Media Select Messages */
+#define KEY_CALENDAR		0x18d
+#define KEY_RED			0x18e
+#define KEY_GREEN		0x18f
+#define KEY_YELLOW		0x190
+#define KEY_BLUE		0x191
+#define KEY_CHANNELUP		0x192	/* Channel Increment */
+#define KEY_CHANNELDOWN		0x193	/* Channel Decrement */
+#define KEY_FIRST		0x194
+#define KEY_LAST		0x195	/* Recall Last */
+#define KEY_AB			0x196
+#define KEY_NEXT		0x197
+#define KEY_RESTART		0x198
+#define KEY_SLOW		0x199
+#define KEY_SHUFFLE		0x19a
+#define KEY_BREAK		0x19b
+#define KEY_PREVIOUS		0x19c
+#define KEY_DIGITS		0x19d
+#define KEY_TEEN		0x19e
+#define KEY_TWEN		0x19f
+#define KEY_VIDEOPHONE		0x1a0	/* Media Select Video Phone */
+#define KEY_GAMES		0x1a1	/* Media Select Games */
+#define KEY_ZOOMIN		0x1a2	/* AC Zoom In */
+#define KEY_ZOOMOUT		0x1a3	/* AC Zoom Out */
+#define KEY_ZOOMRESET		0x1a4	/* AC Zoom */
+#define KEY_WORDPROCESSOR	0x1a5	/* AL Word Processor */
+#define KEY_EDITOR		0x1a6	/* AL Text Editor */
+#define KEY_SPREADSHEET		0x1a7	/* AL Spreadsheet */
+#define KEY_GRAPHICSEDITOR	0x1a8	/* AL Graphics Editor */
+#define KEY_PRESENTATION	0x1a9	/* AL Presentation App */
+#define KEY_DATABASE		0x1aa	/* AL Database App */
+#define KEY_NEWS		0x1ab	/* AL Newsreader */
+#define KEY_VOICEMAIL		0x1ac	/* AL Voicemail */
+#define KEY_ADDRESSBOOK		0x1ad	/* AL Contacts/Address Book */
+#define KEY_MESSENGER		0x1ae	/* AL Instant Messaging */
+#define KEY_DISPLAYTOGGLE	0x1af	/* Turn display (LCD) on and off */
+#define KEY_SPELLCHECK		0x1b0   /* AL Spell Check */
+#define KEY_LOGOFF		0x1b1   /* AL Logoff */
+
+#define KEY_DOLLAR		0x1b2
+#define KEY_EURO		0x1b3
+
+#define KEY_FRAMEBACK		0x1b4	/* Consumer - transport controls */
+#define KEY_FRAMEFORWARD	0x1b5
+#define KEY_CONTEXT_MENU	0x1b6	/* GenDesc - system context menu */
+#define KEY_MEDIA_REPEAT	0x1b7	/* Consumer - transport control */
+#define KEY_10CHANNELSUP	0x1b8	/* 10 channels up (10+) */
+#define KEY_10CHANNELSDOWN	0x1b9	/* 10 channels down (10-) */
+#define KEY_IMAGES		0x1ba	/* AL Image Browser */
+
+#define KEY_DEL_EOL		0x1c0
+#define KEY_DEL_EOS		0x1c1
+#define KEY_INS_LINE		0x1c2
+#define KEY_DEL_LINE		0x1c3
+
+#define KEY_FN			0x1d0
+#define KEY_FN_ESC		0x1d1
+#define KEY_FN_F1		0x1d2
+#define KEY_FN_F2		0x1d3
+#define KEY_FN_F3		0x1d4
+#define KEY_FN_F4		0x1d5
+#define KEY_FN_F5		0x1d6
+#define KEY_FN_F6		0x1d7
+#define KEY_FN_F7		0x1d8
+#define KEY_FN_F8		0x1d9
+#define KEY_FN_F9		0x1da
+#define KEY_FN_F10		0x1db
+#define KEY_FN_F11		0x1dc
+#define KEY_FN_F12		0x1dd
+#define KEY_FN_1		0x1de
+#define KEY_FN_2		0x1df
+#define KEY_FN_D		0x1e0
+#define KEY_FN_E		0x1e1
+#define KEY_FN_F		0x1e2
+#define KEY_FN_S		0x1e3
+#define KEY_FN_B		0x1e4
+
+#define KEY_BRL_DOT1		0x1f1
+#define KEY_BRL_DOT2		0x1f2
+#define KEY_BRL_DOT3		0x1f3
+#define KEY_BRL_DOT4		0x1f4
+#define KEY_BRL_DOT5		0x1f5
+#define KEY_BRL_DOT6		0x1f6
+#define KEY_BRL_DOT7		0x1f7
+#define KEY_BRL_DOT8		0x1f8
+#define KEY_BRL_DOT9		0x1f9
+#define KEY_BRL_DOT10		0x1fa
+
+#define KEY_NUMERIC_0		0x200	/* used by phones, remote controls, */
+#define KEY_NUMERIC_1		0x201	/* and other keypads */
+#define KEY_NUMERIC_2		0x202
+#define KEY_NUMERIC_3		0x203
+#define KEY_NUMERIC_4		0x204
+#define KEY_NUMERIC_5		0x205
+#define KEY_NUMERIC_6		0x206
+#define KEY_NUMERIC_7		0x207
+#define KEY_NUMERIC_8		0x208
+#define KEY_NUMERIC_9		0x209
+#define KEY_NUMERIC_STAR	0x20a
+#define KEY_NUMERIC_POUND	0x20b
+
+#define KEY_CAMERA_FOCUS	0x210
+#define KEY_WPS_BUTTON		0x211	/* WiFi Protected Setup key */
+
+#define KEY_TOUCHPAD_TOGGLE	0x212	/* Request switch touchpad on or off */
+#define KEY_TOUCHPAD_ON		0x213
+#define KEY_TOUCHPAD_OFF	0x214
+
+#define KEY_CAMERA_ZOOMIN	0x215
+#define KEY_CAMERA_ZOOMOUT	0x216
+#define KEY_CAMERA_UP		0x217
+#define KEY_CAMERA_DOWN		0x218
+#define KEY_CAMERA_LEFT		0x219
+#define KEY_CAMERA_RIGHT	0x21a
+
+#define KEY_ATTENDANT_ON	0x21b
+#define KEY_ATTENDANT_OFF	0x21c
+#define KEY_ATTENDANT_TOGGLE	0x21d	/* Attendant call on or off */
+#define KEY_LIGHTS_TOGGLE	0x21e	/* Reading light on or off */
+
+#define BTN_DPAD_UP		0x220
+#define BTN_DPAD_DOWN		0x221
+#define BTN_DPAD_LEFT		0x222
+#define BTN_DPAD_RIGHT		0x223
+
+#define MATRIX_KEY(row, col, code)	\
+	((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))
+
+#endif /* _DT_BINDINGS_INPUT_INPUT_H */
-- 
2.1.0.rc2.206.gedb03e5

^ permalink raw reply related	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 2/6] dm: sunxi: Add a new config for an FDT-based pcDuino3
  2014-10-23  4:02 [U-Boot] [PATCH v2 0/6] dm: Introduce driver model for sunxi Simon Glass
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 1/6] dm: sunxi: dts: Add sun7i device tree files Simon Glass
@ 2014-10-23  4:02 ` Simon Glass
  2014-10-24  8:38   ` [U-Boot] [U-Boot, v2, " Hans de Goede
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 3/6] dm: sunxi: Add pinmux functions which take a bank parameter Simon Glass
                   ` (3 subsequent siblings)
  5 siblings, 1 reply; 37+ messages in thread
From: Simon Glass @ 2014-10-23  4:02 UTC (permalink / raw)
  To: u-boot

For now we won't want to mess with the existing configurations. Create a
new one which will enable device tree and driver model. Note that this
brings the device tree binary into u-boot-sunxi-with-spl.bin.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 Makefile                                  | 3 ++-
 arch/arm/dts/Makefile                     | 1 +
 board/sunxi/MAINTAINERS                   | 1 +
 configs/Linksprite_pcDuino3_fdt_defconfig | 8 ++++++++
 include/configs/sun7i.h                   | 4 ++++
 5 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 configs/Linksprite_pcDuino3_fdt_defconfig

diff --git a/Makefile b/Makefile
index 99097e1..816f859 100644
--- a/Makefile
+++ b/Makefile
@@ -941,7 +941,8 @@ u-boot-nand.gph: u-boot.bin FORCE
 ifneq ($(CONFIG_SUNXI),)
 OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
 				   --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \
+			u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE
 	$(call if_changed,pad_cat)
 endif
 
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3299817..564eb76 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_SUN7I) +=  sun7i-a20-pcduino3.dtb
 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 4f32195..3dbfe15 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -21,6 +21,7 @@ F:	configs/A20-OLinuXino_MICRO_defconfig
 F:	configs/Bananapi_defconfig
 F:	configs/i12-tvbox_defconfig
 F:	configs/Linksprite_pcDuino3_defconfig
+F:	configs/Linksprite_pcDuino3_fdt_defconfig
 F:	configs/qt840a_defconfig
 
 CUBIEBOARD2 BOARD
diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig
new file mode 100644
index 0000000..e5f6236
--- /dev/null
+++ b/configs/Linksprite_pcDuino3_fdt_defconfig
@@ -0,0 +1,8 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PCDUINO3,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI,DM"
+CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_SUN7I=y
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index a902b84..500d0e3 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -36,6 +36,10 @@
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_SYS_CLK_FREQ		24000000
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
+# define CONFIG_CMD_DM
+#endif
+
 /*
  * Include common sunxi configuration where most the settings are
  */
-- 
2.1.0.rc2.206.gedb03e5

^ permalink raw reply related	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 3/6] dm: sunxi: Add pinmux functions which take a bank parameter
  2014-10-23  4:02 [U-Boot] [PATCH v2 0/6] dm: Introduce driver model for sunxi Simon Glass
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 1/6] dm: sunxi: dts: Add sun7i device tree files Simon Glass
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 2/6] dm: sunxi: Add a new config for an FDT-based pcDuino3 Simon Glass
@ 2014-10-23  4:02 ` Simon Glass
  2014-10-24  9:00   ` [U-Boot] [U-Boot, v2, " Hans de Goede
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 4/6] dm: sunxi: Make sure that GPIOs are requested Simon Glass
                   ` (2 subsequent siblings)
  5 siblings, 1 reply; 37+ messages in thread
From: Simon Glass @ 2014-10-23  4:02 UTC (permalink / raw)
  To: u-boot

With driver model we will have access to a bank pointer, so we want to
use it rather than converting back to a number, and then back to a
bank pointer. Add functions to provide this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/arm/cpu/armv7/sunxi/pinmux.c      | 32 +++++++++++++++++++++-----------
 arch/arm/include/asm/arch-sunxi/gpio.h |  4 +++-
 2 files changed, 24 insertions(+), 12 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c
index 1f2843f..b026f78 100644
--- a/arch/arm/cpu/armv7/sunxi/pinmux.c
+++ b/arch/arm/cpu/armv7/sunxi/pinmux.c
@@ -10,32 +10,42 @@
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
 
-int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
 {
-	u32 bank = GPIO_BANK(pin);
-	u32 index = GPIO_CFG_INDEX(pin);
-	u32 offset = GPIO_CFG_OFFSET(pin);
-	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+	u32 index = GPIO_CFG_INDEX(bank_offset);
+	u32 offset = GPIO_CFG_OFFSET(bank_offset);
 
 	clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
-
-	return 0;
 }
 
-int sunxi_gpio_get_cfgpin(u32 pin)
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
 {
-	u32 cfg;
 	u32 bank = GPIO_BANK(pin);
-	u32 index = GPIO_CFG_INDEX(pin);
-	u32 offset = GPIO_CFG_OFFSET(pin);
 	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 
+	sunxi_gpio_set_cfgbank(pio, pin, val);
+}
+
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
+{
+	u32 index = GPIO_CFG_INDEX(bank_offset);
+	u32 offset = GPIO_CFG_OFFSET(bank_offset);
+	u32 cfg;
+
 	cfg = readl(&pio->cfg[0] + index);
 	cfg >>= offset;
 
 	return cfg & 0xf;
 }
 
+int sunxi_gpio_get_cfgpin(u32 pin)
+{
+	u32 bank = GPIO_BANK(pin);
+	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+	return sunxi_gpio_get_cfgbank(pio, pin);
+}
+
 int sunxi_gpio_set_drv(u32 pin, u32 val)
 {
 	u32 bank = GPIO_BANK(pin);
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index f7f3d8c..f72e2fd 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -139,7 +139,9 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_PULL_UP	1
 #define SUNXI_GPIO_PULL_DOWN	2
 
-int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
 int sunxi_gpio_get_cfgpin(u32 pin);
 int sunxi_gpio_set_drv(u32 pin, u32 val);
 int sunxi_gpio_set_pull(u32 pin, u32 val);
-- 
2.1.0.rc2.206.gedb03e5

^ permalink raw reply related	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 4/6] dm: sunxi: Make sure that GPIOs are requested
  2014-10-23  4:02 [U-Boot] [PATCH v2 0/6] dm: Introduce driver model for sunxi Simon Glass
                   ` (2 preceding siblings ...)
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 3/6] dm: sunxi: Add pinmux functions which take a bank parameter Simon Glass
@ 2014-10-23  4:02 ` Simon Glass
  2014-10-24  9:01   ` [U-Boot] [U-Boot, v2, " Hans de Goede
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 5/6] dm: sunxi: Modify the GPIO driver to support driver model Simon Glass
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using " Simon Glass
  5 siblings, 1 reply; 37+ messages in thread
From: Simon Glass @ 2014-10-23  4:02 UTC (permalink / raw)
  To: u-boot

The scsi_init() function uses a GPIO so should request it. There is no
way to return an error here, and the request may be made multiple times,
so just ignore errors for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 board/sunxi/ahci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c
index 0c262ea..5e12328 100644
--- a/board/sunxi/ahci.c
+++ b/board/sunxi/ahci.c
@@ -74,6 +74,7 @@ void scsi_init(void)
 {
 	printf("SUNXI SCSI INIT\n");
 #ifdef CONFIG_SATAPWR
+	gpio_request(CONFIG_SATAPWR, "satapwr");
 	gpio_direction_output(CONFIG_SATAPWR, 1);
 #endif
 
-- 
2.1.0.rc2.206.gedb03e5

^ permalink raw reply related	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 5/6] dm: sunxi: Modify the GPIO driver to support driver model
  2014-10-23  4:02 [U-Boot] [PATCH v2 0/6] dm: Introduce driver model for sunxi Simon Glass
                   ` (3 preceding siblings ...)
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 4/6] dm: sunxi: Make sure that GPIOs are requested Simon Glass
@ 2014-10-23  4:02 ` Simon Glass
  2014-10-24  9:08   ` [U-Boot] [U-Boot, v2, " Hans de Goede
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using " Simon Glass
  5 siblings, 1 reply; 37+ messages in thread
From: Simon Glass @ 2014-10-23  4:02 UTC (permalink / raw)
  To: u-boot

This adds driver model support to the sunxi GPIO driver, using the device
tree to trigger binding of the driver. The driver will still operate
without driver model too.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Remove references to exynos and tegra
- Use the word 'bank' instead of 'port'

 drivers/gpio/sunxi_gpio.c | 170 ++++++++++++++++++++++++++++++++++++++++++++++
 include/configs/sun7i.h   |   1 +
 2 files changed, 171 insertions(+)

diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 0c50a8f..44135e5 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -11,9 +11,25 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
+#include <dm/device-internal.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SUNXI_GPIOS_PER_BANK	SUNXI_GPIO_A_NR
+
+struct sunxi_gpio_platdata {
+	struct sunxi_gpio *regs;
+	const char *bank_name;	/* Name of bank, e.g. "B" */
+	int gpio_count;
+};
+
+#ifndef CONFIG_DM_GPIO
 static int sunxi_gpio_output(u32 pin, u32 val)
 {
 	u32 dat;
@@ -100,3 +116,157 @@ int sunxi_name_to_gpio(const char *name)
 		return -1;
 	return group * 32 + pin;
 }
+#endif
+
+#ifdef CONFIG_DM_GPIO
+static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+
+	sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
+
+	return 0;
+}
+
+static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
+				       int value)
+{
+	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+	u32 num = GPIO_NUM(offset);
+
+	sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
+	clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
+
+	return 0;
+}
+
+static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+	u32 num = GPIO_NUM(offset);
+	unsigned dat;
+
+	dat = readl(&plat->regs->dat);
+	dat >>= num;
+
+	return dat & 0x1;
+}
+
+static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
+				int value)
+{
+	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+	u32 num = GPIO_NUM(offset);
+
+	clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
+	return 0;
+}
+
+static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+	int func;
+
+	func = sunxi_gpio_get_cfgbank(plat->regs, offset);
+	if (func == SUNXI_GPIO_OUTPUT)
+		return GPIOF_OUTPUT;
+	else if (func == SUNXI_GPIO_INPUT)
+		return GPIOF_INPUT;
+	else
+		return GPIOF_FUNC;
+}
+
+static const struct dm_gpio_ops gpio_sunxi_ops = {
+	.direction_input	= sunxi_gpio_direction_input,
+	.direction_output	= sunxi_gpio_direction_output,
+	.get_value		= sunxi_gpio_get_value,
+	.set_value		= sunxi_gpio_set_value,
+	.get_function		= sunxi_gpio_get_function,
+};
+
+/**
+ * Returns the name of a GPIO bank
+ *
+ * GPIO banks are named A, B, C, ...
+ *
+ * @bank:	Bank number (0, 1..n-1)
+ * @return allocated string containing the name
+ */
+static char *gpio_bank_name(int bank)
+{
+	char *name;
+
+	name = malloc(2);
+	if (name) {
+		name[0] = 'A' + bank;
+		name[1] = '\0';
+	}
+
+	return name;
+}
+
+static int gpio_sunxi_probe(struct udevice *dev)
+{
+	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+	/* Tell the uclass how many GPIOs we have */
+	if (plat) {
+		uc_priv->gpio_count = plat->gpio_count;
+		uc_priv->bank_name = plat->bank_name;
+	}
+
+	return 0;
+}
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Sunxi bank.
+ */
+static int gpio_sunxi_bind(struct udevice *parent)
+{
+	struct sunxi_gpio_platdata *plat = parent->platdata;
+	struct sunxi_gpio_reg *ctlr;
+	int bank;
+	int ret;
+
+	/* If this is a child device, there is nothing to do here */
+	if (plat)
+		return 0;
+
+	ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd->fdt_blob,
+						   parent->of_offset, "reg");
+	for (bank = 0; bank < SUNXI_GPIO_BANKS; bank++) {
+		struct sunxi_gpio_platdata *plat;
+		struct udevice *dev;
+
+		plat = calloc(1, sizeof(*plat));
+		if (!plat)
+			return -ENOMEM;
+		plat->regs = &ctlr->gpio_bank[bank];
+		plat->bank_name = gpio_bank_name(bank);
+		plat->gpio_count = SUNXI_GPIOS_PER_BANK;
+
+		ret = device_bind(parent, parent->driver,
+					plat->bank_name, plat, -1, &dev);
+		if (ret)
+			return ret;
+		dev->of_offset = parent->of_offset;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id sunxi_gpio_ids[] = {
+	{ .compatible = "allwinner,sun7i-a20-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_sunxi) = {
+	.name	= "gpio_sunxi",
+	.id	= UCLASS_GPIO,
+	.ops	= &gpio_sunxi_ops,
+	.of_match = sunxi_gpio_ids,
+	.bind	= gpio_sunxi_bind,
+	.probe	= gpio_sunxi_probe,
+};
+#endif
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index 500d0e3..2314e97 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -38,6 +38,7 @@
 
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
 # define CONFIG_CMD_DM
+# define CONFIG_DM_GPIO
 #endif
 
 /*
-- 
2.1.0.rc2.206.gedb03e5

^ permalink raw reply related	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-23  4:02 [U-Boot] [PATCH v2 0/6] dm: Introduce driver model for sunxi Simon Glass
                   ` (4 preceding siblings ...)
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 5/6] dm: sunxi: Modify the GPIO driver to support driver model Simon Glass
@ 2014-10-23  4:02 ` Simon Glass
  2014-10-24  9:10   ` [U-Boot] [U-Boot, v2, " Hans de Goede
  2014-10-24  9:42   ` [U-Boot] [PATCH v2 " Ian Campbell
  5 siblings, 2 replies; 37+ messages in thread
From: Simon Glass @ 2014-10-23  4:02 UTC (permalink / raw)
  To: u-boot

Add a driver for the designware serial UART used on sunxi. This just
redirects to the normal ns16550 driver.

Add a stdout-path to the device tree so that the correct UART is chosen.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Split non-sunxi patches into a separate dependent series

 arch/arm/dts/sun7i-a20-pcduino3.dts |  4 ++++
 drivers/serial/Makefile             |  1 +
 drivers/serial/serial_dw.c          | 39 +++++++++++++++++++++++++++++++++++++
 include/configs/sun7i.h             |  3 +++
 include/configs/sunxi-common.h      | 12 +++++++-----
 5 files changed, 54 insertions(+), 5 deletions(-)
 create mode 100644 drivers/serial/serial_dw.c

diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts
index 046dfc0..f7cc8e7 100644
--- a/arch/arm/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/dts/sun7i-a20-pcduino3.dts
@@ -20,6 +20,10 @@
 	model = "LinkSprite pcDuino3";
 	compatible = "linksprite,pcduino3", "allwinner,sun7i-a20";
 
+	chosen {
+		stdout-path = &uart0;
+	};
+
 	soc at 01c00000 {
 		mmc0: mmc at 01c0f000 {
 			pinctrl-names = "default";
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index cd87d18..588573a 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
+obj-$(CONFIG_DW_SERIAL) += serial_dw.o
 obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 obj-$(CONFIG_MCFUART) += mcfuart.o
 obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
diff --git a/drivers/serial/serial_dw.c b/drivers/serial/serial_dw.c
new file mode 100644
index 0000000..a348f29
--- /dev/null
+++ b/drivers/serial/serial_dw.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+static const struct udevice_id dw_serial_ids[] = {
+	{ .compatible = "snps,dw-apb-uart" },
+	{ }
+};
+
+static int dw_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	struct ns16550_platdata *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = ns16550_serial_ofdata_to_platdata(dev);
+	if (ret)
+		return ret;
+	plat->clock = CONFIG_SYS_NS16550_CLK;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(serial_ns16550) = {
+	.name	= "serial_dw",
+	.id	= UCLASS_SERIAL,
+	.of_match = dw_serial_ids,
+	.ofdata_to_platdata = dw_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+	.priv_auto_alloc_size = sizeof(struct NS16550),
+	.probe = ns16550_serial_probe,
+	.ops	= &ns16550_serial_ops,
+};
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index 2314e97..108694a 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -39,6 +39,9 @@
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
 # define CONFIG_CMD_DM
 # define CONFIG_DM_GPIO
+# define CONFIG_DM_SERIAL
+# define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
+# define CONFIG_DW_SERIAL
 #endif
 
 /*
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 1d947d7..e26bdf9 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -36,12 +36,14 @@
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 /* ns16550 reg in the low bits of cpu reg */
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
 #define CONFIG_SYS_NS16550_CLK		24000000
-#define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
-#define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
-#define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
+#ifndef CONFIG_DM_SERIAL
+# define CONFIG_SYS_NS16550_REG_SIZE	-4
+# define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
+# define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
+# define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
+# define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
+#endif
 
 /* DRAM Base */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
-- 
2.1.0.rc2.206.gedb03e5

^ permalink raw reply related	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 1/6] dm: sunxi: dts: Add sun7i device tree files
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 1/6] dm: sunxi: dts: Add sun7i device tree files Simon Glass
@ 2014-10-24  8:32   ` Hans de Goede
  2014-10-28  1:05     ` Simon Glass
  0 siblings, 1 reply; 37+ messages in thread
From: Hans de Goede @ 2014-10-24  8:32 UTC (permalink / raw)
  To: u-boot

Hi,

On 10/23/2014 06:02 AM, Simon Glass wrote:
> These are from Linux 3.17-rc7 (commit fe82dcec). U-Boot only uses a small
> portion of these, but we may as well have something to look forward to.
> 
> The total compiled size is about 25KB.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>

Looks good:

Acked-by: Hans de Goede <hdegoede@redhat.com>

I assume we should wait with applying this series until the next
dm merge ?

Regards,

Hans

> ---
> 
> Changes in v2: None
> 
>  arch/arm/dts/sun7i-a20-pcduino3.dts       | 173 ++++++
>  arch/arm/dts/sun7i-a20.dtsi               | 988 ++++++++++++++++++++++++++++++
>  arch/arm/dts/sunxi-common-regulators.dtsi |  89 +++
>  include/dt-bindings/input/input.h         | 525 ++++++++++++++++
>  4 files changed, 1775 insertions(+)
>  create mode 100644 arch/arm/dts/sun7i-a20-pcduino3.dts
>  create mode 100644 arch/arm/dts/sun7i-a20.dtsi
>  create mode 100644 arch/arm/dts/sunxi-common-regulators.dtsi
>  create mode 100644 include/dt-bindings/input/input.h
> 
> diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts
> new file mode 100644
> index 0000000..046dfc0
> --- /dev/null
> +++ b/arch/arm/dts/sun7i-a20-pcduino3.dts
> @@ -0,0 +1,173 @@
> +/*
> + * Copyright 2014 Zoltan HERPAI
> + * Zoltan HERPAI <wigyori@uid0.hu>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "sun7i-a20.dtsi"
> +/include/ "sunxi-common-regulators.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +	model = "LinkSprite pcDuino3";
> +	compatible = "linksprite,pcduino3", "allwinner,sun7i-a20";
> +
> +	soc at 01c00000 {
> +		mmc0: mmc at 01c0f000 {
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> +			vmmc-supply = <&reg_vcc3v3>;
> +			bus-width = <4>;
> +			cd-gpios = <&pio 7 1 0>; /* PH1 */
> +			cd-inverted;
> +			status = "okay";
> +		};
> +
> +		usbphy: phy at 01c13400 {
> +			usb1_vbus-supply = <&reg_usb1_vbus>;
> +			usb2_vbus-supply = <&reg_usb2_vbus>;
> +			status = "okay";
> +		};
> +
> +		ehci0: usb at 01c14000 {
> +			status = "okay";
> +		};
> +
> +		ohci0: usb at 01c14400 {
> +			status = "okay";
> +		};
> +
> +		ahci: sata at 01c18000 {
> +			target-supply = <&reg_ahci_5v>;
> +			status = "okay";
> +		};
> +
> +		ehci1: usb at 01c1c000 {
> +			status = "okay";
> +		};
> +
> +		ohci1: usb at 01c1c400 {
> +			status = "okay";
> +		};
> +
> +		pinctrl at 01c20800 {
> +			ahci_pwr_pin_a: ahci_pwr_pin at 0 {
> +				allwinner,pins = "PH2";
> +			};
> +
> +			led_pins_pcduino3: led_pins at 0 {
> +				allwinner,pins = "PH15", "PH16";
> +				allwinner,function = "gpio_out";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			key_pins_pcduino3: key_pins at 0 {
> +				allwinner,pins = "PH17", "PH18", "PH19";
> +				allwinner,function = "gpio_in";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +		};
> +
> +		ir0: ir at 01c21800 {
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&ir0_pins_a>;
> +			status = "okay";
> +		};
> +
> +		uart0: serial at 01c28000 {
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&uart0_pins_a>;
> +			status = "okay";
> +		};
> +
> +		i2c0: i2c at 01c2ac00 {
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&i2c0_pins_a>;
> +			status = "okay";
> +
> +			axp209: pmic at 34 {
> +				compatible = "x-powers,axp209";
> +				reg = <0x34>;
> +				interrupt-parent = <&nmi_intc>;
> +				interrupts = <0 8>;
> +
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		gmac: ethernet at 01c50000 {
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&gmac_pins_mii_a>;
> +			phy = <&phy1>;
> +			phy-mode = "mii";
> +			status = "okay";
> +
> +			phy1: ethernet-phy at 1 {
> +				reg = <1>;
> +			};
> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&led_pins_pcduino3>;
> +
> +		tx {
> +			label = "pcduino3:green:tx";
> +			gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		rx {
> +			label = "pcduino3:green:rx";
> +			gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +
> +	gpio_keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&key_pins_pcduino3>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		button at 0 {
> +			label = "Key Back";
> +			linux,code = <KEY_BACK>;
> +			gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
> +		};
> +		button at 1 {
> +			label = "Key Home";
> +			linux,code = <KEY_HOME>;
> +			gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
> +		};
> +		button at 2 {
> +			label = "Key Menu";
> +			linux,code = <KEY_MENU>;
> +			gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +
> +	reg_usb1_vbus: usb1-vbus {
> +		status = "okay";
> +	};
> +
> +	reg_usb2_vbus: usb2-vbus {
> +		status = "okay";
> +	};
> +
> +	reg_ahci_5v: ahci-5v {
> +		gpio = <&pio 7 2 0>;
> +		status = "okay";
> +	};
> +};
> diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi
> new file mode 100644
> index 0000000..4011628
> --- /dev/null
> +++ b/arch/arm/dts/sun7i-a20.dtsi
> @@ -0,0 +1,988 @@
> +/*
> + * Copyright 2013 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +
> +	aliases {
> +		ethernet0 = &gmac;
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5;
> +		serial6 = &uart6;
> +		serial7 = &uart7;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu at 0 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <0>;
> +		};
> +
> +		cpu at 1 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <1>;
> +		};
> +	};
> +
> +	memory {
> +		reg = <0x40000000 0x80000000>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = <1 13 0xf08>,
> +			     <1 14 0xf08>,
> +			     <1 11 0xf08>,
> +			     <1 10 0xf08>;
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
> +		interrupts = <0 120 4>,
> +			     <0 121 4>;
> +	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		osc24M: clk at 01c20050 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-osc-clk";
> +			reg = <0x01c20050 0x4>;
> +			clock-frequency = <24000000>;
> +			clock-output-names = "osc24M";
> +		};
> +
> +		osc32k: clk at 0 {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <32768>;
> +			clock-output-names = "osc32k";
> +		};
> +
> +		pll1: clk at 01c20000 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-pll1-clk";
> +			reg = <0x01c20000 0x4>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "pll1";
> +		};
> +
> +		pll4: clk at 01c20018 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun7i-a20-pll4-clk";
> +			reg = <0x01c20018 0x4>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "pll4";
> +		};
> +
> +		pll5: clk at 01c20020 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-pll5-clk";
> +			reg = <0x01c20020 0x4>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "pll5_ddr", "pll5_other";
> +		};
> +
> +		pll6: clk at 01c20028 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-pll6-clk";
> +			reg = <0x01c20028 0x4>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "pll6_sata", "pll6_other", "pll6";
> +		};
> +
> +		pll8: clk at 01c20040 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun7i-a20-pll4-clk";
> +			reg = <0x01c20040 0x4>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "pll8";
> +		};
> +
> +		cpu: cpu at 01c20054 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-cpu-clk";
> +			reg = <0x01c20054 0x4>;
> +			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
> +			clock-output-names = "cpu";
> +		};
> +
> +		axi: axi at 01c20054 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-axi-clk";
> +			reg = <0x01c20054 0x4>;
> +			clocks = <&cpu>;
> +			clock-output-names = "axi";
> +		};
> +
> +		ahb: ahb at 01c20054 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-ahb-clk";
> +			reg = <0x01c20054 0x4>;
> +			clocks = <&axi>;
> +			clock-output-names = "ahb";
> +		};
> +
> +		ahb_gates: clk at 01c20060 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun7i-a20-ahb-gates-clk";
> +			reg = <0x01c20060 0x8>;
> +			clocks = <&ahb>;
> +			clock-output-names = "ahb_usb0", "ahb_ehci0",
> +				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
> +				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
> +				"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
> +				"ahb_nand", "ahb_sdram", "ahb_ace",
> +				"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
> +				"ahb_spi2", "ahb_spi3", "ahb_sata",
> +				"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
> +				"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
> +				"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
> +				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
> +				"ahb_de_fe1", "ahb_gmac", "ahb_mp",
> +				"ahb_mali";
> +		};
> +
> +		apb0: apb0 at 01c20054 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-apb0-clk";
> +			reg = <0x01c20054 0x4>;
> +			clocks = <&ahb>;
> +			clock-output-names = "apb0";
> +		};
> +
> +		apb0_gates: clk at 01c20068 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun7i-a20-apb0-gates-clk";
> +			reg = <0x01c20068 0x4>;
> +			clocks = <&apb0>;
> +			clock-output-names = "apb0_codec", "apb0_spdif",
> +				"apb0_ac97", "apb0_iis0", "apb0_iis1",
> +				"apb0_pio", "apb0_ir0", "apb0_ir1",
> +				"apb0_iis2", "apb0_keypad";
> +		};
> +
> +		apb1_mux: apb1_mux at 01c20058 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-apb1-mux-clk";
> +			reg = <0x01c20058 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
> +			clock-output-names = "apb1_mux";
> +		};
> +
> +		apb1: apb1 at 01c20058 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-apb1-clk";
> +			reg = <0x01c20058 0x4>;
> +			clocks = <&apb1_mux>;
> +			clock-output-names = "apb1";
> +		};
> +
> +		apb1_gates: clk at 01c2006c {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun7i-a20-apb1-gates-clk";
> +			reg = <0x01c2006c 0x4>;
> +			clocks = <&apb1>;
> +			clock-output-names = "apb1_i2c0", "apb1_i2c1",
> +				"apb1_i2c2", "apb1_i2c3", "apb1_can",
> +				"apb1_scr", "apb1_ps20", "apb1_ps21",
> +				"apb1_i2c4", "apb1_uart0", "apb1_uart1",
> +				"apb1_uart2", "apb1_uart3", "apb1_uart4",
> +				"apb1_uart5", "apb1_uart6", "apb1_uart7";
> +		};
> +
> +		nand_clk: clk at 01c20080 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c20080 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "nand";
> +		};
> +
> +		ms_clk: clk at 01c20084 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c20084 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "ms";
> +		};
> +
> +		mmc0_clk: clk at 01c20088 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c20088 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "mmc0";
> +		};
> +
> +		mmc1_clk: clk at 01c2008c {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c2008c 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "mmc1";
> +		};
> +
> +		mmc2_clk: clk at 01c20090 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c20090 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "mmc2";
> +		};
> +
> +		mmc3_clk: clk at 01c20094 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c20094 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "mmc3";
> +		};
> +
> +		ts_clk: clk at 01c20098 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c20098 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "ts";
> +		};
> +
> +		ss_clk: clk at 01c2009c {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c2009c 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "ss";
> +		};
> +
> +		spi0_clk: clk at 01c200a0 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c200a0 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "spi0";
> +		};
> +
> +		spi1_clk: clk at 01c200a4 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c200a4 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "spi1";
> +		};
> +
> +		spi2_clk: clk at 01c200a8 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c200a8 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "spi2";
> +		};
> +
> +		pata_clk: clk at 01c200ac {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c200ac 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "pata";
> +		};
> +
> +		ir0_clk: clk at 01c200b0 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c200b0 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "ir0";
> +		};
> +
> +		ir1_clk: clk at 01c200b4 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c200b4 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "ir1";
> +		};
> +
> +		usb_clk: clk at 01c200cc {
> +			#clock-cells = <1>;
> +		        #reset-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-usb-clk";
> +			reg = <0x01c200cc 0x4>;
> +			clocks = <&pll6 1>;
> +			clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
> +		};
> +
> +		spi3_clk: clk at 01c200d4 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c200d4 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> +			clock-output-names = "spi3";
> +		};
> +
> +		mbus_clk: clk at 01c2015c {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c2015c 0x4>;
> +			clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
> +			clock-output-names = "mbus";
> +		};
> +
> +		/*
> +		 * The following two are dummy clocks, placeholders used in the gmac_tx
> +		 * clock. The gmac driver will choose one parent depending on the PHY
> +		 * interface mode, using clk_set_rate auto-reparenting.
> +		 * The actual TX clock rate is not controlled by the gmac_tx clock.
> +		 */
> +		mii_phy_tx_clk: clk at 2 {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <25000000>;
> +			clock-output-names = "mii_phy_tx";
> +		};
> +
> +		gmac_int_tx_clk: clk at 3 {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <125000000>;
> +			clock-output-names = "gmac_int_tx";
> +		};
> +
> +		gmac_tx_clk: clk at 01c20164 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun7i-a20-gmac-clk";
> +			reg = <0x01c20164 0x4>;
> +			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
> +			clock-output-names = "gmac_tx";
> +		};
> +
> +		/*
> +		 * Dummy clock used by output clocks
> +		 */
> +		osc24M_32k: clk at 1 {
> +			#clock-cells = <0>;
> +			compatible = "fixed-factor-clock";
> +			clock-div = <750>;
> +			clock-mult = <1>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "osc24M_32k";
> +		};
> +
> +		clk_out_a: clk at 01c201f0 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun7i-a20-out-clk";
> +			reg = <0x01c201f0 0x4>;
> +			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
> +			clock-output-names = "clk_out_a";
> +		};
> +
> +		clk_out_b: clk at 01c201f4 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun7i-a20-out-clk";
> +			reg = <0x01c201f4 0x4>;
> +			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
> +			clock-output-names = "clk_out_b";
> +		};
> +	};
> +
> +	soc at 01c00000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		nmi_intc: interrupt-controller at 01c00030 {
> +			compatible = "allwinner,sun7i-a20-sc-nmi";
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			reg = <0x01c00030 0x0c>;
> +			interrupts = <0 0 4>;
> +		};
> +
> +		spi0: spi at 01c05000 {
> +			compatible = "allwinner,sun4i-a10-spi";
> +			reg = <0x01c05000 0x1000>;
> +			interrupts = <0 10 4>;
> +			clocks = <&ahb_gates 20>, <&spi0_clk>;
> +			clock-names = "ahb", "mod";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		spi1: spi at 01c06000 {
> +			compatible = "allwinner,sun4i-a10-spi";
> +			reg = <0x01c06000 0x1000>;
> +			interrupts = <0 11 4>;
> +			clocks = <&ahb_gates 21>, <&spi1_clk>;
> +			clock-names = "ahb", "mod";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		emac: ethernet at 01c0b000 {
> +			compatible = "allwinner,sun4i-a10-emac";
> +			reg = <0x01c0b000 0x1000>;
> +			interrupts = <0 55 4>;
> +			clocks = <&ahb_gates 17>;
> +			status = "disabled";
> +		};
> +
> +		mdio at 01c0b080 {
> +			compatible = "allwinner,sun4i-a10-mdio";
> +			reg = <0x01c0b080 0x14>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc0: mmc at 01c0f000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c0f000 0x1000>;
> +			clocks = <&ahb_gates 8>, <&mmc0_clk>;
> +			clock-names = "ahb", "mmc";
> +			interrupts = <0 32 4>;
> +			status = "disabled";
> +		};
> +
> +		mmc1: mmc at 01c10000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c10000 0x1000>;
> +			clocks = <&ahb_gates 9>, <&mmc1_clk>;
> +			clock-names = "ahb", "mmc";
> +			interrupts = <0 33 4>;
> +			status = "disabled";
> +		};
> +
> +		mmc2: mmc at 01c11000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c11000 0x1000>;
> +			clocks = <&ahb_gates 10>, <&mmc2_clk>;
> +			clock-names = "ahb", "mmc";
> +			interrupts = <0 34 4>;
> +			status = "disabled";
> +		};
> +
> +		mmc3: mmc at 01c12000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c12000 0x1000>;
> +			clocks = <&ahb_gates 11>, <&mmc3_clk>;
> +			clock-names = "ahb", "mmc";
> +			interrupts = <0 35 4>;
> +			status = "disabled";
> +		};
> +
> +		usbphy: phy at 01c13400 {
> +			#phy-cells = <1>;
> +			compatible = "allwinner,sun7i-a20-usb-phy";
> +			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
> +			reg-names = "phy_ctrl", "pmu1", "pmu2";
> +			clocks = <&usb_clk 8>;
> +			clock-names = "usb_phy";
> +			resets = <&usb_clk 1>, <&usb_clk 2>;
> +			reset-names = "usb1_reset", "usb2_reset";
> +			status = "disabled";
> +		};
> +
> +		ehci0: usb at 01c14000 {
> +			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
> +			reg = <0x01c14000 0x100>;
> +			interrupts = <0 39 4>;
> +			clocks = <&ahb_gates 1>;
> +			phys = <&usbphy 1>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ohci0: usb at 01c14400 {
> +			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
> +			reg = <0x01c14400 0x100>;
> +			interrupts = <0 64 4>;
> +			clocks = <&usb_clk 6>, <&ahb_gates 2>;
> +			phys = <&usbphy 1>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		spi2: spi at 01c17000 {
> +			compatible = "allwinner,sun4i-a10-spi";
> +			reg = <0x01c17000 0x1000>;
> +			interrupts = <0 12 4>;
> +			clocks = <&ahb_gates 22>, <&spi2_clk>;
> +			clock-names = "ahb", "mod";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		ahci: sata at 01c18000 {
> +			compatible = "allwinner,sun4i-a10-ahci";
> +			reg = <0x01c18000 0x1000>;
> +			interrupts = <0 56 4>;
> +			clocks = <&pll6 0>, <&ahb_gates 25>;
> +			status = "disabled";
> +		};
> +
> +		ehci1: usb at 01c1c000 {
> +			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
> +			reg = <0x01c1c000 0x100>;
> +			interrupts = <0 40 4>;
> +			clocks = <&ahb_gates 3>;
> +			phys = <&usbphy 2>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ohci1: usb at 01c1c400 {
> +			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
> +			reg = <0x01c1c400 0x100>;
> +			interrupts = <0 65 4>;
> +			clocks = <&usb_clk 7>, <&ahb_gates 4>;
> +			phys = <&usbphy 2>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		spi3: spi at 01c1f000 {
> +			compatible = "allwinner,sun4i-a10-spi";
> +			reg = <0x01c1f000 0x1000>;
> +			interrupts = <0 50 4>;
> +			clocks = <&ahb_gates 23>, <&spi3_clk>;
> +			clock-names = "ahb", "mod";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		pio: pinctrl at 01c20800 {
> +			compatible = "allwinner,sun7i-a20-pinctrl";
> +			reg = <0x01c20800 0x400>;
> +			interrupts = <0 28 4>;
> +			clocks = <&apb0_gates 5>;
> +			gpio-controller;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			#size-cells = <0>;
> +			#gpio-cells = <3>;
> +
> +			pwm0_pins_a: pwm0 at 0 {
> +				allwinner,pins = "PB2";
> +				allwinner,function = "pwm";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			pwm1_pins_a: pwm1 at 0 {
> +				allwinner,pins = "PI3";
> +				allwinner,function = "pwm";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			uart0_pins_a: uart0 at 0 {
> +				allwinner,pins = "PB22", "PB23";
> +				allwinner,function = "uart0";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			uart2_pins_a: uart2 at 0 {
> +				allwinner,pins = "PI16", "PI17", "PI18", "PI19";
> +				allwinner,function = "uart2";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			uart6_pins_a: uart6 at 0 {
> +				allwinner,pins = "PI12", "PI13";
> +				allwinner,function = "uart6";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			uart7_pins_a: uart7 at 0 {
> +				allwinner,pins = "PI20", "PI21";
> +				allwinner,function = "uart7";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			i2c0_pins_a: i2c0 at 0 {
> +				allwinner,pins = "PB0", "PB1";
> +				allwinner,function = "i2c0";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			i2c1_pins_a: i2c1 at 0 {
> +				allwinner,pins = "PB18", "PB19";
> +				allwinner,function = "i2c1";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			i2c2_pins_a: i2c2 at 0 {
> +				allwinner,pins = "PB20", "PB21";
> +				allwinner,function = "i2c2";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			emac_pins_a: emac0 at 0 {
> +				allwinner,pins = "PA0", "PA1", "PA2",
> +						"PA3", "PA4", "PA5", "PA6",
> +						"PA7", "PA8", "PA9", "PA10",
> +						"PA11", "PA12", "PA13", "PA14",
> +						"PA15", "PA16";
> +				allwinner,function = "emac";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			clk_out_a_pins_a: clk_out_a at 0 {
> +				allwinner,pins = "PI12";
> +				allwinner,function = "clk_out_a";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			clk_out_b_pins_a: clk_out_b at 0 {
> +				allwinner,pins = "PI13";
> +				allwinner,function = "clk_out_b";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			gmac_pins_mii_a: gmac_mii at 0 {
> +				allwinner,pins = "PA0", "PA1", "PA2",
> +						"PA3", "PA4", "PA5", "PA6",
> +						"PA7", "PA8", "PA9", "PA10",
> +						"PA11", "PA12", "PA13", "PA14",
> +						"PA15", "PA16";
> +				allwinner,function = "gmac";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			gmac_pins_rgmii_a: gmac_rgmii at 0 {
> +				allwinner,pins = "PA0", "PA1", "PA2",
> +						"PA3", "PA4", "PA5", "PA6",
> +						"PA7", "PA8", "PA10",
> +						"PA11", "PA12", "PA13",
> +						"PA15", "PA16";
> +				allwinner,function = "gmac";
> +				/*
> +				 * data lines in RGMII mode use DDR mode
> +				 * and need a higher signal drive strength
> +				 */
> +				allwinner,drive = <3>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			spi1_pins_a: spi1 at 0 {
> +				allwinner,pins = "PI16", "PI17", "PI18", "PI19";
> +				allwinner,function = "spi1";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			spi2_pins_a: spi2 at 0 {
> +				allwinner,pins = "PC19", "PC20", "PC21", "PC22";
> +				allwinner,function = "spi2";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			mmc0_pins_a: mmc0 at 0 {
> +				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
> +				allwinner,function = "mmc0";
> +				allwinner,drive = <2>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
> +				allwinner,pins = "PH1";
> +				allwinner,function = "gpio_in";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <1>;
> +			};
> +
> +			mmc3_pins_a: mmc3 at 0 {
> +				allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
> +				allwinner,function = "mmc3";
> +				allwinner,drive = <2>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			ir0_pins_a: ir0 at 0 {
> +				    allwinner,pins = "PB3","PB4";
> +				    allwinner,function = "ir0";
> +				    allwinner,drive = <0>;
> +				    allwinner,pull = <0>;
> +			};
> +
> +			ir1_pins_a: ir1 at 0 {
> +				    allwinner,pins = "PB22","PB23";
> +				    allwinner,function = "ir1";
> +				    allwinner,drive = <0>;
> +				    allwinner,pull = <0>;
> +			};
> +		};
> +
> +		timer at 01c20c00 {
> +			compatible = "allwinner,sun4i-a10-timer";
> +			reg = <0x01c20c00 0x90>;
> +			interrupts = <0 22 4>,
> +				     <0 23 4>,
> +				     <0 24 4>,
> +				     <0 25 4>,
> +				     <0 67 4>,
> +				     <0 68 4>;
> +			clocks = <&osc24M>;
> +		};
> +
> +		wdt: watchdog at 01c20c90 {
> +			compatible = "allwinner,sun4i-a10-wdt";
> +			reg = <0x01c20c90 0x10>;
> +		};
> +
> +		rtc: rtc at 01c20d00 {
> +			compatible = "allwinner,sun7i-a20-rtc";
> +			reg = <0x01c20d00 0x20>;
> +			interrupts = <0 24 4>;
> +		};
> +
> +		pwm: pwm at 01c20e00 {
> +			compatible = "allwinner,sun7i-a20-pwm";
> +			reg = <0x01c20e00 0xc>;
> +			clocks = <&osc24M>;
> +			#pwm-cells = <3>;
> +			status = "disabled";
> +		};
> +
> +		ir0: ir at 01c21800 {
> +			compatible = "allwinner,sun4i-a10-ir";
> +			clocks = <&apb0_gates 6>, <&ir0_clk>;
> +			clock-names = "apb", "ir";
> +			interrupts = <0 5 4>;
> +			reg = <0x01c21800 0x40>;
> +			status = "disabled";
> +		};
> +
> +		ir1: ir at 01c21c00 {
> +			compatible = "allwinner,sun4i-a10-ir";
> +			clocks = <&apb0_gates 7>, <&ir1_clk>;
> +			clock-names = "apb", "ir";
> +			interrupts = <0 6 4>;
> +			reg = <0x01c21c00 0x40>;
> +			status = "disabled";
> +		};
> +
> +		sid: eeprom at 01c23800 {
> +			compatible = "allwinner,sun7i-a20-sid";
> +			reg = <0x01c23800 0x200>;
> +		};
> +
> +		rtp: rtp at 01c25000 {
> +			compatible = "allwinner,sun4i-a10-ts";
> +			reg = <0x01c25000 0x100>;
> +			interrupts = <0 29 4>;
> +		};
> +
> +		uart0: serial at 01c28000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28000 0x400>;
> +			interrupts = <0 1 4>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&apb1_gates 16>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial at 01c28400 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28400 0x400>;
> +			interrupts = <0 2 4>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&apb1_gates 17>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial at 01c28800 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28800 0x400>;
> +			interrupts = <0 3 4>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&apb1_gates 18>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial at 01c28c00 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28c00 0x400>;
> +			interrupts = <0 4 4>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&apb1_gates 19>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial at 01c29000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c29000 0x400>;
> +			interrupts = <0 17 4>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&apb1_gates 20>;
> +			status = "disabled";
> +		};
> +
> +		uart5: serial at 01c29400 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c29400 0x400>;
> +			interrupts = <0 18 4>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&apb1_gates 21>;
> +			status = "disabled";
> +		};
> +
> +		uart6: serial at 01c29800 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c29800 0x400>;
> +			interrupts = <0 19 4>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&apb1_gates 22>;
> +			status = "disabled";
> +		};
> +
> +		uart7: serial at 01c29c00 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c29c00 0x400>;
> +			interrupts = <0 20 4>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&apb1_gates 23>;
> +			status = "disabled";
> +		};
> +
> +		i2c0: i2c at 01c2ac00 {
> +			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
> +			reg = <0x01c2ac00 0x400>;
> +			interrupts = <0 7 4>;
> +			clocks = <&apb1_gates 0>;
> +			clock-frequency = <100000>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c1: i2c at 01c2b000 {
> +			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
> +			reg = <0x01c2b000 0x400>;
> +			interrupts = <0 8 4>;
> +			clocks = <&apb1_gates 1>;
> +			clock-frequency = <100000>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c2: i2c at 01c2b400 {
> +			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
> +			reg = <0x01c2b400 0x400>;
> +			interrupts = <0 9 4>;
> +			clocks = <&apb1_gates 2>;
> +			clock-frequency = <100000>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c3: i2c at 01c2b800 {
> +			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
> +			reg = <0x01c2b800 0x400>;
> +			interrupts = <0 88 4>;
> +			clocks = <&apb1_gates 3>;
> +			clock-frequency = <100000>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c4: i2c at 01c2c000 {
> +			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
> +			reg = <0x01c2c000 0x400>;
> +			interrupts = <0 89 4>;
> +			clocks = <&apb1_gates 15>;
> +			clock-frequency = <100000>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		gmac: ethernet at 01c50000 {
> +			compatible = "allwinner,sun7i-a20-gmac";
> +			reg = <0x01c50000 0x10000>;
> +			interrupts = <0 85 4>;
> +			interrupt-names = "macirq";
> +			clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
> +			clock-names = "stmmaceth", "allwinner_gmac_tx";
> +			snps,pbl = <2>;
> +			snps,fixed-burst;
> +			snps,force_sf_dma_mode;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		hstimer at 01c60000 {
> +			compatible = "allwinner,sun7i-a20-hstimer";
> +			reg = <0x01c60000 0x1000>;
> +			interrupts = <0 81 4>,
> +				     <0 82 4>,
> +				     <0 83 4>,
> +				     <0 84 4>;
> +			clocks = <&ahb_gates 28>;
> +		};
> +
> +		gic: interrupt-controller at 01c81000 {
> +			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> +			reg = <0x01c81000 0x1000>,
> +			      <0x01c82000 0x1000>,
> +			      <0x01c84000 0x2000>,
> +			      <0x01c86000 0x2000>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupts = <1 9 0xf04>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/dts/sunxi-common-regulators.dtsi b/arch/arm/dts/sunxi-common-regulators.dtsi
> new file mode 100644
> index 0000000..3d021ef
> --- /dev/null
> +++ b/arch/arm/dts/sunxi-common-regulators.dtsi
> @@ -0,0 +1,89 @@
> +/*
> + * sunxi boards common regulator (ahci target power supply, usb-vbus) code
> + *
> + * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/ {
> +	soc at 01c00000 {
> +		pio: pinctrl at 01c20800 {
> +			ahci_pwr_pin_a: ahci_pwr_pin at 0 {
> +				allwinner,pins = "PB8";
> +				allwinner,function = "gpio_out";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			usb1_vbus_pin_a: usb1_vbus_pin at 0 {
> +				allwinner,pins = "PH6";
> +				allwinner,function = "gpio_out";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			usb2_vbus_pin_a: usb2_vbus_pin at 0 {
> +				allwinner,pins = "PH3";
> +				allwinner,function = "gpio_out";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +		};
> +	};
> +
> +	reg_ahci_5v: ahci-5v {
> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&ahci_pwr_pin_a>;
> +		regulator-name = "ahci-5v";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		enable-active-high;
> +		gpio = <&pio 1 8 0>;
> +		status = "disabled";
> +	};
> +
> +	reg_usb1_vbus: usb1-vbus {
> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&usb1_vbus_pin_a>;
> +		regulator-name = "usb1-vbus";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		enable-active-high;
> +		gpio = <&pio 7 6 0>;
> +		status = "disabled";
> +	};
> +
> +	reg_usb2_vbus: usb2-vbus {
> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&usb2_vbus_pin_a>;
> +		regulator-name = "usb2-vbus";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		enable-active-high;
> +		gpio = <&pio 7 3 0>;
> +		status = "disabled";
> +	};
> +
> +	reg_vcc3v0: vcc3v0 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc3v0";
> +		regulator-min-microvolt = <3000000>;
> +		regulator-max-microvolt = <3000000>;
> +	};
> +
> +	reg_vcc3v3: vcc3v3 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc3v3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +	};
> +};
> diff --git a/include/dt-bindings/input/input.h b/include/dt-bindings/input/input.h
> new file mode 100644
> index 0000000..042e7b3
> --- /dev/null
> +++ b/include/dt-bindings/input/input.h
> @@ -0,0 +1,525 @@
> +/*
> + * This header provides constants for most input bindings.
> + *
> + * Most input bindings include key code, matrix key code format.
> + * In most cases, key code and matrix key code format uses
> + * the standard values/macro defined in this header.
> + */
> +
> +#ifndef _DT_BINDINGS_INPUT_INPUT_H
> +#define _DT_BINDINGS_INPUT_INPUT_H
> +
> +#define KEY_RESERVED		0
> +#define KEY_ESC			1
> +#define KEY_1			2
> +#define KEY_2			3
> +#define KEY_3			4
> +#define KEY_4			5
> +#define KEY_5			6
> +#define KEY_6			7
> +#define KEY_7			8
> +#define KEY_8			9
> +#define KEY_9			10
> +#define KEY_0			11
> +#define KEY_MINUS		12
> +#define KEY_EQUAL		13
> +#define KEY_BACKSPACE		14
> +#define KEY_TAB			15
> +#define KEY_Q			16
> +#define KEY_W			17
> +#define KEY_E			18
> +#define KEY_R			19
> +#define KEY_T			20
> +#define KEY_Y			21
> +#define KEY_U			22
> +#define KEY_I			23
> +#define KEY_O			24
> +#define KEY_P			25
> +#define KEY_LEFTBRACE		26
> +#define KEY_RIGHTBRACE		27
> +#define KEY_ENTER		28
> +#define KEY_LEFTCTRL		29
> +#define KEY_A			30
> +#define KEY_S			31
> +#define KEY_D			32
> +#define KEY_F			33
> +#define KEY_G			34
> +#define KEY_H			35
> +#define KEY_J			36
> +#define KEY_K			37
> +#define KEY_L			38
> +#define KEY_SEMICOLON		39
> +#define KEY_APOSTROPHE		40
> +#define KEY_GRAVE		41
> +#define KEY_LEFTSHIFT		42
> +#define KEY_BACKSLASH		43
> +#define KEY_Z			44
> +#define KEY_X			45
> +#define KEY_C			46
> +#define KEY_V			47
> +#define KEY_B			48
> +#define KEY_N			49
> +#define KEY_M			50
> +#define KEY_COMMA		51
> +#define KEY_DOT			52
> +#define KEY_SLASH		53
> +#define KEY_RIGHTSHIFT		54
> +#define KEY_KPASTERISK		55
> +#define KEY_LEFTALT		56
> +#define KEY_SPACE		57
> +#define KEY_CAPSLOCK		58
> +#define KEY_F1			59
> +#define KEY_F2			60
> +#define KEY_F3			61
> +#define KEY_F4			62
> +#define KEY_F5			63
> +#define KEY_F6			64
> +#define KEY_F7			65
> +#define KEY_F8			66
> +#define KEY_F9			67
> +#define KEY_F10			68
> +#define KEY_NUMLOCK		69
> +#define KEY_SCROLLLOCK		70
> +#define KEY_KP7			71
> +#define KEY_KP8			72
> +#define KEY_KP9			73
> +#define KEY_KPMINUS		74
> +#define KEY_KP4			75
> +#define KEY_KP5			76
> +#define KEY_KP6			77
> +#define KEY_KPPLUS		78
> +#define KEY_KP1			79
> +#define KEY_KP2			80
> +#define KEY_KP3			81
> +#define KEY_KP0			82
> +#define KEY_KPDOT		83
> +
> +#define KEY_ZENKAKUHANKAKU	85
> +#define KEY_102ND		86
> +#define KEY_F11			87
> +#define KEY_F12			88
> +#define KEY_RO			89
> +#define KEY_KATAKANA		90
> +#define KEY_HIRAGANA		91
> +#define KEY_HENKAN		92
> +#define KEY_KATAKANAHIRAGANA	93
> +#define KEY_MUHENKAN		94
> +#define KEY_KPJPCOMMA		95
> +#define KEY_KPENTER		96
> +#define KEY_RIGHTCTRL		97
> +#define KEY_KPSLASH		98
> +#define KEY_SYSRQ		99
> +#define KEY_RIGHTALT		100
> +#define KEY_LINEFEED		101
> +#define KEY_HOME		102
> +#define KEY_UP			103
> +#define KEY_PAGEUP		104
> +#define KEY_LEFT		105
> +#define KEY_RIGHT		106
> +#define KEY_END			107
> +#define KEY_DOWN		108
> +#define KEY_PAGEDOWN		109
> +#define KEY_INSERT		110
> +#define KEY_DELETE		111
> +#define KEY_MACRO		112
> +#define KEY_MUTE		113
> +#define KEY_VOLUMEDOWN		114
> +#define KEY_VOLUMEUP		115
> +#define KEY_POWER		116	/* SC System Power Down */
> +#define KEY_KPEQUAL		117
> +#define KEY_KPPLUSMINUS		118
> +#define KEY_PAUSE		119
> +#define KEY_SCALE		120	/* AL Compiz Scale (Expose) */
> +
> +#define KEY_KPCOMMA		121
> +#define KEY_HANGEUL		122
> +#define KEY_HANGUEL		KEY_HANGEUL
> +#define KEY_HANJA		123
> +#define KEY_YEN			124
> +#define KEY_LEFTMETA		125
> +#define KEY_RIGHTMETA		126
> +#define KEY_COMPOSE		127
> +
> +#define KEY_STOP		128	/* AC Stop */
> +#define KEY_AGAIN		129
> +#define KEY_PROPS		130	/* AC Properties */
> +#define KEY_UNDO		131	/* AC Undo */
> +#define KEY_FRONT		132
> +#define KEY_COPY		133	/* AC Copy */
> +#define KEY_OPEN		134	/* AC Open */
> +#define KEY_PASTE		135	/* AC Paste */
> +#define KEY_FIND		136	/* AC Search */
> +#define KEY_CUT			137	/* AC Cut */
> +#define KEY_HELP		138	/* AL Integrated Help Center */
> +#define KEY_MENU		139	/* Menu (show menu) */
> +#define KEY_CALC		140	/* AL Calculator */
> +#define KEY_SETUP		141
> +#define KEY_SLEEP		142	/* SC System Sleep */
> +#define KEY_WAKEUP		143	/* System Wake Up */
> +#define KEY_FILE		144	/* AL Local Machine Browser */
> +#define KEY_SENDFILE		145
> +#define KEY_DELETEFILE		146
> +#define KEY_XFER		147
> +#define KEY_PROG1		148
> +#define KEY_PROG2		149
> +#define KEY_WWW			150	/* AL Internet Browser */
> +#define KEY_MSDOS		151
> +#define KEY_COFFEE		152	/* AL Terminal Lock/Screensaver */
> +#define KEY_SCREENLOCK		KEY_COFFEE
> +#define KEY_DIRECTION		153
> +#define KEY_CYCLEWINDOWS	154
> +#define KEY_MAIL		155
> +#define KEY_BOOKMARKS		156	/* AC Bookmarks */
> +#define KEY_COMPUTER		157
> +#define KEY_BACK		158	/* AC Back */
> +#define KEY_FORWARD		159	/* AC Forward */
> +#define KEY_CLOSECD		160
> +#define KEY_EJECTCD		161
> +#define KEY_EJECTCLOSECD	162
> +#define KEY_NEXTSONG		163
> +#define KEY_PLAYPAUSE		164
> +#define KEY_PREVIOUSSONG	165
> +#define KEY_STOPCD		166
> +#define KEY_RECORD		167
> +#define KEY_REWIND		168
> +#define KEY_PHONE		169	/* Media Select Telephone */
> +#define KEY_ISO			170
> +#define KEY_CONFIG		171	/* AL Consumer Control Configuration */
> +#define KEY_HOMEPAGE		172	/* AC Home */
> +#define KEY_REFRESH		173	/* AC Refresh */
> +#define KEY_EXIT		174	/* AC Exit */
> +#define KEY_MOVE		175
> +#define KEY_EDIT		176
> +#define KEY_SCROLLUP		177
> +#define KEY_SCROLLDOWN		178
> +#define KEY_KPLEFTPAREN		179
> +#define KEY_KPRIGHTPAREN	180
> +#define KEY_NEW			181	/* AC New */
> +#define KEY_REDO		182	/* AC Redo/Repeat */
> +
> +#define KEY_F13			183
> +#define KEY_F14			184
> +#define KEY_F15			185
> +#define KEY_F16			186
> +#define KEY_F17			187
> +#define KEY_F18			188
> +#define KEY_F19			189
> +#define KEY_F20			190
> +#define KEY_F21			191
> +#define KEY_F22			192
> +#define KEY_F23			193
> +#define KEY_F24			194
> +
> +#define KEY_PLAYCD		200
> +#define KEY_PAUSECD		201
> +#define KEY_PROG3		202
> +#define KEY_PROG4		203
> +#define KEY_DASHBOARD		204	/* AL Dashboard */
> +#define KEY_SUSPEND		205
> +#define KEY_CLOSE		206	/* AC Close */
> +#define KEY_PLAY		207
> +#define KEY_FASTFORWARD		208
> +#define KEY_BASSBOOST		209
> +#define KEY_PRINT		210	/* AC Print */
> +#define KEY_HP			211
> +#define KEY_CAMERA		212
> +#define KEY_SOUND		213
> +#define KEY_QUESTION		214
> +#define KEY_EMAIL		215
> +#define KEY_CHAT		216
> +#define KEY_SEARCH		217
> +#define KEY_CONNECT		218
> +#define KEY_FINANCE		219	/* AL Checkbook/Finance */
> +#define KEY_SPORT		220
> +#define KEY_SHOP		221
> +#define KEY_ALTERASE		222
> +#define KEY_CANCEL		223	/* AC Cancel */
> +#define KEY_BRIGHTNESSDOWN	224
> +#define KEY_BRIGHTNESSUP	225
> +#define KEY_MEDIA		226
> +
> +#define KEY_SWITCHVIDEOMODE	227	/* Cycle between available video
> +					   outputs (Monitor/LCD/TV-out/etc) */
> +#define KEY_KBDILLUMTOGGLE	228
> +#define KEY_KBDILLUMDOWN	229
> +#define KEY_KBDILLUMUP		230
> +
> +#define KEY_SEND		231	/* AC Send */
> +#define KEY_REPLY		232	/* AC Reply */
> +#define KEY_FORWARDMAIL		233	/* AC Forward Msg */
> +#define KEY_SAVE		234	/* AC Save */
> +#define KEY_DOCUMENTS		235
> +
> +#define KEY_BATTERY		236
> +
> +#define KEY_BLUETOOTH		237
> +#define KEY_WLAN		238
> +#define KEY_UWB			239
> +
> +#define KEY_UNKNOWN		240
> +
> +#define KEY_VIDEO_NEXT		241	/* drive next video source */
> +#define KEY_VIDEO_PREV		242	/* drive previous video source */
> +#define KEY_BRIGHTNESS_CYCLE	243	/* brightness up, after max is min */
> +#define KEY_BRIGHTNESS_ZERO	244	/* brightness off, use ambient */
> +#define KEY_DISPLAY_OFF		245	/* display device to off state */
> +
> +#define KEY_WIMAX		246
> +#define KEY_RFKILL		247	/* Key that controls all radios */
> +
> +#define KEY_MICMUTE		248	/* Mute / unmute the microphone */
> +
> +/* Code 255 is reserved for special needs of AT keyboard driver */
> +
> +#define BTN_MISC		0x100
> +#define BTN_0			0x100
> +#define BTN_1			0x101
> +#define BTN_2			0x102
> +#define BTN_3			0x103
> +#define BTN_4			0x104
> +#define BTN_5			0x105
> +#define BTN_6			0x106
> +#define BTN_7			0x107
> +#define BTN_8			0x108
> +#define BTN_9			0x109
> +
> +#define BTN_MOUSE		0x110
> +#define BTN_LEFT		0x110
> +#define BTN_RIGHT		0x111
> +#define BTN_MIDDLE		0x112
> +#define BTN_SIDE		0x113
> +#define BTN_EXTRA		0x114
> +#define BTN_FORWARD		0x115
> +#define BTN_BACK		0x116
> +#define BTN_TASK		0x117
> +
> +#define BTN_JOYSTICK		0x120
> +#define BTN_TRIGGER		0x120
> +#define BTN_THUMB		0x121
> +#define BTN_THUMB2		0x122
> +#define BTN_TOP			0x123
> +#define BTN_TOP2		0x124
> +#define BTN_PINKIE		0x125
> +#define BTN_BASE		0x126
> +#define BTN_BASE2		0x127
> +#define BTN_BASE3		0x128
> +#define BTN_BASE4		0x129
> +#define BTN_BASE5		0x12a
> +#define BTN_BASE6		0x12b
> +#define BTN_DEAD		0x12f
> +
> +#define BTN_GAMEPAD		0x130
> +#define BTN_SOUTH		0x130
> +#define BTN_A			BTN_SOUTH
> +#define BTN_EAST		0x131
> +#define BTN_B			BTN_EAST
> +#define BTN_C			0x132
> +#define BTN_NORTH		0x133
> +#define BTN_X			BTN_NORTH
> +#define BTN_WEST		0x134
> +#define BTN_Y			BTN_WEST
> +#define BTN_Z			0x135
> +#define BTN_TL			0x136
> +#define BTN_TR			0x137
> +#define BTN_TL2			0x138
> +#define BTN_TR2			0x139
> +#define BTN_SELECT		0x13a
> +#define BTN_START		0x13b
> +#define BTN_MODE		0x13c
> +#define BTN_THUMBL		0x13d
> +#define BTN_THUMBR		0x13e
> +
> +#define BTN_DIGI		0x140
> +#define BTN_TOOL_PEN		0x140
> +#define BTN_TOOL_RUBBER		0x141
> +#define BTN_TOOL_BRUSH		0x142
> +#define BTN_TOOL_PENCIL		0x143
> +#define BTN_TOOL_AIRBRUSH	0x144
> +#define BTN_TOOL_FINGER		0x145
> +#define BTN_TOOL_MOUSE		0x146
> +#define BTN_TOOL_LENS		0x147
> +#define BTN_TOOL_QUINTTAP	0x148	/* Five fingers on trackpad */
> +#define BTN_TOUCH		0x14a
> +#define BTN_STYLUS		0x14b
> +#define BTN_STYLUS2		0x14c
> +#define BTN_TOOL_DOUBLETAP	0x14d
> +#define BTN_TOOL_TRIPLETAP	0x14e
> +#define BTN_TOOL_QUADTAP	0x14f	/* Four fingers on trackpad */
> +
> +#define BTN_WHEEL		0x150
> +#define BTN_GEAR_DOWN		0x150
> +#define BTN_GEAR_UP		0x151
> +
> +#define KEY_OK			0x160
> +#define KEY_SELECT		0x161
> +#define KEY_GOTO		0x162
> +#define KEY_CLEAR		0x163
> +#define KEY_POWER2		0x164
> +#define KEY_OPTION		0x165
> +#define KEY_INFO		0x166	/* AL OEM Features/Tips/Tutorial */
> +#define KEY_TIME		0x167
> +#define KEY_VENDOR		0x168
> +#define KEY_ARCHIVE		0x169
> +#define KEY_PROGRAM		0x16a	/* Media Select Program Guide */
> +#define KEY_CHANNEL		0x16b
> +#define KEY_FAVORITES		0x16c
> +#define KEY_EPG			0x16d
> +#define KEY_PVR			0x16e	/* Media Select Home */
> +#define KEY_MHP			0x16f
> +#define KEY_LANGUAGE		0x170
> +#define KEY_TITLE		0x171
> +#define KEY_SUBTITLE		0x172
> +#define KEY_ANGLE		0x173
> +#define KEY_ZOOM		0x174
> +#define KEY_MODE		0x175
> +#define KEY_KEYBOARD		0x176
> +#define KEY_SCREEN		0x177
> +#define KEY_PC			0x178	/* Media Select Computer */
> +#define KEY_TV			0x179	/* Media Select TV */
> +#define KEY_TV2			0x17a	/* Media Select Cable */
> +#define KEY_VCR			0x17b	/* Media Select VCR */
> +#define KEY_VCR2		0x17c	/* VCR Plus */
> +#define KEY_SAT			0x17d	/* Media Select Satellite */
> +#define KEY_SAT2		0x17e
> +#define KEY_CD			0x17f	/* Media Select CD */
> +#define KEY_TAPE		0x180	/* Media Select Tape */
> +#define KEY_RADIO		0x181
> +#define KEY_TUNER		0x182	/* Media Select Tuner */
> +#define KEY_PLAYER		0x183
> +#define KEY_TEXT		0x184
> +#define KEY_DVD			0x185	/* Media Select DVD */
> +#define KEY_AUX			0x186
> +#define KEY_MP3			0x187
> +#define KEY_AUDIO		0x188	/* AL Audio Browser */
> +#define KEY_VIDEO		0x189	/* AL Movie Browser */
> +#define KEY_DIRECTORY		0x18a
> +#define KEY_LIST		0x18b
> +#define KEY_MEMO		0x18c	/* Media Select Messages */
> +#define KEY_CALENDAR		0x18d
> +#define KEY_RED			0x18e
> +#define KEY_GREEN		0x18f
> +#define KEY_YELLOW		0x190
> +#define KEY_BLUE		0x191
> +#define KEY_CHANNELUP		0x192	/* Channel Increment */
> +#define KEY_CHANNELDOWN		0x193	/* Channel Decrement */
> +#define KEY_FIRST		0x194
> +#define KEY_LAST		0x195	/* Recall Last */
> +#define KEY_AB			0x196
> +#define KEY_NEXT		0x197
> +#define KEY_RESTART		0x198
> +#define KEY_SLOW		0x199
> +#define KEY_SHUFFLE		0x19a
> +#define KEY_BREAK		0x19b
> +#define KEY_PREVIOUS		0x19c
> +#define KEY_DIGITS		0x19d
> +#define KEY_TEEN		0x19e
> +#define KEY_TWEN		0x19f
> +#define KEY_VIDEOPHONE		0x1a0	/* Media Select Video Phone */
> +#define KEY_GAMES		0x1a1	/* Media Select Games */
> +#define KEY_ZOOMIN		0x1a2	/* AC Zoom In */
> +#define KEY_ZOOMOUT		0x1a3	/* AC Zoom Out */
> +#define KEY_ZOOMRESET		0x1a4	/* AC Zoom */
> +#define KEY_WORDPROCESSOR	0x1a5	/* AL Word Processor */
> +#define KEY_EDITOR		0x1a6	/* AL Text Editor */
> +#define KEY_SPREADSHEET		0x1a7	/* AL Spreadsheet */
> +#define KEY_GRAPHICSEDITOR	0x1a8	/* AL Graphics Editor */
> +#define KEY_PRESENTATION	0x1a9	/* AL Presentation App */
> +#define KEY_DATABASE		0x1aa	/* AL Database App */
> +#define KEY_NEWS		0x1ab	/* AL Newsreader */
> +#define KEY_VOICEMAIL		0x1ac	/* AL Voicemail */
> +#define KEY_ADDRESSBOOK		0x1ad	/* AL Contacts/Address Book */
> +#define KEY_MESSENGER		0x1ae	/* AL Instant Messaging */
> +#define KEY_DISPLAYTOGGLE	0x1af	/* Turn display (LCD) on and off */
> +#define KEY_SPELLCHECK		0x1b0   /* AL Spell Check */
> +#define KEY_LOGOFF		0x1b1   /* AL Logoff */
> +
> +#define KEY_DOLLAR		0x1b2
> +#define KEY_EURO		0x1b3
> +
> +#define KEY_FRAMEBACK		0x1b4	/* Consumer - transport controls */
> +#define KEY_FRAMEFORWARD	0x1b5
> +#define KEY_CONTEXT_MENU	0x1b6	/* GenDesc - system context menu */
> +#define KEY_MEDIA_REPEAT	0x1b7	/* Consumer - transport control */
> +#define KEY_10CHANNELSUP	0x1b8	/* 10 channels up (10+) */
> +#define KEY_10CHANNELSDOWN	0x1b9	/* 10 channels down (10-) */
> +#define KEY_IMAGES		0x1ba	/* AL Image Browser */
> +
> +#define KEY_DEL_EOL		0x1c0
> +#define KEY_DEL_EOS		0x1c1
> +#define KEY_INS_LINE		0x1c2
> +#define KEY_DEL_LINE		0x1c3
> +
> +#define KEY_FN			0x1d0
> +#define KEY_FN_ESC		0x1d1
> +#define KEY_FN_F1		0x1d2
> +#define KEY_FN_F2		0x1d3
> +#define KEY_FN_F3		0x1d4
> +#define KEY_FN_F4		0x1d5
> +#define KEY_FN_F5		0x1d6
> +#define KEY_FN_F6		0x1d7
> +#define KEY_FN_F7		0x1d8
> +#define KEY_FN_F8		0x1d9
> +#define KEY_FN_F9		0x1da
> +#define KEY_FN_F10		0x1db
> +#define KEY_FN_F11		0x1dc
> +#define KEY_FN_F12		0x1dd
> +#define KEY_FN_1		0x1de
> +#define KEY_FN_2		0x1df
> +#define KEY_FN_D		0x1e0
> +#define KEY_FN_E		0x1e1
> +#define KEY_FN_F		0x1e2
> +#define KEY_FN_S		0x1e3
> +#define KEY_FN_B		0x1e4
> +
> +#define KEY_BRL_DOT1		0x1f1
> +#define KEY_BRL_DOT2		0x1f2
> +#define KEY_BRL_DOT3		0x1f3
> +#define KEY_BRL_DOT4		0x1f4
> +#define KEY_BRL_DOT5		0x1f5
> +#define KEY_BRL_DOT6		0x1f6
> +#define KEY_BRL_DOT7		0x1f7
> +#define KEY_BRL_DOT8		0x1f8
> +#define KEY_BRL_DOT9		0x1f9
> +#define KEY_BRL_DOT10		0x1fa
> +
> +#define KEY_NUMERIC_0		0x200	/* used by phones, remote controls, */
> +#define KEY_NUMERIC_1		0x201	/* and other keypads */
> +#define KEY_NUMERIC_2		0x202
> +#define KEY_NUMERIC_3		0x203
> +#define KEY_NUMERIC_4		0x204
> +#define KEY_NUMERIC_5		0x205
> +#define KEY_NUMERIC_6		0x206
> +#define KEY_NUMERIC_7		0x207
> +#define KEY_NUMERIC_8		0x208
> +#define KEY_NUMERIC_9		0x209
> +#define KEY_NUMERIC_STAR	0x20a
> +#define KEY_NUMERIC_POUND	0x20b
> +
> +#define KEY_CAMERA_FOCUS	0x210
> +#define KEY_WPS_BUTTON		0x211	/* WiFi Protected Setup key */
> +
> +#define KEY_TOUCHPAD_TOGGLE	0x212	/* Request switch touchpad on or off */
> +#define KEY_TOUCHPAD_ON		0x213
> +#define KEY_TOUCHPAD_OFF	0x214
> +
> +#define KEY_CAMERA_ZOOMIN	0x215
> +#define KEY_CAMERA_ZOOMOUT	0x216
> +#define KEY_CAMERA_UP		0x217
> +#define KEY_CAMERA_DOWN		0x218
> +#define KEY_CAMERA_LEFT		0x219
> +#define KEY_CAMERA_RIGHT	0x21a
> +
> +#define KEY_ATTENDANT_ON	0x21b
> +#define KEY_ATTENDANT_OFF	0x21c
> +#define KEY_ATTENDANT_TOGGLE	0x21d	/* Attendant call on or off */
> +#define KEY_LIGHTS_TOGGLE	0x21e	/* Reading light on or off */
> +
> +#define BTN_DPAD_UP		0x220
> +#define BTN_DPAD_DOWN		0x221
> +#define BTN_DPAD_LEFT		0x222
> +#define BTN_DPAD_RIGHT		0x223
> +
> +#define MATRIX_KEY(row, col, code)	\
> +	((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))
> +
> +#endif /* _DT_BINDINGS_INPUT_INPUT_H */
> 

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 2/6] dm: sunxi: Add a new config for an FDT-based pcDuino3
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 2/6] dm: sunxi: Add a new config for an FDT-based pcDuino3 Simon Glass
@ 2014-10-24  8:38   ` Hans de Goede
  2014-10-28  0:04     ` Simon Glass
  0 siblings, 1 reply; 37+ messages in thread
From: Hans de Goede @ 2014-10-24  8:38 UTC (permalink / raw)
  To: u-boot

Hi,

On 10/23/2014 06:02 AM, Simon Glass wrote:
> For now we won't want to mess with the existing configurations. Create a
> new one which will enable device tree and driver model. Note that this
> brings the device tree binary into u-boot-sunxi-with-spl.bin.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
> Changes in v2: None
> 
>  Makefile                                  | 3 ++-
>  arch/arm/dts/Makefile                     | 1 +
>  board/sunxi/MAINTAINERS                   | 1 +
>  configs/Linksprite_pcDuino3_fdt_defconfig | 8 ++++++++
>  include/configs/sun7i.h                   | 4 ++++
>  5 files changed, 16 insertions(+), 1 deletion(-)
>  create mode 100644 configs/Linksprite_pcDuino3_fdt_defconfig
> 
> diff --git a/Makefile b/Makefile
> index 99097e1..816f859 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -941,7 +941,8 @@ u-boot-nand.gph: u-boot.bin FORCE
>  ifneq ($(CONFIG_SUNXI),)
>  OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
>  				   --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
> -u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
> +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \
> +			u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE
>  	$(call if_changed,pad_cat)
>  endif
>  
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 3299817..564eb76 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1,3 +1,4 @@
> +dtb-$(CONFIG_SUN7I) +=  sun7i-a20-pcduino3.dtb

Please make this

dtb-$(CONFIG_PCDUINO3) +=  sun7i-a20-pcduino3.dtb

>  dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
>  dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
>  dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
> diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
> index 4f32195..3dbfe15 100644
> --- a/board/sunxi/MAINTAINERS
> +++ b/board/sunxi/MAINTAINERS
> @@ -21,6 +21,7 @@ F:	configs/A20-OLinuXino_MICRO_defconfig
>  F:	configs/Bananapi_defconfig
>  F:	configs/i12-tvbox_defconfig
>  F:	configs/Linksprite_pcDuino3_defconfig
> +F:	configs/Linksprite_pcDuino3_fdt_defconfig
>  F:	configs/qt840a_defconfig
>  
>  CUBIEBOARD2 BOARD
> diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig
> new file mode 100644
> index 0000000..e5f6236
> --- /dev/null
> +++ b/configs/Linksprite_pcDuino3_fdt_defconfig
> @@ -0,0 +1,8 @@
> +CONFIG_SPL=y
> +CONFIG_SYS_EXTRA_OPTIONS="PCDUINO3,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI,DM"
> +CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
> +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"

Hmm, I don't like this doubling of info. CONFIG_FDTFILE is sort of a sunxi specific thing
here (some other boards have local usage of its too, but it is not used globably.

Can you do a patch (and prepend it to this one in the next posting of this series),
which replaces sunxi's CONFIG_FDTFILE usage with CONFIG_DEFAULT_DEVICE_TREE, dropping
the .dtb appending in the defconfigs and instead append the .dtb in include/configs/sunxi-commom.h

Note sunxi uses CONFIG_FDTFILE in 3 places:

1) board/sunxi/Kconfig
2) various board/*_defconfig files
3) include/configs/sunxi-common.h


> +CONFIG_OF_CONTROL=y
> +CONFIG_OF_SEPARATE=y
> ++S:CONFIG_ARM=y
> ++S:CONFIG_TARGET_SUN7I=y
> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
> index a902b84..500d0e3 100644
> --- a/include/configs/sun7i.h
> +++ b/include/configs/sun7i.h
> @@ -36,6 +36,10 @@
>  #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
>  #define CONFIG_SYS_CLK_FREQ		24000000
>  
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
> +# define CONFIG_CMD_DM
> +#endif
> +

Can you please put this in include/configs/sunxi-common.h instead ?

>  /*
>   * Include common sunxi configuration where most the settings are
>   */
> 

Regards,

Hans

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 3/6] dm: sunxi: Add pinmux functions which take a bank parameter
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 3/6] dm: sunxi: Add pinmux functions which take a bank parameter Simon Glass
@ 2014-10-24  9:00   ` Hans de Goede
  0 siblings, 0 replies; 37+ messages in thread
From: Hans de Goede @ 2014-10-24  9:00 UTC (permalink / raw)
  To: u-boot

Hi,

On 10/23/2014 06:02 AM, Simon Glass wrote:
> With driver model we will have access to a bank pointer, so we want to
> use it rather than converting back to a number, and then back to a
> bank pointer. Add functions to provide this feature.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>

Looks good:

Acked-by: Hans de Goede <hdegoede@redhat.com>

Regards,

Hans


> ---
> 
> Changes in v2: None
> 
>  arch/arm/cpu/armv7/sunxi/pinmux.c      | 32 +++++++++++++++++++++-----------
>  arch/arm/include/asm/arch-sunxi/gpio.h |  4 +++-
>  2 files changed, 24 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c
> index 1f2843f..b026f78 100644
> --- a/arch/arm/cpu/armv7/sunxi/pinmux.c
> +++ b/arch/arm/cpu/armv7/sunxi/pinmux.c
> @@ -10,32 +10,42 @@
>  #include <asm/io.h>
>  #include <asm/arch/gpio.h>
>  
> -int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
> +void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
>  {
> -	u32 bank = GPIO_BANK(pin);
> -	u32 index = GPIO_CFG_INDEX(pin);
> -	u32 offset = GPIO_CFG_OFFSET(pin);
> -	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
> +	u32 index = GPIO_CFG_INDEX(bank_offset);
> +	u32 offset = GPIO_CFG_OFFSET(bank_offset);
>  
>  	clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
> -
> -	return 0;
>  }
>  
> -int sunxi_gpio_get_cfgpin(u32 pin)
> +void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
>  {
> -	u32 cfg;
>  	u32 bank = GPIO_BANK(pin);
> -	u32 index = GPIO_CFG_INDEX(pin);
> -	u32 offset = GPIO_CFG_OFFSET(pin);
>  	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
>  
> +	sunxi_gpio_set_cfgbank(pio, pin, val);
> +}
> +
> +int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
> +{
> +	u32 index = GPIO_CFG_INDEX(bank_offset);
> +	u32 offset = GPIO_CFG_OFFSET(bank_offset);
> +	u32 cfg;
> +
>  	cfg = readl(&pio->cfg[0] + index);
>  	cfg >>= offset;
>  
>  	return cfg & 0xf;
>  }
>  
> +int sunxi_gpio_get_cfgpin(u32 pin)
> +{
> +	u32 bank = GPIO_BANK(pin);
> +	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
> +
> +	return sunxi_gpio_get_cfgbank(pio, pin);
> +}
> +
>  int sunxi_gpio_set_drv(u32 pin, u32 val)
>  {
>  	u32 bank = GPIO_BANK(pin);
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
> index f7f3d8c..f72e2fd 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -139,7 +139,9 @@ enum sunxi_gpio_number {
>  #define SUNXI_GPIO_PULL_UP	1
>  #define SUNXI_GPIO_PULL_DOWN	2
>  
> -int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
> +void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
> +void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
> +int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
>  int sunxi_gpio_get_cfgpin(u32 pin);
>  int sunxi_gpio_set_drv(u32 pin, u32 val);
>  int sunxi_gpio_set_pull(u32 pin, u32 val);
> 

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 4/6] dm: sunxi: Make sure that GPIOs are requested
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 4/6] dm: sunxi: Make sure that GPIOs are requested Simon Glass
@ 2014-10-24  9:01   ` Hans de Goede
  0 siblings, 0 replies; 37+ messages in thread
From: Hans de Goede @ 2014-10-24  9:01 UTC (permalink / raw)
  To: u-boot

Hi,

On 10/23/2014 06:02 AM, Simon Glass wrote:
> The scsi_init() function uses a GPIO so should request it. There is no
> way to return an error here, and the request may be made multiple times,
> so just ignore errors for now.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>

Looks good:

Acked-by: Hans de Goede <hdegoede@redhat.com>

Regards,

Hans

> ---
> 
> Changes in v2: None
> 
>  board/sunxi/ahci.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c
> index 0c262ea..5e12328 100644
> --- a/board/sunxi/ahci.c
> +++ b/board/sunxi/ahci.c
> @@ -74,6 +74,7 @@ void scsi_init(void)
>  {
>  	printf("SUNXI SCSI INIT\n");
>  #ifdef CONFIG_SATAPWR
> +	gpio_request(CONFIG_SATAPWR, "satapwr");
>  	gpio_direction_output(CONFIG_SATAPWR, 1);
>  #endif
>  
> 

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 5/6] dm: sunxi: Modify the GPIO driver to support driver model
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 5/6] dm: sunxi: Modify the GPIO driver to support driver model Simon Glass
@ 2014-10-24  9:08   ` Hans de Goede
  2014-10-28  0:05     ` Simon Glass
  0 siblings, 1 reply; 37+ messages in thread
From: Hans de Goede @ 2014-10-24  9:08 UTC (permalink / raw)
  To: u-boot

Hi,

On 10/23/2014 06:02 AM, Simon Glass wrote:
> This adds driver model support to the sunxi GPIO driver, using the device
> tree to trigger binding of the driver. The driver will still operate
> without driver model too.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
> Changes in v2:
> - Remove references to exynos and tegra
> - Use the word 'bank' instead of 'port'
> 
>  drivers/gpio/sunxi_gpio.c | 170 ++++++++++++++++++++++++++++++++++++++++++++++
>  include/configs/sun7i.h   |   1 +
>  2 files changed, 171 insertions(+)
> 
> diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
> index 0c50a8f..44135e5 100644
> --- a/drivers/gpio/sunxi_gpio.c
> +++ b/drivers/gpio/sunxi_gpio.c
> @@ -11,9 +11,25 @@
>   */
>  
>  #include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <fdtdec.h>
> +#include <malloc.h>
>  #include <asm/io.h>
>  #include <asm/gpio.h>
> +#include <dm/device-internal.h>
>  
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define SUNXI_GPIOS_PER_BANK	SUNXI_GPIO_A_NR
> +
> +struct sunxi_gpio_platdata {
> +	struct sunxi_gpio *regs;
> +	const char *bank_name;	/* Name of bank, e.g. "B" */
> +	int gpio_count;
> +};
> +
> +#ifndef CONFIG_DM_GPIO
>  static int sunxi_gpio_output(u32 pin, u32 val)
>  {
>  	u32 dat;
> @@ -100,3 +116,157 @@ int sunxi_name_to_gpio(const char *name)
>  		return -1;
>  	return group * 32 + pin;
>  }
> +#endif
> +
> +#ifdef CONFIG_DM_GPIO
> +static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
> +{
> +	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
> +
> +	sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
> +
> +	return 0;
> +}
> +
> +static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
> +				       int value)
> +{
> +	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
> +	u32 num = GPIO_NUM(offset);
> +
> +	sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
> +	clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
> +
> +	return 0;
> +}
> +
> +static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
> +{
> +	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
> +	u32 num = GPIO_NUM(offset);
> +	unsigned dat;
> +
> +	dat = readl(&plat->regs->dat);
> +	dat >>= num;
> +
> +	return dat & 0x1;
> +}
> +
> +static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
> +				int value)
> +{
> +	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
> +	u32 num = GPIO_NUM(offset);
> +
> +	clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
> +	return 0;
> +}
> +
> +static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
> +{
> +	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
> +	int func;
> +
> +	func = sunxi_gpio_get_cfgbank(plat->regs, offset);
> +	if (func == SUNXI_GPIO_OUTPUT)
> +		return GPIOF_OUTPUT;
> +	else if (func == SUNXI_GPIO_INPUT)
> +		return GPIOF_INPUT;
> +	else
> +		return GPIOF_FUNC;
> +}
> +
> +static const struct dm_gpio_ops gpio_sunxi_ops = {
> +	.direction_input	= sunxi_gpio_direction_input,
> +	.direction_output	= sunxi_gpio_direction_output,
> +	.get_value		= sunxi_gpio_get_value,
> +	.set_value		= sunxi_gpio_set_value,
> +	.get_function		= sunxi_gpio_get_function,
> +};
> +
> +/**
> + * Returns the name of a GPIO bank
> + *
> + * GPIO banks are named A, B, C, ...
> + *
> + * @bank:	Bank number (0, 1..n-1)
> + * @return allocated string containing the name
> + */
> +static char *gpio_bank_name(int bank)
> +{
> +	char *name;
> +
> +	name = malloc(2);
> +	if (name) {
> +		name[0] = 'A' + bank;
> +		name[1] = '\0';
> +	}
> +
> +	return name;
> +}
> +
> +static int gpio_sunxi_probe(struct udevice *dev)
> +{
> +	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
> +	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
> +
> +	/* Tell the uclass how many GPIOs we have */
> +	if (plat) {
> +		uc_priv->gpio_count = plat->gpio_count;
> +		uc_priv->bank_name = plat->bank_name;
> +	}
> +
> +	return 0;
> +}
> +/**
> + * We have a top-level GPIO device with no actual GPIOs. It has a child
> + * device for each Sunxi bank.
> + */
> +static int gpio_sunxi_bind(struct udevice *parent)
> +{
> +	struct sunxi_gpio_platdata *plat = parent->platdata;
> +	struct sunxi_gpio_reg *ctlr;
> +	int bank;
> +	int ret;
> +
> +	/* If this is a child device, there is nothing to do here */
> +	if (plat)
> +		return 0;
> +
> +	ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd->fdt_blob,
> +						   parent->of_offset, "reg");
> +	for (bank = 0; bank < SUNXI_GPIO_BANKS; bank++) {
> +		struct sunxi_gpio_platdata *plat;
> +		struct udevice *dev;
> +
> +		plat = calloc(1, sizeof(*plat));
> +		if (!plat)
> +			return -ENOMEM;
> +		plat->regs = &ctlr->gpio_bank[bank];
> +		plat->bank_name = gpio_bank_name(bank);
> +		plat->gpio_count = SUNXI_GPIOS_PER_BANK;

This is not correct, a bank have a maximum of 32 gpios but most
have less. I assume that this should be the number of actual pins in
the bank, correct ?

Our "gpio-pin-numbers" are based on a sparse numbering
scheme assuming 32 pins / bank, and there are assumptions this is
the case in various places, so we cannot fix this until we've
fully gone dm for all gpio usage. But here it would be nice
to have the actual numbers of pins.

Doing so requires at least one table with bank -> number of gpio-s
mapping. And I think it may also differ on SoC type in some cases
(I would need to take a look at the datasheets)

I suggest keeping this as is for now, and put fixing this with
a follow up patch on the todo list, and otherwise this looks good,
so this is:

Acked-by: Hans de Goede <hdegoede@redhat.com>



> +
> +		ret = device_bind(parent, parent->driver,
> +					plat->bank_name, plat, -1, &dev);
> +		if (ret)
> +			return ret;
> +		dev->of_offset = parent->of_offset;
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct udevice_id sunxi_gpio_ids[] = {
> +	{ .compatible = "allwinner,sun7i-a20-pinctrl" },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(gpio_sunxi) = {
> +	.name	= "gpio_sunxi",
> +	.id	= UCLASS_GPIO,
> +	.ops	= &gpio_sunxi_ops,
> +	.of_match = sunxi_gpio_ids,
> +	.bind	= gpio_sunxi_bind,
> +	.probe	= gpio_sunxi_probe,
> +};
> +#endif
> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
> index 500d0e3..2314e97 100644
> --- a/include/configs/sun7i.h
> +++ b/include/configs/sun7i.h
> @@ -38,6 +38,7 @@
>  
>  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
>  # define CONFIG_CMD_DM
> +# define CONFIG_DM_GPIO
>  #endif
>  
>  /*
> 

Regards,

Hans

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using " Simon Glass
@ 2014-10-24  9:10   ` Hans de Goede
  2014-10-24  9:42   ` [U-Boot] [PATCH v2 " Ian Campbell
  1 sibling, 0 replies; 37+ messages in thread
From: Hans de Goede @ 2014-10-24  9:10 UTC (permalink / raw)
  To: u-boot

Hi,

On 10/23/2014 06:02 AM, Simon Glass wrote:
> Add a driver for the designware serial UART used on sunxi. This just
> redirects to the normal ns16550 driver.
> 
> Add a stdout-path to the device tree so that the correct UART is chosen.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>

Looks good:

Acked-by: Hans de Goede <hdegoede@redhat.com>

Regards,

Hans

> ---
> 
> Changes in v2:
> - Split non-sunxi patches into a separate dependent series
> 
>  arch/arm/dts/sun7i-a20-pcduino3.dts |  4 ++++
>  drivers/serial/Makefile             |  1 +
>  drivers/serial/serial_dw.c          | 39 +++++++++++++++++++++++++++++++++++++
>  include/configs/sun7i.h             |  3 +++
>  include/configs/sunxi-common.h      | 12 +++++++-----
>  5 files changed, 54 insertions(+), 5 deletions(-)
>  create mode 100644 drivers/serial/serial_dw.c
> 
> diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts
> index 046dfc0..f7cc8e7 100644
> --- a/arch/arm/dts/sun7i-a20-pcduino3.dts
> +++ b/arch/arm/dts/sun7i-a20-pcduino3.dts
> @@ -20,6 +20,10 @@
>  	model = "LinkSprite pcDuino3";
>  	compatible = "linksprite,pcduino3", "allwinner,sun7i-a20";
>  
> +	chosen {
> +		stdout-path = &uart0;
> +	};
> +
>  	soc at 01c00000 {
>  		mmc0: mmc at 01c0f000 {
>  			pinctrl-names = "default";
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index cd87d18..588573a 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_UART) += altera_uart.o
>  obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
>  obj-$(CONFIG_ARM_DCC) += arm_dcc.o
>  obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
> +obj-$(CONFIG_DW_SERIAL) += serial_dw.o
>  obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
>  obj-$(CONFIG_MCFUART) += mcfuart.o
>  obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
> diff --git a/drivers/serial/serial_dw.c b/drivers/serial/serial_dw.c
> new file mode 100644
> index 0000000..a348f29
> --- /dev/null
> +++ b/drivers/serial/serial_dw.c
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright (c) 2014 Google, Inc
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <ns16550.h>
> +#include <serial.h>
> +
> +static const struct udevice_id dw_serial_ids[] = {
> +	{ .compatible = "snps,dw-apb-uart" },
> +	{ }
> +};
> +
> +static int dw_serial_ofdata_to_platdata(struct udevice *dev)
> +{
> +	struct ns16550_platdata *plat = dev_get_platdata(dev);
> +	int ret;
> +
> +	ret = ns16550_serial_ofdata_to_platdata(dev);
> +	if (ret)
> +		return ret;
> +	plat->clock = CONFIG_SYS_NS16550_CLK;
> +
> +	return 0;
> +}
> +
> +U_BOOT_DRIVER(serial_ns16550) = {
> +	.name	= "serial_dw",
> +	.id	= UCLASS_SERIAL,
> +	.of_match = dw_serial_ids,
> +	.ofdata_to_platdata = dw_serial_ofdata_to_platdata,
> +	.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
> +	.priv_auto_alloc_size = sizeof(struct NS16550),
> +	.probe = ns16550_serial_probe,
> +	.ops	= &ns16550_serial_ops,
> +};
> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
> index 2314e97..108694a 100644
> --- a/include/configs/sun7i.h
> +++ b/include/configs/sun7i.h
> @@ -39,6 +39,9 @@
>  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
>  # define CONFIG_CMD_DM
>  # define CONFIG_DM_GPIO
> +# define CONFIG_DM_SERIAL
> +# define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
> +# define CONFIG_DW_SERIAL
>  #endif
>  
>  /*
> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
> index 1d947d7..e26bdf9 100644
> --- a/include/configs/sunxi-common.h
> +++ b/include/configs/sunxi-common.h
> @@ -36,12 +36,14 @@
>  #define CONFIG_SYS_NS16550
>  #define CONFIG_SYS_NS16550_SERIAL
>  /* ns16550 reg in the low bits of cpu reg */
> -#define CONFIG_SYS_NS16550_REG_SIZE	-4
>  #define CONFIG_SYS_NS16550_CLK		24000000
> -#define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
> -#define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
> -#define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
> -#define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
> +#ifndef CONFIG_DM_SERIAL
> +# define CONFIG_SYS_NS16550_REG_SIZE	-4
> +# define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
> +# define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
> +# define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
> +# define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
> +#endif
>  
>  /* DRAM Base */
>  #define CONFIG_SYS_SDRAM_BASE		0x40000000
> 

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-23  4:02 ` [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using " Simon Glass
  2014-10-24  9:10   ` [U-Boot] [U-Boot, v2, " Hans de Goede
@ 2014-10-24  9:42   ` Ian Campbell
  2014-10-28  0:06     ` Simon Glass
  1 sibling, 1 reply; 37+ messages in thread
From: Ian Campbell @ 2014-10-24  9:42 UTC (permalink / raw)
  To: u-boot

On Wed, 2014-10-22 at 22:02 -0600, Simon Glass wrote:
> Add a driver for the designware serial UART used on sunxi. This just
> redirects to the normal ns16550 driver.
> 
> Add a stdout-path to the device tree so that the correct UART is chosen.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>

Should the UART related code in
arch/arm/cpu/armv7/sunxi/board.c:gpio_init() be nobbled in this
configuration?

Ian.

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 2/6] dm: sunxi: Add a new config for an FDT-based pcDuino3
  2014-10-24  8:38   ` [U-Boot] [U-Boot, v2, " Hans de Goede
@ 2014-10-28  0:04     ` Simon Glass
  2014-10-28  9:13       ` Hans de Goede
  0 siblings, 1 reply; 37+ messages in thread
From: Simon Glass @ 2014-10-28  0:04 UTC (permalink / raw)
  To: u-boot

Hi Hans,

On 24 October 2014 02:38, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 10/23/2014 06:02 AM, Simon Glass wrote:
>> For now we won't want to mess with the existing configurations. Create a
>> new one which will enable device tree and driver model. Note that this
>> brings the device tree binary into u-boot-sunxi-with-spl.bin.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2: None
>>
>>  Makefile                                  | 3 ++-
>>  arch/arm/dts/Makefile                     | 1 +
>>  board/sunxi/MAINTAINERS                   | 1 +
>>  configs/Linksprite_pcDuino3_fdt_defconfig | 8 ++++++++
>>  include/configs/sun7i.h                   | 4 ++++
>>  5 files changed, 16 insertions(+), 1 deletion(-)
>>  create mode 100644 configs/Linksprite_pcDuino3_fdt_defconfig
>>
>> diff --git a/Makefile b/Makefile
>> index 99097e1..816f859 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -941,7 +941,8 @@ u-boot-nand.gph: u-boot.bin FORCE
>>  ifneq ($(CONFIG_SUNXI),)
>>  OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
>>                                  --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
>> -u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
>> +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \
>> +                     u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE
>>       $(call if_changed,pad_cat)
>>  endif
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index 3299817..564eb76 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -1,3 +1,4 @@
>> +dtb-$(CONFIG_SUN7I) +=  sun7i-a20-pcduino3.dtb
>
> Please make this
>
> dtb-$(CONFIG_PCDUINO3) +=  sun7i-a20-pcduino3.dtb

Well I can do that, but this should have no effect if we don't define
CONFIG_OF_CONTROL. The way I have it we will be able to add more
device tree files for sun7x without anyone having to change it. The
target should build all sun7i device trees eventually.

>
>>  dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
>>  dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
>>  dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
>> diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
>> index 4f32195..3dbfe15 100644
>> --- a/board/sunxi/MAINTAINERS
>> +++ b/board/sunxi/MAINTAINERS
>> @@ -21,6 +21,7 @@ F:  configs/A20-OLinuXino_MICRO_defconfig
>>  F:   configs/Bananapi_defconfig
>>  F:   configs/i12-tvbox_defconfig
>>  F:   configs/Linksprite_pcDuino3_defconfig
>> +F:   configs/Linksprite_pcDuino3_fdt_defconfig
>>  F:   configs/qt840a_defconfig
>>
>>  CUBIEBOARD2 BOARD
>> diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig
>> new file mode 100644
>> index 0000000..e5f6236
>> --- /dev/null
>> +++ b/configs/Linksprite_pcDuino3_fdt_defconfig
>> @@ -0,0 +1,8 @@
>> +CONFIG_SPL=y
>> +CONFIG_SYS_EXTRA_OPTIONS="PCDUINO3,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI,DM"
>> +CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
>> +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
>
> Hmm, I don't like this doubling of info. CONFIG_FDTFILE is sort of a sunxi specific thing
> here (some other boards have local usage of its too, but it is not used globably.
>
> Can you do a patch (and prepend it to this one in the next posting of this series),
> which replaces sunxi's CONFIG_FDTFILE usage with CONFIG_DEFAULT_DEVICE_TREE, dropping
> the .dtb appending in the defconfigs and instead append the .dtb in include/configs/sunxi-commom.h
>
> Note sunxi uses CONFIG_FDTFILE in 3 places:
>
> 1) board/sunxi/Kconfig
> 2) various board/*_defconfig files
> 3) include/configs/sunxi-common.h

But isn't that used for passing to the kernel? Do you want to drop the
ability to have a separate file for each?

>
>
>> +CONFIG_OF_CONTROL=y
>> +CONFIG_OF_SEPARATE=y
>> ++S:CONFIG_ARM=y
>> ++S:CONFIG_TARGET_SUN7I=y
>> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
>> index a902b84..500d0e3 100644
>> --- a/include/configs/sun7i.h
>> +++ b/include/configs/sun7i.h
>> @@ -36,6 +36,10 @@
>>  #define CONFIG_ARMV7_SECURE_BASE     SUNXI_SRAM_B_BASE
>>  #define CONFIG_SYS_CLK_FREQ          24000000
>>
>> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
>> +# define CONFIG_CMD_DM
>> +#endif
>> +
>
> Can you please put this in include/configs/sunxi-common.h instead ?

OK will do.

>
>>  /*
>>   * Include common sunxi configuration where most the settings are
>>   */

Regards,
Simon

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 5/6] dm: sunxi: Modify the GPIO driver to support driver model
  2014-10-24  9:08   ` [U-Boot] [U-Boot, v2, " Hans de Goede
@ 2014-10-28  0:05     ` Simon Glass
  2014-10-28  2:53       ` Chen-Yu Tsai
  0 siblings, 1 reply; 37+ messages in thread
From: Simon Glass @ 2014-10-28  0:05 UTC (permalink / raw)
  To: u-boot

Hi Hans,

On 24 October 2014 03:08, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 10/23/2014 06:02 AM, Simon Glass wrote:
>> This adds driver model support to the sunxi GPIO driver, using the device
>> tree to trigger binding of the driver. The driver will still operate
>> without driver model too.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Remove references to exynos and tegra
>> - Use the word 'bank' instead of 'port'
>>
>>  drivers/gpio/sunxi_gpio.c | 170 ++++++++++++++++++++++++++++++++++++++++++++++
>>  include/configs/sun7i.h   |   1 +
>>  2 files changed, 171 insertions(+)
>>
>> diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
>> index 0c50a8f..44135e5 100644
>> --- a/drivers/gpio/sunxi_gpio.c
>> +++ b/drivers/gpio/sunxi_gpio.c
>> @@ -11,9 +11,25 @@
>>   */
>>
>>  #include <common.h>
>> +#include <dm.h>
>> +#include <errno.h>
>> +#include <fdtdec.h>
>> +#include <malloc.h>
>>  #include <asm/io.h>
>>  #include <asm/gpio.h>
>> +#include <dm/device-internal.h>
>>
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
>> +
>> +struct sunxi_gpio_platdata {
>> +     struct sunxi_gpio *regs;
>> +     const char *bank_name;  /* Name of bank, e.g. "B" */
>> +     int gpio_count;
>> +};
>> +
>> +#ifndef CONFIG_DM_GPIO
>>  static int sunxi_gpio_output(u32 pin, u32 val)
>>  {
>>       u32 dat;
>> @@ -100,3 +116,157 @@ int sunxi_name_to_gpio(const char *name)
>>               return -1;
>>       return group * 32 + pin;
>>  }
>> +#endif
>> +
>> +#ifdef CONFIG_DM_GPIO
>> +static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
>> +{
>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>> +
>> +     sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
>> +
>> +     return 0;
>> +}
>> +
>> +static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
>> +                                    int value)
>> +{
>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>> +     u32 num = GPIO_NUM(offset);
>> +
>> +     sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
>> +     clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
>> +
>> +     return 0;
>> +}
>> +
>> +static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
>> +{
>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>> +     u32 num = GPIO_NUM(offset);
>> +     unsigned dat;
>> +
>> +     dat = readl(&plat->regs->dat);
>> +     dat >>= num;
>> +
>> +     return dat & 0x1;
>> +}
>> +
>> +static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
>> +                             int value)
>> +{
>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>> +     u32 num = GPIO_NUM(offset);
>> +
>> +     clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
>> +     return 0;
>> +}
>> +
>> +static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
>> +{
>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>> +     int func;
>> +
>> +     func = sunxi_gpio_get_cfgbank(plat->regs, offset);
>> +     if (func == SUNXI_GPIO_OUTPUT)
>> +             return GPIOF_OUTPUT;
>> +     else if (func == SUNXI_GPIO_INPUT)
>> +             return GPIOF_INPUT;
>> +     else
>> +             return GPIOF_FUNC;
>> +}
>> +
>> +static const struct dm_gpio_ops gpio_sunxi_ops = {
>> +     .direction_input        = sunxi_gpio_direction_input,
>> +     .direction_output       = sunxi_gpio_direction_output,
>> +     .get_value              = sunxi_gpio_get_value,
>> +     .set_value              = sunxi_gpio_set_value,
>> +     .get_function           = sunxi_gpio_get_function,
>> +};
>> +
>> +/**
>> + * Returns the name of a GPIO bank
>> + *
>> + * GPIO banks are named A, B, C, ...
>> + *
>> + * @bank:    Bank number (0, 1..n-1)
>> + * @return allocated string containing the name
>> + */
>> +static char *gpio_bank_name(int bank)
>> +{
>> +     char *name;
>> +
>> +     name = malloc(2);
>> +     if (name) {
>> +             name[0] = 'A' + bank;
>> +             name[1] = '\0';
>> +     }
>> +
>> +     return name;
>> +}
>> +
>> +static int gpio_sunxi_probe(struct udevice *dev)
>> +{
>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>> +     struct gpio_dev_priv *uc_priv = dev->uclass_priv;
>> +
>> +     /* Tell the uclass how many GPIOs we have */
>> +     if (plat) {
>> +             uc_priv->gpio_count = plat->gpio_count;
>> +             uc_priv->bank_name = plat->bank_name;
>> +     }
>> +
>> +     return 0;
>> +}
>> +/**
>> + * We have a top-level GPIO device with no actual GPIOs. It has a child
>> + * device for each Sunxi bank.
>> + */
>> +static int gpio_sunxi_bind(struct udevice *parent)
>> +{
>> +     struct sunxi_gpio_platdata *plat = parent->platdata;
>> +     struct sunxi_gpio_reg *ctlr;
>> +     int bank;
>> +     int ret;
>> +
>> +     /* If this is a child device, there is nothing to do here */
>> +     if (plat)
>> +             return 0;
>> +
>> +     ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd->fdt_blob,
>> +                                                parent->of_offset, "reg");
>> +     for (bank = 0; bank < SUNXI_GPIO_BANKS; bank++) {
>> +             struct sunxi_gpio_platdata *plat;
>> +             struct udevice *dev;
>> +
>> +             plat = calloc(1, sizeof(*plat));
>> +             if (!plat)
>> +                     return -ENOMEM;
>> +             plat->regs = &ctlr->gpio_bank[bank];
>> +             plat->bank_name = gpio_bank_name(bank);
>> +             plat->gpio_count = SUNXI_GPIOS_PER_BANK;
>
> This is not correct, a bank have a maximum of 32 gpios but most
> have less. I assume that this should be the number of actual pins in
> the bank, correct ?

Well I worry that we need to maintain compatibility with what is
there. At some point we can change it, but for now the GPIO numbering
is done assuming 32 GPIOs per bank, right?

When everything is moved to driver model I suppose we can be more clever.

>
> Our "gpio-pin-numbers" are based on a sparse numbering
> scheme assuming 32 pins / bank, and there are assumptions this is
> the case in various places, so we cannot fix this until we've
> fully gone dm for all gpio usage. But here it would be nice
> to have the actual numbers of pins.
>
> Doing so requires at least one table with bank -> number of gpio-s
> mapping. And I think it may also differ on SoC type in some cases
> (I would need to take a look at the datasheets)

Hoping this can be in the device tree. Do you have a binding for it?

>
> I suggest keeping this as is for now, and put fixing this with
> a follow up patch on the todo list, and otherwise this looks good,
> so this is:
>
> Acked-by: Hans de Goede <hdegoede@redhat.com>

OK

>
>
>
>> +
>> +             ret = device_bind(parent, parent->driver,
>> +                                     plat->bank_name, plat, -1, &dev);
>> +             if (ret)
>> +                     return ret;
>> +             dev->of_offset = parent->of_offset;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +static const struct udevice_id sunxi_gpio_ids[] = {
>> +     { .compatible = "allwinner,sun7i-a20-pinctrl" },
>> +     { }
>> +};
>> +
>> +U_BOOT_DRIVER(gpio_sunxi) = {
>> +     .name   = "gpio_sunxi",
>> +     .id     = UCLASS_GPIO,
>> +     .ops    = &gpio_sunxi_ops,
>> +     .of_match = sunxi_gpio_ids,
>> +     .bind   = gpio_sunxi_bind,
>> +     .probe  = gpio_sunxi_probe,
>> +};
>> +#endif
>> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
>> index 500d0e3..2314e97 100644
>> --- a/include/configs/sun7i.h
>> +++ b/include/configs/sun7i.h
>> @@ -38,6 +38,7 @@
>>
>>  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
>>  # define CONFIG_CMD_DM
>> +# define CONFIG_DM_GPIO
>>  #endif
>>
>>  /*
>>
>
> Regards,
>
> Hans

Regards,
Simon

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-24  9:42   ` [U-Boot] [PATCH v2 " Ian Campbell
@ 2014-10-28  0:06     ` Simon Glass
  2014-10-29  8:05       ` Ian Campbell
  0 siblings, 1 reply; 37+ messages in thread
From: Simon Glass @ 2014-10-28  0:06 UTC (permalink / raw)
  To: u-boot

Hi Ian,

On 24 October 2014 03:42, Ian Campbell <ijc@hellion.org.uk> wrote:
> On Wed, 2014-10-22 at 22:02 -0600, Simon Glass wrote:
>> Add a driver for the designware serial UART used on sunxi. This just
>> redirects to the normal ns16550 driver.
>>
>> Add a stdout-path to the device tree so that the correct UART is chosen.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>
> Should the UART related code in
> arch/arm/cpu/armv7/sunxi/board.c:gpio_init() be nobbled in this
> configuration?

Yes I think that needs attention. Ideally we should be able to have
this handled by the serial driver (requesting the pinmux it needs) but
we don't have infrastructure for that as yet. Suggestions? What does
the kernel do here?

Regards,
Simon

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 1/6] dm: sunxi: dts: Add sun7i device tree files
  2014-10-24  8:32   ` [U-Boot] [U-Boot, v2, " Hans de Goede
@ 2014-10-28  1:05     ` Simon Glass
  0 siblings, 0 replies; 37+ messages in thread
From: Simon Glass @ 2014-10-28  1:05 UTC (permalink / raw)
  To: u-boot

Hi Hans,

On 24 October 2014 02:32, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 10/23/2014 06:02 AM, Simon Glass wrote:
>> These are from Linux 3.17-rc7 (commit fe82dcec). U-Boot only uses a small
>> portion of these, but we may as well have something to look forward to.
>>
>> The total compiled size is about 25KB.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>
> Looks good:
>
> Acked-by: Hans de Goede <hdegoede@redhat.com>
>
> I assume we should wait with applying this series until the next
> dm merge ?

Yes, this has just happened. But I need to respin this series.

[snip]

Regards,
Simon

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 5/6] dm: sunxi: Modify the GPIO driver to support driver model
  2014-10-28  0:05     ` Simon Glass
@ 2014-10-28  2:53       ` Chen-Yu Tsai
  2014-10-28  3:29         ` Simon Glass
  0 siblings, 1 reply; 37+ messages in thread
From: Chen-Yu Tsai @ 2014-10-28  2:53 UTC (permalink / raw)
  To: u-boot

Hi,

On Tue, Oct 28, 2014 at 8:05 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Hans,
>
> On 24 October 2014 03:08, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 10/23/2014 06:02 AM, Simon Glass wrote:
>>> This adds driver model support to the sunxi GPIO driver, using the device
>>> tree to trigger binding of the driver. The driver will still operate
>>> without driver model too.
>>>
>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>> ---
>>>
>>> Changes in v2:
>>> - Remove references to exynos and tegra
>>> - Use the word 'bank' instead of 'port'
>>>
>>>  drivers/gpio/sunxi_gpio.c | 170 ++++++++++++++++++++++++++++++++++++++++++++++
>>>  include/configs/sun7i.h   |   1 +
>>>  2 files changed, 171 insertions(+)
>>>
>>> diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
>>> index 0c50a8f..44135e5 100644
>>> --- a/drivers/gpio/sunxi_gpio.c
>>> +++ b/drivers/gpio/sunxi_gpio.c
>>> @@ -11,9 +11,25 @@
>>>   */
>>>
>>>  #include <common.h>
>>> +#include <dm.h>
>>> +#include <errno.h>
>>> +#include <fdtdec.h>
>>> +#include <malloc.h>
>>>  #include <asm/io.h>
>>>  #include <asm/gpio.h>
>>> +#include <dm/device-internal.h>
>>>
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
>>> +
>>> +struct sunxi_gpio_platdata {
>>> +     struct sunxi_gpio *regs;
>>> +     const char *bank_name;  /* Name of bank, e.g. "B" */
>>> +     int gpio_count;
>>> +};
>>> +
>>> +#ifndef CONFIG_DM_GPIO
>>>  static int sunxi_gpio_output(u32 pin, u32 val)
>>>  {
>>>       u32 dat;
>>> @@ -100,3 +116,157 @@ int sunxi_name_to_gpio(const char *name)
>>>               return -1;
>>>       return group * 32 + pin;
>>>  }
>>> +#endif
>>> +
>>> +#ifdef CONFIG_DM_GPIO
>>> +static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
>>> +{
>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>> +
>>> +     sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
>>> +
>>> +     return 0;
>>> +}
>>> +
>>> +static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
>>> +                                    int value)
>>> +{
>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>> +     u32 num = GPIO_NUM(offset);
>>> +
>>> +     sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
>>> +     clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
>>> +
>>> +     return 0;
>>> +}
>>> +
>>> +static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
>>> +{
>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>> +     u32 num = GPIO_NUM(offset);
>>> +     unsigned dat;
>>> +
>>> +     dat = readl(&plat->regs->dat);
>>> +     dat >>= num;
>>> +
>>> +     return dat & 0x1;
>>> +}
>>> +
>>> +static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
>>> +                             int value)
>>> +{
>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>> +     u32 num = GPIO_NUM(offset);
>>> +
>>> +     clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
>>> +     return 0;
>>> +}
>>> +
>>> +static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
>>> +{
>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>> +     int func;
>>> +
>>> +     func = sunxi_gpio_get_cfgbank(plat->regs, offset);
>>> +     if (func == SUNXI_GPIO_OUTPUT)
>>> +             return GPIOF_OUTPUT;
>>> +     else if (func == SUNXI_GPIO_INPUT)
>>> +             return GPIOF_INPUT;
>>> +     else
>>> +             return GPIOF_FUNC;
>>> +}
>>> +
>>> +static const struct dm_gpio_ops gpio_sunxi_ops = {
>>> +     .direction_input        = sunxi_gpio_direction_input,
>>> +     .direction_output       = sunxi_gpio_direction_output,
>>> +     .get_value              = sunxi_gpio_get_value,
>>> +     .set_value              = sunxi_gpio_set_value,
>>> +     .get_function           = sunxi_gpio_get_function,
>>> +};
>>> +
>>> +/**
>>> + * Returns the name of a GPIO bank
>>> + *
>>> + * GPIO banks are named A, B, C, ...
>>> + *
>>> + * @bank:    Bank number (0, 1..n-1)
>>> + * @return allocated string containing the name
>>> + */
>>> +static char *gpio_bank_name(int bank)
>>> +{
>>> +     char *name;
>>> +
>>> +     name = malloc(2);
>>> +     if (name) {
>>> +             name[0] = 'A' + bank;
>>> +             name[1] = '\0';
>>> +     }
>>> +
>>> +     return name;
>>> +}
>>> +
>>> +static int gpio_sunxi_probe(struct udevice *dev)
>>> +{
>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>> +     struct gpio_dev_priv *uc_priv = dev->uclass_priv;
>>> +
>>> +     /* Tell the uclass how many GPIOs we have */
>>> +     if (plat) {
>>> +             uc_priv->gpio_count = plat->gpio_count;
>>> +             uc_priv->bank_name = plat->bank_name;
>>> +     }
>>> +
>>> +     return 0;
>>> +}
>>> +/**
>>> + * We have a top-level GPIO device with no actual GPIOs. It has a child
>>> + * device for each Sunxi bank.
>>> + */
>>> +static int gpio_sunxi_bind(struct udevice *parent)
>>> +{
>>> +     struct sunxi_gpio_platdata *plat = parent->platdata;
>>> +     struct sunxi_gpio_reg *ctlr;
>>> +     int bank;
>>> +     int ret;
>>> +
>>> +     /* If this is a child device, there is nothing to do here */
>>> +     if (plat)
>>> +             return 0;
>>> +
>>> +     ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd->fdt_blob,
>>> +                                                parent->of_offset, "reg");
>>> +     for (bank = 0; bank < SUNXI_GPIO_BANKS; bank++) {
>>> +             struct sunxi_gpio_platdata *plat;
>>> +             struct udevice *dev;
>>> +
>>> +             plat = calloc(1, sizeof(*plat));
>>> +             if (!plat)
>>> +                     return -ENOMEM;
>>> +             plat->regs = &ctlr->gpio_bank[bank];
>>> +             plat->bank_name = gpio_bank_name(bank);
>>> +             plat->gpio_count = SUNXI_GPIOS_PER_BANK;
>>
>> This is not correct, a bank have a maximum of 32 gpios but most
>> have less. I assume that this should be the number of actual pins in
>> the bank, correct ?
>
> Well I worry that we need to maintain compatibility with what is
> there. At some point we can change it, but for now the GPIO numbering
> is done assuming 32 GPIOs per bank, right?

The numbering always assumed 32 GPIOs per bank, just some of them may
be empty. IMHO it simplifies register/bit offset conversions, and
it's easier to convert the numbers to the designations in the datasheet
by hand, for example PA0 = 0, PB0 = 32.

We also do this in the kernel driver. But the bindings are 3 cell:
<bank pin flags>.

> When everything is moved to driver model I suppose we can be more clever.
>
>>
>> Our "gpio-pin-numbers" are based on a sparse numbering
>> scheme assuming 32 pins / bank, and there are assumptions this is
>> the case in various places, so we cannot fix this until we've
>> fully gone dm for all gpio usage. But here it would be nice
>> to have the actual numbers of pins.
>>
>> Doing so requires at least one table with bank -> number of gpio-s
>> mapping. And I think it may also differ on SoC type in some cases
>> (I would need to take a look at the datasheets)
>
> Hoping this can be in the device tree. Do you have a binding for it?

This is in the (kernel) driver, not the device tree bindings.
So we would need to at least add a table for that.

I don't see any pinmux related stuff in this patch. Does the gpio
dm handle that?


ChenYu

>>
>> I suggest keeping this as is for now, and put fixing this with
>> a follow up patch on the todo list, and otherwise this looks good,
>> so this is:
>>
>> Acked-by: Hans de Goede <hdegoede@redhat.com>
>
> OK
>
>>
>>
>>
>>> +
>>> +             ret = device_bind(parent, parent->driver,
>>> +                                     plat->bank_name, plat, -1, &dev);
>>> +             if (ret)
>>> +                     return ret;
>>> +             dev->of_offset = parent->of_offset;
>>> +     }
>>> +
>>> +     return 0;
>>> +}
>>> +
>>> +static const struct udevice_id sunxi_gpio_ids[] = {
>>> +     { .compatible = "allwinner,sun7i-a20-pinctrl" },
>>> +     { }
>>> +};
>>> +
>>> +U_BOOT_DRIVER(gpio_sunxi) = {
>>> +     .name   = "gpio_sunxi",
>>> +     .id     = UCLASS_GPIO,
>>> +     .ops    = &gpio_sunxi_ops,
>>> +     .of_match = sunxi_gpio_ids,
>>> +     .bind   = gpio_sunxi_bind,
>>> +     .probe  = gpio_sunxi_probe,
>>> +};
>>> +#endif
>>> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
>>> index 500d0e3..2314e97 100644
>>> --- a/include/configs/sun7i.h
>>> +++ b/include/configs/sun7i.h
>>> @@ -38,6 +38,7 @@
>>>
>>>  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
>>>  # define CONFIG_CMD_DM
>>> +# define CONFIG_DM_GPIO
>>>  #endif
>>>
>>>  /*

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 5/6] dm: sunxi: Modify the GPIO driver to support driver model
  2014-10-28  2:53       ` Chen-Yu Tsai
@ 2014-10-28  3:29         ` Simon Glass
  2014-10-28  3:39           ` Chen-Yu Tsai
  0 siblings, 1 reply; 37+ messages in thread
From: Simon Glass @ 2014-10-28  3:29 UTC (permalink / raw)
  To: u-boot

Hi Chen-Yu,

On 27 October 2014 20:53, Chen-Yu Tsai <wens@csie.org> wrote:
> Hi,
>
> On Tue, Oct 28, 2014 at 8:05 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Hans,
>>
>> On 24 October 2014 03:08, Hans de Goede <hdegoede@redhat.com> wrote:
>>> Hi,
>>>
>>> On 10/23/2014 06:02 AM, Simon Glass wrote:
>>>> This adds driver model support to the sunxi GPIO driver, using the device
>>>> tree to trigger binding of the driver. The driver will still operate
>>>> without driver model too.
>>>>
>>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>>> ---
>>>>
>>>> Changes in v2:
>>>> - Remove references to exynos and tegra
>>>> - Use the word 'bank' instead of 'port'
>>>>
>>>>  drivers/gpio/sunxi_gpio.c | 170 ++++++++++++++++++++++++++++++++++++++++++++++
>>>>  include/configs/sun7i.h   |   1 +
>>>>  2 files changed, 171 insertions(+)
>>>>
>>>> diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
>>>> index 0c50a8f..44135e5 100644
>>>> --- a/drivers/gpio/sunxi_gpio.c
>>>> +++ b/drivers/gpio/sunxi_gpio.c
>>>> @@ -11,9 +11,25 @@
>>>>   */
>>>>
>>>>  #include <common.h>
>>>> +#include <dm.h>
>>>> +#include <errno.h>
>>>> +#include <fdtdec.h>
>>>> +#include <malloc.h>
>>>>  #include <asm/io.h>
>>>>  #include <asm/gpio.h>
>>>> +#include <dm/device-internal.h>
>>>>
>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>> +
>>>> +#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
>>>> +
>>>> +struct sunxi_gpio_platdata {
>>>> +     struct sunxi_gpio *regs;
>>>> +     const char *bank_name;  /* Name of bank, e.g. "B" */
>>>> +     int gpio_count;
>>>> +};
>>>> +
>>>> +#ifndef CONFIG_DM_GPIO
>>>>  static int sunxi_gpio_output(u32 pin, u32 val)
>>>>  {
>>>>       u32 dat;
>>>> @@ -100,3 +116,157 @@ int sunxi_name_to_gpio(const char *name)
>>>>               return -1;
>>>>       return group * 32 + pin;
>>>>  }
>>>> +#endif
>>>> +
>>>> +#ifdef CONFIG_DM_GPIO
>>>> +static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
>>>> +{
>>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>>> +
>>>> +     sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
>>>> +
>>>> +     return 0;
>>>> +}
>>>> +
>>>> +static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
>>>> +                                    int value)
>>>> +{
>>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>>> +     u32 num = GPIO_NUM(offset);
>>>> +
>>>> +     sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
>>>> +     clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
>>>> +
>>>> +     return 0;
>>>> +}
>>>> +
>>>> +static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
>>>> +{
>>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>>> +     u32 num = GPIO_NUM(offset);
>>>> +     unsigned dat;
>>>> +
>>>> +     dat = readl(&plat->regs->dat);
>>>> +     dat >>= num;
>>>> +
>>>> +     return dat & 0x1;
>>>> +}
>>>> +
>>>> +static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
>>>> +                             int value)
>>>> +{
>>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>>> +     u32 num = GPIO_NUM(offset);
>>>> +
>>>> +     clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
>>>> +     return 0;
>>>> +}
>>>> +
>>>> +static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
>>>> +{
>>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>>> +     int func;
>>>> +
>>>> +     func = sunxi_gpio_get_cfgbank(plat->regs, offset);
>>>> +     if (func == SUNXI_GPIO_OUTPUT)
>>>> +             return GPIOF_OUTPUT;
>>>> +     else if (func == SUNXI_GPIO_INPUT)
>>>> +             return GPIOF_INPUT;
>>>> +     else
>>>> +             return GPIOF_FUNC;
>>>> +}
>>>> +
>>>> +static const struct dm_gpio_ops gpio_sunxi_ops = {
>>>> +     .direction_input        = sunxi_gpio_direction_input,
>>>> +     .direction_output       = sunxi_gpio_direction_output,
>>>> +     .get_value              = sunxi_gpio_get_value,
>>>> +     .set_value              = sunxi_gpio_set_value,
>>>> +     .get_function           = sunxi_gpio_get_function,
>>>> +};
>>>> +
>>>> +/**
>>>> + * Returns the name of a GPIO bank
>>>> + *
>>>> + * GPIO banks are named A, B, C, ...
>>>> + *
>>>> + * @bank:    Bank number (0, 1..n-1)
>>>> + * @return allocated string containing the name
>>>> + */
>>>> +static char *gpio_bank_name(int bank)
>>>> +{
>>>> +     char *name;
>>>> +
>>>> +     name = malloc(2);
>>>> +     if (name) {
>>>> +             name[0] = 'A' + bank;
>>>> +             name[1] = '\0';
>>>> +     }
>>>> +
>>>> +     return name;
>>>> +}
>>>> +
>>>> +static int gpio_sunxi_probe(struct udevice *dev)
>>>> +{
>>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>>> +     struct gpio_dev_priv *uc_priv = dev->uclass_priv;
>>>> +
>>>> +     /* Tell the uclass how many GPIOs we have */
>>>> +     if (plat) {
>>>> +             uc_priv->gpio_count = plat->gpio_count;
>>>> +             uc_priv->bank_name = plat->bank_name;
>>>> +     }
>>>> +
>>>> +     return 0;
>>>> +}
>>>> +/**
>>>> + * We have a top-level GPIO device with no actual GPIOs. It has a child
>>>> + * device for each Sunxi bank.
>>>> + */
>>>> +static int gpio_sunxi_bind(struct udevice *parent)
>>>> +{
>>>> +     struct sunxi_gpio_platdata *plat = parent->platdata;
>>>> +     struct sunxi_gpio_reg *ctlr;
>>>> +     int bank;
>>>> +     int ret;
>>>> +
>>>> +     /* If this is a child device, there is nothing to do here */
>>>> +     if (plat)
>>>> +             return 0;
>>>> +
>>>> +     ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd->fdt_blob,
>>>> +                                                parent->of_offset, "reg");
>>>> +     for (bank = 0; bank < SUNXI_GPIO_BANKS; bank++) {
>>>> +             struct sunxi_gpio_platdata *plat;
>>>> +             struct udevice *dev;
>>>> +
>>>> +             plat = calloc(1, sizeof(*plat));
>>>> +             if (!plat)
>>>> +                     return -ENOMEM;
>>>> +             plat->regs = &ctlr->gpio_bank[bank];
>>>> +             plat->bank_name = gpio_bank_name(bank);
>>>> +             plat->gpio_count = SUNXI_GPIOS_PER_BANK;
>>>
>>> This is not correct, a bank have a maximum of 32 gpios but most
>>> have less. I assume that this should be the number of actual pins in
>>> the bank, correct ?
>>
>> Well I worry that we need to maintain compatibility with what is
>> there. At some point we can change it, but for now the GPIO numbering
>> is done assuming 32 GPIOs per bank, right?
>
> The numbering always assumed 32 GPIOs per bank, just some of them may
> be empty. IMHO it simplifies register/bit offset conversions, and
> it's easier to convert the numbers to the designations in the datasheet
> by hand, for example PA0 = 0, PB0 = 32.
>
> We also do this in the kernel driver. But the bindings are 3 cell:
> <bank pin flags>.

OK, well we can leave the 'holes' for now.

>
>> When everything is moved to driver model I suppose we can be more clever.
>>
>>>
>>> Our "gpio-pin-numbers" are based on a sparse numbering
>>> scheme assuming 32 pins / bank, and there are assumptions this is
>>> the case in various places, so we cannot fix this until we've
>>> fully gone dm for all gpio usage. But here it would be nice
>>> to have the actual numbers of pins.
>>>
>>> Doing so requires at least one table with bank -> number of gpio-s
>>> mapping. And I think it may also differ on SoC type in some cases
>>> (I would need to take a look at the datasheets)
>>
>> Hoping this can be in the device tree. Do you have a binding for it?
>
> This is in the (kernel) driver, not the device tree bindings.
> So we would need to at least add a table for that.
>
> I don't see any pinmux related stuff in this patch. Does the gpio
> dm handle that?

No, or at least not yet. Does sunxi have kernel support for pinctrl?
We could perhaps use that binding if it exists. Otherwise I think the
current code is our best bet - we can select the correct serial port
based on static configuration (CONFIG) for now.

Regards,
Simon

>
>
> ChenYu
>
>>>
>>> I suggest keeping this as is for now, and put fixing this with
>>> a follow up patch on the todo list, and otherwise this looks good,
>>> so this is:
>>>
>>> Acked-by: Hans de Goede <hdegoede@redhat.com>
>>
>> OK
>>
>>>
>>>
>>>
>>>> +
>>>> +             ret = device_bind(parent, parent->driver,
>>>> +                                     plat->bank_name, plat, -1, &dev);
>>>> +             if (ret)
>>>> +                     return ret;
>>>> +             dev->of_offset = parent->of_offset;
>>>> +     }
>>>> +
>>>> +     return 0;
>>>> +}
>>>> +
>>>> +static const struct udevice_id sunxi_gpio_ids[] = {
>>>> +     { .compatible = "allwinner,sun7i-a20-pinctrl" },
>>>> +     { }
>>>> +};
>>>> +
>>>> +U_BOOT_DRIVER(gpio_sunxi) = {
>>>> +     .name   = "gpio_sunxi",
>>>> +     .id     = UCLASS_GPIO,
>>>> +     .ops    = &gpio_sunxi_ops,
>>>> +     .of_match = sunxi_gpio_ids,
>>>> +     .bind   = gpio_sunxi_bind,
>>>> +     .probe  = gpio_sunxi_probe,
>>>> +};
>>>> +#endif
>>>> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
>>>> index 500d0e3..2314e97 100644
>>>> --- a/include/configs/sun7i.h
>>>> +++ b/include/configs/sun7i.h
>>>> @@ -38,6 +38,7 @@
>>>>
>>>>  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
>>>>  # define CONFIG_CMD_DM
>>>> +# define CONFIG_DM_GPIO
>>>>  #endif
>>>>
>>>>  /*

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 5/6] dm: sunxi: Modify the GPIO driver to support driver model
  2014-10-28  3:29         ` Simon Glass
@ 2014-10-28  3:39           ` Chen-Yu Tsai
  2014-10-28 14:30             ` Maxime Ripard
  0 siblings, 1 reply; 37+ messages in thread
From: Chen-Yu Tsai @ 2014-10-28  3:39 UTC (permalink / raw)
  To: u-boot

Hi,

On Tue, Oct 28, 2014 at 11:29 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Chen-Yu,
>
> On 27 October 2014 20:53, Chen-Yu Tsai <wens@csie.org> wrote:
>> Hi,
>>
>> On Tue, Oct 28, 2014 at 8:05 AM, Simon Glass <sjg@chromium.org> wrote:
>>> Hi Hans,
>>>
>>> On 24 October 2014 03:08, Hans de Goede <hdegoede@redhat.com> wrote:
>>>> Hi,
>>>>
>>>> On 10/23/2014 06:02 AM, Simon Glass wrote:
>>>>> This adds driver model support to the sunxi GPIO driver, using the device
>>>>> tree to trigger binding of the driver. The driver will still operate
>>>>> without driver model too.
>>>>>
>>>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>>>> ---
>>>>>
>>>>> Changes in v2:
>>>>> - Remove references to exynos and tegra
>>>>> - Use the word 'bank' instead of 'port'
>>>>>
>>>>>  drivers/gpio/sunxi_gpio.c | 170 ++++++++++++++++++++++++++++++++++++++++++++++
>>>>>  include/configs/sun7i.h   |   1 +
>>>>>  2 files changed, 171 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
>>>>> index 0c50a8f..44135e5 100644
>>>>> --- a/drivers/gpio/sunxi_gpio.c
>>>>> +++ b/drivers/gpio/sunxi_gpio.c
>>>>> @@ -11,9 +11,25 @@
>>>>>   */
>>>>>
>>>>>  #include <common.h>
>>>>> +#include <dm.h>
>>>>> +#include <errno.h>
>>>>> +#include <fdtdec.h>
>>>>> +#include <malloc.h>
>>>>>  #include <asm/io.h>
>>>>>  #include <asm/gpio.h>
>>>>> +#include <dm/device-internal.h>
>>>>>
>>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>>> +
>>>>> +#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
>>>>> +
>>>>> +struct sunxi_gpio_platdata {
>>>>> +     struct sunxi_gpio *regs;
>>>>> +     const char *bank_name;  /* Name of bank, e.g. "B" */
>>>>> +     int gpio_count;
>>>>> +};
>>>>> +
>>>>> +#ifndef CONFIG_DM_GPIO
>>>>>  static int sunxi_gpio_output(u32 pin, u32 val)
>>>>>  {
>>>>>       u32 dat;
>>>>> @@ -100,3 +116,157 @@ int sunxi_name_to_gpio(const char *name)
>>>>>               return -1;
>>>>>       return group * 32 + pin;
>>>>>  }
>>>>> +#endif
>>>>> +
>>>>> +#ifdef CONFIG_DM_GPIO
>>>>> +static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
>>>>> +{
>>>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>>>> +
>>>>> +     sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
>>>>> +
>>>>> +     return 0;
>>>>> +}
>>>>> +
>>>>> +static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
>>>>> +                                    int value)
>>>>> +{
>>>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>>>> +     u32 num = GPIO_NUM(offset);
>>>>> +
>>>>> +     sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
>>>>> +     clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
>>>>> +
>>>>> +     return 0;
>>>>> +}
>>>>> +
>>>>> +static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
>>>>> +{
>>>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>>>> +     u32 num = GPIO_NUM(offset);
>>>>> +     unsigned dat;
>>>>> +
>>>>> +     dat = readl(&plat->regs->dat);
>>>>> +     dat >>= num;
>>>>> +
>>>>> +     return dat & 0x1;
>>>>> +}
>>>>> +
>>>>> +static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
>>>>> +                             int value)
>>>>> +{
>>>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>>>> +     u32 num = GPIO_NUM(offset);
>>>>> +
>>>>> +     clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
>>>>> +     return 0;
>>>>> +}
>>>>> +
>>>>> +static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
>>>>> +{
>>>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>>>> +     int func;
>>>>> +
>>>>> +     func = sunxi_gpio_get_cfgbank(plat->regs, offset);
>>>>> +     if (func == SUNXI_GPIO_OUTPUT)
>>>>> +             return GPIOF_OUTPUT;
>>>>> +     else if (func == SUNXI_GPIO_INPUT)
>>>>> +             return GPIOF_INPUT;
>>>>> +     else
>>>>> +             return GPIOF_FUNC;
>>>>> +}
>>>>> +
>>>>> +static const struct dm_gpio_ops gpio_sunxi_ops = {
>>>>> +     .direction_input        = sunxi_gpio_direction_input,
>>>>> +     .direction_output       = sunxi_gpio_direction_output,
>>>>> +     .get_value              = sunxi_gpio_get_value,
>>>>> +     .set_value              = sunxi_gpio_set_value,
>>>>> +     .get_function           = sunxi_gpio_get_function,
>>>>> +};
>>>>> +
>>>>> +/**
>>>>> + * Returns the name of a GPIO bank
>>>>> + *
>>>>> + * GPIO banks are named A, B, C, ...
>>>>> + *
>>>>> + * @bank:    Bank number (0, 1..n-1)
>>>>> + * @return allocated string containing the name
>>>>> + */
>>>>> +static char *gpio_bank_name(int bank)
>>>>> +{
>>>>> +     char *name;
>>>>> +
>>>>> +     name = malloc(2);
>>>>> +     if (name) {
>>>>> +             name[0] = 'A' + bank;
>>>>> +             name[1] = '\0';
>>>>> +     }
>>>>> +
>>>>> +     return name;
>>>>> +}
>>>>> +
>>>>> +static int gpio_sunxi_probe(struct udevice *dev)
>>>>> +{
>>>>> +     struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
>>>>> +     struct gpio_dev_priv *uc_priv = dev->uclass_priv;
>>>>> +
>>>>> +     /* Tell the uclass how many GPIOs we have */
>>>>> +     if (plat) {
>>>>> +             uc_priv->gpio_count = plat->gpio_count;
>>>>> +             uc_priv->bank_name = plat->bank_name;
>>>>> +     }
>>>>> +
>>>>> +     return 0;
>>>>> +}
>>>>> +/**
>>>>> + * We have a top-level GPIO device with no actual GPIOs. It has a child
>>>>> + * device for each Sunxi bank.
>>>>> + */
>>>>> +static int gpio_sunxi_bind(struct udevice *parent)
>>>>> +{
>>>>> +     struct sunxi_gpio_platdata *plat = parent->platdata;
>>>>> +     struct sunxi_gpio_reg *ctlr;
>>>>> +     int bank;
>>>>> +     int ret;
>>>>> +
>>>>> +     /* If this is a child device, there is nothing to do here */
>>>>> +     if (plat)
>>>>> +             return 0;
>>>>> +
>>>>> +     ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd->fdt_blob,
>>>>> +                                                parent->of_offset, "reg");
>>>>> +     for (bank = 0; bank < SUNXI_GPIO_BANKS; bank++) {
>>>>> +             struct sunxi_gpio_platdata *plat;
>>>>> +             struct udevice *dev;
>>>>> +
>>>>> +             plat = calloc(1, sizeof(*plat));
>>>>> +             if (!plat)
>>>>> +                     return -ENOMEM;
>>>>> +             plat->regs = &ctlr->gpio_bank[bank];
>>>>> +             plat->bank_name = gpio_bank_name(bank);
>>>>> +             plat->gpio_count = SUNXI_GPIOS_PER_BANK;
>>>>
>>>> This is not correct, a bank have a maximum of 32 gpios but most
>>>> have less. I assume that this should be the number of actual pins in
>>>> the bank, correct ?
>>>
>>> Well I worry that we need to maintain compatibility with what is
>>> there. At some point we can change it, but for now the GPIO numbering
>>> is done assuming 32 GPIOs per bank, right?
>>
>> The numbering always assumed 32 GPIOs per bank, just some of them may
>> be empty. IMHO it simplifies register/bit offset conversions, and
>> it's easier to convert the numbers to the designations in the datasheet
>> by hand, for example PA0 = 0, PB0 = 32.
>>
>> We also do this in the kernel driver. But the bindings are 3 cell:
>> <bank pin flags>.
>
> OK, well we can leave the 'holes' for now.
>
>>
>>> When everything is moved to driver model I suppose we can be more clever.
>>>
>>>>
>>>> Our "gpio-pin-numbers" are based on a sparse numbering
>>>> scheme assuming 32 pins / bank, and there are assumptions this is
>>>> the case in various places, so we cannot fix this until we've
>>>> fully gone dm for all gpio usage. But here it would be nice
>>>> to have the actual numbers of pins.
>>>>
>>>> Doing so requires at least one table with bank -> number of gpio-s
>>>> mapping. And I think it may also differ on SoC type in some cases
>>>> (I would need to take a look at the datasheets)
>>>
>>> Hoping this can be in the device tree. Do you have a binding for it?
>>
>> This is in the (kernel) driver, not the device tree bindings.
>> So we would need to at least add a table for that.
>>
>> I don't see any pinmux related stuff in this patch. Does the gpio
>> dm handle that?
>
> No, or at least not yet. Does sunxi have kernel support for pinctrl?
> We could perhaps use that binding if it exists. Otherwise I think the
> current code is our best bet - we can select the correct serial port
> based on static configuration (CONFIG) for now.

It does. But the bindings are based on strings for function descriptions,
which implies a whole lookup table in the driver. Not sure this would be
great for SPL.

Also Linus Walleij (pinctrl maintainer) proposed some new generic
bindings, though I don't know if we will ever switch over.
CCing Maxime Ripard (sunxi maintainer) on this.


ChenYu

>>>>
>>>> I suggest keeping this as is for now, and put fixing this with
>>>> a follow up patch on the todo list, and otherwise this looks good,
>>>> so this is:
>>>>
>>>> Acked-by: Hans de Goede <hdegoede@redhat.com>
>>>
>>> OK
>>>
>>>>
>>>>
>>>>
>>>>> +
>>>>> +             ret = device_bind(parent, parent->driver,
>>>>> +                                     plat->bank_name, plat, -1, &dev);
>>>>> +             if (ret)
>>>>> +                     return ret;
>>>>> +             dev->of_offset = parent->of_offset;
>>>>> +     }
>>>>> +
>>>>> +     return 0;
>>>>> +}
>>>>> +
>>>>> +static const struct udevice_id sunxi_gpio_ids[] = {
>>>>> +     { .compatible = "allwinner,sun7i-a20-pinctrl" },
>>>>> +     { }
>>>>> +};
>>>>> +
>>>>> +U_BOOT_DRIVER(gpio_sunxi) = {
>>>>> +     .name   = "gpio_sunxi",
>>>>> +     .id     = UCLASS_GPIO,
>>>>> +     .ops    = &gpio_sunxi_ops,
>>>>> +     .of_match = sunxi_gpio_ids,
>>>>> +     .bind   = gpio_sunxi_bind,
>>>>> +     .probe  = gpio_sunxi_probe,
>>>>> +};
>>>>> +#endif
>>>>> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
>>>>> index 500d0e3..2314e97 100644
>>>>> --- a/include/configs/sun7i.h
>>>>> +++ b/include/configs/sun7i.h
>>>>> @@ -38,6 +38,7 @@
>>>>>
>>>>>  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
>>>>>  # define CONFIG_CMD_DM
>>>>> +# define CONFIG_DM_GPIO
>>>>>  #endif
>>>>>
>>>>>  /*

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 2/6] dm: sunxi: Add a new config for an FDT-based pcDuino3
  2014-10-28  0:04     ` Simon Glass
@ 2014-10-28  9:13       ` Hans de Goede
  2014-10-29  3:02         ` Simon Glass
  0 siblings, 1 reply; 37+ messages in thread
From: Hans de Goede @ 2014-10-28  9:13 UTC (permalink / raw)
  To: u-boot

Hi,

On 10/28/2014 01:04 AM, Simon Glass wrote:
> Hi Hans,
> 
> On 24 October 2014 02:38, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 10/23/2014 06:02 AM, Simon Glass wrote:
>>> For now we won't want to mess with the existing configurations. Create a
>>> new one which will enable device tree and driver model. Note that this
>>> brings the device tree binary into u-boot-sunxi-with-spl.bin.
>>>
>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>> ---
>>>
>>> Changes in v2: None
>>>
>>>  Makefile                                  | 3 ++-
>>>  arch/arm/dts/Makefile                     | 1 +
>>>  board/sunxi/MAINTAINERS                   | 1 +
>>>  configs/Linksprite_pcDuino3_fdt_defconfig | 8 ++++++++
>>>  include/configs/sun7i.h                   | 4 ++++
>>>  5 files changed, 16 insertions(+), 1 deletion(-)
>>>  create mode 100644 configs/Linksprite_pcDuino3_fdt_defconfig
>>>
>>> diff --git a/Makefile b/Makefile
>>> index 99097e1..816f859 100644
>>> --- a/Makefile
>>> +++ b/Makefile
>>> @@ -941,7 +941,8 @@ u-boot-nand.gph: u-boot.bin FORCE
>>>  ifneq ($(CONFIG_SUNXI),)
>>>  OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
>>>                                  --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
>>> -u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
>>> +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \
>>> +                     u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE
>>>       $(call if_changed,pad_cat)
>>>  endif
>>>
>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>> index 3299817..564eb76 100644
>>> --- a/arch/arm/dts/Makefile
>>> +++ b/arch/arm/dts/Makefile
>>> @@ -1,3 +1,4 @@
>>> +dtb-$(CONFIG_SUN7I) +=  sun7i-a20-pcduino3.dtb
>>
>> Please make this
>>
>> dtb-$(CONFIG_PCDUINO3) +=  sun7i-a20-pcduino3.dtb
> 
> Well I can do that, but this should have no effect if we don't define
> CONFIG_OF_CONTROL. The way I have it we will be able to add more
> device tree files for sun7x without anyone having to change it. The
> target should build all sun7i device trees eventually.

Ah, I see, ok lets keep this as is then.

> 
>>
>>>  dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
>>>  dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
>>>  dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
>>> diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
>>> index 4f32195..3dbfe15 100644
>>> --- a/board/sunxi/MAINTAINERS
>>> +++ b/board/sunxi/MAINTAINERS
>>> @@ -21,6 +21,7 @@ F:  configs/A20-OLinuXino_MICRO_defconfig
>>>  F:   configs/Bananapi_defconfig
>>>  F:   configs/i12-tvbox_defconfig
>>>  F:   configs/Linksprite_pcDuino3_defconfig
>>> +F:   configs/Linksprite_pcDuino3_fdt_defconfig
>>>  F:   configs/qt840a_defconfig
>>>
>>>  CUBIEBOARD2 BOARD
>>> diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig
>>> new file mode 100644
>>> index 0000000..e5f6236
>>> --- /dev/null
>>> +++ b/configs/Linksprite_pcDuino3_fdt_defconfig
>>> @@ -0,0 +1,8 @@
>>> +CONFIG_SPL=y
>>> +CONFIG_SYS_EXTRA_OPTIONS="PCDUINO3,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI,DM"
>>> +CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
>>> +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
>>
>> Hmm, I don't like this doubling of info. CONFIG_FDTFILE is sort of a sunxi specific thing
>> here (some other boards have local usage of its too, but it is not used globably.
>>
>> Can you do a patch (and prepend it to this one in the next posting of this series),
>> which replaces sunxi's CONFIG_FDTFILE usage with CONFIG_DEFAULT_DEVICE_TREE, dropping
>> the .dtb appending in the defconfigs and instead append the .dtb in include/configs/sunxi-commom.h
>>
>> Note sunxi uses CONFIG_FDTFILE in 3 places:
>>
>> 1) board/sunxi/Kconfig
>> 2) various board/*_defconfig files
>> 3) include/configs/sunxi-common.h
> 
> But isn't that used for passing to the kernel? Do you want to drop the
> ability to have a separate file for each?

A good question, there are 2 things here:

1) This is just the filename, it gets combined with a "basedir" set through extlinux.conf
when booting the real kernel, so they can still be different

2) TBH even if this would make it mandatory for them to be 1 and the same file, I would
not consider that a problem, I would very much like to avoid the need to have separate
u-boot and kernel devicetree flavors for sunxi.


> 
>>
>>
>>> +CONFIG_OF_CONTROL=y
>>> +CONFIG_OF_SEPARATE=y
>>> ++S:CONFIG_ARM=y
>>> ++S:CONFIG_TARGET_SUN7I=y
>>> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
>>> index a902b84..500d0e3 100644
>>> --- a/include/configs/sun7i.h
>>> +++ b/include/configs/sun7i.h
>>> @@ -36,6 +36,10 @@
>>>  #define CONFIG_ARMV7_SECURE_BASE     SUNXI_SRAM_B_BASE
>>>  #define CONFIG_SYS_CLK_FREQ          24000000
>>>
>>> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
>>> +# define CONFIG_CMD_DM
>>> +#endif
>>> +
>>
>> Can you please put this in include/configs/sunxi-common.h instead ?
> 
> OK will do.
> 
>>
>>>  /*
>>>   * Include common sunxi configuration where most the settings are
>>>   */
> 
> Regards,
> Simon
> 

Regards,

Hans

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 5/6] dm: sunxi: Modify the GPIO driver to support driver model
  2014-10-28  3:39           ` Chen-Yu Tsai
@ 2014-10-28 14:30             ` Maxime Ripard
  0 siblings, 0 replies; 37+ messages in thread
From: Maxime Ripard @ 2014-10-28 14:30 UTC (permalink / raw)
  To: u-boot

Hi,

On Tue, Oct 28, 2014 at 11:39:07AM +0800, Chen-Yu Tsai wrote:
> Hi,
> >>> When everything is moved to driver model I suppose we can be more clever.
> >>>
> >>>>
> >>>> Our "gpio-pin-numbers" are based on a sparse numbering
> >>>> scheme assuming 32 pins / bank, and there are assumptions this is
> >>>> the case in various places, so we cannot fix this until we've
> >>>> fully gone dm for all gpio usage. But here it would be nice
> >>>> to have the actual numbers of pins.
> >>>>
> >>>> Doing so requires at least one table with bank -> number of gpio-s
> >>>> mapping. And I think it may also differ on SoC type in some cases
> >>>> (I would need to take a look at the datasheets)
> >>>
> >>> Hoping this can be in the device tree. Do you have a binding for it?
> >>
> >> This is in the (kernel) driver, not the device tree bindings.
> >> So we would need to at least add a table for that.
> >>
> >> I don't see any pinmux related stuff in this patch. Does the gpio
> >> dm handle that?
> >
> > No, or at least not yet. Does sunxi have kernel support for pinctrl?
> > We could perhaps use that binding if it exists. Otherwise I think the
> > current code is our best bet - we can select the correct serial port
> > based on static configuration (CONFIG) for now.
> 
> It does. But the bindings are based on strings for function descriptions,
> which implies a whole lookup table in the driver. Not sure this would be
> great for SPL.
> 
> Also Linus Walleij (pinctrl maintainer) proposed some new generic
> bindings, though I don't know if we will ever switch over.
> CCing Maxime Ripard (sunxi maintainer) on this.

I'm not planning to move to the new bindings any time soon, and no one
is actively working on that to my knowledge either.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 2/6] dm: sunxi: Add a new config for an FDT-based pcDuino3
  2014-10-28  9:13       ` Hans de Goede
@ 2014-10-29  3:02         ` Simon Glass
  2014-10-29  9:32           ` Hans de Goede
  0 siblings, 1 reply; 37+ messages in thread
From: Simon Glass @ 2014-10-29  3:02 UTC (permalink / raw)
  To: u-boot

Hi Hans,

On 28 October 2014 03:13, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 10/28/2014 01:04 AM, Simon Glass wrote:
>> Hi Hans,
>>
>> On 24 October 2014 02:38, Hans de Goede <hdegoede@redhat.com> wrote:
>>> Hi,
>>>
>>> On 10/23/2014 06:02 AM, Simon Glass wrote:
>>>> For now we won't want to mess with the existing configurations. Create a
>>>> new one which will enable device tree and driver model. Note that this
>>>> brings the device tree binary into u-boot-sunxi-with-spl.bin.
>>>>
>>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>>> ---
>>>>
>>>> Changes in v2: None
>>>>
>>>>  Makefile                                  | 3 ++-
>>>>  arch/arm/dts/Makefile                     | 1 +
>>>>  board/sunxi/MAINTAINERS                   | 1 +
>>>>  configs/Linksprite_pcDuino3_fdt_defconfig | 8 ++++++++
>>>>  include/configs/sun7i.h                   | 4 ++++
>>>>  5 files changed, 16 insertions(+), 1 deletion(-)
>>>>  create mode 100644 configs/Linksprite_pcDuino3_fdt_defconfig
>>>>
>>>> diff --git a/Makefile b/Makefile
>>>> index 99097e1..816f859 100644
>>>> --- a/Makefile
>>>> +++ b/Makefile
>>>> @@ -941,7 +941,8 @@ u-boot-nand.gph: u-boot.bin FORCE
>>>>  ifneq ($(CONFIG_SUNXI),)
>>>>  OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
>>>>                                  --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
>>>> -u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
>>>> +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \
>>>> +                     u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE
>>>>       $(call if_changed,pad_cat)
>>>>  endif
>>>>
>>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>>> index 3299817..564eb76 100644
>>>> --- a/arch/arm/dts/Makefile
>>>> +++ b/arch/arm/dts/Makefile
>>>> @@ -1,3 +1,4 @@
>>>> +dtb-$(CONFIG_SUN7I) +=  sun7i-a20-pcduino3.dtb
>>>
>>> Please make this
>>>
>>> dtb-$(CONFIG_PCDUINO3) +=  sun7i-a20-pcduino3.dtb
>>
>> Well I can do that, but this should have no effect if we don't define
>> CONFIG_OF_CONTROL. The way I have it we will be able to add more
>> device tree files for sun7x without anyone having to change it. The
>> target should build all sun7i device trees eventually.
>
> Ah, I see, ok lets keep this as is then.
>
>>
>>>
>>>>  dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
>>>>  dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
>>>>  dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
>>>> diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
>>>> index 4f32195..3dbfe15 100644
>>>> --- a/board/sunxi/MAINTAINERS
>>>> +++ b/board/sunxi/MAINTAINERS
>>>> @@ -21,6 +21,7 @@ F:  configs/A20-OLinuXino_MICRO_defconfig
>>>>  F:   configs/Bananapi_defconfig
>>>>  F:   configs/i12-tvbox_defconfig
>>>>  F:   configs/Linksprite_pcDuino3_defconfig
>>>> +F:   configs/Linksprite_pcDuino3_fdt_defconfig
>>>>  F:   configs/qt840a_defconfig
>>>>
>>>>  CUBIEBOARD2 BOARD
>>>> diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig
>>>> new file mode 100644
>>>> index 0000000..e5f6236
>>>> --- /dev/null
>>>> +++ b/configs/Linksprite_pcDuino3_fdt_defconfig
>>>> @@ -0,0 +1,8 @@
>>>> +CONFIG_SPL=y
>>>> +CONFIG_SYS_EXTRA_OPTIONS="PCDUINO3,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI,DM"
>>>> +CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
>>>> +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
>>>
>>> Hmm, I don't like this doubling of info. CONFIG_FDTFILE is sort of a sunxi specific thing
>>> here (some other boards have local usage of its too, but it is not used globably.
>>>
>>> Can you do a patch (and prepend it to this one in the next posting of this series),
>>> which replaces sunxi's CONFIG_FDTFILE usage with CONFIG_DEFAULT_DEVICE_TREE, dropping
>>> the .dtb appending in the defconfigs and instead append the .dtb in include/configs/sunxi-commom.h
>>>
>>> Note sunxi uses CONFIG_FDTFILE in 3 places:
>>>
>>> 1) board/sunxi/Kconfig
>>> 2) various board/*_defconfig files
>>> 3) include/configs/sunxi-common.h
>>
>> But isn't that used for passing to the kernel? Do you want to drop the
>> ability to have a separate file for each?
>
> A good question, there are 2 things here:
>
> 1) This is just the filename, it gets combined with a "basedir" set through extlinux.conf
> when booting the real kernel, so they can still be different
>
> 2) TBH even if this would make it mandatory for them to be 1 and the same file, I would
> not consider that a problem, I would very much like to avoid the need to have separate
> u-boot and kernel devicetree flavors for sunxi.

OK fair enough, but actually I feel that this should be unrelated to
my change. The CONFIG_DEFAULT_DEVICE_TREE setting is used by all
boards that use device tree. It seems that CONFIG_FDTFILE is used in a
few places but is not very widespread.

So I suppose what I am saying is, how about you do the patch you are
talking about? I need to be careful to focus on drivel model changes
and not boil the ocearn, or I will never get done!

>
>
>>
>>>
>>>
>>>> +CONFIG_OF_CONTROL=y
>>>> +CONFIG_OF_SEPARATE=y
>>>> ++S:CONFIG_ARM=y
>>>> ++S:CONFIG_TARGET_SUN7I=y
>>>> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
>>>> index a902b84..500d0e3 100644
>>>> --- a/include/configs/sun7i.h
>>>> +++ b/include/configs/sun7i.h
>>>> @@ -36,6 +36,10 @@
>>>>  #define CONFIG_ARMV7_SECURE_BASE     SUNXI_SRAM_B_BASE
>>>>  #define CONFIG_SYS_CLK_FREQ          24000000
>>>>
>>>> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
>>>> +# define CONFIG_CMD_DM
>>>> +#endif
>>>> +
>>>
>>> Can you please put this in include/configs/sunxi-common.h instead ?
>>
>> OK will do.
>>
>>>
>>>>  /*
>>>>   * Include common sunxi configuration where most the settings are
>>>>   */
Regards,
Simon

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-28  0:06     ` Simon Glass
@ 2014-10-29  8:05       ` Ian Campbell
  2014-10-29 19:28         ` Simon Glass
  0 siblings, 1 reply; 37+ messages in thread
From: Ian Campbell @ 2014-10-29  8:05 UTC (permalink / raw)
  To: u-boot

On Mon, 2014-10-27 at 18:06 -0600, Simon Glass wrote:
> Hi Ian,
> 
> On 24 October 2014 03:42, Ian Campbell <ijc@hellion.org.uk> wrote:
> > On Wed, 2014-10-22 at 22:02 -0600, Simon Glass wrote:
> >> Add a driver for the designware serial UART used on sunxi. This just
> >> redirects to the normal ns16550 driver.
> >>
> >> Add a stdout-path to the device tree so that the correct UART is chosen.
> >>
> >> Signed-off-by: Simon Glass <sjg@chromium.org>
> >
> > Should the UART related code in
> > arch/arm/cpu/armv7/sunxi/board.c:gpio_init() be nobbled in this
> > configuration?
> 
> Yes I think that needs attention. Ideally we should be able to have
> this handled by the serial driver (requesting the pinmux it needs) but
> we don't have infrastructure for that as yet.

Ah, I thought your earlier GPIO patches were that, but I suppose not.

> Suggestions? What does the kernel do here?

It has pinmux infra.

In the meantime could we somehow replace/augment the #ifdef chain in
gpio_init with something keyed off the stdout alias perhaps?

Ian.

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 2/6] dm: sunxi: Add a new config for an FDT-based pcDuino3
  2014-10-29  3:02         ` Simon Glass
@ 2014-10-29  9:32           ` Hans de Goede
  2014-10-29 19:30             ` Simon Glass
  0 siblings, 1 reply; 37+ messages in thread
From: Hans de Goede @ 2014-10-29  9:32 UTC (permalink / raw)
  To: u-boot

Hi,

On 10/29/2014 04:02 AM, Simon Glass wrote:
> Hi Hans,
> 
> On 28 October 2014 03:13, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 10/28/2014 01:04 AM, Simon Glass wrote:
>>> Hi Hans,
>>>
>>> On 24 October 2014 02:38, Hans de Goede <hdegoede@redhat.com> wrote:
>>>> Hi,
>>>>
>>>> On 10/23/2014 06:02 AM, Simon Glass wrote:
>>>>> For now we won't want to mess with the existing configurations. Create a
>>>>> new one which will enable device tree and driver model. Note that this
>>>>> brings the device tree binary into u-boot-sunxi-with-spl.bin.
>>>>>
>>>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>>>> ---
>>>>>
>>>>> Changes in v2: None
>>>>>
>>>>>  Makefile                                  | 3 ++-
>>>>>  arch/arm/dts/Makefile                     | 1 +
>>>>>  board/sunxi/MAINTAINERS                   | 1 +
>>>>>  configs/Linksprite_pcDuino3_fdt_defconfig | 8 ++++++++
>>>>>  include/configs/sun7i.h                   | 4 ++++
>>>>>  5 files changed, 16 insertions(+), 1 deletion(-)
>>>>>  create mode 100644 configs/Linksprite_pcDuino3_fdt_defconfig
>>>>>
>>>>> diff --git a/Makefile b/Makefile
>>>>> index 99097e1..816f859 100644
>>>>> --- a/Makefile
>>>>> +++ b/Makefile
>>>>> @@ -941,7 +941,8 @@ u-boot-nand.gph: u-boot.bin FORCE
>>>>>  ifneq ($(CONFIG_SUNXI),)
>>>>>  OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
>>>>>                                  --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
>>>>> -u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
>>>>> +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \
>>>>> +                     u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE
>>>>>       $(call if_changed,pad_cat)
>>>>>  endif
>>>>>
>>>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>>>> index 3299817..564eb76 100644
>>>>> --- a/arch/arm/dts/Makefile
>>>>> +++ b/arch/arm/dts/Makefile
>>>>> @@ -1,3 +1,4 @@
>>>>> +dtb-$(CONFIG_SUN7I) +=  sun7i-a20-pcduino3.dtb
>>>>
>>>> Please make this
>>>>
>>>> dtb-$(CONFIG_PCDUINO3) +=  sun7i-a20-pcduino3.dtb
>>>
>>> Well I can do that, but this should have no effect if we don't define
>>> CONFIG_OF_CONTROL. The way I have it we will be able to add more
>>> device tree files for sun7x without anyone having to change it. The
>>> target should build all sun7i device trees eventually.
>>
>> Ah, I see, ok lets keep this as is then.
>>
>>>
>>>>
>>>>>  dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
>>>>>  dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
>>>>>  dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
>>>>> diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
>>>>> index 4f32195..3dbfe15 100644
>>>>> --- a/board/sunxi/MAINTAINERS
>>>>> +++ b/board/sunxi/MAINTAINERS
>>>>> @@ -21,6 +21,7 @@ F:  configs/A20-OLinuXino_MICRO_defconfig
>>>>>  F:   configs/Bananapi_defconfig
>>>>>  F:   configs/i12-tvbox_defconfig
>>>>>  F:   configs/Linksprite_pcDuino3_defconfig
>>>>> +F:   configs/Linksprite_pcDuino3_fdt_defconfig
>>>>>  F:   configs/qt840a_defconfig
>>>>>
>>>>>  CUBIEBOARD2 BOARD
>>>>> diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig
>>>>> new file mode 100644
>>>>> index 0000000..e5f6236
>>>>> --- /dev/null
>>>>> +++ b/configs/Linksprite_pcDuino3_fdt_defconfig
>>>>> @@ -0,0 +1,8 @@
>>>>> +CONFIG_SPL=y
>>>>> +CONFIG_SYS_EXTRA_OPTIONS="PCDUINO3,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI,DM"
>>>>> +CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
>>>>> +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
>>>>
>>>> Hmm, I don't like this doubling of info. CONFIG_FDTFILE is sort of a sunxi specific thing
>>>> here (some other boards have local usage of its too, but it is not used globably.
>>>>
>>>> Can you do a patch (and prepend it to this one in the next posting of this series),
>>>> which replaces sunxi's CONFIG_FDTFILE usage with CONFIG_DEFAULT_DEVICE_TREE, dropping
>>>> the .dtb appending in the defconfigs and instead append the .dtb in include/configs/sunxi-commom.h
>>>>
>>>> Note sunxi uses CONFIG_FDTFILE in 3 places:
>>>>
>>>> 1) board/sunxi/Kconfig
>>>> 2) various board/*_defconfig files
>>>> 3) include/configs/sunxi-common.h
>>>
>>> But isn't that used for passing to the kernel? Do you want to drop the
>>> ability to have a separate file for each?
>>
>> A good question, there are 2 things here:
>>
>> 1) This is just the filename, it gets combined with a "basedir" set through extlinux.conf
>> when booting the real kernel, so they can still be different
>>
>> 2) TBH even if this would make it mandatory for them to be 1 and the same file, I would
>> not consider that a problem, I would very much like to avoid the need to have separate
>> u-boot and kernel devicetree flavors for sunxi.
> 
> OK fair enough, but actually I feel that this should be unrelated to
> my change. The CONFIG_DEFAULT_DEVICE_TREE setting is used by all
> boards that use device tree. It seems that CONFIG_FDTFILE is used in a
> few places but is not very widespread.
> 
> So I suppose what I am saying is, how about you do the patch you are
> talking about? I need to be careful to focus on drivel model changes
> and not boil the ocearn, or I will never get done!

Ok, I lets leave this bit of the patch as is then, and I'll put fixing this
on my todo list.

So...

> 
>>
>>
>>>
>>>>
>>>>
>>>>> +CONFIG_OF_CONTROL=y
>>>>> +CONFIG_OF_SEPARATE=y
>>>>> ++S:CONFIG_ARM=y
>>>>> ++S:CONFIG_TARGET_SUN7I=y
>>>>> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
>>>>> index a902b84..500d0e3 100644
>>>>> --- a/include/configs/sun7i.h
>>>>> +++ b/include/configs/sun7i.h
>>>>> @@ -36,6 +36,10 @@
>>>>>  #define CONFIG_ARMV7_SECURE_BASE     SUNXI_SRAM_B_BASE
>>>>>  #define CONFIG_SYS_CLK_FREQ          24000000
>>>>>
>>>>> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
>>>>> +# define CONFIG_CMD_DM
>>>>> +#endif
>>>>> +
>>>>
>>>> Can you please put this in include/configs/sunxi-common.h instead ?
>>>
>>> OK will do.

If you can do a respin based on tip of the latest master and with this one
small item fixed, then I'll queue up your patches in u-boot-sunxi/next

Thanks & Regards,

Hans

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-29  8:05       ` Ian Campbell
@ 2014-10-29 19:28         ` Simon Glass
  2014-10-30  9:08           ` Ian Campbell
  0 siblings, 1 reply; 37+ messages in thread
From: Simon Glass @ 2014-10-29 19:28 UTC (permalink / raw)
  To: u-boot

Hi Ian,

On 29 October 2014 02:05, Ian Campbell <ijc@hellion.org.uk> wrote:
> On Mon, 2014-10-27 at 18:06 -0600, Simon Glass wrote:
>> Hi Ian,
>>
>> On 24 October 2014 03:42, Ian Campbell <ijc@hellion.org.uk> wrote:
>> > On Wed, 2014-10-22 at 22:02 -0600, Simon Glass wrote:
>> >> Add a driver for the designware serial UART used on sunxi. This just
>> >> redirects to the normal ns16550 driver.
>> >>
>> >> Add a stdout-path to the device tree so that the correct UART is chosen.
>> >>
>> >> Signed-off-by: Simon Glass <sjg@chromium.org>
>> >
>> > Should the UART related code in
>> > arch/arm/cpu/armv7/sunxi/board.c:gpio_init() be nobbled in this
>> > configuration?
>>
>> Yes I think that needs attention. Ideally we should be able to have
>> this handled by the serial driver (requesting the pinmux it needs) but
>> we don't have infrastructure for that as yet.
>
> Ah, I thought your earlier GPIO patches were that, but I suppose not.
>
>> Suggestions? What does the kernel do here?
>
> It has pinmux infra.
>
> In the meantime could we somehow replace/augment the #ifdef chain in
> gpio_init with something keyed off the stdout alias perhaps?

Tegra has code to convert a device interrupt number (which uniquely
identifies a peripheral in that SoC) to an internal peripheral ID,
then these is a function which can enable a peripheral given the ID
(funcmux). In some cases you could have multiple options for the
funcmux, but there is no easy way to support this. But this approach
might be good enough for sunxi. We can easily write the function to
enable the pins for a particular port, and this could go in
arch/arm/...sunxi/ perhaps.

Regards,
Simon

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 2/6] dm: sunxi: Add a new config for an FDT-based pcDuino3
  2014-10-29  9:32           ` Hans de Goede
@ 2014-10-29 19:30             ` Simon Glass
  2014-10-30  8:36               ` Hans de Goede
  0 siblings, 1 reply; 37+ messages in thread
From: Simon Glass @ 2014-10-29 19:30 UTC (permalink / raw)
  To: u-boot

Hi Hans,

On 29 October 2014 03:32, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 10/29/2014 04:02 AM, Simon Glass wrote:
>> Hi Hans,
>>
>> On 28 October 2014 03:13, Hans de Goede <hdegoede@redhat.com> wrote:
>>> Hi,
>>>
>>> On 10/28/2014 01:04 AM, Simon Glass wrote:
>>>> Hi Hans,
>>>>
>>>> On 24 October 2014 02:38, Hans de Goede <hdegoede@redhat.com> wrote:
>>>>> Hi,
>>>>>
>>>>> On 10/23/2014 06:02 AM, Simon Glass wrote:
>>>>>> For now we won't want to mess with the existing configurations. Create a
>>>>>> new one which will enable device tree and driver model. Note that this
>>>>>> brings the device tree binary into u-boot-sunxi-with-spl.bin.
>>>>>>
>>>>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>>>>> ---
>>>>>>
>>>>>> Changes in v2: None
>>>>>>
>>>>>>  Makefile                                  | 3 ++-
>>>>>>  arch/arm/dts/Makefile                     | 1 +
>>>>>>  board/sunxi/MAINTAINERS                   | 1 +
>>>>>>  configs/Linksprite_pcDuino3_fdt_defconfig | 8 ++++++++
>>>>>>  include/configs/sun7i.h                   | 4 ++++
>>>>>>  5 files changed, 16 insertions(+), 1 deletion(-)
>>>>>>  create mode 100644 configs/Linksprite_pcDuino3_fdt_defconfig
>>>>>>
>>>>>> diff --git a/Makefile b/Makefile
>>>>>> index 99097e1..816f859 100644
>>>>>> --- a/Makefile
>>>>>> +++ b/Makefile
>>>>>> @@ -941,7 +941,8 @@ u-boot-nand.gph: u-boot.bin FORCE
>>>>>>  ifneq ($(CONFIG_SUNXI),)
>>>>>>  OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
>>>>>>                                  --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
>>>>>> -u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
>>>>>> +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \
>>>>>> +                     u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE
>>>>>>       $(call if_changed,pad_cat)
>>>>>>  endif
>>>>>>
>>>>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>>>>> index 3299817..564eb76 100644
>>>>>> --- a/arch/arm/dts/Makefile
>>>>>> +++ b/arch/arm/dts/Makefile
>>>>>> @@ -1,3 +1,4 @@
>>>>>> +dtb-$(CONFIG_SUN7I) +=  sun7i-a20-pcduino3.dtb
>>>>>
>>>>> Please make this
>>>>>
>>>>> dtb-$(CONFIG_PCDUINO3) +=  sun7i-a20-pcduino3.dtb
>>>>
>>>> Well I can do that, but this should have no effect if we don't define
>>>> CONFIG_OF_CONTROL. The way I have it we will be able to add more
>>>> device tree files for sun7x without anyone having to change it. The
>>>> target should build all sun7i device trees eventually.
>>>
>>> Ah, I see, ok lets keep this as is then.
>>>
>>>>
>>>>>
>>>>>>  dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
>>>>>>  dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
>>>>>>  dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
>>>>>> diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
>>>>>> index 4f32195..3dbfe15 100644
>>>>>> --- a/board/sunxi/MAINTAINERS
>>>>>> +++ b/board/sunxi/MAINTAINERS
>>>>>> @@ -21,6 +21,7 @@ F:  configs/A20-OLinuXino_MICRO_defconfig
>>>>>>  F:   configs/Bananapi_defconfig
>>>>>>  F:   configs/i12-tvbox_defconfig
>>>>>>  F:   configs/Linksprite_pcDuino3_defconfig
>>>>>> +F:   configs/Linksprite_pcDuino3_fdt_defconfig
>>>>>>  F:   configs/qt840a_defconfig
>>>>>>
>>>>>>  CUBIEBOARD2 BOARD
>>>>>> diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig
>>>>>> new file mode 100644
>>>>>> index 0000000..e5f6236
>>>>>> --- /dev/null
>>>>>> +++ b/configs/Linksprite_pcDuino3_fdt_defconfig
>>>>>> @@ -0,0 +1,8 @@
>>>>>> +CONFIG_SPL=y
>>>>>> +CONFIG_SYS_EXTRA_OPTIONS="PCDUINO3,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI,DM"
>>>>>> +CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
>>>>>> +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
>>>>>
>>>>> Hmm, I don't like this doubling of info. CONFIG_FDTFILE is sort of a sunxi specific thing
>>>>> here (some other boards have local usage of its too, but it is not used globably.
>>>>>
>>>>> Can you do a patch (and prepend it to this one in the next posting of this series),
>>>>> which replaces sunxi's CONFIG_FDTFILE usage with CONFIG_DEFAULT_DEVICE_TREE, dropping
>>>>> the .dtb appending in the defconfigs and instead append the .dtb in include/configs/sunxi-commom.h
>>>>>
>>>>> Note sunxi uses CONFIG_FDTFILE in 3 places:
>>>>>
>>>>> 1) board/sunxi/Kconfig
>>>>> 2) various board/*_defconfig files
>>>>> 3) include/configs/sunxi-common.h
>>>>
>>>> But isn't that used for passing to the kernel? Do you want to drop the
>>>> ability to have a separate file for each?
>>>
>>> A good question, there are 2 things here:
>>>
>>> 1) This is just the filename, it gets combined with a "basedir" set through extlinux.conf
>>> when booting the real kernel, so they can still be different
>>>
>>> 2) TBH even if this would make it mandatory for them to be 1 and the same file, I would
>>> not consider that a problem, I would very much like to avoid the need to have separate
>>> u-boot and kernel devicetree flavors for sunxi.
>>
>> OK fair enough, but actually I feel that this should be unrelated to
>> my change. The CONFIG_DEFAULT_DEVICE_TREE setting is used by all
>> boards that use device tree. It seems that CONFIG_FDTFILE is used in a
>> few places but is not very widespread.
>>
>> So I suppose what I am saying is, how about you do the patch you are
>> talking about? I need to be careful to focus on drivel model changes
>> and not boil the ocearn, or I will never get done!
>
> Ok, I lets leave this bit of the patch as is then, and I'll put fixing this
> on my todo list.
>
> So...

Thank you, you are very kind :-) I still have a sunxi board and expect
to be doing more here in future, but right now am a bit tight for
time.

>
>>
>>>
>>>
>>>>
>>>>>
>>>>>
>>>>>> +CONFIG_OF_CONTROL=y
>>>>>> +CONFIG_OF_SEPARATE=y
>>>>>> ++S:CONFIG_ARM=y
>>>>>> ++S:CONFIG_TARGET_SUN7I=y
>>>>>> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
>>>>>> index a902b84..500d0e3 100644
>>>>>> --- a/include/configs/sun7i.h
>>>>>> +++ b/include/configs/sun7i.h
>>>>>> @@ -36,6 +36,10 @@
>>>>>>  #define CONFIG_ARMV7_SECURE_BASE     SUNXI_SRAM_B_BASE
>>>>>>  #define CONFIG_SYS_CLK_FREQ          24000000
>>>>>>
>>>>>> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
>>>>>> +# define CONFIG_CMD_DM
>>>>>> +#endif
>>>>>> +
>>>>>
>>>>> Can you please put this in include/configs/sunxi-common.h instead ?
>>>>
>>>> OK will do.
>
> If you can do a respin based on tip of the latest master and with this one
> small item fixed, then I'll queue up your patches in u-boot-sunxi/next

I will respin with the changes and retest. I was planning to bring it
through -dm with suitable acks, but it is all sunxi stuff now and
there are no DM-dependent patches outstanding, so going through sunxi
sounds good. But would like to make sure it merges to mainline next
week.

Regards,
Simon

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [U-Boot, v2, 2/6] dm: sunxi: Add a new config for an FDT-based pcDuino3
  2014-10-29 19:30             ` Simon Glass
@ 2014-10-30  8:36               ` Hans de Goede
  0 siblings, 0 replies; 37+ messages in thread
From: Hans de Goede @ 2014-10-30  8:36 UTC (permalink / raw)
  To: u-boot

Hi,

On 10/29/2014 08:30 PM, Simon Glass wrote:
> Hi Hans,
> 
> On 29 October 2014 03:32, Hans de Goede <hdegoede@redhat.com> wrote:

<snip>

>> If you can do a respin based on tip of the latest master and with this one
>> small item fixed, then I'll queue up your patches in u-boot-sunxi/next
> 
> I will respin with the changes and retest. I was planning to bring it
> through -dm with suitable acks, but it is all sunxi stuff now and
> there are no DM-dependent patches outstanding, so going through sunxi
> sounds good. But would like to make sure it merges to mainline next
> week.

I can do a pull-req as soon as you've a v3 ready. Or if you prefer you
can take this in through the dm tree, that works for me too.

In that case consider this patch:

Acked-by: Hans de Goede <hdegoede@redhat.com>

Once the CONFIG_CMD_DM defining code block has been moved to sunxi-common.h

Regards,

Hans

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-29 19:28         ` Simon Glass
@ 2014-10-30  9:08           ` Ian Campbell
  2014-10-30  9:36             ` Hans de Goede
  0 siblings, 1 reply; 37+ messages in thread
From: Ian Campbell @ 2014-10-30  9:08 UTC (permalink / raw)
  To: u-boot

On Wed, 2014-10-29 at 13:28 -0600, Simon Glass wrote:
> > In the meantime could we somehow replace/augment the #ifdef chain in
> > gpio_init with something keyed off the stdout alias perhaps?
> 
> Tegra has code to convert a device interrupt number (which uniquely
> identifies a peripheral in that SoC) to an internal peripheral ID,
> then these is a function which can enable a peripheral given the ID
> (funcmux). In some cases you could have multiple options for the
> funcmux, but there is no easy way to support this.

I think that although there are multiple options for some functions
(UARTs come to mind) we haven't yet found the need to make any dynamic
choices, so it's all static right now.

>  But this approach
> might be good enough for sunxi. We can easily write the function to
> enable the pins for a particular port, and this could go in
> arch/arm/...sunxi/ perhaps.

I'm ok with it so long as it isn't going to stand in the way of proper
dt based pinmux in the future.

One way to help with that might be to use the allwinner,function
property in DT as the funcmux name.

Hans, what do you think?

Ian.

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-30  9:08           ` Ian Campbell
@ 2014-10-30  9:36             ` Hans de Goede
  2014-10-30 10:14               ` Ian Campbell
  0 siblings, 1 reply; 37+ messages in thread
From: Hans de Goede @ 2014-10-30  9:36 UTC (permalink / raw)
  To: u-boot

Hi,

On 10/30/2014 10:08 AM, Ian Campbell wrote:
> On Wed, 2014-10-29 at 13:28 -0600, Simon Glass wrote:
>>> In the meantime could we somehow replace/augment the #ifdef chain in
>>> gpio_init with something keyed off the stdout alias perhaps?
>>
>> Tegra has code to convert a device interrupt number (which uniquely
>> identifies a peripheral in that SoC) to an internal peripheral ID,
>> then these is a function which can enable a peripheral given the ID
>> (funcmux). In some cases you could have multiple options for the
>> funcmux, but there is no easy way to support this.
> 
> I think that although there are multiple options for some functions
> (UARTs come to mind) we haven't yet found the need to make any dynamic
> choices, so it's all static right now.
> 
>>  But this approach
>> might be good enough for sunxi. We can easily write the function to
>> enable the pins for a particular port, and this could go in
>> arch/arm/...sunxi/ perhaps.
> 
> I'm ok with it so long as it isn't going to stand in the way of proper
> dt based pinmux in the future.
> 
> One way to help with that might be to use the allwinner,function
> property in DT as the funcmux name.
> 
> Hans, what do you think?

I'm not 100% sure what you're suggesting here, are you suggesting to
have a 1:1 mapping between function names as stored in allwinner,function
in dts and the value to pass to sunxi_gpio_set_cfgpin ?

This is not going to fly very far, e.g. the "uart0" function has cfg value
of 2 on portb while it has a value of 4 on portf.

So we will really need a sunxi specific function to go from port-no +
allwinner,function-string to a sunxi_gpio_set_cfgpin function.

I think the best thing we can do to not make this function too big is do 3
things:

1) Have a table which only contains mapping where the cfg value is not 2,
most ipblocks have a "primary" gpio port they are intended to be used with,
and this usage maps to a cfg value of 2, and most designs use this, so have
a list of exceptions and return 2 otherwise, this will make debugging of
issues where the mux is not setup a bit harder, but it will keep things a
lot smaller.

2) Only but things in there which are actually used by boards, or we expect
to need in the near future.

3) Have #ifndef CONFIG_SPL_BUILD .. #endif around anything but mmc / uart
entries in that table.

Together those should keep things small enough for the SPL.

Regards,

Hans

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-30  9:36             ` Hans de Goede
@ 2014-10-30 10:14               ` Ian Campbell
  2014-10-31  2:45                 ` Simon Glass
  2014-10-31  9:07                 ` Hans de Goede
  0 siblings, 2 replies; 37+ messages in thread
From: Ian Campbell @ 2014-10-30 10:14 UTC (permalink / raw)
  To: u-boot

On Thu, 2014-10-30 at 10:36 +0100, Hans de Goede wrote:
> Hi,
> 
> On 10/30/2014 10:08 AM, Ian Campbell wrote:
> > On Wed, 2014-10-29 at 13:28 -0600, Simon Glass wrote:
> >>> In the meantime could we somehow replace/augment the #ifdef chain in
> >>> gpio_init with something keyed off the stdout alias perhaps?
> >>
> >> Tegra has code to convert a device interrupt number (which uniquely
> >> identifies a peripheral in that SoC) to an internal peripheral ID,
> >> then these is a function which can enable a peripheral given the ID
> >> (funcmux). In some cases you could have multiple options for the
> >> funcmux, but there is no easy way to support this.
> > 
> > I think that although there are multiple options for some functions
> > (UARTs come to mind) we haven't yet found the need to make any dynamic
> > choices, so it's all static right now.
> > 
> >>  But this approach
> >> might be good enough for sunxi. We can easily write the function to
> >> enable the pins for a particular port, and this could go in
> >> arch/arm/...sunxi/ perhaps.
> > 
> > I'm ok with it so long as it isn't going to stand in the way of proper
> > dt based pinmux in the future.
> > 
> > One way to help with that might be to use the allwinner,function
> > property in DT as the funcmux name.
> > 
> > Hans, what do you think?
> 
> I'm not 100% sure what you're suggesting here, are you suggesting to
> have a 1:1 mapping between function names as stored in allwinner,function
> in dts and the value to pass to sunxi_gpio_set_cfgpin ?

I was imagining a function which would take the string "uart0" and would
call sunxi_gpio_set_cfgpin with whatever values that would entail in
order to make uart0 work, not one which would try and return something
that the caller would then use.

> This is not going to fly very far, e.g. the "uart0" function has cfg value
> of 2 on portb while it has a value of 4 on portf.

I believe we currently statically use either portb or portf (I've not
looked up which, IIRC it changed recently, but I don't recall which
way), so my proposed function would just DTRT. Of course if we ever find
we need something more dynamic then we would have to do a proper pinmux
implementation (or at least something closer to a proper one)

Ian.

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-30 10:14               ` Ian Campbell
@ 2014-10-31  2:45                 ` Simon Glass
  2014-10-31  9:07                 ` Hans de Goede
  1 sibling, 0 replies; 37+ messages in thread
From: Simon Glass @ 2014-10-31  2:45 UTC (permalink / raw)
  To: u-boot

Hi Ian,

On 30 October 2014 04:14, Ian Campbell <ijc@hellion.org.uk> wrote:
> On Thu, 2014-10-30 at 10:36 +0100, Hans de Goede wrote:
>> Hi,
>>
>> On 10/30/2014 10:08 AM, Ian Campbell wrote:
>> > On Wed, 2014-10-29 at 13:28 -0600, Simon Glass wrote:
>> >>> In the meantime could we somehow replace/augment the #ifdef chain in
>> >>> gpio_init with something keyed off the stdout alias perhaps?
>> >>
>> >> Tegra has code to convert a device interrupt number (which uniquely
>> >> identifies a peripheral in that SoC) to an internal peripheral ID,
>> >> then these is a function which can enable a peripheral given the ID
>> >> (funcmux). In some cases you could have multiple options for the
>> >> funcmux, but there is no easy way to support this.
>> >
>> > I think that although there are multiple options for some functions
>> > (UARTs come to mind) we haven't yet found the need to make any dynamic
>> > choices, so it's all static right now.
>> >
>> >>  But this approach
>> >> might be good enough for sunxi. We can easily write the function to
>> >> enable the pins for a particular port, and this could go in
>> >> arch/arm/...sunxi/ perhaps.
>> >
>> > I'm ok with it so long as it isn't going to stand in the way of proper
>> > dt based pinmux in the future.
>> >
>> > One way to help with that might be to use the allwinner,function
>> > property in DT as the funcmux name.
>> >
>> > Hans, what do you think?
>>
>> I'm not 100% sure what you're suggesting here, are you suggesting to
>> have a 1:1 mapping between function names as stored in allwinner,function
>> in dts and the value to pass to sunxi_gpio_set_cfgpin ?
>
> I was imagining a function which would take the string "uart0" and would
> call sunxi_gpio_set_cfgpin with whatever values that would entail in
> order to make uart0 work, not one which would try and return something
> that the caller would then use.

If you only have a few pins that uart0 can appear on, then you could
pass a parameter telling the function which combination to use. I'm
not sure about passing a string for the uart0 - would not an enum
defined globally for sunix not be better?

>
>> This is not going to fly very far, e.g. the "uart0" function has cfg value
>> of 2 on portb while it has a value of 4 on portf.
>
> I believe we currently statically use either portb or portf (I've not
> looked up which, IIRC it changed recently, but I don't recall which
> way), so my proposed function would just DTRT. Of course if we ever find
> we need something more dynamic then we would have to do a proper pinmux
> implementation (or at least something closer to a proper one)

SGTM.

Regards,
Simon

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-30 10:14               ` Ian Campbell
  2014-10-31  2:45                 ` Simon Glass
@ 2014-10-31  9:07                 ` Hans de Goede
  2014-10-31  9:30                   ` Ian Campbell
  1 sibling, 1 reply; 37+ messages in thread
From: Hans de Goede @ 2014-10-31  9:07 UTC (permalink / raw)
  To: u-boot

Hi Ian,

On 30 October 2014 04:14, Ian Campbell <ijc@hellion.org.uk> wrote:
> On Thu, 2014-10-30 at 10:36 +0100, Hans de Goede wrote:
>> Hi,
>>
>> On 10/30/2014 10:08 AM, Ian Campbell wrote:
>> > On Wed, 2014-10-29 at 13:28 -0600, Simon Glass wrote:
>> >>> In the meantime could we somehow replace/augment the #ifdef chain in
>> >>> gpio_init with something keyed off the stdout alias perhaps?
>> >>
>> >> Tegra has code to convert a device interrupt number (which uniquely
>> >> identifies a peripheral in that SoC) to an internal peripheral ID,
>> >> then these is a function which can enable a peripheral given the ID
>> >> (funcmux). In some cases you could have multiple options for the
>> >> funcmux, but there is no easy way to support this.
>> >
>> > I think that although there are multiple options for some functions
>> > (UARTs come to mind) we haven't yet found the need to make any dynamic
>> > choices, so it's all static right now.
>> >
>> >>  But this approach
>> >> might be good enough for sunxi. We can easily write the function to
>> >> enable the pins for a particular port, and this could go in
>> >> arch/arm/...sunxi/ perhaps.
>> >
>> > I'm ok with it so long as it isn't going to stand in the way of proper
>> > dt based pinmux in the future.
>> >
>> > One way to help with that might be to use the allwinner,function
>> > property in DT as the funcmux name.
>> >
>> > Hans, what do you think?
>>
>> I'm not 100% sure what you're suggesting here, are you suggesting to
>> have a 1:1 mapping between function names as stored in allwinner,function
>> in dts and the value to pass to sunxi_gpio_set_cfgpin ?
>
> I was imagining a function which would take the string "uart0" and would
> call sunxi_gpio_set_cfgpin with whatever values that would entail in
> order to make uart0 work, not one which would try and return something
> that the caller would then use.

I assume that it will take a string, e.g. "uart0" and a pin, since
uart0 can be routed to either porta or portb, other then that having the
function directly call sunxi_gpio_set_cfgpin rather then returning the
value to pass to sunxi_gpio_set_cfgpin is a good idea.

>
>> This is not going to fly very far, e.g. the "uart0" function has cfg value
>> of 2 on portb while it has a value of 4 on portf.
>
> I believe we currently statically use either portb or portf (I've not
> looked up which, IIRC it changed recently, but I don't recall which
> way), so my proposed function would just DTRT. Of course if we ever find
> we need something more dynamic then we would have to do a proper pinmux
> implementation (or at least something closer to a proper one)

Ah, so you mainly just want to clean up the existing #ifdef mess ? I was aiming
for something which we could eventually use to get the info from devicetree
and not have any uart info hardcoded into the binaries at all.

Regards,

Hans

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-31  9:07                 ` Hans de Goede
@ 2014-10-31  9:30                   ` Ian Campbell
  2014-10-31  9:33                     ` Hans de Goede
  0 siblings, 1 reply; 37+ messages in thread
From: Ian Campbell @ 2014-10-31  9:30 UTC (permalink / raw)
  To: u-boot

On Fri, 2014-10-31 at 10:07 +0100, Hans de Goede wrote:
> Hi Ian,
> 
> On 30 October 2014 04:14, Ian Campbell <ijc@hellion.org.uk> wrote:
> > On Thu, 2014-10-30 at 10:36 +0100, Hans de Goede wrote:
> >> Hi,
> >>
> >> On 10/30/2014 10:08 AM, Ian Campbell wrote:
> >> > On Wed, 2014-10-29 at 13:28 -0600, Simon Glass wrote:
> >> >>> In the meantime could we somehow replace/augment the #ifdef chain in
> >> >>> gpio_init with something keyed off the stdout alias perhaps?
> >> >>
> >> >> Tegra has code to convert a device interrupt number (which uniquely
> >> >> identifies a peripheral in that SoC) to an internal peripheral ID,
> >> >> then these is a function which can enable a peripheral given the ID
> >> >> (funcmux). In some cases you could have multiple options for the
> >> >> funcmux, but there is no easy way to support this.
> >> >
> >> > I think that although there are multiple options for some functions
> >> > (UARTs come to mind) we haven't yet found the need to make any dynamic
> >> > choices, so it's all static right now.
> >> >
> >> >>  But this approach
> >> >> might be good enough for sunxi. We can easily write the function to
> >> >> enable the pins for a particular port, and this could go in
> >> >> arch/arm/...sunxi/ perhaps.
> >> >
> >> > I'm ok with it so long as it isn't going to stand in the way of proper
> >> > dt based pinmux in the future.
> >> >
> >> > One way to help with that might be to use the allwinner,function
> >> > property in DT as the funcmux name.
> >> >
> >> > Hans, what do you think?
> >>
> >> I'm not 100% sure what you're suggesting here, are you suggesting to
> >> have a 1:1 mapping between function names as stored in allwinner,function
> >> in dts and the value to pass to sunxi_gpio_set_cfgpin ?
> >
> > I was imagining a function which would take the string "uart0" and would
> > call sunxi_gpio_set_cfgpin with whatever values that would entail in
> > order to make uart0 work, not one which would try and return something
> > that the caller would then use.
> 
> I assume that it will take a string, e.g. "uart0" and a pin, since
> uart0 can be routed to either porta or portb, other then that having the
> function directly call sunxi_gpio_set_cfgpin rather then returning the
> value to pass to sunxi_gpio_set_cfgpin is a good idea.

Actually right now we don't actually dynamically select anything for
uarts, so we could just as easily hardcode which pins to use in this new
function as we do now, it's still a step in the right direction.

> >> This is not going to fly very far, e.g. the "uart0" function has cfg value
> >> of 2 on portb while it has a value of 4 on portf.
> >
> > I believe we currently statically use either portb or portf (I've not
> > looked up which, IIRC it changed recently, but I don't recall which
> > way), so my proposed function would just DTRT. Of course if we ever find
> > we need something more dynamic then we would have to do a proper pinmux
> > implementation (or at least something closer to a proper one)
> 
> Ah, so you mainly just want to clean up the existing #ifdef mess ? I was aiming
> for something which we could eventually use to get the info from devicetree
> and not have any uart info hardcoded into the binaries at all.

What I'm really hoping for is to enable Simon to get his DM series
accepted, but in a way which won't get in the way of future work to use
DT fully. Even better if it takes us a little nearer to the full DT
path, at least in terms of the interfaces used.

This subthreaded initially started with the suggestion from Simon: "We
can easily write the function to enable the pins for a particular port,
and this could go in arch/arm/...sunxi/ perhaps.". Which sounded OK to
me so long as it doesn't get in the way of future work to fully use DT.
So with that in mind I suggested that using the DT function name as the
key passed to that function would help achieve that aim.

My thinking was that this function would be a nexus point where we could
independently replace the callers (individually on a driver by driver
basis) with code parsing the DT to find the function name and the
backend with code to lookup the correct pinmux stuff in DT and do the
necessary setup.

Maybe I've misjudged what the final DT pinmux thing would look like
though, in which case maybe this suggestion doesn't actually achieve the
aim of not getting in the way.

Ian.

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-31  9:30                   ` Ian Campbell
@ 2014-10-31  9:33                     ` Hans de Goede
  2014-10-31  9:55                       ` Ian Campbell
  0 siblings, 1 reply; 37+ messages in thread
From: Hans de Goede @ 2014-10-31  9:33 UTC (permalink / raw)
  To: u-boot

Hi,

On 10/31/2014 10:30 AM, Ian Campbell wrote:
> On Fri, 2014-10-31 at 10:07 +0100, Hans de Goede wrote:
>> Hi Ian,
>>
>> On 30 October 2014 04:14, Ian Campbell <ijc@hellion.org.uk> wrote:
>>> On Thu, 2014-10-30 at 10:36 +0100, Hans de Goede wrote:
>>>> Hi,
>>>>
>>>> On 10/30/2014 10:08 AM, Ian Campbell wrote:
>>>>> On Wed, 2014-10-29 at 13:28 -0600, Simon Glass wrote:
>>>>>>> In the meantime could we somehow replace/augment the #ifdef chain in
>>>>>>> gpio_init with something keyed off the stdout alias perhaps?
>>>>>>
>>>>>> Tegra has code to convert a device interrupt number (which uniquely
>>>>>> identifies a peripheral in that SoC) to an internal peripheral ID,
>>>>>> then these is a function which can enable a peripheral given the ID
>>>>>> (funcmux). In some cases you could have multiple options for the
>>>>>> funcmux, but there is no easy way to support this.
>>>>>
>>>>> I think that although there are multiple options for some functions
>>>>> (UARTs come to mind) we haven't yet found the need to make any dynamic
>>>>> choices, so it's all static right now.
>>>>>
>>>>>>  But this approach
>>>>>> might be good enough for sunxi. We can easily write the function to
>>>>>> enable the pins for a particular port, and this could go in
>>>>>> arch/arm/...sunxi/ perhaps.
>>>>>
>>>>> I'm ok with it so long as it isn't going to stand in the way of proper
>>>>> dt based pinmux in the future.
>>>>>
>>>>> One way to help with that might be to use the allwinner,function
>>>>> property in DT as the funcmux name.
>>>>>
>>>>> Hans, what do you think?
>>>>
>>>> I'm not 100% sure what you're suggesting here, are you suggesting to
>>>> have a 1:1 mapping between function names as stored in allwinner,function
>>>> in dts and the value to pass to sunxi_gpio_set_cfgpin ?
>>>
>>> I was imagining a function which would take the string "uart0" and would
>>> call sunxi_gpio_set_cfgpin with whatever values that would entail in
>>> order to make uart0 work, not one which would try and return something
>>> that the caller would then use.
>>
>> I assume that it will take a string, e.g. "uart0" and a pin, since
>> uart0 can be routed to either porta or portb, other then that having the
>> function directly call sunxi_gpio_set_cfgpin rather then returning the
>> value to pass to sunxi_gpio_set_cfgpin is a good idea.
> 
> Actually right now we don't actually dynamically select anything for
> uarts, so we could just as easily hardcode which pins to use in this new
> function as we do now, it's still a step in the right direction.
> 
>>>> This is not going to fly very far, e.g. the "uart0" function has cfg value
>>>> of 2 on portb while it has a value of 4 on portf.
>>>
>>> I believe we currently statically use either portb or portf (I've not
>>> looked up which, IIRC it changed recently, but I don't recall which
>>> way), so my proposed function would just DTRT. Of course if we ever find
>>> we need something more dynamic then we would have to do a proper pinmux
>>> implementation (or at least something closer to a proper one)
>>
>> Ah, so you mainly just want to clean up the existing #ifdef mess ? I was aiming
>> for something which we could eventually use to get the info from devicetree
>> and not have any uart info hardcoded into the binaries at all.
> 
> What I'm really hoping for is to enable Simon to get his DM series
> accepted, but in a way which won't get in the way of future work to use
> DT fully. Even better if it takes us a little nearer to the full DT
> path, at least in terms of the interfaces used.

Ah, but I plan to merge the v3 Simon has posted to u-boot-sunxi/next and then
do a pull-req with that in there this weekend. IOW we don't need to solve
the pinmux problem for that series to get merged (from my pov). So maybe we
should just delay dealing with the pinmux issue until we really need to ?

Regards,

Hans

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
  2014-10-31  9:33                     ` Hans de Goede
@ 2014-10-31  9:55                       ` Ian Campbell
  0 siblings, 0 replies; 37+ messages in thread
From: Ian Campbell @ 2014-10-31  9:55 UTC (permalink / raw)
  To: u-boot

On Fri, 2014-10-31 at 10:33 +0100, Hans de Goede wrote:

> Ah, but I plan to merge the v3 Simon has posted to u-boot-sunxi/next and then
> do a pull-req with that in there this weekend. IOW we don't need to solve
> the pinmux problem for that series to get merged (from my pov). So maybe we
> should just delay dealing with the pinmux issue until we really need to ?

Does it work without having done *something* about this?

AFAICT it currently relies on the stdout-path in the DT precisely
matching CONFIG_CONS_INDEX (due to its affect on the code in
gpio_init()), doesn't it?

Ian.

^ permalink raw reply	[flat|nested] 37+ messages in thread
end of thread, other threads:[~2014-10-31  9:55 UTC | newest]

Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-10-23  4:02 [U-Boot] [PATCH v2 0/6] dm: Introduce driver model for sunxi Simon Glass
2014-10-23  4:02 ` [U-Boot] [PATCH v2 1/6] dm: sunxi: dts: Add sun7i device tree files Simon Glass
2014-10-24  8:32   ` [U-Boot] [U-Boot, v2, " Hans de Goede
2014-10-28  1:05     ` Simon Glass
2014-10-23  4:02 ` [U-Boot] [PATCH v2 2/6] dm: sunxi: Add a new config for an FDT-based pcDuino3 Simon Glass
2014-10-24  8:38   ` [U-Boot] [U-Boot, v2, " Hans de Goede
2014-10-28  0:04     ` Simon Glass
2014-10-28  9:13       ` Hans de Goede
2014-10-29  3:02         ` Simon Glass
2014-10-29  9:32           ` Hans de Goede
2014-10-29 19:30             ` Simon Glass
2014-10-30  8:36               ` Hans de Goede
2014-10-23  4:02 ` [U-Boot] [PATCH v2 3/6] dm: sunxi: Add pinmux functions which take a bank parameter Simon Glass
2014-10-24  9:00   ` [U-Boot] [U-Boot, v2, " Hans de Goede
2014-10-23  4:02 ` [U-Boot] [PATCH v2 4/6] dm: sunxi: Make sure that GPIOs are requested Simon Glass
2014-10-24  9:01   ` [U-Boot] [U-Boot, v2, " Hans de Goede
2014-10-23  4:02 ` [U-Boot] [PATCH v2 5/6] dm: sunxi: Modify the GPIO driver to support driver model Simon Glass
2014-10-24  9:08   ` [U-Boot] [U-Boot, v2, " Hans de Goede
2014-10-28  0:05     ` Simon Glass
2014-10-28  2:53       ` Chen-Yu Tsai
2014-10-28  3:29         ` Simon Glass
2014-10-28  3:39           ` Chen-Yu Tsai
2014-10-28 14:30             ` Maxime Ripard
2014-10-23  4:02 ` [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using " Simon Glass
2014-10-24  9:10   ` [U-Boot] [U-Boot, v2, " Hans de Goede
2014-10-24  9:42   ` [U-Boot] [PATCH v2 " Ian Campbell
2014-10-28  0:06     ` Simon Glass
2014-10-29  8:05       ` Ian Campbell
2014-10-29 19:28         ` Simon Glass
2014-10-30  9:08           ` Ian Campbell
2014-10-30  9:36             ` Hans de Goede
2014-10-30 10:14               ` Ian Campbell
2014-10-31  2:45                 ` Simon Glass
2014-10-31  9:07                 ` Hans de Goede
2014-10-31  9:30                   ` Ian Campbell
2014-10-31  9:33                     ` Hans de Goede
2014-10-31  9:55                       ` Ian Campbell

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