[PATCH v4 0/6] sh73a0 common clock framework implementation

[PATCH v4 0/6] sh73a0 common clock framework implementation

[Ulrich Hecht]

Hi!

This integrates the consistency fixes suggested by Laurent and omits the
ethernet clock hack.

CU
Uli


Changes since v3:
- fixed bindings to match the implementation
- handle extal division in CPG driver, dump extal?_div2_clk
- added acks
- dropped eth clock hack

Changes since v2:
- split CCF DT description
- tabbed constants in CPG bits header file
- reordered patches to avoid need for shmobile_clk_workaround()
- removed said workaround
- squashed unmerged remains of CMT1 DT description into MSTP clocks patch
- renamed clock zb1 to zb
- removed DIV6 stuff, will be a separate series

Changes since v1:
- div6 patch replaced with v4
- split off div6 extended clocks
- added cmt1 DT description
- added MSTP clock assignments
- reordered according to dependencies
- removed dummy frequencies in extal2, extcki
- removed enable_on_init on zb1 and flctlck
- added missing tpu4 in mstp3_clks
- use c->parent in cpg driver
- fix some style issues


Ulrich Hecht (6):
  clk: shmobile: sh73a0 common clock framework implementation
  ARM: shmobile: sh73a0: Add CPG register bits header
  ARM: shmobile: sh73a0: Common clock framework DT description
  ARM: shmobile: kzm9g-reference: Common clock framework DT description
  ARM: shmobile: sh73a0: add MSTP clock assignments to DT
  ARM: shmobile: sh73a0: disable legacy clock initialization

 .../bindings/clock/renesas,sh73a0-cpg-clocks.txt   |  35 ++
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts       |   4 +
 arch/arm/boot/dts/sh73a0.dtsi                      | 358 +++++++++++++++++++++
 arch/arm/mach-shmobile/setup-sh73a0.c              |   5 +-
 drivers/clk/shmobile/Makefile                      |   1 +
 drivers/clk/shmobile/clk-sh73a0.c                  | 204 ++++++++++++
 include/dt-bindings/clock/sh73a0-clock.h           |  79 +++++
 7 files changed, 685 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt
 create mode 100644 drivers/clk/shmobile/clk-sh73a0.c
 create mode 100644 include/dt-bindings/clock/sh73a0-clock.h

-- 
1.8.4.5

Re: [PATCH v4 0/6] sh73a0 common clock framework implementation

[Geert Uytterhoeven]

Hi Ulrich

With this series applied (also with the previous version), kzm9g-multiplatform
(with sh73a0-kzm9g-reference.dtb) locks up after initializing ttySC4, i.e.
after printing

    sh-sci e6c80000.serial: ttySC4 at MMIO 0xe6c80000 (irq = 110,
base_baud = 0) is a scifa

If I comment out the "clocks" property of scifa4 in the dtsi, it continues
(without any serial output, of course).

Do you have any clue?

I'm also using the scif early debug patch, else I don't see any serial output
at all.

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v4 0/6] sh73a0 common clock framework implementation

[Ulrich Hecht]

On Fri, Nov 7, 2014 at 3:20 PM, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> Hi Ulrich
>
> With this series applied (also with the previous version), kzm9g-multiplatform
> (with sh73a0-kzm9g-reference.dtb) locks up after initializing ttySC4, i.e.
> after printing
>
>     sh-sci e6c80000.serial: ttySC4 at MMIO 0xe6c80000 (irq = 110,
> base_baud = 0) is a scifa
>
> If I comment out the "clocks" property of scifa4 in the dtsi, it continues
> (without any serial output, of course).
>
> Do you have any clue?

You might have better luck with the div6 patch applied as well. The
upstream div6 driver resets the EXSRC bits when setting the divider,
and IIRC that switches the parent of sub from extal2 to pll1_div2 on
the kzm9g board. With the patch applied, the bits are preserved.

CU
Uli

Re: [PATCH v4 0/6] sh73a0 common clock framework implementation

[Geert Uytterhoeven]

Hi Ulrich,

On Fri, Nov 7, 2014 at 4:07 PM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> On Fri, Nov 7, 2014 at 3:20 PM, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>> With this series applied (also with the previous version), kzm9g-multiplatform
>> (with sh73a0-kzm9g-reference.dtb) locks up after initializing ttySC4, i.e.
>> after printing
>>
>>     sh-sci e6c80000.serial: ttySC4 at MMIO 0xe6c80000 (irq = 110,
>> base_baud = 0) is a scifa
>>
>> If I comment out the "clocks" property of scifa4 in the dtsi, it continues
>> (without any serial output, of course).
>>
>> Do you have any clue?
>
> You might have better luck with the div6 patch applied as well. The
> upstream div6 driver resets the EXSRC bits when setting the divider,
> and IIRC that switches the parent of sub from extal2 to pll1_div2 on
> the kzm9g board. With the patch applied, the bits are preserved.

Right. After applying the div6 series, and a modified version of "ARM:
shmobile: sh73a0: add selectable sources to DIV6 clocks" (dropped
renesas,src-shift/renesas,src-width, padded clocks to 4 or 8 parents) it
works. Thanks!

kzm9g-multiplatform is getting in good shape now...

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v4 0/6] sh73a0 common clock framework implementation

[Geert Uytterhoeven]

	Hi Ulrich,

On Thu, 6 Nov 2014, Ulrich Hecht wrote:
> This integrates the consistency fixes suggested by Laurent and omits the
> ethernet clock hack.

Thanks for your updated series!

Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
in combination with:

  - your patch "[PATCH v3 7/7] ARM: shmobile: kzm9g-reference: require ZB clock
    for Ethernet controller", else the Ethernet doesn't work,
  - your series "[PATCH v7 0/2] clk: shmobile: DIV6 clock variable parent
    support",
  - your patch "[PATCH] ARM: shmobile: sh73a0: add selectable sources to
    DIV6", which I updated for the series above, result below.

From a93dfe32b2ed92048d812b000c7b80fcf6d87c42 Mon Sep 17 00:00:00 2001
From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Date: Tue, 2 Sep 2014 11:13:06 +0200
Subject: [PATCH] ARM: shmobile: sh73a0: add selectable sources to DIV6
 clocks

Specifies clock sources and register bits.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
[geert: Drop renesas,src-shift/renesas,src-width, pad to 4 or 8 parents]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/boot/dts/sh73a0.dtsi | 64 ++++++++++++++++++++++++++++++-------------
 1 file changed, 45 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 31332c662a409bf2..ccb2b2c54d4711c4 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -410,133 +410,159 @@
 		vclk1_clk: vclk1_clk@e6150008 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150008 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
+				 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
+				 <0>;
 			#clock-cells = <0>;
 			clock-output-names = "vclk1";
 		};
 		vclk2_clk: vclk2_clk@e615000c {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe615000c 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
+				 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
+				 <0>;
 			#clock-cells = <0>;
 			clock-output-names = "vclk2";
 		};
 		vclk3_clk: vclk3_clk@e615001c {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe615001c 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
+				 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
+				 <0>;
 			#clock-cells = <0>;
 			clock-output-names = "vclk3";
 		};
 		zb_clk: zb_clk@e6150010 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150010 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>,
+				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>, <0>;
 			#clock-cells = <0>;
 			clock-output-names = "zb";
 		};
 		flctl_clk: flctl_clk@e6150014 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150014 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>,
+				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>, <0>;
 			#clock-cells = <0>;
 			clock-output-names = "flctlck";
 		};
 		sdhi0_clk: sdhi0_clk@e6150074 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150074 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&pll1_div13_clk>, <0>;
 			#clock-cells = <0>;
 			clock-output-names = "sdhi0ck";
 		};
 		sdhi1_clk: sdhi1_clk@e6150078 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150078 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&pll1_div13_clk>, <0>;
 			#clock-cells = <0>;
 			clock-output-names = "sdhi1ck";
 		};
 		sdhi2_clk: sdhi2_clk@e615007c {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe615007c 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&pll1_div13_clk>, <0>;
 			#clock-cells = <0>;
 			clock-output-names = "sdhi2ck";
 		};
 		fsia_clk: fsia_clk@e6150018 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150018 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&fsiack_clk>, <&fsiack_clk>;
 			#clock-cells = <0>;
 			clock-output-names = "fsia";
 		};
 		fsib_clk: fsib_clk@e6150090 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150090 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&fsibck_clk>, <&fsibck_clk>;
 			#clock-cells = <0>;
 			clock-output-names = "fsib";
 		};
 		sub_clk: sub_clk@e6150080 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150080 4>;
-			clocks = <&extal2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&extal2_clk>, <&extal2_clk>;
 			#clock-cells = <0>;
 			clock-output-names = "sub";
 		};
 		spua_clk: spua_clk@e6150084 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150084 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&extal2_clk>, <&extal2_clk>;
 			#clock-cells = <0>;
 			clock-output-names = "spua";
 		};
 		spuv_clk: spuv_clk@e6150094 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150094 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&extal2_clk>, <&extal2_clk>;
 			#clock-cells = <0>;
 			clock-output-names = "spuv";
 		};
 		msu_clk: msu_clk@e6150088 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150088 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <0>, <0>;
 			#clock-cells = <0>;
 			clock-output-names = "msu";
 		};
 		hsi_clk: hsi_clk@e615008c {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe615008c 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&pll1_div7_clk>, <0>;
 			#clock-cells = <0>;
 			clock-output-names = "hsi";
 		};
 		mfg1_clk: mfg1_clk@e6150098 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150098 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <0>, <0>;
 			#clock-cells = <0>;
 			clock-output-names = "mfg1";
 		};
 		mfg2_clk: mfg2_clk@e615009c {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe615009c 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <0>, <0>;
 			#clock-cells = <0>;
 			clock-output-names = "mfg2";
 		};
 		dsit_clk: dsit_clk@e6150060 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150060 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <0>, <0>;
 			#clock-cells = <0>;
 			clock-output-names = "dsit";
 		};
 		dsi0p_clk: dsi0p_clk@e6150064 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150064 4>;
-			clocks = <&pll1_div2_clk>;
+			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+				 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
+				 <&extcki_clk>, <0>, <0>, <0>;
 			#clock-cells = <0>;
 			clock-output-names = "dsi0pck";
 		};
-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds