* [PATCH 0/2] vlv: fix some runtime PM errors
@ 2014-11-19 14:25 Imre Deak
2014-11-19 14:25 ` [PATCH 1/2] drm/i915: vlv: fix cdclk setting during modeset while suspended Imre Deak
2014-11-19 14:25 ` [PATCH 2/2] drm/i915: vlv: increase timeout when setting idle GPU freq Imre Deak
0 siblings, 2 replies; 7+ messages in thread
From: Imre Deak @ 2014-11-19 14:25 UTC (permalink / raw)
To: intel-gfx
While running pm_rpm subtests on VLV I saw some errors, even with the
pending fix on the ML applied (the one for gem pwrite while suspended
fix). With the following 2 patches all subtests passed for me. There
is still one ERROR remaining, reported by vlv_check_no_gt_access(), I
haven't looked into that yet.
Imre Deak (2):
drm/i915: vlv: fix cdclk setting during modeset while suspended
drm/i915: vlv: increase timeout when setting idle GPU freq
drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
drivers/gpu/drm/i915/intel_pm.c | 2 +-
2 files changed, 14 insertions(+), 1 deletion(-)
--
1.8.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] drm/i915: vlv: fix cdclk setting during modeset while suspended
2014-11-19 14:25 [PATCH 0/2] vlv: fix some runtime PM errors Imre Deak
@ 2014-11-19 14:25 ` Imre Deak
2014-11-20 14:49 ` Ville Syrjälä
2014-11-19 14:25 ` [PATCH 2/2] drm/i915: vlv: increase timeout when setting idle GPU freq Imre Deak
1 sibling, 1 reply; 7+ messages in thread
From: Imre Deak @ 2014-11-19 14:25 UTC (permalink / raw)
To: intel-gfx
Currently after doing DPMS-OFF on all outputs CDCLK won't be set to its
minimum value as it should. A subsequent modeset to turn off all outputs
will thus run with all power domains disabled, and notice that it needs
to change CDCLK to its minimum value. Since the power domains are
disabled this will emit a register-access-while-suspended WARN and fail
to set the minimum freq.
The proper solution for this is to set the minimum frequency during
DPMS-OFF. That needs a bigger rework that would take into account the
user DPMS setting too during the calculation of the new modesetting
configuration. Until that's done this stop-gap solution gets the PIPE-A
power domain during setting the CDCLK; this domain covers the HW blocks
needed for this.
Idea to use PIPE-A domain from Ville.
Testcase: igt/pm_rpm
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=82939
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9de2f69..6f29a72 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4939,10 +4939,23 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
if (req_cdclk != dev_priv->vlv_cdclk_freq) {
+ /*
+ * FIXME: We can end up here with all power domains off, yet
+ * with a CDCLK frequency other than the minimum. To account
+ * for this take the PIPE-A power domain, which covers the HW
+ * blocks needed for the following programming. This can be
+ * removed once it's guaranteed that we get here either with
+ * the minimum CDCLK set, or the required power domains
+ * enabled.
+ */
+ intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
+
if (IS_CHERRYVIEW(dev))
cherryview_set_cdclk(dev, req_cdclk);
else
valleyview_set_cdclk(dev, req_cdclk);
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
}
}
--
1.8.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915: vlv: increase timeout when setting idle GPU freq
2014-11-19 14:25 [PATCH 0/2] vlv: fix some runtime PM errors Imre Deak
2014-11-19 14:25 ` [PATCH 1/2] drm/i915: vlv: fix cdclk setting during modeset while suspended Imre Deak
@ 2014-11-19 14:25 ` Imre Deak
2014-11-20 14:12 ` Daniel Vetter
` (2 more replies)
1 sibling, 3 replies; 7+ messages in thread
From: Imre Deak @ 2014-11-19 14:25 UTC (permalink / raw)
To: intel-gfx
I saw punit timeouts in vlv_set_rps_idle() while running various
subtests of pm_rpm. Increasing the timeout to 100ms got rid of the
issue.
Testcase: igt/pm_rpm
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=82939
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5cc0ebc..3a58797 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4451,7 +4451,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
dev_priv->rps.min_freq_softlimit);
if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
- & GENFREQSTATUS) == 0, 5))
+ & GENFREQSTATUS) == 0, 100))
DRM_ERROR("timed out waiting for Punit\n");
vlv_force_gfx_clock(dev_priv, false);
--
1.8.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: vlv: increase timeout when setting idle GPU freq
2014-11-19 14:25 ` [PATCH 2/2] drm/i915: vlv: increase timeout when setting idle GPU freq Imre Deak
@ 2014-11-20 14:12 ` Daniel Vetter
2014-11-20 14:52 ` Ville Syrjälä
2014-11-21 1:15 ` [PATCH 2/2] drm/i915: vlv: increase timeout when shuang.he
2 siblings, 0 replies; 7+ messages in thread
From: Daniel Vetter @ 2014-11-20 14:12 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Nov 19, 2014 at 04:25:38PM +0200, Imre Deak wrote:
> I saw punit timeouts in vlv_set_rps_idle() while running various
> subtests of pm_rpm. Increasing the timeout to 100ms got rid of the
> issue.
>
> Testcase: igt/pm_rpm
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=82939
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Tested-by: Guo Jinxian <jinxianx.guo@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5cc0ebc..3a58797 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4451,7 +4451,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
> dev_priv->rps.min_freq_softlimit);
>
> if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
> - & GENFREQSTATUS) == 0, 5))
> + & GENFREQSTATUS) == 0, 100))
> DRM_ERROR("timed out waiting for Punit\n");
>
> vlv_force_gfx_clock(dev_priv, false);
> --
> 1.8.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915: vlv: fix cdclk setting during modeset while suspended
2014-11-19 14:25 ` [PATCH 1/2] drm/i915: vlv: fix cdclk setting during modeset while suspended Imre Deak
@ 2014-11-20 14:49 ` Ville Syrjälä
0 siblings, 0 replies; 7+ messages in thread
From: Ville Syrjälä @ 2014-11-20 14:49 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Nov 19, 2014 at 04:25:37PM +0200, Imre Deak wrote:
> Currently after doing DPMS-OFF on all outputs CDCLK won't be set to its
> minimum value as it should. A subsequent modeset to turn off all outputs
> will thus run with all power domains disabled, and notice that it needs
> to change CDCLK to its minimum value. Since the power domains are
> disabled this will emit a register-access-while-suspended WARN and fail
> to set the minimum freq.
>
> The proper solution for this is to set the minimum frequency during
> DPMS-OFF. That needs a bigger rework that would take into account the
> user DPMS setting too during the calculation of the new modesetting
> configuration. Until that's done this stop-gap solution gets the PIPE-A
> power domain during setting the CDCLK; this domain covers the HW blocks
> needed for this.
>
> Idea to use PIPE-A domain from Ville.
>
> Testcase: igt/pm_rpm
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=82939
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Yeah, not exactly pretty but rearranging the DPMS code seems like a
fairly sizeable task, so I think adding a kludge in the meantime is
acceptable.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9de2f69..6f29a72 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4939,10 +4939,23 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
> int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
>
> if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> + /*
> + * FIXME: We can end up here with all power domains off, yet
> + * with a CDCLK frequency other than the minimum. To account
> + * for this take the PIPE-A power domain, which covers the HW
> + * blocks needed for the following programming. This can be
> + * removed once it's guaranteed that we get here either with
> + * the minimum CDCLK set, or the required power domains
> + * enabled.
> + */
> + intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
> +
> if (IS_CHERRYVIEW(dev))
> cherryview_set_cdclk(dev, req_cdclk);
> else
> valleyview_set_cdclk(dev, req_cdclk);
> +
> + intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
> }
> }
>
> --
> 1.8.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: vlv: increase timeout when setting idle GPU freq
2014-11-19 14:25 ` [PATCH 2/2] drm/i915: vlv: increase timeout when setting idle GPU freq Imre Deak
2014-11-20 14:12 ` Daniel Vetter
@ 2014-11-20 14:52 ` Ville Syrjälä
2014-11-21 1:15 ` [PATCH 2/2] drm/i915: vlv: increase timeout when shuang.he
2 siblings, 0 replies; 7+ messages in thread
From: Ville Syrjälä @ 2014-11-20 14:52 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Nov 19, 2014 at 04:25:38PM +0200, Imre Deak wrote:
> I saw punit timeouts in vlv_set_rps_idle() while running various
> subtests of pm_rpm. Increasing the timeout to 100ms got rid of the
> issue.
>
> Testcase: igt/pm_rpm
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=82939
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5cc0ebc..3a58797 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4451,7 +4451,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
> dev_priv->rps.min_freq_softlimit);
>
> if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
> - & GENFREQSTATUS) == 0, 5))
> + & GENFREQSTATUS) == 0, 100))
If it takes a while then it takes a while. Nothing we can do about
that.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> DRM_ERROR("timed out waiting for Punit\n");
>
> vlv_force_gfx_clock(dev_priv, false);
> --
> 1.8.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: vlv: increase timeout when
2014-11-19 14:25 ` [PATCH 2/2] drm/i915: vlv: increase timeout when setting idle GPU freq Imre Deak
2014-11-20 14:12 ` Daniel Vetter
2014-11-20 14:52 ` Ville Syrjälä
@ 2014-11-21 1:15 ` shuang.he
2 siblings, 0 replies; 7+ messages in thread
From: shuang.he @ 2014-11-21 1:15 UTC (permalink / raw)
To: shuang.he, intel-gfx, imre.deak
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -2 369/369 367/369
ILK +11-17 362/379 356/379
SNB -9 459/459 450/459
IVB -32 535/545 503/545
BYT -1 290/290 289/290
HSW -43 610/610 567/610
BDW -34 451/451 417/451
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_drv_hangman_error-state-capture-render TIMEOUT(27, M25M7M23)PASS(4, M23) TIMEOUT(1, M7)PASS(3, M7)
PNV igt_drv_missed_irq_hang TIMEOUT(28, M23M25M7)PASS(1, M23) TIMEOUT(1, M7)PASS(3, M7)
ILK igt_drv_hangman_error-state-basic TIMEOUT(12, M37M26)PASS(4, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_drv_hangman_error-state-capture-bsd TIMEOUT(2, M26M37)PASS(1, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_drv_hangman_error-state-capture-render PASS(1, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_drv_missed_irq_hang PASS(1, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_gem_reset_stats_ban-render PASS(4, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_gem_reset_stats_close-pending-fork-render PASS(1, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_gem_reset_stats_close-pending-fork-reverse-render PASS(1, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_gem_reset_stats_close-pending-render PASS(1, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_gem_reset_stats_reset-count-render PASS(1, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_gem_reset_stats_reset-stats-render PASS(1, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_gem_workarounds_reset PASS(1, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_kms_flip_absolute-wf_vblank PASS(1, M26) DMESG_WARN(1, M26)PASS(3, M26)
ILK igt_kms_flip_bcs-flip-vs-modeset-interruptible DMESG_WARN(1, M26)PASS(3, M26) DMESG_WARN(1, M26)PASS(3, M26)
ILK igt_kms_flip_bcs-wf_vblank-vs-dpms DMESG_WARN(2, M26)PASS(2, M26) PASS(4, M26)
ILK igt_kms_flip_bcs-wf_vblank-vs-dpms-interruptible DMESG_WARN(1, M26) DMESG_WARN(1, M26)PASS(3, M26)
ILK igt_kms_flip_blocking-wf_vblank DMESG_WARN(1, M26)PASS(3, M26) PASS(4, M26)
ILK igt_kms_flip_flip-vs-absolute-wf_vblank DMESG_WARN(1, M26) PASS(4, M26)
ILK igt_kms_flip_flip-vs-absolute-wf_vblank-interruptible DMESG_WARN(1, M26)PASS(3, M26) PASS(4, M26)
ILK igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible DMESG_WARN(2, M26)PASS(2, M26) PASS(4, M26)
ILK igt_kms_flip_flip-vs-expired-vblank-interruptible DMESG_WARN(2, M26)PASS(2, M26) DMESG_WARN(1, M26)PASS(3, M26)
ILK igt_kms_flip_flip-vs-modeset-vs-hang DMESG_WARN(2, M26)PASS(2, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_kms_flip_flip-vs-modeset-vs-hang-interruptible DMESG_WARN(1, M26)PASS(3, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_kms_flip_flip-vs-panning NSPT(1, M26) DMESG_WARN(3, M26)PASS(1, M26)
ILK igt_kms_flip_flip-vs-panning-vs-hang-interruptible DMESG_WARN(1, M26)PASS(3, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_kms_flip_flip-vs-wf_vblank DMESG_WARN(1, M26)PASS(3, M26) DMESG_WARN(1, M26)PASS(3, M26)
ILK igt_kms_flip_nonexisting-fb-interruptible DMESG_WARN(1, M26)PASS(3, M26) PASS(4, M26)
ILK igt_kms_flip_plain-flip-interruptible DMESG_WARN(1, M26)PASS(3, M26) PASS(4, M26)
ILK igt_kms_flip_rcs-flip-vs-panning PASS(1, M26) DMESG_WARN(1, M26)PASS(3, M26)
ILK igt_kms_flip_rcs-flip-vs-panning-interruptible PASS(1, M26) DMESG_WARN(1, M26)PASS(3, M26)
ILK igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset DMESG_WARN(1, M26) PASS(4, M26)
ILK igt_kms_flip_vblank-vs-hang PASS(1, M26) TIMEOUT(1, M26)PASS(3, M26)
ILK igt_kms_flip_vblank-vs-hang-interruptible PASS(1, M26) TIMEOUT(1, M26)PASS(3, M26)
SNB igt_drv_hangman_error-state-basic TIMEOUT(21, M35M22)PASS(1, M35) TIMEOUT(1, M35)PASS(3, M35)
SNB igt_drv_hangman_error-state-capture-bsd TIMEOUT(21, M35M22)PASS(1, M35) TIMEOUT(1, M35)PASS(3, M35)
SNB igt_drv_hangman_error-state-capture-render TIMEOUT(7, M35M22)PASS(1, M35) TIMEOUT(1, M35)PASS(3, M35)
SNB igt_drv_missed_irq_hang PASS(1, M35) TIMEOUT(1, M35)PASS(3, M35)
SNB igt_gem_reset_stats_reset-count-render PASS(1, M35) TIMEOUT(1, M35)PASS(3, M35)
SNB igt_gem_reset_stats_unrelated-ctx-render PASS(1, M35) TIMEOUT(1, M35)PASS(3, M35)
SNB igt_kms_pipe_crc_basic_hang-read-crc-pipe-A PASS(4, M35) TIMEOUT(1, M35)PASS(3, M35)
SNB igt_kms_pipe_crc_basic_hang-read-crc-pipe-B PASS(1, M35) TIMEOUT(1, M35)PASS(3, M35)
SNB igt_pm_rps_min-max-config-idle PASS(1, M35) FAIL(1, M35)PASS(3, M35)
IVB igt_drv_hangman_error-state-basic TIMEOUT(15, M34M21M4)PASS(4, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_drv_hangman_error-state-capture-blt TIMEOUT(15, M34M21M4)PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_drv_hangman_error-state-capture-bsd TIMEOUT(1, M34)PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_drv_hangman_error-state-capture-render PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_drv_missed_irq_hang PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_bad_reloc_negative-reloc PASS(1, M21) NSPT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_ban-ctx-render DMESG_WARN(2, M21)PASS(2, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_ban-render DMESG_WARN(2, M21)PASS(2, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_close-pending-blt PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_close-pending-bsd PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_close-pending-ctx-render PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_close-pending-fork-blt PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_close-pending-fork-bsd PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_close-pending-fork-render PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_close-pending-fork-reverse-blt PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_close-pending-fork-reverse-bsd PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_close-pending-fork-reverse-render PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_close-pending-render PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_reset-count-blt PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_reset-count-bsd PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_reset-count-ctx-render PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_reset-count-render PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_reset-stats-blt PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_reset-stats-bsd PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_reset-stats-ctx-render PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_reset-stats-render PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_reset_stats_unrelated-ctx-render PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_gem_workarounds_reset PASS(4, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_kms_pipe_crc_basic_hang-read-crc-pipe-A PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_kms_pipe_crc_basic_hang-read-crc-pipe-B PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_kms_pipe_crc_basic_hang-read-crc-pipe-C PASS(1, M21) TIMEOUT(1, M34)PASS(3, M34)
IVB igt_pm_rps_min-max-config-idle PASS(1, M21) FAIL(1, M34)PASS(3, M34)
BYT igt_drv_missed_irq_hang TIMEOUT(32, M36M31)PASS(2, M36M31) TIMEOUT(1, M31)PASS(3, M31)
HSW igt_drv_hangman_error-state-basic TIMEOUT(8, M20M40)PASS(4, M19M40) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_drv_hangman_error-state-capture-blt TIMEOUT(4, M20M40)PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_drv_hangman_error-state-capture-bsd PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_drv_hangman_error-state-capture-render PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_drv_hangman_error-state-capture-vebox PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_drv_missed_irq_hang PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_ban-bsd PASS(4, M19M40) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_ban-ctx-render PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_ban-render PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_ban-vebox PASS(1, M19) TIMEOUT(1, M20)PASS(2, M20)
HSW igt_gem_reset_stats_close-pending-blt PASS(1, M19) FAIL(1, M20)TIMEOUT(1, M20)PASS(2, M20)
HSW igt_gem_reset_stats_close-pending-bsd PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_close-pending-ctx-render PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_close-pending-fork-blt PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_close-pending-fork-bsd PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_close-pending-fork-render PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_close-pending-fork-reverse-blt PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_close-pending-fork-reverse-bsd PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_close-pending-fork-reverse-render PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_close-pending-fork-reverse-vebox PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_close-pending-render PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_close-pending-vebox PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_reset-count-blt PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_reset-count-bsd PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_reset-count-ctx-render PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_reset-count-render PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_reset-count-vebox PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_reset-stats-blt PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_reset-stats-bsd PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_reset-stats-ctx-render PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_reset-stats-render PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_reset_stats_reset-stats-vebox PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_gem_workarounds_reset PASS(4, M19M40) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_kms_flip_flip-vs-modeset-vs-hang PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_kms_flip_flip-vs-modeset-vs-hang-interruptible PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_kms_flip_flip-vs-panning-vs-hang PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_kms_flip_flip-vs-panning-vs-hang-interruptible PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_kms_flip_vblank-vs-hang PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_kms_flip_vblank-vs-hang-interruptible PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_kms_pipe_crc_basic_hang-read-crc-pipe-A PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_kms_pipe_crc_basic_hang-read-crc-pipe-B PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_kms_pipe_crc_basic_hang-read-crc-pipe-C PASS(1, M19) TIMEOUT(1, M20)PASS(3, M20)
HSW igt_pm_rps_min-max-config-idle PASS(4, M19M40) FAIL(1, M20)PASS(3, M20)
BDW igt_drv_hangman_error-state-basic TIMEOUT(12, M28M30)PASS(4, M28M30) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_drv_hangman_error-state-capture-blt TIMEOUT(11, M28M30)PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_drv_hangman_error-state-capture-bsd TIMEOUT(1, M28)PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_drv_hangman_error-state-capture-render PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_drv_hangman_error-state-capture-vebox PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_ban-blt PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_ban-bsd PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_ban-ctx-render PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_ban-render PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_ban-vebox PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-blt PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-bsd PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-ctx-render PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-fork-blt PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-fork-bsd PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-fork-render PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-fork-reverse-blt PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-fork-reverse-bsd PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-fork-reverse-render PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-fork-reverse-vebox PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-fork-vebox PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-render PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_close-pending-vebox PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_reset-count-blt PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_reset-count-bsd PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_reset-count-ctx-render PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_reset-count-render PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_reset-count-vebox PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_reset-stats-blt PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_reset-stats-bsd PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_reset-stats-ctx-render PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_reset-stats-render PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_reset-stats-vebox PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
BDW igt_gem_reset_stats_unrelated-ctx-render PASS(1, M28) TIMEOUT(1, M28)PASS(3, M28)
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2014-11-21 1:15 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-11-19 14:25 [PATCH 0/2] vlv: fix some runtime PM errors Imre Deak
2014-11-19 14:25 ` [PATCH 1/2] drm/i915: vlv: fix cdclk setting during modeset while suspended Imre Deak
2014-11-20 14:49 ` Ville Syrjälä
2014-11-19 14:25 ` [PATCH 2/2] drm/i915: vlv: increase timeout when setting idle GPU freq Imre Deak
2014-11-20 14:12 ` Daniel Vetter
2014-11-20 14:52 ` Ville Syrjälä
2014-11-21 1:15 ` [PATCH 2/2] drm/i915: vlv: increase timeout when shuang.he
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