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* [PATCH 00/10] BYT DSI Dual Link Support
@ 2014-12-04  5:28 Gaurav K Singh
  2014-12-04  5:28 ` [PATCH 01/10] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg Gaurav K Singh
                   ` (9 more replies)
  0 siblings, 10 replies; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-04  5:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

Hi,

These set of patches build on top of the existing DSI Video mode support to
enable dual link MIPI panels with high resolutions. These patches have been
tested on a 25x16 panel and works well.

v2: Commit message added to all patches. All review comments of Jani, Nikula
have been addressed in the second version of patches.

v3: for_each_dsi_port macro used instead of for loop for dual link support

v4: From 6th patch, separte patch created for DSI Pll lock check. All review
comments of Jani, Nikula have been addressed.

Regards
Gaurav

Gaurav K Singh (10):
  drm/i915: New functions added for enabling & disabling MIPI Port Ctrl
    reg
  drm/i915: Added port as parameter to the functions which does
    read/write of DSI Controller
  drm/i915: Add support for port enable/disable for dual link
    configuration
  drm/i915: Pixel Clock changes for DSI dual link
  drm/i915: Dual link needs Shutdown and Turn on packet for both ports
  drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
  drm/i915: cck reg used for checking DSI Pll locked
  drm/i915: MIPI Timings related changes for dual link
  drm/i915: Update the DSI disable path to support dual link panel
    disabling
  drm/i915: Update the DSI enable path to support dual link panel
    enabling

 drivers/gpu/drm/i915/i915_reg.h            |    5 +
 drivers/gpu/drm/i915/intel_bios.h          |    3 +-
 drivers/gpu/drm/i915/intel_dsi.c           |  413 +++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_dsi.h           |    7 +
 drivers/gpu/drm/i915/intel_dsi_cmd.c       |  101 ++++---
 drivers/gpu/drm/i915/intel_dsi_cmd.h       |   46 ++--
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   50 +++-
 drivers/gpu/drm/i915/intel_dsi_pll.c       |    8 +-
 8 files changed, 380 insertions(+), 253 deletions(-)

-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* [PATCH 01/10] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg
  2014-12-04  5:28 [PATCH 00/10] BYT DSI Dual Link Support Gaurav K Singh
@ 2014-12-04  5:28 ` Gaurav K Singh
  2014-12-04  9:13   ` Jani Nikula
  2014-12-04  5:28 ` [PATCH 02/10] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller Gaurav K Singh
                   ` (8 subsequent siblings)
  9 siblings, 1 reply; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-04  5:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

This patch is in preparation for the DSI dual link
port enable and disable related changes.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   43 ++++++++++++++++++++++++++++----------
 1 file changed, 32 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 259cb4a..693736b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -102,6 +102,36 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	return true;
 }
 
+static void intel_dsi_port_enable(struct intel_encoder *encoder)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	u32 temp;
+
+	/* assert ip_tg_enable signal */
+	temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
+	temp = temp | intel_dsi->port_bits;
+	I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
+	POSTING_READ(MIPI_PORT_CTRL(port));
+}
+
+static void intel_dsi_port_disable(struct intel_encoder *encoder)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	u32 temp;
+
+	/* de-assert ip_tg_enable signal */
+	temp = I915_READ(MIPI_PORT_CTRL(port));
+	I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
+	POSTING_READ(MIPI_PORT_CTRL(port));
+}
+
 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
@@ -141,7 +171,6 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
-	u32 temp;
 
 	DRM_DEBUG_KMS("\n");
 
@@ -157,11 +186,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
 
 		wait_for_dsi_fifo_empty(intel_dsi);
 
-		/* assert ip_tg_enable signal */
-		temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
-		temp = temp | intel_dsi->port_bits;
-		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
-		POSTING_READ(MIPI_PORT_CTRL(port));
+		intel_dsi_port_enable(encoder);
 	}
 }
 
@@ -245,11 +270,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 	if (is_vid_mode(intel_dsi)) {
 		wait_for_dsi_fifo_empty(intel_dsi);
 
-		/* de-assert ip_tg_enable signal */
-		temp = I915_READ(MIPI_PORT_CTRL(port));
-		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
-		POSTING_READ(MIPI_PORT_CTRL(port));
-
+		intel_dsi_port_disable(encoder);
 		msleep(2);
 	}
 
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 02/10] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller
  2014-12-04  5:28 [PATCH 00/10] BYT DSI Dual Link Support Gaurav K Singh
  2014-12-04  5:28 ` [PATCH 01/10] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg Gaurav K Singh
@ 2014-12-04  5:28 ` Gaurav K Singh
  2014-12-04  9:14   ` Jani Nikula
  2014-12-04  5:28 ` [PATCH 03/10] drm/i915: Add support for port enable/disable for dual link configuration Gaurav K Singh
                   ` (7 subsequent siblings)
  9 siblings, 1 reply; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-04  5:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

This patch is in preparation of DSI dual link panels. For dual link
panels, few packets needs to be sent to Port A or Port C or both. Based
on the portno from MIPI Sequence Block#53, these sequences needs to be
sent accordingly.

v2: Addressed review comments by Jani
    - port variables named properly

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_cmd.c       |   75 ++++++++++++----------------
 drivers/gpu/drm/i915/intel_dsi_cmd.h       |   46 +++++++++--------
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   25 ++++++----
 3 files changed, 74 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 004fa91..8e30684 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -48,13 +48,11 @@
  * For memory writes, these should probably be used for performance.
  */
 
-static void print_stat(struct intel_dsi *intel_dsi)
+static void print_stat(struct intel_dsi *intel_dsi, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	u32 val;
 
 	val = I915_READ(MIPI_INTR_STAT(port));
@@ -104,13 +102,12 @@ enum dsi_type {
 };
 
 /* enable or disable command mode hs transmissions */
-void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
+void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
+						enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	u32 temp;
 	u32 mask = DBI_FIFO_EMPTY;
 
@@ -125,13 +122,11 @@ void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
 }
 
 static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
-			     u8 data_type, u16 data)
+			     u8 data_type, u16 data, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	u32 ctrl_reg;
 	u32 ctrl;
 	u32 mask;
@@ -149,7 +144,7 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
 
 	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) {
 		DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
-		print_stat(intel_dsi);
+		print_stat(intel_dsi, port);
 	}
 
 	/*
@@ -167,13 +162,11 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
 }
 
 static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
-			    u8 data_type, const u8 *data, int len)
+		u8 data_type, const u8 *data, int len, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	u32 data_reg;
 	int i, j, n;
 	u32 mask;
@@ -204,12 +197,12 @@ static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
 		 * dwords, then wait for not set, then continue. */
 	}
 
-	return dsi_vc_send_short(intel_dsi, channel, data_type, len);
+	return dsi_vc_send_short(intel_dsi, channel, data_type, len, port);
 }
 
 static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
 			       int channel, const u8 *data, int len,
-			       enum dsi_type type)
+			       enum dsi_type type, enum port port)
 {
 	int ret;
 
@@ -217,50 +210,54 @@ static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
 		BUG_ON(type == DSI_GENERIC);
 		ret = dsi_vc_send_short(intel_dsi, channel,
 					MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
-					0);
+					0, port);
 	} else if (len == 1) {
 		ret = dsi_vc_send_short(intel_dsi, channel,
 					type == DSI_GENERIC ?
 					MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
-					MIPI_DSI_DCS_SHORT_WRITE, data[0]);
+					MIPI_DSI_DCS_SHORT_WRITE, data[0],
+					port);
 	} else if (len == 2) {
 		ret = dsi_vc_send_short(intel_dsi, channel,
 					type == DSI_GENERIC ?
 					MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
 					MIPI_DSI_DCS_SHORT_WRITE_PARAM,
-					(data[1] << 8) | data[0]);
+					(data[1] << 8) | data[0], port);
 	} else {
 		ret = dsi_vc_send_long(intel_dsi, channel,
-				       type == DSI_GENERIC ?
-				       MIPI_DSI_GENERIC_LONG_WRITE :
-				       MIPI_DSI_DCS_LONG_WRITE, data, len);
+					type == DSI_GENERIC ?
+					MIPI_DSI_GENERIC_LONG_WRITE :
+					MIPI_DSI_DCS_LONG_WRITE, data, len,
+					port);
 	}
 
 	return ret;
 }
 
 int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
-		     const u8 *data, int len)
+		     const u8 *data, int len, enum port port)
 {
-	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS);
+	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS,
+									port);
 }
 
 int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
-			 const u8 *data, int len)
+			 const u8 *data, int len, enum port port)
 {
-	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC);
+	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC,
+									port);
 }
 
 static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
-					int channel, u8 dcs_cmd)
+				int channel, u8 dcs_cmd, enum port port)
 {
 	return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
-				 dcs_cmd);
+				 dcs_cmd, port);
 }
 
 static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
 					    int channel, u8 *reqdata,
-					    int reqlen)
+					    int reqlen, enum port port)
 {
 	u16 data;
 	u8 data_type;
@@ -282,17 +279,15 @@ static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
 		BUG();
 	}
 
-	return dsi_vc_send_short(intel_dsi, channel, data_type, data);
+	return dsi_vc_send_short(intel_dsi, channel, data_type, data, port);
 }
 
 static int dsi_read_data_return(struct intel_dsi *intel_dsi,
-				u8 *buf, int buflen)
+				u8 *buf, int buflen, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	int i, len = 0;
 	u32 data_reg, val;
 
@@ -312,13 +307,11 @@ static int dsi_read_data_return(struct intel_dsi *intel_dsi,
 }
 
 int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
-		    u8 *buf, int buflen)
+		    u8 *buf, int buflen, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	u32 mask;
 	int ret;
 
@@ -329,7 +322,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
 
 	I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 
-	ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd);
+	ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd, port);
 	if (ret)
 		return ret;
 
@@ -337,7 +330,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
 	if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
 		DRM_ERROR("Timeout waiting for read data.\n");
 
-	ret = dsi_read_data_return(intel_dsi, buf, buflen);
+	ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
 	if (ret < 0)
 		return ret;
 
@@ -348,13 +341,11 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
 }
 
 int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
-			u8 *reqdata, int reqlen, u8 *buf, int buflen)
+		u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	u32 mask;
 	int ret;
 
@@ -366,7 +357,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
 	I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 
 	ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
-					       reqlen);
+					       reqlen, port);
 	if (ret)
 		return ret;
 
@@ -374,7 +365,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
 	if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
 		DRM_ERROR("Timeout waiting for read data.\n");
 
-	ret = dsi_read_data_return(intel_dsi, buf, buflen);
+	ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
 	if (ret < 0)
 		return ret;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h b/drivers/gpu/drm/i915/intel_dsi_cmd.h
index 46aa1ac..326a5ac 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.h
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h
@@ -36,77 +36,81 @@
 #define DPI_LP_MODE_EN	false
 #define DPI_HS_MODE_EN	true
 
-void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable);
+void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
+						enum port port);
 
 int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
-		     const u8 *data, int len);
+		     const u8 *data, int len, enum port port);
 
 int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
-			 const u8 *data, int len);
+			 const u8 *data, int len, enum port port);
 
 int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
-		    u8 *buf, int buflen);
+		    u8 *buf, int buflen, enum port port);
 
 int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
-			u8 *reqdata, int reqlen, u8 *buf, int buflen);
+		u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port);
 
 int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs);
 void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi);
 
 /* XXX: questionable write helpers */
 static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
-				     int channel, u8 dcs_cmd)
+				     int channel, u8 dcs_cmd, enum port port)
 {
-	return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1);
+	return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1, port);
 }
 
 static inline int dsi_vc_dcs_write_1(struct intel_dsi *intel_dsi,
-				     int channel, u8 dcs_cmd, u8 param)
+			int channel, u8 dcs_cmd, u8 param, enum port port)
 {
 	u8 buf[2] = { dcs_cmd, param };
-	return dsi_vc_dcs_write(intel_dsi, channel, buf, 2);
+	return dsi_vc_dcs_write(intel_dsi, channel, buf, 2, port);
 }
 
 static inline int dsi_vc_generic_write_0(struct intel_dsi *intel_dsi,
-					 int channel)
+					 int channel, enum port port)
 {
-	return dsi_vc_generic_write(intel_dsi, channel, NULL, 0);
+	return dsi_vc_generic_write(intel_dsi, channel, NULL, 0, port);
 }
 
 static inline int dsi_vc_generic_write_1(struct intel_dsi *intel_dsi,
-					 int channel, u8 param)
+					 int channel, u8 param, enum port port)
 {
-	return dsi_vc_generic_write(intel_dsi, channel, &param, 1);
+	return dsi_vc_generic_write(intel_dsi, channel, &param, 1, port);
 }
 
 static inline int dsi_vc_generic_write_2(struct intel_dsi *intel_dsi,
-					 int channel, u8 param1, u8 param2)
+			int channel, u8 param1, u8 param2, enum port port)
 {
 	u8 buf[2] = { param1, param2 };
-	return dsi_vc_generic_write(intel_dsi, channel, buf, 2);
+	return dsi_vc_generic_write(intel_dsi, channel, buf, 2, port);
 }
 
 /* XXX: questionable read helpers */
 static inline int dsi_vc_generic_read_0(struct intel_dsi *intel_dsi,
-					int channel, u8 *buf, int buflen)
+			int channel, u8 *buf, int buflen, enum port port)
 {
-	return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen);
+	return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen,
+									port);
 }
 
 static inline int dsi_vc_generic_read_1(struct intel_dsi *intel_dsi,
 					int channel, u8 param, u8 *buf,
-					int buflen)
+					int buflen, enum port port)
 {
-	return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen);
+	return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen,
+									port);
 }
 
 static inline int dsi_vc_generic_read_2(struct intel_dsi *intel_dsi,
 					int channel, u8 param1, u8 param2,
-					u8 *buf, int buflen)
+					u8 *buf, int buflen, enum port port)
 {
 	u8 req[2] = { param1, param2 };
 
-	return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen);
+	return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen,
+									port);
 }
 
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f6bdd44..7766c42 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -94,16 +94,23 @@ static struct gpio_table gtable[] = {
 	{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
 };
 
+static inline enum port intel_dsi_seq_port_to_port(u8 port)
+{
+	return port ? PORT_C : PORT_A;
+}
+
 static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
 {
-	u8 type, byte, mode, vc, port;
+	u8 type, byte, mode, vc, seq_port;
 	u16 len;
+	enum port port;
 
 	byte = *data++;
 	mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1;
 	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
-	port = (byte >> MIPI_PORT_SHIFT) & 0x3;
+	seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
 
+	port = intel_dsi_seq_port_to_port(seq_port);
 	/* LP or HS mode */
 	intel_dsi->hs = mode;
 
@@ -115,13 +122,13 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
 
 	switch (type) {
 	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
-		dsi_vc_generic_write_0(intel_dsi, vc);
+		dsi_vc_generic_write_0(intel_dsi, vc, port);
 		break;
 	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
-		dsi_vc_generic_write_1(intel_dsi, vc, *data);
+		dsi_vc_generic_write_1(intel_dsi, vc, *data, port);
 		break;
 	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
-		dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1));
+		dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1), port);
 		break;
 	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
 	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
@@ -129,19 +136,19 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
 		DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
 		break;
 	case MIPI_DSI_GENERIC_LONG_WRITE:
-		dsi_vc_generic_write(intel_dsi, vc, data, len);
+		dsi_vc_generic_write(intel_dsi, vc, data, len, port);
 		break;
 	case MIPI_DSI_DCS_SHORT_WRITE:
-		dsi_vc_dcs_write_0(intel_dsi, vc, *data);
+		dsi_vc_dcs_write_0(intel_dsi, vc, *data, port);
 		break;
 	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
-		dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1));
+		dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1), port);
 		break;
 	case MIPI_DSI_DCS_READ:
 		DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
 		break;
 	case MIPI_DSI_DCS_LONG_WRITE:
-		dsi_vc_dcs_write(intel_dsi, vc, data, len);
+		dsi_vc_dcs_write(intel_dsi, vc, data, len, port);
 		break;
 	}
 
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 03/10] drm/i915: Add support for port enable/disable for dual link configuration
  2014-12-04  5:28 [PATCH 00/10] BYT DSI Dual Link Support Gaurav K Singh
  2014-12-04  5:28 ` [PATCH 01/10] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg Gaurav K Singh
  2014-12-04  5:28 ` [PATCH 02/10] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller Gaurav K Singh
@ 2014-12-04  5:28 ` Gaurav K Singh
  2014-12-04  9:17   ` Jani Nikula
  2014-12-04  5:28 ` [PATCH 04/10] drm/i915: Pixel Clock changes for DSI dual link Gaurav K Singh
                   ` (6 subsequent siblings)
  9 siblings, 1 reply; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-04  5:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

For Dual Link MIPI Panels, both Port A and Port C should be enabled
during the MIPI encoder enabling sequence. Similarly, during the
disabling sequence, both ports needs to be disabled.

v2: Used for_each_dsi_port macro instead of for loop

v3: Used intel_dsi->ports instead of dual_link var for dual link configuration check

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h            |    1 +
 drivers/gpu/drm/i915/intel_dsi.c           |   37 +++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_dsi.h           |    1 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    4 +++
 4 files changed, 31 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc03fac..c981f5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6664,6 +6664,7 @@ enum punit_power_well {
 #define  DPI_ENABLE					(1 << 31) /* A + C */
 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
+#define  DUAL_LINK_MODE_SHIFT				26
 #define  DUAL_LINK_MODE_MASK				(1 << 26)
 #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
 #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 693736b..dbe52e9 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -108,28 +108,41 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	u32 temp;
 
-	/* assert ip_tg_enable signal */
-	temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
-	temp = temp | intel_dsi->port_bits;
-	I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
-	POSTING_READ(MIPI_PORT_CTRL(port));
+	for_each_dsi_port(port, intel_dsi->ports) {
+		temp = I915_READ(MIPI_PORT_CTRL(port));
+
+		if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
+			temp |= (intel_dsi->dual_link - 1)
+						<< DUAL_LINK_MODE_SHIFT;
+			temp |= intel_crtc->pipe ?
+					LANE_CONFIGURATION_DUAL_LINK_B :
+					LANE_CONFIGURATION_DUAL_LINK_A;
+		} else
+			temp &= ~LANE_CONFIGURATION_MASK;
+
+		/* assert ip_tg_enable signal */
+		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
+		POSTING_READ(MIPI_PORT_CTRL(port));
+	}
 }
 
 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
 	u32 temp;
 
-	/* de-assert ip_tg_enable signal */
-	temp = I915_READ(MIPI_PORT_CTRL(port));
-	I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
-	POSTING_READ(MIPI_PORT_CTRL(port));
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* de-assert ip_tg_enable signal */
+		temp = I915_READ(MIPI_PORT_CTRL(port));
+		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
+		POSTING_READ(MIPI_PORT_CTRL(port));
+	}
 }
 
 static void intel_dsi_device_ready(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 7f5d028..f2cc2fc 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -104,6 +104,7 @@ struct intel_dsi {
 	u8 clock_stop;
 
 	u8 escape_clk_div;
+	u8 dual_link;
 	u32 port_bits;
 	u32 bw_timer;
 	u32 dphy_reg;
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 7766c42..f60146f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -287,6 +287,10 @@ static bool generic_init(struct intel_dsi_device *dsi)
 	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
 	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
+	intel_dsi->dual_link = mipi_config->dual_link;
+
+	if (intel_dsi->dual_link)
+		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
 
 	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
 		bits_per_pixel = 18;
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 04/10] drm/i915: Pixel Clock changes for DSI dual link
  2014-12-04  5:28 [PATCH 00/10] BYT DSI Dual Link Support Gaurav K Singh
                   ` (2 preceding siblings ...)
  2014-12-04  5:28 ` [PATCH 03/10] drm/i915: Add support for port enable/disable for dual link configuration Gaurav K Singh
@ 2014-12-04  5:28 ` Gaurav K Singh
  2014-12-04  9:27   ` Jani Nikula
  2014-12-04  5:28 ` [PATCH 05/10] drm/i915: Dual link needs Shutdown and Turn on packet for both ports Gaurav K Singh
                   ` (5 subsequent siblings)
  9 siblings, 1 reply; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-04  5:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for extra pixels.

v2 : Address review comments by Jani
     - Removed the bit mask used for ->dual_link
     - Used DSI instead of MIPI for #define variables

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h            |    4 ++++
 drivers/gpu/drm/i915/intel_bios.h          |    3 ++-
 drivers/gpu/drm/i915/intel_dsi.c           |    8 ++++++++
 drivers/gpu/drm/i915/intel_dsi.h           |    6 ++++++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 +++++++++++++++++++++
 5 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c981f5d..87149ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6029,6 +6029,10 @@ enum punit_power_well {
 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
 #define VLV_PWRDWNUPCTL				0xA294
 
+#define VLV_CHICKEN_3				0x7040C
+#define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
+#define  PIXEL_OVERLAP_CNT_SHIFT		30
+
 #define GEN6_PMISR				0x44020
 #define GEN6_PMIMR				0x44024 /* rps_lock */
 #define GEN6_PMIIR				0x44028
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index de01167..a6a8710 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -818,7 +818,8 @@ struct mipi_config {
 #define DUAL_LINK_PIXEL_ALT	2
 	u16 dual_link:2;
 	u16 lane_cnt:2;
-	u16 rsvd3:12;
+	u16 pixel_overlap:3;
+	u16 rsvd3:9;
 
 	u16 rsvd4;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index dbe52e9..4e18abd 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -111,6 +111,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 	enum port port;
 	u32 temp;
 
+	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+		temp = I915_READ(VLV_CHICKEN_3);
+		temp &= ~PIXEL_OVERLAP_CNT_MASK |
+					intel_dsi->pixel_overlap <<
+					PIXEL_OVERLAP_CNT_SHIFT;
+		I915_WRITE(VLV_CHICKEN_3, temp);
+	}
+
 	for_each_dsi_port(port, intel_dsi->ports) {
 		temp = I915_READ(MIPI_PORT_CTRL(port));
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index f2cc2fc..8fe2064 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -28,6 +28,11 @@
 #include <drm/drm_crtc.h>
 #include "intel_drv.h"
 
+/* Dual Link support */
+#define DSI_DUAL_LINK_NONE		0
+#define DSI_DUAL_LINK_FRONT_BACK	1
+#define DSI_DUAL_LINK_PIXEL_ALT		2
+
 struct intel_dsi_device {
 	unsigned int panel_id;
 	const char *name;
@@ -105,6 +110,7 @@ struct intel_dsi {
 
 	u8 escape_clk_div;
 	u8 dual_link;
+	u8 pixel_overlap;
 	u32 port_bits;
 	u32 bw_timer;
 	u32 dphy_reg;
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f60146f..f8c2269 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -288,6 +288,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
 	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
 	intel_dsi->dual_link = mipi_config->dual_link;
+	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
 
 	if (intel_dsi->dual_link)
 		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
@@ -310,6 +311,20 @@ static bool generic_init(struct intel_dsi_device *dsi)
 
 	pclk = mode->clock;
 
+	/* In dual link mode each port needs half of pixel clock */
+	if (intel_dsi->dual_link) {
+		pclk = pclk / 2;
+
+		/* we can enable pixel_overlap if needed by panel. In this
+		 * case we need to increase the pixelclock for extra pixels
+		 */
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+			pclk += DIV_ROUND_UP(mode->vtotal *
+						intel_dsi->pixel_overlap *
+						60, 1000);
+		}
+	}
+
 	/* Burst Mode Ratio
 	 * Target ddr frequency from VBT / non burst ddr freq
 	 * multiply by 100 to preserve remainder
@@ -504,6 +519,12 @@ static bool generic_init(struct intel_dsi_device *dsi)
 	DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
 						"disabled" : "enabled");
 	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
+	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
+	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
+		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
+	else
+		DRM_DEBUG_KMS("Dual link: NONE\n");
 	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
 	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
 	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 05/10] drm/i915: Dual link needs Shutdown and Turn on packet for both ports
  2014-12-04  5:28 [PATCH 00/10] BYT DSI Dual Link Support Gaurav K Singh
                   ` (3 preceding siblings ...)
  2014-12-04  5:28 ` [PATCH 04/10] drm/i915: Pixel Clock changes for DSI dual link Gaurav K Singh
@ 2014-12-04  5:28 ` Gaurav K Singh
  2014-12-04 10:41   ` Jani Nikula
  2014-12-04  5:28 ` [PATCH 06/10] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link Gaurav K Singh
                   ` (4 subsequent siblings)
  9 siblings, 1 reply; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-04  5:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports
A & C during MIPI encoder disabling sequence. Similarly, TURN ON packet
to be sent to both Ports during MIPI encoder enabling sequence.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_cmd.c |   26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 8e30684..562811c 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -385,8 +385,7 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	u32 mask;
 
 	/* XXX: pipe, hs */
@@ -395,18 +394,23 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
 	else
 		cmd |= DPI_LP_MODE;
 
-	/* clear bit */
-	I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* clear bit */
+		I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 
-	/* XXX: old code skips write if control unchanged */
-	if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
-		DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
+		/* XXX: old code skips write if control unchanged */
+		if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
+			DRM_ERROR("Same special packet %02x twice in a row.\n",
+									cmd);
 
-	I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
+		I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 
-	mask = SPL_PKT_SENT_INTERRUPT;
-	if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
-		DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
+		mask = SPL_PKT_SENT_INTERRUPT;
+		if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask,
+									100))
+			DRM_ERROR("Video mode command 0x%08x send failed.\n",
+									cmd);
+	}
 
 	return 0;
 }
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 06/10] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
  2014-12-04  5:28 [PATCH 00/10] BYT DSI Dual Link Support Gaurav K Singh
                   ` (4 preceding siblings ...)
  2014-12-04  5:28 ` [PATCH 05/10] drm/i915: Dual link needs Shutdown and Turn on packet for both ports Gaurav K Singh
@ 2014-12-04  5:28 ` Gaurav K Singh
  2014-12-04 11:17   ` Jani Nikula
  2014-12-04  5:28 ` [PATCH 07/10] drm/i915: cck reg used for checking DSI Pll locked Gaurav K Singh
                   ` (3 subsequent siblings)
  9 siblings, 1 reply; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-04  5:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.

v2: Address review comments by Jani
    - Added wait time for PLL to be locked.

v3: separate patch created for cck read for checking PLL to be locked

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index fa7a6ca..636d72f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
 
 	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
 
+	if (intel_dsi->dual_link)
+		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
+
 	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
 		      dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
 
-- 
1.7.9.5

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^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 07/10] drm/i915: cck reg used for checking DSI Pll locked
  2014-12-04  5:28 [PATCH 00/10] BYT DSI Dual Link Support Gaurav K Singh
                   ` (5 preceding siblings ...)
  2014-12-04  5:28 ` [PATCH 06/10] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link Gaurav K Singh
@ 2014-12-04  5:28 ` Gaurav K Singh
  2014-12-04 11:22   ` Jani Nikula
  2014-12-04  5:28 ` [PATCH 08/10] drm/i915: MIPI Timings related changes for dual link Gaurav K Singh
                   ` (2 subsequent siblings)
  9 siblings, 1 reply; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-04  5:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

Instead of pipe configuration reg, cck reg to be used for checking whether
DSI Pll is getting locked or not.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 636d72f..dd45484 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -272,12 +272,13 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
 	tmp |= DSI_PLL_VCO_EN;
 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
 
-	mutex_unlock(&dev_priv->dpio_lock);
+	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
+						DSI_PLL_LOCK, 20)) {
 
-	if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
 		DRM_ERROR("DSI PLL lock failed\n");
 		return;
 	}
+	mutex_unlock(&dev_priv->dpio_lock);
 
 	DRM_DEBUG_KMS("DSI PLL locked\n");
 }
-- 
1.7.9.5

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^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 08/10] drm/i915: MIPI Timings related changes for dual link
  2014-12-04  5:28 [PATCH 00/10] BYT DSI Dual Link Support Gaurav K Singh
                   ` (6 preceding siblings ...)
  2014-12-04  5:28 ` [PATCH 07/10] drm/i915: cck reg used for checking DSI Pll locked Gaurav K Singh
@ 2014-12-04  5:28 ` Gaurav K Singh
  2014-12-04 11:24   ` Jani Nikula
  2014-12-04  5:28 ` [PATCH 09/10] drm/i915: Update the DSI disable path to support dual link panel disabling Gaurav K Singh
  2014-12-04  5:28 ` [PATCH 10/10] drm/i915: Update the DSI enable path to support dual link panel enabling Gaurav K Singh
  9 siblings, 1 reply; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-04  5:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
Accordingly timing related mmio regs needs to be programmed for both MIPI Ports.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   37 ++++++++++++++++++++++++-------------
 1 file changed, 24 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4e18abd..22b1570 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -479,7 +479,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	unsigned int bpp = intel_crtc->config.pipe_bpp;
 	unsigned int lane_count = intel_dsi->lane_count;
 
@@ -490,6 +490,15 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 	hsync = mode->hsync_end - mode->hsync_start;
 	hbp = mode->htotal - mode->hsync_end;
 
+	if (intel_dsi->dual_link) {
+		hactive /= 2;
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+			hactive += intel_dsi->pixel_overlap;
+		hfp /= 2;
+		hsync /= 2;
+		hbp /= 2;
+	}
+
 	vfp = mode->vsync_start - mode->vdisplay;
 	vsync = mode->vsync_end - mode->vsync_start;
 	vbp = mode->vtotal - mode->vsync_end;
@@ -502,18 +511,20 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 			    intel_dsi->burst_mode_ratio);
 	hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 
-	I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
-	I915_WRITE(MIPI_HFP_COUNT(port), hfp);
-
-	/* meaningful for video mode non-burst sync pulse mode only, can be zero
-	 * for non-burst sync events and burst modes */
-	I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
-	I915_WRITE(MIPI_HBP_COUNT(port), hbp);
-
-	/* vertical values are in terms of lines */
-	I915_WRITE(MIPI_VFP_COUNT(port), vfp);
-	I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
-	I915_WRITE(MIPI_VBP_COUNT(port), vbp);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
+		I915_WRITE(MIPI_HFP_COUNT(port), hfp);
+
+		/* meaningful for video mode non-burst sync pulse mode only,
+		 * can be zero for non-burst sync events and burst modes */
+		I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
+		I915_WRITE(MIPI_HBP_COUNT(port), hbp);
+
+		/* vertical values are in terms of lines */
+		I915_WRITE(MIPI_VFP_COUNT(port), vfp);
+		I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
+		I915_WRITE(MIPI_VBP_COUNT(port), vbp);
+	}
 }
 
 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
-- 
1.7.9.5

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^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 09/10] drm/i915: Update the DSI disable path to support dual link panel disabling
  2014-12-04  5:28 [PATCH 00/10] BYT DSI Dual Link Support Gaurav K Singh
                   ` (7 preceding siblings ...)
  2014-12-04  5:28 ` [PATCH 08/10] drm/i915: MIPI Timings related changes for dual link Gaurav K Singh
@ 2014-12-04  5:28 ` Gaurav K Singh
  2014-12-04 11:37   ` Jani Nikula
  2014-12-04  5:28 ` [PATCH 10/10] drm/i915: Update the DSI enable path to support dual link panel enabling Gaurav K Singh
  9 siblings, 1 reply; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-04  5:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

We need to program both port registers during dual link disable path.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   67 ++++++++++++++++++++------------------
 1 file changed, 36 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 22b1570..5ae4015 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -281,9 +281,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	u32 temp;
 
 	DRM_DEBUG_KMS("\n");
@@ -295,23 +294,24 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 		msleep(2);
 	}
 
-	/* Panel commands can be sent when clock is in LP11 */
-	I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
-
-	temp = I915_READ(MIPI_CTRL(port));
-	temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
-	I915_WRITE(MIPI_CTRL(port), temp |
-		   intel_dsi->escape_clk_div <<
-		   ESCAPE_CLOCK_DIVIDER_SHIFT);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* Panel commands can be sent when clock is in LP11 */
+		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 
-	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
+		temp = I915_READ(MIPI_CTRL(port));
+		temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+		I915_WRITE(MIPI_CTRL(port), temp |
+			   intel_dsi->escape_clk_div <<
+			   ESCAPE_CLOCK_DIVIDER_SHIFT);
 
-	temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
-	temp &= ~VID_MODE_FORMAT_MASK;
-	I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
+		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
+		temp &= ~VID_MODE_FORMAT_MASK;
+		I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 
+		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+	}
 	/* if disable packets are sent before sending shutdown packet then in
 	 * some next enable sequence send turn on packet error is observed */
 	if (intel_dsi->dev.dev_ops->disable)
@@ -323,31 +323,36 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
 	u32 val;
 
 	DRM_DEBUG_KMS("\n");
+	for_each_dsi_port(port, intel_dsi->ports) {
 
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER);
-	usleep_range(2000, 2500);
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
+							ULPS_STATE_ENTER);
+		usleep_range(2000, 2500);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_EXIT);
-	usleep_range(2000, 2500);
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
+							ULPS_STATE_EXIT);
+		usleep_range(2000, 2500);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER);
-	usleep_range(2000, 2500);
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
+							ULPS_STATE_ENTER);
+		usleep_range(2000, 2500);
 
-	if (wait_for(((I915_READ(MIPI_PORT_CTRL(port)) & AFE_LATCHOUT)
-		      == 0x00000), 30))
-		DRM_ERROR("DSI LP not going Low\n");
+		if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
+							== 0x00000), 30))
+			DRM_ERROR("DSI LP not going Low\n");
 
-	val = I915_READ(MIPI_PORT_CTRL(port));
-	I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD);
-	usleep_range(1000, 1500);
+		val = I915_READ(MIPI_PORT_CTRL(port));
+		I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD);
+		usleep_range(1000, 1500);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
-	usleep_range(2000, 2500);
+		I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
+		usleep_range(2000, 2500);
+	}
 
 	vlv_disable_dsi_pll(encoder);
 }
-- 
1.7.9.5

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 10/10] drm/i915: Update the DSI enable path to support dual link panel enabling
  2014-12-04  5:28 [PATCH 00/10] BYT DSI Dual Link Support Gaurav K Singh
                   ` (8 preceding siblings ...)
  2014-12-04  5:28 ` [PATCH 09/10] drm/i915: Update the DSI disable path to support dual link panel disabling Gaurav K Singh
@ 2014-12-04  5:28 ` Gaurav K Singh
  2014-12-04 11:49   ` Jani Nikula
  2014-12-05  4:04   ` [PATCH 10/10] drm/i915: Update the DSI enable path to support dual link panel enabling shuang.he
  9 siblings, 2 replies; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-04  5:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

We need to program both port registers during dual link enable path.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |  251 +++++++++++++++++++++-----------------
 1 file changed, 136 insertions(+), 115 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 5ae4015..ad82d0d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -156,8 +156,8 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
 	u32 val;
 
 	DRM_DEBUG_KMS("\n");
@@ -171,18 +171,21 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 	/* bandgap reset is needed after everytime we do power gate */
 	band_gap_reset(dev_priv);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
-	usleep_range(2500, 3000);
+	for_each_dsi_port(port, intel_dsi->ports) {
 
-	val = I915_READ(MIPI_PORT_CTRL(port));
-	I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
-	usleep_range(1000, 1500);
+		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
+		usleep_range(2500, 3000);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
-	usleep_range(2500, 3000);
+		val = I915_READ(MIPI_PORT_CTRL(port));
+		I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
+		usleep_range(1000, 1500);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
-	usleep_range(2500, 3000);
+		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
+		usleep_range(2500, 3000);
+
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
+		usleep_range(2500, 3000);
+	}
 }
 
 static void intel_dsi_enable(struct intel_encoder *encoder)
@@ -541,32 +544,43 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	struct drm_display_mode *adjusted_mode =
 		&intel_crtc->config.adjusted_mode;
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	unsigned int bpp = intel_crtc->config.pipe_bpp;
 	u32 val, tmp;
+	u16 mode_hactive;
 
 	DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
 
-	/* escape clock divider, 20MHz, shared for A and C. device ready must be
-	 * off when doing this! txclkesc? */
-	tmp = I915_READ(MIPI_CTRL(PORT_A));
-	tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
-	I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
-
-	/* read request priority is per pipe */
-	tmp = I915_READ(MIPI_CTRL(port));
-	tmp &= ~READ_REQUEST_PRIORITY_MASK;
-	I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
+	mode_hactive = adjusted_mode->hdisplay;
 
-	/* XXX: why here, why like this? handling in irq handler?! */
-	I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
-	I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
-
-	I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
+	if (intel_dsi->dual_link) {
+		mode_hactive /= 2;
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+			mode_hactive += intel_dsi->pixel_overlap;
+	}
 
-	I915_WRITE(MIPI_DPI_RESOLUTION(port),
-		   adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
-		   adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* escape clock divider, 20MHz, shared for A and C.
+		 * device ready must be off when doing this! txclkesc? */
+		tmp = I915_READ(MIPI_CTRL(PORT_A));
+		tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+		I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
+
+		/* read request priority is per pipe */
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp &= ~READ_REQUEST_PRIORITY_MASK;
+		I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
+
+		/* XXX: why here, why like this? handling in irq handler?! */
+		I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
+		I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
+
+		I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
+
+		I915_WRITE(MIPI_DPI_RESOLUTION(port),
+			adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
+			mode_hactive << HORIZONTAL_ADDRESS_SHIFT);
+	}
 
 	set_dsi_timings(encoder, adjusted_mode);
 
@@ -580,95 +594,102 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 		/* XXX: cross-check bpp vs. pixel format? */
 		val |= intel_dsi->pixel_format;
 	}
-	I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
 
-	/* timeouts for recovery. one frame IIUC. if counter expires, EOT and
-	 * stop state. */
-
-	/*
-	 * In burst mode, value greater than one DPI line Time in byte clock
-	 * (txbyteclkhs) To timeout this timer 1+ of the above said value is
-	 * recommended.
-	 *
-	 * In non-burst mode, Value greater than one DPI frame time in byte
-	 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
-	 * is recommended.
-	 *
-	 * In DBI only mode, value greater than one DBI frame time in byte
-	 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
-	 * is recommended.
-	 */
-
-	if (is_vid_mode(intel_dsi) &&
-	    intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
-		I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
-			   txbyteclkhs(adjusted_mode->htotal, bpp,
-				       intel_dsi->lane_count,
-				       intel_dsi->burst_mode_ratio) + 1);
-	} else {
-		I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
-			   txbyteclkhs(adjusted_mode->vtotal *
-				       adjusted_mode->htotal,
-				       bpp, intel_dsi->lane_count,
-				       intel_dsi->burst_mode_ratio) + 1);
-	}
-	I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
-	I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), intel_dsi->turn_arnd_val);
-	I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), intel_dsi->rst_timer_val);
-
-	/* dphy stuff */
-
-	/* in terms of low power clock */
-	I915_WRITE(MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100));
-
-	val = 0;
+	tmp = 0;
 	if (intel_dsi->eotp_pkt == 0)
-		val |= EOT_DISABLE;
-
+		tmp |= EOT_DISABLE;
 	if (intel_dsi->clock_stop)
-		val |= CLOCKSTOP;
-
-	/* recovery disables */
-	I915_WRITE(MIPI_EOT_DISABLE(port), val);
-
-	/* in terms of low power clock */
-	I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
-
-	/* in terms of txbyteclkhs. actual high to low switch +
-	 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
-	 *
-	 * XXX: write MIPI_STOP_STATE_STALL?
-	 */
-	I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
-		   intel_dsi->hs_to_lp_count);
+		tmp |= CLOCKSTOP;
 
-	/* XXX: low power clock equivalence in terms of byte clock. the number
-	 * of byte clocks occupied in one low power clock. based on txbyteclkhs
-	 * and txclkesc. txclkesc time / txbyteclk time * (105 +
-	 * MIPI_STOP_STATE_STALL) / 105.???
-	 */
-	I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
-
-	/* the bw essential for transmitting 16 long packets containing 252
-	 * bytes meant for dcs write memory command is programmed in this
-	 * register in terms of byte clocks. based on dsi transfer rate and the
-	 * number of lanes configured the time taken to transmit 16 long packets
-	 * in a dsi stream varies. */
-	I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
-
-	I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
-		   intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
-		   intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
-
-	if (is_vid_mode(intel_dsi))
-		/* Some panels might have resolution which is not a multiple of
-		 * 64 like 1366 x 768. Enable RANDOM resolution support for such
-		 * panels by default */
-		I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
-			   intel_dsi->video_frmt_cfg_bits |
-			   intel_dsi->video_mode_format |
-			   IP_TG_CONFIG |
-			   RANDOM_DPI_DISPLAY_RESOLUTION);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
+
+		/* timeouts for recovery. one frame IIUC. if counter expires,
+		 * EOT and stop state. */
+
+		/*
+		 * In burst mode, value greater than one DPI line Time in byte
+		 * clock (txbyteclkhs) To timeout this timer 1+ of the above
+		 * said value is recommended.
+		 *
+		 * In non-burst mode, Value greater than one DPI frame time in
+		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
+		 * said value is recommended.
+		 *
+		 * In DBI only mode, value greater than one DBI frame time in
+		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
+		 * said value is recommended.
+		 */
+
+		if (is_vid_mode(intel_dsi) &&
+			intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
+			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
+				txbyteclkhs(adjusted_mode->htotal, bpp,
+					intel_dsi->lane_count,
+					intel_dsi->burst_mode_ratio) + 1);
+		} else {
+			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
+				txbyteclkhs(adjusted_mode->vtotal *
+					adjusted_mode->htotal,
+					bpp, intel_dsi->lane_count,
+					intel_dsi->burst_mode_ratio) + 1);
+		}
+		I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
+		I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
+						intel_dsi->turn_arnd_val);
+		I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
+						intel_dsi->rst_timer_val);
+
+		/* dphy stuff */
+
+		/* in terms of low power clock */
+		I915_WRITE(MIPI_INIT_COUNT(port),
+				txclkesc(intel_dsi->escape_clk_div, 100));
+
+
+		/* recovery disables */
+		I915_WRITE(MIPI_EOT_DISABLE(port), val);
+
+		/* in terms of low power clock */
+		I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
+
+		/* in terms of txbyteclkhs. actual high to low switch +
+		 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
+		 *
+		 * XXX: write MIPI_STOP_STATE_STALL?
+		 */
+		I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
+						intel_dsi->hs_to_lp_count);
+
+		/* XXX: low power clock equivalence in terms of byte clock.
+		 * the number of byte clocks occupied in one low power clock.
+		 * based on txbyteclkhs and txclkesc.
+		 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
+		 * ) / 105.???
+		 */
+		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
+
+		/* the bw essential for transmitting 16 long packets containing
+		 * 252 bytes meant for dcs write memory command is programmed in
+		 * this register in terms of byte clocks. based on dsi transfer
+		 * rate and the number of lanes configured the time taken to
+		 * transmit 16 long packets in a dsi stream varies. */
+		I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
+
+		I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
+		intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
+		intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
+
+		if (is_vid_mode(intel_dsi))
+			/* Some panels might have resolution which is not a
+			 * multiple of 64 like 1366 x 768. Enable RANDOM
+			 * resolution support for such panels by default */
+			I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
+				intel_dsi->video_frmt_cfg_bits |
+				intel_dsi->video_mode_format |
+				IP_TG_CONFIG |
+				RANDOM_DPI_DISPLAY_RESOLUTION);
+	}
 }
 
 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* Re: [PATCH 01/10] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg
  2014-12-04  5:28 ` [PATCH 01/10] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg Gaurav K Singh
@ 2014-12-04  9:13   ` Jani Nikula
  0 siblings, 0 replies; 41+ messages in thread
From: Jani Nikula @ 2014-12-04  9:13 UTC (permalink / raw)
  To: Gaurav K Singh, intel-gfx; +Cc: Shobhit Kumar

On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> This patch is in preparation for the DSI dual link
> port enable and disable related changes.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_dsi.c |   43 ++++++++++++++++++++++++++++----------
>  1 file changed, 32 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 259cb4a..693736b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -102,6 +102,36 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>  	return true;
>  }
>  
> +static void intel_dsi_port_enable(struct intel_encoder *encoder)
> +{
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	u32 temp;
> +
> +	/* assert ip_tg_enable signal */
> +	temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
> +	temp = temp | intel_dsi->port_bits;
> +	I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
> +	POSTING_READ(MIPI_PORT_CTRL(port));
> +}
> +
> +static void intel_dsi_port_disable(struct intel_encoder *encoder)
> +{
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> +	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	u32 temp;
> +
> +	/* de-assert ip_tg_enable signal */
> +	temp = I915_READ(MIPI_PORT_CTRL(port));
> +	I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> +	POSTING_READ(MIPI_PORT_CTRL(port));
> +}
> +
>  static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> @@ -141,7 +171,6 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> -	u32 temp;
>  
>  	DRM_DEBUG_KMS("\n");
>  
> @@ -157,11 +186,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
>  
>  		wait_for_dsi_fifo_empty(intel_dsi);
>  
> -		/* assert ip_tg_enable signal */
> -		temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
> -		temp = temp | intel_dsi->port_bits;
> -		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
> -		POSTING_READ(MIPI_PORT_CTRL(port));
> +		intel_dsi_port_enable(encoder);
>  	}
>  }
>  
> @@ -245,11 +270,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>  	if (is_vid_mode(intel_dsi)) {
>  		wait_for_dsi_fifo_empty(intel_dsi);
>  
> -		/* de-assert ip_tg_enable signal */
> -		temp = I915_READ(MIPI_PORT_CTRL(port));
> -		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> -		POSTING_READ(MIPI_PORT_CTRL(port));
> -
> +		intel_dsi_port_disable(encoder);
>  		msleep(2);
>  	}
>  
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 02/10] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller
  2014-12-04  5:28 ` [PATCH 02/10] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller Gaurav K Singh
@ 2014-12-04  9:14   ` Jani Nikula
  2014-12-04 11:22     ` Daniel Vetter
  0 siblings, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2014-12-04  9:14 UTC (permalink / raw)
  To: Gaurav K Singh, intel-gfx; +Cc: Shobhit Kumar

On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> This patch is in preparation of DSI dual link panels. For dual link
> panels, few packets needs to be sent to Port A or Port C or both. Based
> on the portno from MIPI Sequence Block#53, these sequences needs to be
> sent accordingly.
>
> v2: Addressed review comments by Jani
>     - port variables named properly
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dsi_cmd.c       |   75 ++++++++++++----------------
>  drivers/gpu/drm/i915/intel_dsi_cmd.h       |   46 +++++++++--------
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   25 ++++++----
>  3 files changed, 74 insertions(+), 72 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
> index 004fa91..8e30684 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
> @@ -48,13 +48,11 @@
>   * For memory writes, these should probably be used for performance.
>   */
>  
> -static void print_stat(struct intel_dsi *intel_dsi)
> +static void print_stat(struct intel_dsi *intel_dsi, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	u32 val;
>  
>  	val = I915_READ(MIPI_INTR_STAT(port));
> @@ -104,13 +102,12 @@ enum dsi_type {
>  };
>  
>  /* enable or disable command mode hs transmissions */
> -void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
> +void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
> +						enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	u32 temp;
>  	u32 mask = DBI_FIFO_EMPTY;
>  
> @@ -125,13 +122,11 @@ void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
>  }
>  
>  static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
> -			     u8 data_type, u16 data)
> +			     u8 data_type, u16 data, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	u32 ctrl_reg;
>  	u32 ctrl;
>  	u32 mask;
> @@ -149,7 +144,7 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
>  
>  	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) {
>  		DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
> -		print_stat(intel_dsi);
> +		print_stat(intel_dsi, port);
>  	}
>  
>  	/*
> @@ -167,13 +162,11 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
>  }
>  
>  static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
> -			    u8 data_type, const u8 *data, int len)
> +		u8 data_type, const u8 *data, int len, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	u32 data_reg;
>  	int i, j, n;
>  	u32 mask;
> @@ -204,12 +197,12 @@ static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
>  		 * dwords, then wait for not set, then continue. */
>  	}
>  
> -	return dsi_vc_send_short(intel_dsi, channel, data_type, len);
> +	return dsi_vc_send_short(intel_dsi, channel, data_type, len, port);
>  }
>  
>  static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
>  			       int channel, const u8 *data, int len,
> -			       enum dsi_type type)
> +			       enum dsi_type type, enum port port)
>  {
>  	int ret;
>  
> @@ -217,50 +210,54 @@ static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
>  		BUG_ON(type == DSI_GENERIC);
>  		ret = dsi_vc_send_short(intel_dsi, channel,
>  					MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
> -					0);
> +					0, port);
>  	} else if (len == 1) {
>  		ret = dsi_vc_send_short(intel_dsi, channel,
>  					type == DSI_GENERIC ?
>  					MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
> -					MIPI_DSI_DCS_SHORT_WRITE, data[0]);
> +					MIPI_DSI_DCS_SHORT_WRITE, data[0],
> +					port);
>  	} else if (len == 2) {
>  		ret = dsi_vc_send_short(intel_dsi, channel,
>  					type == DSI_GENERIC ?
>  					MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
>  					MIPI_DSI_DCS_SHORT_WRITE_PARAM,
> -					(data[1] << 8) | data[0]);
> +					(data[1] << 8) | data[0], port);
>  	} else {
>  		ret = dsi_vc_send_long(intel_dsi, channel,
> -				       type == DSI_GENERIC ?
> -				       MIPI_DSI_GENERIC_LONG_WRITE :
> -				       MIPI_DSI_DCS_LONG_WRITE, data, len);
> +					type == DSI_GENERIC ?
> +					MIPI_DSI_GENERIC_LONG_WRITE :
> +					MIPI_DSI_DCS_LONG_WRITE, data, len,
> +					port);
>  	}
>  
>  	return ret;
>  }
>  
>  int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
> -		     const u8 *data, int len)
> +		     const u8 *data, int len, enum port port)
>  {
> -	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS);
> +	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS,
> +									port);
>  }
>  
>  int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
> -			 const u8 *data, int len)
> +			 const u8 *data, int len, enum port port)
>  {
> -	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC);
> +	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC,
> +									port);
>  }
>  
>  static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
> -					int channel, u8 dcs_cmd)
> +				int channel, u8 dcs_cmd, enum port port)
>  {
>  	return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
> -				 dcs_cmd);
> +				 dcs_cmd, port);
>  }
>  
>  static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
>  					    int channel, u8 *reqdata,
> -					    int reqlen)
> +					    int reqlen, enum port port)
>  {
>  	u16 data;
>  	u8 data_type;
> @@ -282,17 +279,15 @@ static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
>  		BUG();
>  	}
>  
> -	return dsi_vc_send_short(intel_dsi, channel, data_type, data);
> +	return dsi_vc_send_short(intel_dsi, channel, data_type, data, port);
>  }
>  
>  static int dsi_read_data_return(struct intel_dsi *intel_dsi,
> -				u8 *buf, int buflen)
> +				u8 *buf, int buflen, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	int i, len = 0;
>  	u32 data_reg, val;
>  
> @@ -312,13 +307,11 @@ static int dsi_read_data_return(struct intel_dsi *intel_dsi,
>  }
>  
>  int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
> -		    u8 *buf, int buflen)
> +		    u8 *buf, int buflen, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	u32 mask;
>  	int ret;
>  
> @@ -329,7 +322,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
>  
>  	I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
>  
> -	ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd);
> +	ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd, port);
>  	if (ret)
>  		return ret;
>  
> @@ -337,7 +330,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
>  	if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
>  		DRM_ERROR("Timeout waiting for read data.\n");
>  
> -	ret = dsi_read_data_return(intel_dsi, buf, buflen);
> +	ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
>  	if (ret < 0)
>  		return ret;
>  
> @@ -348,13 +341,11 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
>  }
>  
>  int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
> -			u8 *reqdata, int reqlen, u8 *buf, int buflen)
> +		u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	u32 mask;
>  	int ret;
>  
> @@ -366,7 +357,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
>  	I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
>  
>  	ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
> -					       reqlen);
> +					       reqlen, port);
>  	if (ret)
>  		return ret;
>  
> @@ -374,7 +365,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
>  	if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
>  		DRM_ERROR("Timeout waiting for read data.\n");
>  
> -	ret = dsi_read_data_return(intel_dsi, buf, buflen);
> +	ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
>  	if (ret < 0)
>  		return ret;
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h b/drivers/gpu/drm/i915/intel_dsi_cmd.h
> index 46aa1ac..326a5ac 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_cmd.h
> +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h
> @@ -36,77 +36,81 @@
>  #define DPI_LP_MODE_EN	false
>  #define DPI_HS_MODE_EN	true
>  
> -void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable);
> +void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
> +						enum port port);
>  
>  int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
> -		     const u8 *data, int len);
> +		     const u8 *data, int len, enum port port);
>  
>  int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
> -			 const u8 *data, int len);
> +			 const u8 *data, int len, enum port port);
>  
>  int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
> -		    u8 *buf, int buflen);
> +		    u8 *buf, int buflen, enum port port);
>  
>  int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
> -			u8 *reqdata, int reqlen, u8 *buf, int buflen);
> +		u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port);
>  
>  int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs);
>  void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi);
>  
>  /* XXX: questionable write helpers */
>  static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
> -				     int channel, u8 dcs_cmd)
> +				     int channel, u8 dcs_cmd, enum port port)
>  {
> -	return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1);
> +	return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1, port);
>  }
>  
>  static inline int dsi_vc_dcs_write_1(struct intel_dsi *intel_dsi,
> -				     int channel, u8 dcs_cmd, u8 param)
> +			int channel, u8 dcs_cmd, u8 param, enum port port)
>  {
>  	u8 buf[2] = { dcs_cmd, param };
> -	return dsi_vc_dcs_write(intel_dsi, channel, buf, 2);
> +	return dsi_vc_dcs_write(intel_dsi, channel, buf, 2, port);
>  }
>  
>  static inline int dsi_vc_generic_write_0(struct intel_dsi *intel_dsi,
> -					 int channel)
> +					 int channel, enum port port)
>  {
> -	return dsi_vc_generic_write(intel_dsi, channel, NULL, 0);
> +	return dsi_vc_generic_write(intel_dsi, channel, NULL, 0, port);
>  }
>  
>  static inline int dsi_vc_generic_write_1(struct intel_dsi *intel_dsi,
> -					 int channel, u8 param)
> +					 int channel, u8 param, enum port port)
>  {
> -	return dsi_vc_generic_write(intel_dsi, channel, &param, 1);
> +	return dsi_vc_generic_write(intel_dsi, channel, &param, 1, port);
>  }
>  
>  static inline int dsi_vc_generic_write_2(struct intel_dsi *intel_dsi,
> -					 int channel, u8 param1, u8 param2)
> +			int channel, u8 param1, u8 param2, enum port port)
>  {
>  	u8 buf[2] = { param1, param2 };
> -	return dsi_vc_generic_write(intel_dsi, channel, buf, 2);
> +	return dsi_vc_generic_write(intel_dsi, channel, buf, 2, port);
>  }
>  
>  /* XXX: questionable read helpers */
>  static inline int dsi_vc_generic_read_0(struct intel_dsi *intel_dsi,
> -					int channel, u8 *buf, int buflen)
> +			int channel, u8 *buf, int buflen, enum port port)
>  {
> -	return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen);
> +	return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen,
> +									port);
>  }
>  
>  static inline int dsi_vc_generic_read_1(struct intel_dsi *intel_dsi,
>  					int channel, u8 param, u8 *buf,
> -					int buflen)
> +					int buflen, enum port port)
>  {
> -	return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen);
> +	return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen,
> +									port);
>  }
>  
>  static inline int dsi_vc_generic_read_2(struct intel_dsi *intel_dsi,
>  					int channel, u8 param1, u8 param2,
> -					u8 *buf, int buflen)
> +					u8 *buf, int buflen, enum port port)
>  {
>  	u8 req[2] = { param1, param2 };
>  
> -	return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen);
> +	return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen,
> +									port);
>  }
>  
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index f6bdd44..7766c42 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -94,16 +94,23 @@ static struct gpio_table gtable[] = {
>  	{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
>  };
>  
> +static inline enum port intel_dsi_seq_port_to_port(u8 port)
> +{
> +	return port ? PORT_C : PORT_A;
> +}
> +
>  static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
>  {
> -	u8 type, byte, mode, vc, port;
> +	u8 type, byte, mode, vc, seq_port;
>  	u16 len;
> +	enum port port;
>  
>  	byte = *data++;
>  	mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1;
>  	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
> -	port = (byte >> MIPI_PORT_SHIFT) & 0x3;
> +	seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
>  
> +	port = intel_dsi_seq_port_to_port(seq_port);
>  	/* LP or HS mode */
>  	intel_dsi->hs = mode;
>  
> @@ -115,13 +122,13 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
>  
>  	switch (type) {
>  	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
> -		dsi_vc_generic_write_0(intel_dsi, vc);
> +		dsi_vc_generic_write_0(intel_dsi, vc, port);
>  		break;
>  	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
> -		dsi_vc_generic_write_1(intel_dsi, vc, *data);
> +		dsi_vc_generic_write_1(intel_dsi, vc, *data, port);
>  		break;
>  	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
> -		dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1));
> +		dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1), port);
>  		break;
>  	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
>  	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
> @@ -129,19 +136,19 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
>  		DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
>  		break;
>  	case MIPI_DSI_GENERIC_LONG_WRITE:
> -		dsi_vc_generic_write(intel_dsi, vc, data, len);
> +		dsi_vc_generic_write(intel_dsi, vc, data, len, port);
>  		break;
>  	case MIPI_DSI_DCS_SHORT_WRITE:
> -		dsi_vc_dcs_write_0(intel_dsi, vc, *data);
> +		dsi_vc_dcs_write_0(intel_dsi, vc, *data, port);
>  		break;
>  	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> -		dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1));
> +		dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1), port);
>  		break;
>  	case MIPI_DSI_DCS_READ:
>  		DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
>  		break;
>  	case MIPI_DSI_DCS_LONG_WRITE:
> -		dsi_vc_dcs_write(intel_dsi, vc, data, len);
> +		dsi_vc_dcs_write(intel_dsi, vc, data, len, port);
>  		break;
>  	}
>  
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 03/10] drm/i915: Add support for port enable/disable for dual link configuration
  2014-12-04  5:28 ` [PATCH 03/10] drm/i915: Add support for port enable/disable for dual link configuration Gaurav K Singh
@ 2014-12-04  9:17   ` Jani Nikula
  2014-12-05  8:39     ` [PATCH v4 " Gaurav K Singh
  0 siblings, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2014-12-04  9:17 UTC (permalink / raw)
  To: Gaurav K Singh, intel-gfx; +Cc: Shobhit Kumar

On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> For Dual Link MIPI Panels, both Port A and Port C should be enabled
> during the MIPI encoder enabling sequence. Similarly, during the
> disabling sequence, both ports needs to be disabled.
>
> v2: Used for_each_dsi_port macro instead of for loop
>
> v3: Used intel_dsi->ports instead of dual_link var for dual link configuration check
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h            |    1 +
>  drivers/gpu/drm/i915/intel_dsi.c           |   37 +++++++++++++++++++---------
>  drivers/gpu/drm/i915/intel_dsi.h           |    1 +
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    4 +++
>  4 files changed, 31 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dc03fac..c981f5d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6664,6 +6664,7 @@ enum punit_power_well {
>  #define  DPI_ENABLE					(1 << 31) /* A + C */
>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
> +#define  DUAL_LINK_MODE_SHIFT				26
>  #define  DUAL_LINK_MODE_MASK				(1 << 26)
>  #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
>  #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 693736b..dbe52e9 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -108,28 +108,41 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	enum port port;
>  	u32 temp;
>  
> -	/* assert ip_tg_enable signal */
> -	temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
> -	temp = temp | intel_dsi->port_bits;
> -	I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
> -	POSTING_READ(MIPI_PORT_CTRL(port));
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		temp = I915_READ(MIPI_PORT_CTRL(port));
> +
> +		if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
> +			temp |= (intel_dsi->dual_link - 1)
> +						<< DUAL_LINK_MODE_SHIFT;

You should do temp &= ~DUAL_LINK_MODE_MASK first.

> +			temp |= intel_crtc->pipe ?
> +					LANE_CONFIGURATION_DUAL_LINK_B :
> +					LANE_CONFIGURATION_DUAL_LINK_A;
> +		} else
> +			temp &= ~LANE_CONFIGURATION_MASK;

I think you need to do this unconditionally after reading the register.

With those fixed,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +
> +		/* assert ip_tg_enable signal */
> +		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
> +		POSTING_READ(MIPI_PORT_CTRL(port));
> +	}
>  }
>  
>  static void intel_dsi_port_disable(struct intel_encoder *encoder)
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
>  	u32 temp;
>  
> -	/* de-assert ip_tg_enable signal */
> -	temp = I915_READ(MIPI_PORT_CTRL(port));
> -	I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> -	POSTING_READ(MIPI_PORT_CTRL(port));
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		/* de-assert ip_tg_enable signal */
> +		temp = I915_READ(MIPI_PORT_CTRL(port));
> +		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> +		POSTING_READ(MIPI_PORT_CTRL(port));
> +	}
>  }
>  
>  static void intel_dsi_device_ready(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 7f5d028..f2cc2fc 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -104,6 +104,7 @@ struct intel_dsi {
>  	u8 clock_stop;
>  
>  	u8 escape_clk_div;
> +	u8 dual_link;
>  	u32 port_bits;
>  	u32 bw_timer;
>  	u32 dphy_reg;
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 7766c42..f60146f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -287,6 +287,10 @@ static bool generic_init(struct intel_dsi_device *dsi)
>  	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
>  	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>  	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
> +	intel_dsi->dual_link = mipi_config->dual_link;
> +
> +	if (intel_dsi->dual_link)
> +		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
>  
>  	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
>  		bits_per_pixel = 18;
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 04/10] drm/i915: Pixel Clock changes for DSI dual link
  2014-12-04  5:28 ` [PATCH 04/10] drm/i915: Pixel Clock changes for DSI dual link Gaurav K Singh
@ 2014-12-04  9:27   ` Jani Nikula
  2014-12-05  8:43     ` [PATCH v3 " Gaurav K Singh
  2014-12-05 16:33     ` [PATCH " Singh, Gaurav K
  0 siblings, 2 replies; 41+ messages in thread
From: Jani Nikula @ 2014-12-04  9:27 UTC (permalink / raw)
  To: Gaurav K Singh, intel-gfx; +Cc: Shobhit Kumar

On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
> can be enabled if needed by panel, then in that case, pixel clock will be
> increased for extra pixels.
>
> v2 : Address review comments by Jani
>      - Removed the bit mask used for ->dual_link
>      - Used DSI instead of MIPI for #define variables
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h            |    4 ++++
>  drivers/gpu/drm/i915/intel_bios.h          |    3 ++-
>  drivers/gpu/drm/i915/intel_dsi.c           |    8 ++++++++
>  drivers/gpu/drm/i915/intel_dsi.h           |    6 ++++++
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 +++++++++++++++++++++
>  5 files changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c981f5d..87149ba 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6029,6 +6029,10 @@ enum punit_power_well {
>  #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
>  #define VLV_PWRDWNUPCTL				0xA294
>  
> +#define VLV_CHICKEN_3				0x7040C
> +#define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
> +#define  PIXEL_OVERLAP_CNT_SHIFT		30

I didn't find this register, but does it not need + VLV_DISPLAY_BASE?

Given that I can't find the register my review is pretty shallow, but I
don't spot anything obviously wrong either. With these caveats,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +
>  #define GEN6_PMISR				0x44020
>  #define GEN6_PMIMR				0x44024 /* rps_lock */
>  #define GEN6_PMIIR				0x44028
> diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
> index de01167..a6a8710 100644
> --- a/drivers/gpu/drm/i915/intel_bios.h
> +++ b/drivers/gpu/drm/i915/intel_bios.h
> @@ -818,7 +818,8 @@ struct mipi_config {
>  #define DUAL_LINK_PIXEL_ALT	2
>  	u16 dual_link:2;
>  	u16 lane_cnt:2;
> -	u16 rsvd3:12;
> +	u16 pixel_overlap:3;
> +	u16 rsvd3:9;
>  
>  	u16 rsvd4;
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index dbe52e9..4e18abd 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -111,6 +111,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  	enum port port;
>  	u32 temp;
>  
> +	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> +		temp = I915_READ(VLV_CHICKEN_3);
> +		temp &= ~PIXEL_OVERLAP_CNT_MASK |
> +					intel_dsi->pixel_overlap <<
> +					PIXEL_OVERLAP_CNT_SHIFT;
> +		I915_WRITE(VLV_CHICKEN_3, temp);
> +	}
> +
>  	for_each_dsi_port(port, intel_dsi->ports) {
>  		temp = I915_READ(MIPI_PORT_CTRL(port));
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index f2cc2fc..8fe2064 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -28,6 +28,11 @@
>  #include <drm/drm_crtc.h>
>  #include "intel_drv.h"
>  
> +/* Dual Link support */
> +#define DSI_DUAL_LINK_NONE		0
> +#define DSI_DUAL_LINK_FRONT_BACK	1
> +#define DSI_DUAL_LINK_PIXEL_ALT		2
> +
>  struct intel_dsi_device {
>  	unsigned int panel_id;
>  	const char *name;
> @@ -105,6 +110,7 @@ struct intel_dsi {
>  
>  	u8 escape_clk_div;
>  	u8 dual_link;
> +	u8 pixel_overlap;
>  	u32 port_bits;
>  	u32 bw_timer;
>  	u32 dphy_reg;
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index f60146f..f8c2269 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -288,6 +288,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
>  	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>  	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
>  	intel_dsi->dual_link = mipi_config->dual_link;
> +	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>  
>  	if (intel_dsi->dual_link)
>  		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
> @@ -310,6 +311,20 @@ static bool generic_init(struct intel_dsi_device *dsi)
>  
>  	pclk = mode->clock;
>  
> +	/* In dual link mode each port needs half of pixel clock */
> +	if (intel_dsi->dual_link) {
> +		pclk = pclk / 2;
> +
> +		/* we can enable pixel_overlap if needed by panel. In this
> +		 * case we need to increase the pixelclock for extra pixels
> +		 */
> +		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> +			pclk += DIV_ROUND_UP(mode->vtotal *
> +						intel_dsi->pixel_overlap *
> +						60, 1000);
> +		}
> +	}
> +
>  	/* Burst Mode Ratio
>  	 * Target ddr frequency from VBT / non burst ddr freq
>  	 * multiply by 100 to preserve remainder
> @@ -504,6 +519,12 @@ static bool generic_init(struct intel_dsi_device *dsi)
>  	DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
>  						"disabled" : "enabled");
>  	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
> +	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
> +		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
> +	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
> +		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
> +	else
> +		DRM_DEBUG_KMS("Dual link: NONE\n");
>  	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
>  	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
>  	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 05/10] drm/i915: Dual link needs Shutdown and Turn on packet for both ports
  2014-12-04  5:28 ` [PATCH 05/10] drm/i915: Dual link needs Shutdown and Turn on packet for both ports Gaurav K Singh
@ 2014-12-04 10:41   ` Jani Nikula
  2014-12-05 19:10     ` [PATCH 5/5] " Gaurav K Singh
  0 siblings, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2014-12-04 10:41 UTC (permalink / raw)
  To: Gaurav K Singh, intel-gfx; +Cc: Shobhit Kumar

On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports
> A & C during MIPI encoder disabling sequence. Similarly, TURN ON packet
> to be sent to both Ports during MIPI encoder enabling sequence.
>
> v2: Address review comments by Jani
>     - Used a for loop instead of do-while loop.
>
> v3: Used for_each_dsi_port macro instead of for loop
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_dsi_cmd.c |   26 +++++++++++++++-----------
>  1 file changed, 15 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
> index 8e30684..562811c 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
> @@ -385,8 +385,7 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	enum port port;
>  	u32 mask;
>  
>  	/* XXX: pipe, hs */
> @@ -395,18 +394,23 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
>  	else
>  		cmd |= DPI_LP_MODE;
>  
> -	/* clear bit */
> -	I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		/* clear bit */
> +		I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
>  
> -	/* XXX: old code skips write if control unchanged */
> -	if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
> -		DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
> +		/* XXX: old code skips write if control unchanged */
> +		if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
> +			DRM_ERROR("Same special packet %02x twice in a row.\n",
> +									cmd);
>  
> -	I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
> +		I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
>  
> -	mask = SPL_PKT_SENT_INTERRUPT;
> -	if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
> -		DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
> +		mask = SPL_PKT_SENT_INTERRUPT;
> +		if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask,
> +									100))
> +			DRM_ERROR("Video mode command 0x%08x send failed.\n",
> +									cmd);
> +	}
>  
>  	return 0;
>  }
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 06/10] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
  2014-12-04  5:28 ` [PATCH 06/10] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link Gaurav K Singh
@ 2014-12-04 11:17   ` Jani Nikula
  0 siblings, 0 replies; 41+ messages in thread
From: Jani Nikula @ 2014-12-04 11:17 UTC (permalink / raw)
  To: Gaurav K Singh, intel-gfx; +Cc: Shobhit Kumar

On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.
>
> v2: Address review comments by Jani
>     - Added wait time for PLL to be locked.
>
> v3: separate patch created for cck read for checking PLL to be locked
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c |    3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index fa7a6ca..636d72f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>  
>  	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
>  
> +	if (intel_dsi->dual_link)
> +		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
> +
>  	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
>  		      dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
>  
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 07/10] drm/i915: cck reg used for checking DSI Pll locked
  2014-12-04  5:28 ` [PATCH 07/10] drm/i915: cck reg used for checking DSI Pll locked Gaurav K Singh
@ 2014-12-04 11:22   ` Jani Nikula
  2014-12-05  8:46     ` [PATCH v2 " Gaurav K Singh
  0 siblings, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2014-12-04 11:22 UTC (permalink / raw)
  To: Gaurav K Singh, intel-gfx; +Cc: Shobhit Kumar

On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> Instead of pipe configuration reg, cck reg to be used for checking whether
> DSI Pll is getting locked or not.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c |    5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 636d72f..dd45484 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -272,12 +272,13 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
>  	tmp |= DSI_PLL_VCO_EN;
>  	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
>  
> -	mutex_unlock(&dev_priv->dpio_lock);
> +	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
> +						DSI_PLL_LOCK, 20)) {
>  
> -	if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
>  		DRM_ERROR("DSI PLL lock failed\n");
>  		return;
>  	}
> +	mutex_unlock(&dev_priv->dpio_lock);

If DSI PLL lock fails, you leave dpio_lock locked.

BR,
Jani.

>  
>  	DRM_DEBUG_KMS("DSI PLL locked\n");
>  }
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 02/10] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller
  2014-12-04  9:14   ` Jani Nikula
@ 2014-12-04 11:22     ` Daniel Vetter
  2014-12-05 12:50       ` Singh, Gaurav K
  0 siblings, 1 reply; 41+ messages in thread
From: Daniel Vetter @ 2014-12-04 11:22 UTC (permalink / raw)
  To: Jani Nikula; +Cc: Shobhit Kumar, intel-gfx

On Thu, Dec 04, 2014 at 11:14:01AM +0200, Jani Nikula wrote:
> On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> > This patch is in preparation of DSI dual link panels. For dual link
> > panels, few packets needs to be sent to Port A or Port C or both. Based
> > on the portno from MIPI Sequence Block#53, these sequences needs to be
> > sent accordingly.
> >
> > v2: Addressed review comments by Jani
> >     - port variables named properly
> >
> > Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Merged the first two patches, thanks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 08/10] drm/i915: MIPI Timings related changes for dual link
  2014-12-04  5:28 ` [PATCH 08/10] drm/i915: MIPI Timings related changes for dual link Gaurav K Singh
@ 2014-12-04 11:24   ` Jani Nikula
  0 siblings, 0 replies; 41+ messages in thread
From: Jani Nikula @ 2014-12-04 11:24 UTC (permalink / raw)
  To: Gaurav K Singh, intel-gfx; +Cc: Shobhit Kumar

On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
> Accordingly timing related mmio regs needs to be programmed for both MIPI Ports.
>
> v2: Address review comments by Jani
>     - Used a for loop instead of do-while loop
>
> v3: Used for_each_dsi_port macro instead of for loop
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_dsi.c |   37 ++++++++++++++++++++++++-------------
>  1 file changed, 24 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 4e18abd..22b1570 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -479,7 +479,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	enum port port;
>  	unsigned int bpp = intel_crtc->config.pipe_bpp;
>  	unsigned int lane_count = intel_dsi->lane_count;
>  
> @@ -490,6 +490,15 @@ static void set_dsi_timings(struct drm_encoder *encoder,
>  	hsync = mode->hsync_end - mode->hsync_start;
>  	hbp = mode->htotal - mode->hsync_end;
>  
> +	if (intel_dsi->dual_link) {
> +		hactive /= 2;
> +		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
> +			hactive += intel_dsi->pixel_overlap;
> +		hfp /= 2;
> +		hsync /= 2;
> +		hbp /= 2;
> +	}
> +
>  	vfp = mode->vsync_start - mode->vdisplay;
>  	vsync = mode->vsync_end - mode->vsync_start;
>  	vbp = mode->vtotal - mode->vsync_end;
> @@ -502,18 +511,20 @@ static void set_dsi_timings(struct drm_encoder *encoder,
>  			    intel_dsi->burst_mode_ratio);
>  	hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>  
> -	I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
> -	I915_WRITE(MIPI_HFP_COUNT(port), hfp);
> -
> -	/* meaningful for video mode non-burst sync pulse mode only, can be zero
> -	 * for non-burst sync events and burst modes */
> -	I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
> -	I915_WRITE(MIPI_HBP_COUNT(port), hbp);
> -
> -	/* vertical values are in terms of lines */
> -	I915_WRITE(MIPI_VFP_COUNT(port), vfp);
> -	I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
> -	I915_WRITE(MIPI_VBP_COUNT(port), vbp);
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
> +		I915_WRITE(MIPI_HFP_COUNT(port), hfp);
> +
> +		/* meaningful for video mode non-burst sync pulse mode only,
> +		 * can be zero for non-burst sync events and burst modes */
> +		I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
> +		I915_WRITE(MIPI_HBP_COUNT(port), hbp);
> +
> +		/* vertical values are in terms of lines */
> +		I915_WRITE(MIPI_VFP_COUNT(port), vfp);
> +		I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
> +		I915_WRITE(MIPI_VBP_COUNT(port), vbp);
> +	}
>  }
>  
>  static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 09/10] drm/i915: Update the DSI disable path to support dual link panel disabling
  2014-12-04  5:28 ` [PATCH 09/10] drm/i915: Update the DSI disable path to support dual link panel disabling Gaurav K Singh
@ 2014-12-04 11:37   ` Jani Nikula
  2014-12-05  8:52     ` [PATCH v4 " Gaurav K Singh
  0 siblings, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2014-12-04 11:37 UTC (permalink / raw)
  To: Gaurav K Singh, intel-gfx; +Cc: Shobhit Kumar

On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> We need to program both port registers during dual link disable path.
>
> v2: Address review comments by Jani
>     - Used a for loop instead of do-while loop.
>
> v3: Used for_each_dsi_port macro instead of for loop
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c |   67 ++++++++++++++++++++------------------
>  1 file changed, 36 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 22b1570..5ae4015 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -281,9 +281,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	enum port port;
>  	u32 temp;
>  
>  	DRM_DEBUG_KMS("\n");
> @@ -295,23 +294,24 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>  		msleep(2);
>  	}
>  
> -	/* Panel commands can be sent when clock is in LP11 */
> -	I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> -
> -	temp = I915_READ(MIPI_CTRL(port));
> -	temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> -	I915_WRITE(MIPI_CTRL(port), temp |
> -		   intel_dsi->escape_clk_div <<
> -		   ESCAPE_CLOCK_DIVIDER_SHIFT);
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		/* Panel commands can be sent when clock is in LP11 */
> +		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
>  
> -	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> +		temp = I915_READ(MIPI_CTRL(port));
> +		temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> +		I915_WRITE(MIPI_CTRL(port), temp |
> +			   intel_dsi->escape_clk_div <<
> +			   ESCAPE_CLOCK_DIVIDER_SHIFT);
>  
> -	temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> -	temp &= ~VID_MODE_FORMAT_MASK;
> -	I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
> +		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>  
> -	I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> +		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> +		temp &= ~VID_MODE_FORMAT_MASK;
> +		I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
>  
> +		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> +	}
>  	/* if disable packets are sent before sending shutdown packet then in
>  	 * some next enable sequence send turn on packet error is observed */
>  	if (intel_dsi->dev.dev_ops->disable)
> @@ -323,31 +323,36 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>  static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
>  	u32 val;
>  
>  	DRM_DEBUG_KMS("\n");
> +	for_each_dsi_port(port, intel_dsi->ports) {
>  
> -	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER);
> -	usleep_range(2000, 2500);
> +		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
> +							ULPS_STATE_ENTER);
> +		usleep_range(2000, 2500);
>  
> -	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_EXIT);
> -	usleep_range(2000, 2500);
> +		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
> +							ULPS_STATE_EXIT);
> +		usleep_range(2000, 2500);
>  
> -	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER);
> -	usleep_range(2000, 2500);
> +		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
> +							ULPS_STATE_ENTER);
> +		usleep_range(2000, 2500);
>  
> -	if (wait_for(((I915_READ(MIPI_PORT_CTRL(port)) & AFE_LATCHOUT)
> -		      == 0x00000), 30))
> -		DRM_ERROR("DSI LP not going Low\n");
> +		if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
> +							== 0x00000), 30))
> +			DRM_ERROR("DSI LP not going Low\n");

I find it a bit odd that you do the sequence for each port, while this
bit is specific to port A. It deserves a comment at the very least.

But perhaps we need several for_each_dsi_port() loops here, doing some
things for all ports, then common things (like this one, and maybe group
sleeps into one too?), then again some things for all ports, etc.

I am really not sure what the right thing is, but this *feels* a bit
odd. Please explain at least.

In the end, I don't see anything particularly wrong with the patch, so

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  
> -	val = I915_READ(MIPI_PORT_CTRL(port));
> -	I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD);
> -	usleep_range(1000, 1500);
> +		val = I915_READ(MIPI_PORT_CTRL(port));
> +		I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD);
> +		usleep_range(1000, 1500);
>  
> -	I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
> -	usleep_range(2000, 2500);
> +		I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
> +		usleep_range(2000, 2500);
> +	}
>  
>  	vlv_disable_dsi_pll(encoder);
>  }
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 10/10] drm/i915: Update the DSI enable path to support dual link panel enabling
  2014-12-04  5:28 ` [PATCH 10/10] drm/i915: Update the DSI enable path to support dual link panel enabling Gaurav K Singh
@ 2014-12-04 11:49   ` Jani Nikula
  2014-12-05  8:54     ` [PATCH v4 10/10] drm/i915: Update the DSI enable path to support dual Gaurav K Singh
  2014-12-05  4:04   ` [PATCH 10/10] drm/i915: Update the DSI enable path to support dual link panel enabling shuang.he
  1 sibling, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2014-12-04 11:49 UTC (permalink / raw)
  To: Gaurav K Singh, intel-gfx; +Cc: Shobhit Kumar

On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> We need to program both port registers during dual link enable path.
>
> v2: Address review comments by Jani
>     - Used a for loop instead of do-while loop.
>
> v3: Used for_each_dsi_port macro instead of for loop
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c |  251 +++++++++++++++++++++-----------------
>  1 file changed, 136 insertions(+), 115 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 5ae4015..ad82d0d 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -156,8 +156,8 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
>  static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
>  	u32 val;
>  
>  	DRM_DEBUG_KMS("\n");
> @@ -171,18 +171,21 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  	/* bandgap reset is needed after everytime we do power gate */
>  	band_gap_reset(dev_priv);
>  
> -	I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
> -	usleep_range(2500, 3000);
> +	for_each_dsi_port(port, intel_dsi->ports) {
>  
> -	val = I915_READ(MIPI_PORT_CTRL(port));
> -	I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
> -	usleep_range(1000, 1500);
> +		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
> +		usleep_range(2500, 3000);
>  
> -	I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
> -	usleep_range(2500, 3000);
> +		val = I915_READ(MIPI_PORT_CTRL(port));
> +		I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
> +		usleep_range(1000, 1500);
>  
> -	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
> -	usleep_range(2500, 3000);
> +		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
> +		usleep_range(2500, 3000);
> +
> +		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
> +		usleep_range(2500, 3000);
> +	}
>  }
>  
>  static void intel_dsi_enable(struct intel_encoder *encoder)
> @@ -541,32 +544,43 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>  	struct drm_display_mode *adjusted_mode =
>  		&intel_crtc->config.adjusted_mode;
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	enum port port;
>  	unsigned int bpp = intel_crtc->config.pipe_bpp;
>  	u32 val, tmp;
> +	u16 mode_hactive;
>  
>  	DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
>  
> -	/* escape clock divider, 20MHz, shared for A and C. device ready must be
> -	 * off when doing this! txclkesc? */
> -	tmp = I915_READ(MIPI_CTRL(PORT_A));
> -	tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> -	I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
> -
> -	/* read request priority is per pipe */
> -	tmp = I915_READ(MIPI_CTRL(port));
> -	tmp &= ~READ_REQUEST_PRIORITY_MASK;
> -	I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
> +	mode_hactive = adjusted_mode->hdisplay;

hactive vs. hdisplay is a bit confusing perhaps?

>  
> -	/* XXX: why here, why like this? handling in irq handler?! */
> -	I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
> -	I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
> -
> -	I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
> +	if (intel_dsi->dual_link) {
> +		mode_hactive /= 2;
> +		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
> +			mode_hactive += intel_dsi->pixel_overlap;
> +	}
>  
> -	I915_WRITE(MIPI_DPI_RESOLUTION(port),
> -		   adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
> -		   adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		/* escape clock divider, 20MHz, shared for A and C.
> +		 * device ready must be off when doing this! txclkesc? */
> +		tmp = I915_READ(MIPI_CTRL(PORT_A));
> +		tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> +		I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);

I think this part could be left outside of the loop, but no big deal
IMO.

> +
> +		/* read request priority is per pipe */
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		tmp &= ~READ_REQUEST_PRIORITY_MASK;
> +		I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
> +
> +		/* XXX: why here, why like this? handling in irq handler?! */
> +		I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
> +		I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
> +
> +		I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
> +
> +		I915_WRITE(MIPI_DPI_RESOLUTION(port),
> +			adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
> +			mode_hactive << HORIZONTAL_ADDRESS_SHIFT);
> +	}
>  
>  	set_dsi_timings(encoder, adjusted_mode);
>  
> @@ -580,95 +594,102 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>  		/* XXX: cross-check bpp vs. pixel format? */
>  		val |= intel_dsi->pixel_format;
>  	}
> -	I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
>  
> -	/* timeouts for recovery. one frame IIUC. if counter expires, EOT and
> -	 * stop state. */
> -
> -	/*
> -	 * In burst mode, value greater than one DPI line Time in byte clock
> -	 * (txbyteclkhs) To timeout this timer 1+ of the above said value is
> -	 * recommended.
> -	 *
> -	 * In non-burst mode, Value greater than one DPI frame time in byte
> -	 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
> -	 * is recommended.
> -	 *
> -	 * In DBI only mode, value greater than one DBI frame time in byte
> -	 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
> -	 * is recommended.
> -	 */
> -
> -	if (is_vid_mode(intel_dsi) &&
> -	    intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
> -		I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
> -			   txbyteclkhs(adjusted_mode->htotal, bpp,
> -				       intel_dsi->lane_count,
> -				       intel_dsi->burst_mode_ratio) + 1);
> -	} else {
> -		I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
> -			   txbyteclkhs(adjusted_mode->vtotal *
> -				       adjusted_mode->htotal,
> -				       bpp, intel_dsi->lane_count,
> -				       intel_dsi->burst_mode_ratio) + 1);
> -	}
> -	I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
> -	I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), intel_dsi->turn_arnd_val);
> -	I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), intel_dsi->rst_timer_val);
> -
> -	/* dphy stuff */
> -
> -	/* in terms of low power clock */
> -	I915_WRITE(MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100));
> -
> -	val = 0;
> +	tmp = 0;
>  	if (intel_dsi->eotp_pkt == 0)
> -		val |= EOT_DISABLE;
> -
> +		tmp |= EOT_DISABLE;
>  	if (intel_dsi->clock_stop)
> -		val |= CLOCKSTOP;
> -
> -	/* recovery disables */
> -	I915_WRITE(MIPI_EOT_DISABLE(port), val);
> -
> -	/* in terms of low power clock */
> -	I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
> -
> -	/* in terms of txbyteclkhs. actual high to low switch +
> -	 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
> -	 *
> -	 * XXX: write MIPI_STOP_STATE_STALL?
> -	 */
> -	I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
> -		   intel_dsi->hs_to_lp_count);
> +		tmp |= CLOCKSTOP;
>  
> -	/* XXX: low power clock equivalence in terms of byte clock. the number
> -	 * of byte clocks occupied in one low power clock. based on txbyteclkhs
> -	 * and txclkesc. txclkesc time / txbyteclk time * (105 +
> -	 * MIPI_STOP_STATE_STALL) / 105.???
> -	 */
> -	I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
> -
> -	/* the bw essential for transmitting 16 long packets containing 252
> -	 * bytes meant for dcs write memory command is programmed in this
> -	 * register in terms of byte clocks. based on dsi transfer rate and the
> -	 * number of lanes configured the time taken to transmit 16 long packets
> -	 * in a dsi stream varies. */
> -	I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
> -
> -	I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
> -		   intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
> -		   intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
> -
> -	if (is_vid_mode(intel_dsi))
> -		/* Some panels might have resolution which is not a multiple of
> -		 * 64 like 1366 x 768. Enable RANDOM resolution support for such
> -		 * panels by default */
> -		I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
> -			   intel_dsi->video_frmt_cfg_bits |
> -			   intel_dsi->video_mode_format |
> -			   IP_TG_CONFIG |
> -			   RANDOM_DPI_DISPLAY_RESOLUTION);
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
> +
> +		/* timeouts for recovery. one frame IIUC. if counter expires,
> +		 * EOT and stop state. */
> +
> +		/*
> +		 * In burst mode, value greater than one DPI line Time in byte
> +		 * clock (txbyteclkhs) To timeout this timer 1+ of the above
> +		 * said value is recommended.
> +		 *
> +		 * In non-burst mode, Value greater than one DPI frame time in
> +		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
> +		 * said value is recommended.
> +		 *
> +		 * In DBI only mode, value greater than one DBI frame time in
> +		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
> +		 * said value is recommended.
> +		 */
> +
> +		if (is_vid_mode(intel_dsi) &&
> +			intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
> +			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
> +				txbyteclkhs(adjusted_mode->htotal, bpp,
> +					intel_dsi->lane_count,
> +					intel_dsi->burst_mode_ratio) + 1);
> +		} else {
> +			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
> +				txbyteclkhs(adjusted_mode->vtotal *
> +					adjusted_mode->htotal,
> +					bpp, intel_dsi->lane_count,
> +					intel_dsi->burst_mode_ratio) + 1);
> +		}
> +		I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
> +		I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
> +						intel_dsi->turn_arnd_val);
> +		I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
> +						intel_dsi->rst_timer_val);
> +
> +		/* dphy stuff */
> +
> +		/* in terms of low power clock */
> +		I915_WRITE(MIPI_INIT_COUNT(port),
> +				txclkesc(intel_dsi->escape_clk_div, 100));
> +
> +
> +		/* recovery disables */
> +		I915_WRITE(MIPI_EOT_DISABLE(port), val);
> +
> +		/* in terms of low power clock */
> +		I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);

Side note not related to this patch: MIPI_INIT_COUNT gets written twice,
probably not intentionally. Follow-up fix for the future.


Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +
> +		/* in terms of txbyteclkhs. actual high to low switch +
> +		 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
> +		 *
> +		 * XXX: write MIPI_STOP_STATE_STALL?
> +		 */
> +		I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
> +						intel_dsi->hs_to_lp_count);
> +
> +		/* XXX: low power clock equivalence in terms of byte clock.
> +		 * the number of byte clocks occupied in one low power clock.
> +		 * based on txbyteclkhs and txclkesc.
> +		 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
> +		 * ) / 105.???
> +		 */
> +		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
> +
> +		/* the bw essential for transmitting 16 long packets containing
> +		 * 252 bytes meant for dcs write memory command is programmed in
> +		 * this register in terms of byte clocks. based on dsi transfer
> +		 * rate and the number of lanes configured the time taken to
> +		 * transmit 16 long packets in a dsi stream varies. */
> +		I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
> +
> +		I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
> +		intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
> +		intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
> +
> +		if (is_vid_mode(intel_dsi))
> +			/* Some panels might have resolution which is not a
> +			 * multiple of 64 like 1366 x 768. Enable RANDOM
> +			 * resolution support for such panels by default */
> +			I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
> +				intel_dsi->video_frmt_cfg_bits |
> +				intel_dsi->video_mode_format |
> +				IP_TG_CONFIG |
> +				RANDOM_DPI_DISPLAY_RESOLUTION);
> +	}
>  }
>  
>  static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 10/10] drm/i915: Update the DSI enable path to support dual link panel enabling
  2014-12-04  5:28 ` [PATCH 10/10] drm/i915: Update the DSI enable path to support dual link panel enabling Gaurav K Singh
  2014-12-04 11:49   ` Jani Nikula
@ 2014-12-05  4:04   ` shuang.he
  1 sibling, 0 replies; 41+ messages in thread
From: shuang.he @ 2014-12-05  4:04 UTC (permalink / raw)
  To: shuang.he, intel-gfx, gaurav.k.singh

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  364/364              364/364
ILK                                  366/366              366/366
SNB                                  450/450              450/450
IVB              +17                 481/498              498/498
BYT                                  289/289              289/289
HSW                                  564/564              564/564
BDW                                  417/417              417/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 IVB  igt_kms_3d      DMESG_WARN(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_cursor_crc_cursor-128x128-onscreen      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_cursor_crc_cursor-128x128-random      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_cursor_crc_cursor-128x128-sliding      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_cursor_crc_cursor-256x256-offscreen      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_cursor_crc_cursor-256x256-onscreen      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_cursor_crc_cursor-256x256-sliding      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_cursor_crc_cursor-64x64-offscreen      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_cursor_crc_cursor-64x64-onscreen      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_cursor_crc_cursor-64x64-random      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_cursor_crc_cursor-64x64-sliding      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_cursor_crc_cursor-size-change      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_fence_pin_leak      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_rotation_crc_primary-rotation      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
 IVB  igt_kms_rotation_crc_sprite-rotation      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M4)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply	[flat|nested] 41+ messages in thread
* [PATCH v4 03/10] drm/i915: Add support for port enable/disable for dual link configuration
  2014-12-04  9:17   ` Jani Nikula
@ 2014-12-05  8:39     ` Gaurav K Singh
  2014-12-05 12:52       ` Jani Nikula
  0 siblings, 1 reply; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-05  8:39 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

For Dual Link MIPI Panels, both Port A and Port C should be enabled
during the MIPI encoder enabling sequence. Similarly, during the
disabling sequence, both ports needs to be disabled.

v2: Used for_each_dsi_port macro instead of for loop

v3: Used intel_dsi->ports instead of dual_link var for dual link configuration check

v4: Masking of the required MIPI port bits before writing proper values

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h            |    1 +
 drivers/gpu/drm/i915/intel_dsi.c           |   37 +++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_dsi.h           |    1 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    4 +++
 4 files changed, 31 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc03fac..c981f5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6664,6 +6664,7 @@ enum punit_power_well {
 #define  DPI_ENABLE					(1 << 31) /* A + C */
 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
+#define  DUAL_LINK_MODE_SHIFT				26
 #define  DUAL_LINK_MODE_MASK				(1 << 26)
 #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
 #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 693736b..fd4d397 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -108,28 +108,41 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	u32 temp;
 
-	/* assert ip_tg_enable signal */
-	temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
-	temp = temp | intel_dsi->port_bits;
-	I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
-	POSTING_READ(MIPI_PORT_CTRL(port));
+	for_each_dsi_port(port, intel_dsi->ports) {
+		temp = I915_READ(MIPI_PORT_CTRL(port));
+		temp &= ~LANE_CONFIGURATION_MASK;
+		temp &= ~DUAL_LINK_MODE_MASK;
+
+		if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
+			temp |= (intel_dsi->dual_link - 1)
+						<< DUAL_LINK_MODE_SHIFT;
+			temp |= intel_crtc->pipe ?
+					LANE_CONFIGURATION_DUAL_LINK_B :
+					LANE_CONFIGURATION_DUAL_LINK_A;
+		}
+		/* assert ip_tg_enable signal */
+		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
+		POSTING_READ(MIPI_PORT_CTRL(port));
+	}
 }
 
 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
 	u32 temp;
 
-	/* de-assert ip_tg_enable signal */
-	temp = I915_READ(MIPI_PORT_CTRL(port));
-	I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
-	POSTING_READ(MIPI_PORT_CTRL(port));
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* de-assert ip_tg_enable signal */
+		temp = I915_READ(MIPI_PORT_CTRL(port));
+		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
+		POSTING_READ(MIPI_PORT_CTRL(port));
+	}
 }
 
 static void intel_dsi_device_ready(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 7f5d028..f2cc2fc 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -104,6 +104,7 @@ struct intel_dsi {
 	u8 clock_stop;
 
 	u8 escape_clk_div;
+	u8 dual_link;
 	u32 port_bits;
 	u32 bw_timer;
 	u32 dphy_reg;
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 7766c42..f60146f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -287,6 +287,10 @@ static bool generic_init(struct intel_dsi_device *dsi)
 	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
 	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
+	intel_dsi->dual_link = mipi_config->dual_link;
+
+	if (intel_dsi->dual_link)
+		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
 
 	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
 		bits_per_pixel = 18;
-- 
1.7.9.5

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH v3 04/10] drm/i915: Pixel Clock changes for DSI dual link
  2014-12-04  9:27   ` Jani Nikula
@ 2014-12-05  8:43     ` Gaurav K Singh
  2014-12-05 16:33     ` [PATCH " Singh, Gaurav K
  1 sibling, 0 replies; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-05  8:43 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for extra pixels.

v2 : Address review comments by Jani
     - Removed the bit mask used for ->dual_link
     - Used DSI instead of MIPI for #define variables

v3: Added the VLV_DISPLAY_BASE to VLV_CHICKEN_3 register

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h            |    4 ++++
 drivers/gpu/drm/i915/intel_bios.h          |    3 ++-
 drivers/gpu/drm/i915/intel_dsi.c           |    8 ++++++++
 drivers/gpu/drm/i915/intel_dsi.h           |    6 ++++++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 +++++++++++++++++++++
 5 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c981f5d..92dd142 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6029,6 +6029,10 @@ enum punit_power_well {
 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
 #define VLV_PWRDWNUPCTL				0xA294
 
+#define VLV_CHICKEN_3				(VLV_DISPLAY_BASE + 0x7040C)
+#define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
+#define  PIXEL_OVERLAP_CNT_SHIFT		30
+
 #define GEN6_PMISR				0x44020
 #define GEN6_PMIMR				0x44024 /* rps_lock */
 #define GEN6_PMIIR				0x44028
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index de01167..a6a8710 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -818,7 +818,8 @@ struct mipi_config {
 #define DUAL_LINK_PIXEL_ALT	2
 	u16 dual_link:2;
 	u16 lane_cnt:2;
-	u16 rsvd3:12;
+	u16 pixel_overlap:3;
+	u16 rsvd3:9;
 
 	u16 rsvd4;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index fd4d397..a1b93c5 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -111,6 +111,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 	enum port port;
 	u32 temp;
 
+	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+		temp = I915_READ(VLV_CHICKEN_3);
+		temp &= ~PIXEL_OVERLAP_CNT_MASK |
+					intel_dsi->pixel_overlap <<
+					PIXEL_OVERLAP_CNT_SHIFT;
+		I915_WRITE(VLV_CHICKEN_3, temp);
+	}
+
 	for_each_dsi_port(port, intel_dsi->ports) {
 		temp = I915_READ(MIPI_PORT_CTRL(port));
 		temp &= ~LANE_CONFIGURATION_MASK;
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index f2cc2fc..8fe2064 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -28,6 +28,11 @@
 #include <drm/drm_crtc.h>
 #include "intel_drv.h"
 
+/* Dual Link support */
+#define DSI_DUAL_LINK_NONE		0
+#define DSI_DUAL_LINK_FRONT_BACK	1
+#define DSI_DUAL_LINK_PIXEL_ALT		2
+
 struct intel_dsi_device {
 	unsigned int panel_id;
 	const char *name;
@@ -105,6 +110,7 @@ struct intel_dsi {
 
 	u8 escape_clk_div;
 	u8 dual_link;
+	u8 pixel_overlap;
 	u32 port_bits;
 	u32 bw_timer;
 	u32 dphy_reg;
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f60146f..f8c2269 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -288,6 +288,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
 	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
 	intel_dsi->dual_link = mipi_config->dual_link;
+	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
 
 	if (intel_dsi->dual_link)
 		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
@@ -310,6 +311,20 @@ static bool generic_init(struct intel_dsi_device *dsi)
 
 	pclk = mode->clock;
 
+	/* In dual link mode each port needs half of pixel clock */
+	if (intel_dsi->dual_link) {
+		pclk = pclk / 2;
+
+		/* we can enable pixel_overlap if needed by panel. In this
+		 * case we need to increase the pixelclock for extra pixels
+		 */
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+			pclk += DIV_ROUND_UP(mode->vtotal *
+						intel_dsi->pixel_overlap *
+						60, 1000);
+		}
+	}
+
 	/* Burst Mode Ratio
 	 * Target ddr frequency from VBT / non burst ddr freq
 	 * multiply by 100 to preserve remainder
@@ -504,6 +519,12 @@ static bool generic_init(struct intel_dsi_device *dsi)
 	DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
 						"disabled" : "enabled");
 	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
+	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
+	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
+		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
+	else
+		DRM_DEBUG_KMS("Dual link: NONE\n");
 	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
 	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
 	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
-- 
1.7.9.5

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH v2 07/10] drm/i915: cck reg used for checking DSI Pll locked
  2014-12-04 11:22   ` Jani Nikula
@ 2014-12-05  8:46     ` Gaurav K Singh
  0 siblings, 0 replies; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-05  8:46 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

Instead of pipe configuration reg, cck reg to be used for checking whether
DSI Pll is getting locked or not.

v2: dpio_lock unlocked now in case DSI PLL lock fails

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 636d72f..8957f10 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -272,12 +272,14 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
 	tmp |= DSI_PLL_VCO_EN;
 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
 
-	mutex_unlock(&dev_priv->dpio_lock);
+	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
+						DSI_PLL_LOCK, 20)) {
 
-	if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
+		mutex_unlock(&dev_priv->dpio_lock);
 		DRM_ERROR("DSI PLL lock failed\n");
 		return;
 	}
+	mutex_unlock(&dev_priv->dpio_lock);
 
 	DRM_DEBUG_KMS("DSI PLL locked\n");
 }
-- 
1.7.9.5

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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH v4 09/10] drm/i915: Update the DSI disable path to support dual link panel disabling
  2014-12-04 11:37   ` Jani Nikula
@ 2014-12-05  8:52     ` Gaurav K Singh
  0 siblings, 0 replies; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-05  8:52 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

We need to program both port registers during dual link disable path.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

v4: Added comments for the usage of AFE latchout bit

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   83 +++++++++++++++++++++-----------------
 1 file changed, 47 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 585538b..8054928 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -281,9 +281,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	u32 temp;
 
 	DRM_DEBUG_KMS("\n");
@@ -295,23 +294,24 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 		msleep(2);
 	}
 
-	/* Panel commands can be sent when clock is in LP11 */
-	I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
-
-	temp = I915_READ(MIPI_CTRL(port));
-	temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
-	I915_WRITE(MIPI_CTRL(port), temp |
-		   intel_dsi->escape_clk_div <<
-		   ESCAPE_CLOCK_DIVIDER_SHIFT);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* Panel commands can be sent when clock is in LP11 */
+		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 
-	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
+		temp = I915_READ(MIPI_CTRL(port));
+		temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+		I915_WRITE(MIPI_CTRL(port), temp |
+			   intel_dsi->escape_clk_div <<
+			   ESCAPE_CLOCK_DIVIDER_SHIFT);
 
-	temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
-	temp &= ~VID_MODE_FORMAT_MASK;
-	I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
+		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
+		temp &= ~VID_MODE_FORMAT_MASK;
+		I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 
+		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+	}
 	/* if disable packets are sent before sending shutdown packet then in
 	 * some next enable sequence send turn on packet error is observed */
 	if (intel_dsi->dev.dev_ops->disable)
@@ -323,31 +323,42 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
 	u32 val;
 
 	DRM_DEBUG_KMS("\n");
+	for_each_dsi_port(port, intel_dsi->ports) {
 
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER);
-	usleep_range(2000, 2500);
-
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_EXIT);
-	usleep_range(2000, 2500);
-
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER);
-	usleep_range(2000, 2500);
-
-	if (wait_for(((I915_READ(MIPI_PORT_CTRL(port)) & AFE_LATCHOUT)
-		      == 0x00000), 30))
-		DRM_ERROR("DSI LP not going Low\n");
-
-	val = I915_READ(MIPI_PORT_CTRL(port));
-	I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD);
-	usleep_range(1000, 1500);
-
-	I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
-	usleep_range(2000, 2500);
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
+							ULPS_STATE_ENTER);
+		usleep_range(2000, 2500);
+
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
+							ULPS_STATE_EXIT);
+		usleep_range(2000, 2500);
+
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
+							ULPS_STATE_ENTER);
+		usleep_range(2000, 2500);
+
+		/* Wait till Clock lanes are in LP-00 state for MIPI Port A
+		 * only. MIPI Port C has no similar bit for checking
+		 */
+		if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
+							== 0x00000), 30))
+			DRM_ERROR("DSI LP not going Low\n");
+
+		val = I915_READ(MIPI_PORT_CTRL(port));
+		/* Disable MIPI PHY transparent latch
+		 * Common bit for both MIPI Port A & MIPI Port C
+		 */
+		I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
+		usleep_range(1000, 1500);
+
+		I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
+		usleep_range(2000, 2500);
+	}
 
 	vlv_disable_dsi_pll(encoder);
 }
-- 
1.7.9.5

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^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH v4 10/10] drm/i915: Update the DSI enable path to support dual
  2014-12-04 11:49   ` Jani Nikula
@ 2014-12-05  8:54     ` Gaurav K Singh
  2014-12-05 20:31       ` [PATCH " Gaurav K Singh
  0 siblings, 1 reply; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-05  8:54 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

We need to program both port registers during dual link enable path.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

v4: Renamed mode_hactive variable to mode_hdisplay

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |  241 +++++++++++++++++++++-----------------
 1 file changed, 131 insertions(+), 110 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 8054928..8f8b952 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -156,8 +156,8 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
 	u32 val;
 
 	DRM_DEBUG_KMS("\n");
@@ -171,18 +171,21 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 	/* bandgap reset is needed after everytime we do power gate */
 	band_gap_reset(dev_priv);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
-	usleep_range(2500, 3000);
+	for_each_dsi_port(port, intel_dsi->ports) {
 
-	val = I915_READ(MIPI_PORT_CTRL(port));
-	I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
-	usleep_range(1000, 1500);
+		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
+		usleep_range(2500, 3000);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
-	usleep_range(2500, 3000);
+		val = I915_READ(MIPI_PORT_CTRL(port));
+		I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
+		usleep_range(1000, 1500);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
-	usleep_range(2500, 3000);
+		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
+		usleep_range(2500, 3000);
+
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
+		usleep_range(2500, 3000);
+	}
 }
 
 static void intel_dsi_enable(struct intel_encoder *encoder)
@@ -547,32 +550,43 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	struct drm_display_mode *adjusted_mode =
 		&intel_crtc->config.adjusted_mode;
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	unsigned int bpp = intel_crtc->config.pipe_bpp;
 	u32 val, tmp;
+	u16 mode_hdisplay;
 
 	DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
 
-	/* escape clock divider, 20MHz, shared for A and C. device ready must be
-	 * off when doing this! txclkesc? */
-	tmp = I915_READ(MIPI_CTRL(PORT_A));
-	tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
-	I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
-
-	/* read request priority is per pipe */
-	tmp = I915_READ(MIPI_CTRL(port));
-	tmp &= ~READ_REQUEST_PRIORITY_MASK;
-	I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
+	mode_hdisplay = adjusted_mode->hdisplay;
 
-	/* XXX: why here, why like this? handling in irq handler?! */
-	I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
-	I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
-
-	I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
+	if (intel_dsi->dual_link) {
+		mode_hdisplay /= 2;
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+			mode_hdisplay += intel_dsi->pixel_overlap;
+	}
 
-	I915_WRITE(MIPI_DPI_RESOLUTION(port),
-		   adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
-		   adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* escape clock divider, 20MHz, shared for A and C.
+		 * device ready must be off when doing this! txclkesc? */
+		tmp = I915_READ(MIPI_CTRL(PORT_A));
+		tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+		I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
+
+		/* read request priority is per pipe */
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp &= ~READ_REQUEST_PRIORITY_MASK;
+		I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
+
+		/* XXX: why here, why like this? handling in irq handler?! */
+		I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
+		I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
+
+		I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
+
+		I915_WRITE(MIPI_DPI_RESOLUTION(port),
+			adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
+			mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
+	}
 
 	set_dsi_timings(encoder, adjusted_mode);
 
@@ -586,95 +600,102 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 		/* XXX: cross-check bpp vs. pixel format? */
 		val |= intel_dsi->pixel_format;
 	}
-	I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
 
-	/* timeouts for recovery. one frame IIUC. if counter expires, EOT and
-	 * stop state. */
-
-	/*
-	 * In burst mode, value greater than one DPI line Time in byte clock
-	 * (txbyteclkhs) To timeout this timer 1+ of the above said value is
-	 * recommended.
-	 *
-	 * In non-burst mode, Value greater than one DPI frame time in byte
-	 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
-	 * is recommended.
-	 *
-	 * In DBI only mode, value greater than one DBI frame time in byte
-	 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
-	 * is recommended.
-	 */
-
-	if (is_vid_mode(intel_dsi) &&
-	    intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
-		I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
-			   txbyteclkhs(adjusted_mode->htotal, bpp,
-				       intel_dsi->lane_count,
-				       intel_dsi->burst_mode_ratio) + 1);
-	} else {
-		I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
-			   txbyteclkhs(adjusted_mode->vtotal *
-				       adjusted_mode->htotal,
-				       bpp, intel_dsi->lane_count,
-				       intel_dsi->burst_mode_ratio) + 1);
-	}
-	I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
-	I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), intel_dsi->turn_arnd_val);
-	I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), intel_dsi->rst_timer_val);
+	tmp = 0;
+	if (intel_dsi->eotp_pkt == 0)
+		tmp |= EOT_DISABLE;
+	if (intel_dsi->clock_stop)
+		tmp |= CLOCKSTOP;
 
-	/* dphy stuff */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
+
+		/* timeouts for recovery. one frame IIUC. if counter expires,
+		 * EOT and stop state. */
+
+		/*
+		 * In burst mode, value greater than one DPI line Time in byte
+		 * clock (txbyteclkhs) To timeout this timer 1+ of the above
+		 * said value is recommended.
+		 *
+		 * In non-burst mode, Value greater than one DPI frame time in
+		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
+		 * said value is recommended.
+		 *
+		 * In DBI only mode, value greater than one DBI frame time in
+		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
+		 * said value is recommended.
+		 */
 
-	/* in terms of low power clock */
-	I915_WRITE(MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100));
+		if (is_vid_mode(intel_dsi) &&
+			intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
+			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
+				txbyteclkhs(adjusted_mode->htotal, bpp,
+					intel_dsi->lane_count,
+					intel_dsi->burst_mode_ratio) + 1);
+		} else {
+			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
+				txbyteclkhs(adjusted_mode->vtotal *
+					adjusted_mode->htotal,
+					bpp, intel_dsi->lane_count,
+					intel_dsi->burst_mode_ratio) + 1);
+		}
+		I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
+		I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
+						intel_dsi->turn_arnd_val);
+		I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
+						intel_dsi->rst_timer_val);
 
-	val = 0;
-	if (intel_dsi->eotp_pkt == 0)
-		val |= EOT_DISABLE;
+		/* dphy stuff */
 
-	if (intel_dsi->clock_stop)
-		val |= CLOCKSTOP;
+		/* in terms of low power clock */
+		I915_WRITE(MIPI_INIT_COUNT(port),
+				txclkesc(intel_dsi->escape_clk_div, 100));
 
-	/* recovery disables */
-	I915_WRITE(MIPI_EOT_DISABLE(port), val);
 
-	/* in terms of low power clock */
-	I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
+		/* recovery disables */
+		I915_WRITE(MIPI_EOT_DISABLE(port), val);
 
-	/* in terms of txbyteclkhs. actual high to low switch +
-	 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
-	 *
-	 * XXX: write MIPI_STOP_STATE_STALL?
-	 */
-	I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
-		   intel_dsi->hs_to_lp_count);
+		/* in terms of low power clock */
+		I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
 
-	/* XXX: low power clock equivalence in terms of byte clock. the number
-	 * of byte clocks occupied in one low power clock. based on txbyteclkhs
-	 * and txclkesc. txclkesc time / txbyteclk time * (105 +
-	 * MIPI_STOP_STATE_STALL) / 105.???
-	 */
-	I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
-
-	/* the bw essential for transmitting 16 long packets containing 252
-	 * bytes meant for dcs write memory command is programmed in this
-	 * register in terms of byte clocks. based on dsi transfer rate and the
-	 * number of lanes configured the time taken to transmit 16 long packets
-	 * in a dsi stream varies. */
-	I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
-
-	I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
-		   intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
-		   intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
-
-	if (is_vid_mode(intel_dsi))
-		/* Some panels might have resolution which is not a multiple of
-		 * 64 like 1366 x 768. Enable RANDOM resolution support for such
-		 * panels by default */
-		I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
-			   intel_dsi->video_frmt_cfg_bits |
-			   intel_dsi->video_mode_format |
-			   IP_TG_CONFIG |
-			   RANDOM_DPI_DISPLAY_RESOLUTION);
+		/* in terms of txbyteclkhs. actual high to low switch +
+		 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
+		 *
+		 * XXX: write MIPI_STOP_STATE_STALL?
+		 */
+		I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
+						intel_dsi->hs_to_lp_count);
+
+		/* XXX: low power clock equivalence in terms of byte clock.
+		 * the number of byte clocks occupied in one low power clock.
+		 * based on txbyteclkhs and txclkesc.
+		 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
+		 * ) / 105.???
+		 */
+		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
+
+		/* the bw essential for transmitting 16 long packets containing
+		 * 252 bytes meant for dcs write memory command is programmed in
+		 * this register in terms of byte clocks. based on dsi transfer
+		 * rate and the number of lanes configured the time taken to
+		 * transmit 16 long packets in a dsi stream varies. */
+		I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
+
+		I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
+		intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
+		intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
+
+		if (is_vid_mode(intel_dsi))
+			/* Some panels might have resolution which is not a
+			 * multiple of 64 like 1366 x 768. Enable RANDOM
+			 * resolution support for such panels by default */
+			I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
+				intel_dsi->video_frmt_cfg_bits |
+				intel_dsi->video_mode_format |
+				IP_TG_CONFIG |
+				RANDOM_DPI_DISPLAY_RESOLUTION);
+	}
 }
 
 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
-- 
1.7.9.5

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^ permalink raw reply related	[flat|nested] 41+ messages in thread
* Re: [PATCH 02/10] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller
  2014-12-04 11:22     ` Daniel Vetter
@ 2014-12-05 12:50       ` Singh, Gaurav K
  2014-12-05 14:38         ` Daniel Vetter
  0 siblings, 1 reply; 41+ messages in thread
From: Singh, Gaurav K @ 2014-12-05 12:50 UTC (permalink / raw)
  To: Daniel Vetter, Jani Nikula; +Cc: Shobhit Kumar, intel-gfx


On 12/4/2014 4:52 PM, Daniel Vetter wrote:
> On Thu, Dec 04, 2014 at 11:14:01AM +0200, Jani Nikula wrote:
>> On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>>> This patch is in preparation of DSI dual link panels. For dual link
>>> panels, few packets needs to be sent to Port A or Port C or both. Based
>>> on the portno from MIPI Sequence Block#53, these sequences needs to be
>>> sent accordingly.
>>>
>>> v2: Addressed review comments by Jani
>>>      - port variables named properly
>>>
>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Merged the first two patches, thanks.
> -Daniel
Hi Daniel,

Thanks. I have addressed Jani's review comments too for the rest of the 
patches.

With regards,
Gaurav
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^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH v4 03/10] drm/i915: Add support for port enable/disable for dual link configuration
  2014-12-05  8:39     ` [PATCH v4 " Gaurav K Singh
@ 2014-12-05 12:52       ` Jani Nikula
  0 siblings, 0 replies; 41+ messages in thread
From: Jani Nikula @ 2014-12-05 12:52 UTC (permalink / raw)
  To: Gaurav K Singh, intel-gfx; +Cc: Shobhit Kumar

On Fri, 05 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> For Dual Link MIPI Panels, both Port A and Port C should be enabled
> during the MIPI encoder enabling sequence. Similarly, during the
> disabling sequence, both ports needs to be disabled.
>
> v2: Used for_each_dsi_port macro instead of for loop
>
> v3: Used intel_dsi->ports instead of dual_link var for dual link configuration check
>
> v4: Masking of the required MIPI port bits before writing proper values
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Yup.

> ---
>  drivers/gpu/drm/i915/i915_reg.h            |    1 +
>  drivers/gpu/drm/i915/intel_dsi.c           |   37 +++++++++++++++++++---------
>  drivers/gpu/drm/i915/intel_dsi.h           |    1 +
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    4 +++
>  4 files changed, 31 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dc03fac..c981f5d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6664,6 +6664,7 @@ enum punit_power_well {
>  #define  DPI_ENABLE					(1 << 31) /* A + C */
>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
> +#define  DUAL_LINK_MODE_SHIFT				26
>  #define  DUAL_LINK_MODE_MASK				(1 << 26)
>  #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
>  #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 693736b..fd4d397 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -108,28 +108,41 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	enum port port;
>  	u32 temp;
>  
> -	/* assert ip_tg_enable signal */
> -	temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
> -	temp = temp | intel_dsi->port_bits;
> -	I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
> -	POSTING_READ(MIPI_PORT_CTRL(port));
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		temp = I915_READ(MIPI_PORT_CTRL(port));
> +		temp &= ~LANE_CONFIGURATION_MASK;
> +		temp &= ~DUAL_LINK_MODE_MASK;
> +
> +		if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
> +			temp |= (intel_dsi->dual_link - 1)
> +						<< DUAL_LINK_MODE_SHIFT;
> +			temp |= intel_crtc->pipe ?
> +					LANE_CONFIGURATION_DUAL_LINK_B :
> +					LANE_CONFIGURATION_DUAL_LINK_A;
> +		}
> +		/* assert ip_tg_enable signal */
> +		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
> +		POSTING_READ(MIPI_PORT_CTRL(port));
> +	}
>  }
>  
>  static void intel_dsi_port_disable(struct intel_encoder *encoder)
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
>  	u32 temp;
>  
> -	/* de-assert ip_tg_enable signal */
> -	temp = I915_READ(MIPI_PORT_CTRL(port));
> -	I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> -	POSTING_READ(MIPI_PORT_CTRL(port));
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		/* de-assert ip_tg_enable signal */
> +		temp = I915_READ(MIPI_PORT_CTRL(port));
> +		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> +		POSTING_READ(MIPI_PORT_CTRL(port));
> +	}
>  }
>  
>  static void intel_dsi_device_ready(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 7f5d028..f2cc2fc 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -104,6 +104,7 @@ struct intel_dsi {
>  	u8 clock_stop;
>  
>  	u8 escape_clk_div;
> +	u8 dual_link;
>  	u32 port_bits;
>  	u32 bw_timer;
>  	u32 dphy_reg;
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 7766c42..f60146f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -287,6 +287,10 @@ static bool generic_init(struct intel_dsi_device *dsi)
>  	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
>  	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>  	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
> +	intel_dsi->dual_link = mipi_config->dual_link;
> +
> +	if (intel_dsi->dual_link)
> +		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
>  
>  	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
>  		bits_per_pixel = 18;
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 02/10] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller
  2014-12-05 12:50       ` Singh, Gaurav K
@ 2014-12-05 14:38         ` Daniel Vetter
  2014-12-05 20:35           ` Singh, Gaurav K
  0 siblings, 1 reply; 41+ messages in thread
From: Daniel Vetter @ 2014-12-05 14:38 UTC (permalink / raw)
  To: Singh, Gaurav K; +Cc: Shobhit Kumar, intel-gfx

On Fri, Dec 05, 2014 at 06:20:43PM +0530, Singh, Gaurav K wrote:
> 
> On 12/4/2014 4:52 PM, Daniel Vetter wrote:
> >On Thu, Dec 04, 2014 at 11:14:01AM +0200, Jani Nikula wrote:
> >>On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> >>>This patch is in preparation of DSI dual link panels. For dual link
> >>>panels, few packets needs to be sent to Port A or Port C or both. Based
> >>>on the portno from MIPI Sequence Block#53, these sequences needs to be
> >>>sent accordingly.
> >>>
> >>>v2: Addressed review comments by Jani
> >>>     - port variables named properly
> >>>
> >>>Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> >>Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> >Merged the first two patches, thanks.
> >-Daniel
> Hi Daniel,
> 
> Thanks. I have addressed Jani's review comments too for the rest of the
> patches.

Well looking through the resend patches your changes look a bit minimal.
Which might be the right thing to do, but review is also about
communication and sharing expert knowledge. So please follow up to the
questions from Jani where you didn't adjust the code. And if there's any
follow-up patches from those discussions please submit them.

Another part: Your editor doesn't seem to align continuation lines quite
how we usually do that. checkpatch --strict will catch that. Two big
rules:
- function paramater lists should be aligned to the opening ( on the next
  line.
- Continuations of boolean logic checks (e.g. in if checks) same, with the
  special rule that && or || should be on the previous line as the last
  thing.
- continuation of any other long lines should be indented 1 or two spaces
  (just to make sure it sticks out without looking jarring).

Especially the first two help readability a lot of you're used to them, so
please do a follow-up patch to rectify this in intel_dsi*.c.

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 04/10] drm/i915: Pixel Clock changes for DSI dual link
  2014-12-04  9:27   ` Jani Nikula
  2014-12-05  8:43     ` [PATCH v3 " Gaurav K Singh
@ 2014-12-05 16:33     ` Singh, Gaurav K
  2014-12-05 16:54       ` Siluvery, Arun
  1 sibling, 1 reply; 41+ messages in thread
From: Singh, Gaurav K @ 2014-12-05 16:33 UTC (permalink / raw)
  To: Jani Nikula, intel-gfx; +Cc: Shobhit Kumar


On 12/4/2014 2:57 PM, Jani Nikula wrote:
> On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>> For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
>> can be enabled if needed by panel, then in that case, pixel clock will be
>> increased for extra pixels.
>>
>> v2 : Address review comments by Jani
>>       - Removed the bit mask used for ->dual_link
>>       - Used DSI instead of MIPI for #define variables
>>
>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h            |    4 ++++
>>   drivers/gpu/drm/i915/intel_bios.h          |    3 ++-
>>   drivers/gpu/drm/i915/intel_dsi.c           |    8 ++++++++
>>   drivers/gpu/drm/i915/intel_dsi.h           |    6 ++++++
>>   drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 +++++++++++++++++++++
>>   5 files changed, 41 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index c981f5d..87149ba 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6029,6 +6029,10 @@ enum punit_power_well {
>>   #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
>>   #define VLV_PWRDWNUPCTL				0xA294
>>   
>> +#define VLV_CHICKEN_3				0x7040C
>> +#define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
>> +#define  PIXEL_OVERLAP_CNT_SHIFT		30
> I didn't find this register, but does it not need + VLV_DISPLAY_BASE?
>
> Given that I can't find the register my review is pretty shallow, but I
> don't spot anything obviously wrong either. With these caveats,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> This reg is available in BSpec though the bit definitions have not been updated in the BSpec. Also, it was communicated by the BIOS team.
>> +
>>   #define GEN6_PMISR				0x44020
>>   #define GEN6_PMIMR				0x44024 /* rps_lock */
>>   #define GEN6_PMIIR				0x44028
>> diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
>> index de01167..a6a8710 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.h
>> +++ b/drivers/gpu/drm/i915/intel_bios.h
>> @@ -818,7 +818,8 @@ struct mipi_config {
>>   #define DUAL_LINK_PIXEL_ALT	2
>>   	u16 dual_link:2;
>>   	u16 lane_cnt:2;
>> -	u16 rsvd3:12;
>> +	u16 pixel_overlap:3;
>> +	u16 rsvd3:9;
>>   
>>   	u16 rsvd4;
>>   
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index dbe52e9..4e18abd 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -111,6 +111,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>>   	enum port port;
>>   	u32 temp;
>>   
>> +	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>> +		temp = I915_READ(VLV_CHICKEN_3);
>> +		temp &= ~PIXEL_OVERLAP_CNT_MASK |
>> +					intel_dsi->pixel_overlap <<
>> +					PIXEL_OVERLAP_CNT_SHIFT;
>> +		I915_WRITE(VLV_CHICKEN_3, temp);
>> +	}
>> +
>>   	for_each_dsi_port(port, intel_dsi->ports) {
>>   		temp = I915_READ(MIPI_PORT_CTRL(port));
>>   
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>> index f2cc2fc..8fe2064 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> @@ -28,6 +28,11 @@
>>   #include <drm/drm_crtc.h>
>>   #include "intel_drv.h"
>>   
>> +/* Dual Link support */
>> +#define DSI_DUAL_LINK_NONE		0
>> +#define DSI_DUAL_LINK_FRONT_BACK	1
>> +#define DSI_DUAL_LINK_PIXEL_ALT		2
>> +
>>   struct intel_dsi_device {
>>   	unsigned int panel_id;
>>   	const char *name;
>> @@ -105,6 +110,7 @@ struct intel_dsi {
>>   
>>   	u8 escape_clk_div;
>>   	u8 dual_link;
>> +	u8 pixel_overlap;
>>   	u32 port_bits;
>>   	u32 bw_timer;
>>   	u32 dphy_reg;
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index f60146f..f8c2269 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -288,6 +288,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>   	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>>   	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
>>   	intel_dsi->dual_link = mipi_config->dual_link;
>> +	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>>   
>>   	if (intel_dsi->dual_link)
>>   		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
>> @@ -310,6 +311,20 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>   
>>   	pclk = mode->clock;
>>   
>> +	/* In dual link mode each port needs half of pixel clock */
>> +	if (intel_dsi->dual_link) {
>> +		pclk = pclk / 2;
>> +
>> +		/* we can enable pixel_overlap if needed by panel. In this
>> +		 * case we need to increase the pixelclock for extra pixels
>> +		 */
>> +		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>> +			pclk += DIV_ROUND_UP(mode->vtotal *
>> +						intel_dsi->pixel_overlap *
>> +						60, 1000);
>> +		}
>> +	}
>> +
>>   	/* Burst Mode Ratio
>>   	 * Target ddr frequency from VBT / non burst ddr freq
>>   	 * multiply by 100 to preserve remainder
>> @@ -504,6 +519,12 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>   	DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
>>   						"disabled" : "enabled");
>>   	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
>> +	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
>> +		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
>> +	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
>> +		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
>> +	else
>> +		DRM_DEBUG_KMS("Dual link: NONE\n");
>>   	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
>>   	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
>>   	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 04/10] drm/i915: Pixel Clock changes for DSI dual link
  2014-12-05 16:33     ` [PATCH " Singh, Gaurav K
@ 2014-12-05 16:54       ` Siluvery, Arun
  2014-12-05 17:18         ` Singh, Gaurav K
  2014-12-05 17:36         ` Jani Nikula
  0 siblings, 2 replies; 41+ messages in thread
From: Siluvery, Arun @ 2014-12-05 16:54 UTC (permalink / raw)
  To: Singh, Gaurav K, Jani Nikula, intel-gfx; +Cc: Shobhit Kumar

On 05/12/2014 16:33, Singh, Gaurav K wrote:
>
> On 12/4/2014 2:57 PM, Jani Nikula wrote:
>> On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>>> For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
>>> can be enabled if needed by panel, then in that case, pixel clock will be
>>> increased for extra pixels.

just a question, why do we need pixel overlap?
I couldn't find more details from spec other than that when overlap is 
set some extra pixels are sent.

regards
Arun

>>>
>>> v2 : Address review comments by Jani
>>>        - Removed the bit mask used for ->dual_link
>>>        - Used DSI instead of MIPI for #define variables
>>>
>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/i915_reg.h            |    4 ++++
>>>    drivers/gpu/drm/i915/intel_bios.h          |    3 ++-
>>>    drivers/gpu/drm/i915/intel_dsi.c           |    8 ++++++++
>>>    drivers/gpu/drm/i915/intel_dsi.h           |    6 ++++++
>>>    drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 +++++++++++++++++++++
>>>    5 files changed, 41 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index c981f5d..87149ba 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -6029,6 +6029,10 @@ enum punit_power_well {
>>>    #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
>>>    #define VLV_PWRDWNUPCTL				0xA294
>>>
>>> +#define VLV_CHICKEN_3				0x7040C
>>> +#define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
>>> +#define  PIXEL_OVERLAP_CNT_SHIFT		30
>> I didn't find this register, but does it not need + VLV_DISPLAY_BASE?
>>
>> Given that I can't find the register my review is pretty shallow, but I
>> don't spot anything obviously wrong either. With these caveats,
>>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>
>> This reg is available in BSpec though the bit definitions have not been updated in the BSpec. Also, it was communicated by the BIOS team.
>>> +
>>>    #define GEN6_PMISR				0x44020
>>>    #define GEN6_PMIMR				0x44024 /* rps_lock */
>>>    #define GEN6_PMIIR				0x44028
>>> diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
>>> index de01167..a6a8710 100644
>>> --- a/drivers/gpu/drm/i915/intel_bios.h
>>> +++ b/drivers/gpu/drm/i915/intel_bios.h
>>> @@ -818,7 +818,8 @@ struct mipi_config {
>>>    #define DUAL_LINK_PIXEL_ALT	2
>>>    	u16 dual_link:2;
>>>    	u16 lane_cnt:2;
>>> -	u16 rsvd3:12;
>>> +	u16 pixel_overlap:3;
>>> +	u16 rsvd3:9;
>>>
>>>    	u16 rsvd4;
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>>> index dbe52e9..4e18abd 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>>> @@ -111,6 +111,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>>>    	enum port port;
>>>    	u32 temp;
>>>
>>> +	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>>> +		temp = I915_READ(VLV_CHICKEN_3);
>>> +		temp &= ~PIXEL_OVERLAP_CNT_MASK |
>>> +					intel_dsi->pixel_overlap <<
>>> +					PIXEL_OVERLAP_CNT_SHIFT;
>>> +		I915_WRITE(VLV_CHICKEN_3, temp);
>>> +	}
>>> +
>>>    	for_each_dsi_port(port, intel_dsi->ports) {
>>>    		temp = I915_READ(MIPI_PORT_CTRL(port));
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>>> index f2cc2fc..8fe2064 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>> @@ -28,6 +28,11 @@
>>>    #include <drm/drm_crtc.h>
>>>    #include "intel_drv.h"
>>>
>>> +/* Dual Link support */
>>> +#define DSI_DUAL_LINK_NONE		0
>>> +#define DSI_DUAL_LINK_FRONT_BACK	1
>>> +#define DSI_DUAL_LINK_PIXEL_ALT		2
>>> +
>>>    struct intel_dsi_device {
>>>    	unsigned int panel_id;
>>>    	const char *name;
>>> @@ -105,6 +110,7 @@ struct intel_dsi {
>>>
>>>    	u8 escape_clk_div;
>>>    	u8 dual_link;
>>> +	u8 pixel_overlap;
>>>    	u32 port_bits;
>>>    	u32 bw_timer;
>>>    	u32 dphy_reg;
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>> index f60146f..f8c2269 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>> @@ -288,6 +288,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>>    	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>>>    	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
>>>    	intel_dsi->dual_link = mipi_config->dual_link;
>>> +	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>>>
>>>    	if (intel_dsi->dual_link)
>>>    		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
>>> @@ -310,6 +311,20 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>>
>>>    	pclk = mode->clock;
>>>
>>> +	/* In dual link mode each port needs half of pixel clock */
>>> +	if (intel_dsi->dual_link) {
>>> +		pclk = pclk / 2;
>>> +
>>> +		/* we can enable pixel_overlap if needed by panel. In this
>>> +		 * case we need to increase the pixelclock for extra pixels
>>> +		 */
>>> +		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>>> +			pclk += DIV_ROUND_UP(mode->vtotal *
>>> +						intel_dsi->pixel_overlap *
>>> +						60, 1000);
>>> +		}
>>> +	}
>>> +
>>>    	/* Burst Mode Ratio
>>>    	 * Target ddr frequency from VBT / non burst ddr freq
>>>    	 * multiply by 100 to preserve remainder
>>> @@ -504,6 +519,12 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>>    	DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
>>>    						"disabled" : "enabled");
>>>    	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
>>> +	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
>>> +		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
>>> +	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
>>> +		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
>>> +	else
>>> +		DRM_DEBUG_KMS("Dual link: NONE\n");
>>>    	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
>>>    	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
>>>    	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
>>> --
>>> 1.7.9.5
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 04/10] drm/i915: Pixel Clock changes for DSI dual link
  2014-12-05 16:54       ` Siluvery, Arun
@ 2014-12-05 17:18         ` Singh, Gaurav K
  2014-12-05 17:36         ` Jani Nikula
  1 sibling, 0 replies; 41+ messages in thread
From: Singh, Gaurav K @ 2014-12-05 17:18 UTC (permalink / raw)
  To: Siluvery, Arun, Jani Nikula, intel-gfx; +Cc: Shobhit Kumar


On 12/5/2014 10:24 PM, Siluvery, Arun wrote:
> On 05/12/2014 16:33, Singh, Gaurav K wrote:
>>
>> On 12/4/2014 2:57 PM, Jani Nikula wrote:
>>> On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>>>> For dual link MIPI Panels, each port needs half of pixel clock. 
>>>> Pixel overlap
>>>> can be enabled if needed by panel, then in that case, pixel clock 
>>>> will be
>>>> increased for extra pixels.
>
> just a question, why do we need pixel overlap?
> I couldn't find more details from spec other than that when overlap is 
> set some extra pixels are sent.
>
> regards
> Arun

In Front-Back video mode for MIPI Dual Link the first half of columns of 
pixel is always transmitted by MIPI Port A  and second half in MIPI Port C.
Pixel Overlap Count sets the number of Pixels to be overlapped per half 
of Scanline in Front-Back video mode. In dual link front-back mode,
pixel overlap count needs to be added to HActive to account for the 
additional pixels added due to overlap.
>
>>>>
>>>> v2 : Address review comments by Jani
>>>>        - Removed the bit mask used for ->dual_link
>>>>        - Used DSI instead of MIPI for #define variables
>>>>
>>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/i915_reg.h            |    4 ++++
>>>>    drivers/gpu/drm/i915/intel_bios.h          |    3 ++-
>>>>    drivers/gpu/drm/i915/intel_dsi.c           |    8 ++++++++
>>>>    drivers/gpu/drm/i915/intel_dsi.h           |    6 ++++++
>>>>    drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 
>>>> +++++++++++++++++++++
>>>>    5 files changed, 41 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>>>> b/drivers/gpu/drm/i915/i915_reg.h
>>>> index c981f5d..87149ba 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -6029,6 +6029,10 @@ enum punit_power_well {
>>>>    #define GEN8_PMINTR_REDIRECT_TO_NON_DISP    (1<<31)
>>>>    #define VLV_PWRDWNUPCTL                0xA294
>>>>
>>>> +#define VLV_CHICKEN_3                0x7040C
>>>> +#define  PIXEL_OVERLAP_CNT_MASK            (3 << 30)
>>>> +#define  PIXEL_OVERLAP_CNT_SHIFT        30
>>> I didn't find this register, but does it not need + VLV_DISPLAY_BASE?
>>>
>>> Given that I can't find the register my review is pretty shallow, but I
>>> don't spot anything obviously wrong either. With these caveats,
>>>
>>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>>
>>> This reg is available in BSpec though the bit definitions have not 
>>> been updated in the BSpec. Also, it was communicated by the BIOS team.
>>>> +
>>>>    #define GEN6_PMISR                0x44020
>>>>    #define GEN6_PMIMR                0x44024 /* rps_lock */
>>>>    #define GEN6_PMIIR                0x44028
>>>> diff --git a/drivers/gpu/drm/i915/intel_bios.h 
>>>> b/drivers/gpu/drm/i915/intel_bios.h
>>>> index de01167..a6a8710 100644
>>>> --- a/drivers/gpu/drm/i915/intel_bios.h
>>>> +++ b/drivers/gpu/drm/i915/intel_bios.h
>>>> @@ -818,7 +818,8 @@ struct mipi_config {
>>>>    #define DUAL_LINK_PIXEL_ALT    2
>>>>        u16 dual_link:2;
>>>>        u16 lane_cnt:2;
>>>> -    u16 rsvd3:12;
>>>> +    u16 pixel_overlap:3;
>>>> +    u16 rsvd3:9;
>>>>
>>>>        u16 rsvd4;
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
>>>> b/drivers/gpu/drm/i915/intel_dsi.c
>>>> index dbe52e9..4e18abd 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>>>> @@ -111,6 +111,14 @@ static void intel_dsi_port_enable(struct 
>>>> intel_encoder *encoder)
>>>>        enum port port;
>>>>        u32 temp;
>>>>
>>>> +    if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>>>> +        temp = I915_READ(VLV_CHICKEN_3);
>>>> +        temp &= ~PIXEL_OVERLAP_CNT_MASK |
>>>> +                    intel_dsi->pixel_overlap <<
>>>> +                    PIXEL_OVERLAP_CNT_SHIFT;
>>>> +        I915_WRITE(VLV_CHICKEN_3, temp);
>>>> +    }
>>>> +
>>>>        for_each_dsi_port(port, intel_dsi->ports) {
>>>>            temp = I915_READ(MIPI_PORT_CTRL(port));
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h 
>>>> b/drivers/gpu/drm/i915/intel_dsi.h
>>>> index f2cc2fc..8fe2064 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>>> @@ -28,6 +28,11 @@
>>>>    #include <drm/drm_crtc.h>
>>>>    #include "intel_drv.h"
>>>>
>>>> +/* Dual Link support */
>>>> +#define DSI_DUAL_LINK_NONE        0
>>>> +#define DSI_DUAL_LINK_FRONT_BACK    1
>>>> +#define DSI_DUAL_LINK_PIXEL_ALT        2
>>>> +
>>>>    struct intel_dsi_device {
>>>>        unsigned int panel_id;
>>>>        const char *name;
>>>> @@ -105,6 +110,7 @@ struct intel_dsi {
>>>>
>>>>        u8 escape_clk_div;
>>>>        u8 dual_link;
>>>> +    u8 pixel_overlap;
>>>>        u32 port_bits;
>>>>        u32 bw_timer;
>>>>        u32 dphy_reg;
>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
>>>> b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>> index f60146f..f8c2269 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>> @@ -288,6 +288,7 @@ static bool generic_init(struct 
>>>> intel_dsi_device *dsi)
>>>>        intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>>>>        intel_dsi->pixel_format = 
>>>> mipi_config->videomode_color_format << 7;
>>>>        intel_dsi->dual_link = mipi_config->dual_link;
>>>> +    intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>>>>
>>>>        if (intel_dsi->dual_link)
>>>>            intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
>>>> @@ -310,6 +311,20 @@ static bool generic_init(struct 
>>>> intel_dsi_device *dsi)
>>>>
>>>>        pclk = mode->clock;
>>>>
>>>> +    /* In dual link mode each port needs half of pixel clock */
>>>> +    if (intel_dsi->dual_link) {
>>>> +        pclk = pclk / 2;
>>>> +
>>>> +        /* we can enable pixel_overlap if needed by panel. In this
>>>> +         * case we need to increase the pixelclock for extra pixels
>>>> +         */
>>>> +        if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>>>> +            pclk += DIV_ROUND_UP(mode->vtotal *
>>>> +                        intel_dsi->pixel_overlap *
>>>> +                        60, 1000);
>>>> +        }
>>>> +    }
>>>> +
>>>>        /* Burst Mode Ratio
>>>>         * Target ddr frequency from VBT / non burst ddr freq
>>>>         * multiply by 100 to preserve remainder
>>>> @@ -504,6 +519,12 @@ static bool generic_init(struct 
>>>> intel_dsi_device *dsi)
>>>>        DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
>>>>                            "disabled" : "enabled");
>>>>        DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? 
>>>> "command" : "video");
>>>> +    if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
>>>> +        DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
>>>> +    else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
>>>> +        DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
>>>> +    else
>>>> +        DRM_DEBUG_KMS("Dual link: NONE\n");
>>>>        DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
>>>>        DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
>>>>        DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", 
>>>> intel_dsi->lp_rx_timeout);
>>>> -- 
>>>> 1.7.9.5
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>
>
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 04/10] drm/i915: Pixel Clock changes for DSI dual link
  2014-12-05 16:54       ` Siluvery, Arun
  2014-12-05 17:18         ` Singh, Gaurav K
@ 2014-12-05 17:36         ` Jani Nikula
  2014-12-05 17:48           ` Siluvery, Arun
  1 sibling, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2014-12-05 17:36 UTC (permalink / raw)
  To: Siluvery, Arun, Singh, Gaurav K, intel-gfx; +Cc: Shobhit Kumar

On Fri, 05 Dec 2014, "Siluvery, Arun" <arun.siluvery@linux.intel.com> wrote:
> On 05/12/2014 16:33, Singh, Gaurav K wrote:
>>
>> On 12/4/2014 2:57 PM, Jani Nikula wrote:
>>> On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>>>> For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
>>>> can be enabled if needed by panel, then in that case, pixel clock will be
>>>> increased for extra pixels.
>
> just a question, why do we need pixel overlap?
> I couldn't find more details from spec other than that when overlap is 
> set some extra pixels are sent.

From the host perspective a dual link (or dual channel) DSI device is
two independent peripheral devices. On the peripheral side the display
has to combine the input from the two links (which may be two
independent DSI blocks on the peripheral as well) into one contiguous
display. I don't know the details, but I'm guessing pixel overlap just
makes it easier for the peripheral implementation to get it all
together.

BR,
Jani.

>
> regards
> Arun
>
>>>>
>>>> v2 : Address review comments by Jani
>>>>        - Removed the bit mask used for ->dual_link
>>>>        - Used DSI instead of MIPI for #define variables
>>>>
>>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/i915_reg.h            |    4 ++++
>>>>    drivers/gpu/drm/i915/intel_bios.h          |    3 ++-
>>>>    drivers/gpu/drm/i915/intel_dsi.c           |    8 ++++++++
>>>>    drivers/gpu/drm/i915/intel_dsi.h           |    6 ++++++
>>>>    drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 +++++++++++++++++++++
>>>>    5 files changed, 41 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>> index c981f5d..87149ba 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -6029,6 +6029,10 @@ enum punit_power_well {
>>>>    #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
>>>>    #define VLV_PWRDWNUPCTL				0xA294
>>>>
>>>> +#define VLV_CHICKEN_3				0x7040C
>>>> +#define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
>>>> +#define  PIXEL_OVERLAP_CNT_SHIFT		30
>>> I didn't find this register, but does it not need + VLV_DISPLAY_BASE?
>>>
>>> Given that I can't find the register my review is pretty shallow, but I
>>> don't spot anything obviously wrong either. With these caveats,
>>>
>>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>>
>>> This reg is available in BSpec though the bit definitions have not been updated in the BSpec. Also, it was communicated by the BIOS team.
>>>> +
>>>>    #define GEN6_PMISR				0x44020
>>>>    #define GEN6_PMIMR				0x44024 /* rps_lock */
>>>>    #define GEN6_PMIIR				0x44028
>>>> diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
>>>> index de01167..a6a8710 100644
>>>> --- a/drivers/gpu/drm/i915/intel_bios.h
>>>> +++ b/drivers/gpu/drm/i915/intel_bios.h
>>>> @@ -818,7 +818,8 @@ struct mipi_config {
>>>>    #define DUAL_LINK_PIXEL_ALT	2
>>>>    	u16 dual_link:2;
>>>>    	u16 lane_cnt:2;
>>>> -	u16 rsvd3:12;
>>>> +	u16 pixel_overlap:3;
>>>> +	u16 rsvd3:9;
>>>>
>>>>    	u16 rsvd4;
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>>>> index dbe52e9..4e18abd 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>>>> @@ -111,6 +111,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>>>>    	enum port port;
>>>>    	u32 temp;
>>>>
>>>> +	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>>>> +		temp = I915_READ(VLV_CHICKEN_3);
>>>> +		temp &= ~PIXEL_OVERLAP_CNT_MASK |
>>>> +					intel_dsi->pixel_overlap <<
>>>> +					PIXEL_OVERLAP_CNT_SHIFT;
>>>> +		I915_WRITE(VLV_CHICKEN_3, temp);
>>>> +	}
>>>> +
>>>>    	for_each_dsi_port(port, intel_dsi->ports) {
>>>>    		temp = I915_READ(MIPI_PORT_CTRL(port));
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>>>> index f2cc2fc..8fe2064 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>>> @@ -28,6 +28,11 @@
>>>>    #include <drm/drm_crtc.h>
>>>>    #include "intel_drv.h"
>>>>
>>>> +/* Dual Link support */
>>>> +#define DSI_DUAL_LINK_NONE		0
>>>> +#define DSI_DUAL_LINK_FRONT_BACK	1
>>>> +#define DSI_DUAL_LINK_PIXEL_ALT		2
>>>> +
>>>>    struct intel_dsi_device {
>>>>    	unsigned int panel_id;
>>>>    	const char *name;
>>>> @@ -105,6 +110,7 @@ struct intel_dsi {
>>>>
>>>>    	u8 escape_clk_div;
>>>>    	u8 dual_link;
>>>> +	u8 pixel_overlap;
>>>>    	u32 port_bits;
>>>>    	u32 bw_timer;
>>>>    	u32 dphy_reg;
>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>> index f60146f..f8c2269 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>> @@ -288,6 +288,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>>>    	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>>>>    	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
>>>>    	intel_dsi->dual_link = mipi_config->dual_link;
>>>> +	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>>>>
>>>>    	if (intel_dsi->dual_link)
>>>>    		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
>>>> @@ -310,6 +311,20 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>>>
>>>>    	pclk = mode->clock;
>>>>
>>>> +	/* In dual link mode each port needs half of pixel clock */
>>>> +	if (intel_dsi->dual_link) {
>>>> +		pclk = pclk / 2;
>>>> +
>>>> +		/* we can enable pixel_overlap if needed by panel. In this
>>>> +		 * case we need to increase the pixelclock for extra pixels
>>>> +		 */
>>>> +		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>>>> +			pclk += DIV_ROUND_UP(mode->vtotal *
>>>> +						intel_dsi->pixel_overlap *
>>>> +						60, 1000);
>>>> +		}
>>>> +	}
>>>> +
>>>>    	/* Burst Mode Ratio
>>>>    	 * Target ddr frequency from VBT / non burst ddr freq
>>>>    	 * multiply by 100 to preserve remainder
>>>> @@ -504,6 +519,12 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>>>    	DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
>>>>    						"disabled" : "enabled");
>>>>    	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
>>>> +	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
>>>> +		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
>>>> +	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
>>>> +		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
>>>> +	else
>>>> +		DRM_DEBUG_KMS("Dual link: NONE\n");
>>>>    	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
>>>>    	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
>>>>    	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
>>>> --
>>>> 1.7.9.5
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 04/10] drm/i915: Pixel Clock changes for DSI dual link
  2014-12-05 17:36         ` Jani Nikula
@ 2014-12-05 17:48           ` Siluvery, Arun
  2014-12-05 20:43             ` Singh, Gaurav K
  0 siblings, 1 reply; 41+ messages in thread
From: Siluvery, Arun @ 2014-12-05 17:48 UTC (permalink / raw)
  To: Jani Nikula, Singh, Gaurav K, intel-gfx; +Cc: Shobhit Kumar

On 05/12/2014 17:36, Jani Nikula wrote:
> On Fri, 05 Dec 2014, "Siluvery, Arun" <arun.siluvery@linux.intel.com> wrote:
>> On 05/12/2014 16:33, Singh, Gaurav K wrote:
>>>
>>> On 12/4/2014 2:57 PM, Jani Nikula wrote:
>>>> On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>>>>> For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
>>>>> can be enabled if needed by panel, then in that case, pixel clock will be
>>>>> increased for extra pixels.
>>
>> just a question, why do we need pixel overlap?
>> I couldn't find more details from spec other than that when overlap is
>> set some extra pixels are sent.
>
>>From the host perspective a dual link (or dual channel) DSI device is
> two independent peripheral devices. On the peripheral side the display
> has to combine the input from the two links (which may be two
> independent DSI blocks on the peripheral as well) into one contiguous
> display. I don't know the details, but I'm guessing pixel overlap just
> makes it easier for the peripheral implementation to get it all
> together.

Thank you for the details.
I am just wondering how few extra pixels help on the display side unless 
they are fixed values which act like some kind of markers to synchronize 
between two halves.

regards
Arun

>
> BR,
> Jani.
>
>>
>> regards
>> Arun
>>
>>>>>
>>>>> v2 : Address review comments by Jani
>>>>>         - Removed the bit mask used for ->dual_link
>>>>>         - Used DSI instead of MIPI for #define variables
>>>>>
>>>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>>>>> ---
>>>>>     drivers/gpu/drm/i915/i915_reg.h            |    4 ++++
>>>>>     drivers/gpu/drm/i915/intel_bios.h          |    3 ++-
>>>>>     drivers/gpu/drm/i915/intel_dsi.c           |    8 ++++++++
>>>>>     drivers/gpu/drm/i915/intel_dsi.h           |    6 ++++++
>>>>>     drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 +++++++++++++++++++++
>>>>>     5 files changed, 41 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>>> index c981f5d..87149ba 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>>> @@ -6029,6 +6029,10 @@ enum punit_power_well {
>>>>>     #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
>>>>>     #define VLV_PWRDWNUPCTL				0xA294
>>>>>
>>>>> +#define VLV_CHICKEN_3				0x7040C
>>>>> +#define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
>>>>> +#define  PIXEL_OVERLAP_CNT_SHIFT		30
>>>> I didn't find this register, but does it not need + VLV_DISPLAY_BASE?
>>>>
>>>> Given that I can't find the register my review is pretty shallow, but I
>>>> don't spot anything obviously wrong either. With these caveats,
>>>>
>>>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>>>
>>>> This reg is available in BSpec though the bit definitions have not been updated in the BSpec. Also, it was communicated by the BIOS team.
>>>>> +
>>>>>     #define GEN6_PMISR				0x44020
>>>>>     #define GEN6_PMIMR				0x44024 /* rps_lock */
>>>>>     #define GEN6_PMIIR				0x44028
>>>>> diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
>>>>> index de01167..a6a8710 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_bios.h
>>>>> +++ b/drivers/gpu/drm/i915/intel_bios.h
>>>>> @@ -818,7 +818,8 @@ struct mipi_config {
>>>>>     #define DUAL_LINK_PIXEL_ALT	2
>>>>>     	u16 dual_link:2;
>>>>>     	u16 lane_cnt:2;
>>>>> -	u16 rsvd3:12;
>>>>> +	u16 pixel_overlap:3;
>>>>> +	u16 rsvd3:9;
>>>>>
>>>>>     	u16 rsvd4;
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>>>>> index dbe52e9..4e18abd 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>>>>> @@ -111,6 +111,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>>>>>     	enum port port;
>>>>>     	u32 temp;
>>>>>
>>>>> +	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>>>>> +		temp = I915_READ(VLV_CHICKEN_3);
>>>>> +		temp &= ~PIXEL_OVERLAP_CNT_MASK |
>>>>> +					intel_dsi->pixel_overlap <<
>>>>> +					PIXEL_OVERLAP_CNT_SHIFT;
>>>>> +		I915_WRITE(VLV_CHICKEN_3, temp);
>>>>> +	}
>>>>> +
>>>>>     	for_each_dsi_port(port, intel_dsi->ports) {
>>>>>     		temp = I915_READ(MIPI_PORT_CTRL(port));
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>>>>> index f2cc2fc..8fe2064 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>>>> @@ -28,6 +28,11 @@
>>>>>     #include <drm/drm_crtc.h>
>>>>>     #include "intel_drv.h"
>>>>>
>>>>> +/* Dual Link support */
>>>>> +#define DSI_DUAL_LINK_NONE		0
>>>>> +#define DSI_DUAL_LINK_FRONT_BACK	1
>>>>> +#define DSI_DUAL_LINK_PIXEL_ALT		2
>>>>> +
>>>>>     struct intel_dsi_device {
>>>>>     	unsigned int panel_id;
>>>>>     	const char *name;
>>>>> @@ -105,6 +110,7 @@ struct intel_dsi {
>>>>>
>>>>>     	u8 escape_clk_div;
>>>>>     	u8 dual_link;
>>>>> +	u8 pixel_overlap;
>>>>>     	u32 port_bits;
>>>>>     	u32 bw_timer;
>>>>>     	u32 dphy_reg;
>>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>>> index f60146f..f8c2269 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>>> @@ -288,6 +288,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>>>>     	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>>>>>     	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
>>>>>     	intel_dsi->dual_link = mipi_config->dual_link;
>>>>> +	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>>>>>
>>>>>     	if (intel_dsi->dual_link)
>>>>>     		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
>>>>> @@ -310,6 +311,20 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>>>>
>>>>>     	pclk = mode->clock;
>>>>>
>>>>> +	/* In dual link mode each port needs half of pixel clock */
>>>>> +	if (intel_dsi->dual_link) {
>>>>> +		pclk = pclk / 2;
>>>>> +
>>>>> +		/* we can enable pixel_overlap if needed by panel. In this
>>>>> +		 * case we need to increase the pixelclock for extra pixels
>>>>> +		 */
>>>>> +		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>>>>> +			pclk += DIV_ROUND_UP(mode->vtotal *
>>>>> +						intel_dsi->pixel_overlap *
>>>>> +						60, 1000);
>>>>> +		}
>>>>> +	}
>>>>> +
>>>>>     	/* Burst Mode Ratio
>>>>>     	 * Target ddr frequency from VBT / non burst ddr freq
>>>>>     	 * multiply by 100 to preserve remainder
>>>>> @@ -504,6 +519,12 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>>>>     	DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
>>>>>     						"disabled" : "enabled");
>>>>>     	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
>>>>> +	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
>>>>> +		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
>>>>> +	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
>>>>> +		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
>>>>> +	else
>>>>> +		DRM_DEBUG_KMS("Dual link: NONE\n");
>>>>>     	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
>>>>>     	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
>>>>>     	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
>>>>> --
>>>>> 1.7.9.5
>>>>>
>>>>> _______________________________________________
>>>>> Intel-gfx mailing list
>>>>> Intel-gfx@lists.freedesktop.org
>>>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>
>>
>

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^ permalink raw reply	[flat|nested] 41+ messages in thread
* [PATCH 5/5] drm/i915: Dual link needs Shutdown and Turn on packet for both ports
  2014-12-04 10:41   ` Jani Nikula
@ 2014-12-05 19:10     ` Gaurav K Singh
  2014-12-05 20:53       ` Daniel Vetter
  0 siblings, 1 reply; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-05 19:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports
A & C during MIPI encoder disabling sequence. Similarly, TURN ON packet
to be sent to both Ports during MIPI encoder enabling sequence.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_cmd.c |   26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 8e30684..e97fb6a 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -385,8 +385,7 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	u32 mask;
 
 	/* XXX: pipe, hs */
@@ -395,18 +394,23 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
 	else
 		cmd |= DPI_LP_MODE;
 
-	/* clear bit */
-	I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* clear bit */
+		I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 
-	/* XXX: old code skips write if control unchanged */
-	if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
-		DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
+		/* XXX: old code skips write if control unchanged */
+		if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
+			DRM_ERROR("Same special packet %02x twice in a row.\n",
+				  cmd);
 
-	I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
+		I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 
-	mask = SPL_PKT_SENT_INTERRUPT;
-	if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
-		DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
+		mask = SPL_PKT_SENT_INTERRUPT;
+		if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask,
+			     100))
+			DRM_ERROR("Video mode command 0x%08x send failed.\n",
+				  cmd);
+	}
 
 	return 0;
 }
-- 
1.7.9.5

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^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 10/10] drm/i915: Update the DSI enable path to support dual
  2014-12-05  8:54     ` [PATCH v4 10/10] drm/i915: Update the DSI enable path to support dual Gaurav K Singh
@ 2014-12-05 20:31       ` Gaurav K Singh
  0 siblings, 0 replies; 41+ messages in thread
From: Gaurav K Singh @ 2014-12-05 20:31 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

We need to program both port registers during dual link enable path.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

v4: Renamed mode_hactive variable to mode_hdisplay

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |  244 +++++++++++++++++++++-----------------
 1 file changed, 134 insertions(+), 110 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 8054928..84e0231 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -156,8 +156,8 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
 	u32 val;
 
 	DRM_DEBUG_KMS("\n");
@@ -171,18 +171,21 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 	/* bandgap reset is needed after everytime we do power gate */
 	band_gap_reset(dev_priv);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
-	usleep_range(2500, 3000);
+	for_each_dsi_port(port, intel_dsi->ports) {
 
-	val = I915_READ(MIPI_PORT_CTRL(port));
-	I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
-	usleep_range(1000, 1500);
+		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
+		usleep_range(2500, 3000);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
-	usleep_range(2500, 3000);
+		val = I915_READ(MIPI_PORT_CTRL(port));
+		I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
+		usleep_range(1000, 1500);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
-	usleep_range(2500, 3000);
+		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
+		usleep_range(2500, 3000);
+
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
+		usleep_range(2500, 3000);
+	}
 }
 
 static void intel_dsi_enable(struct intel_encoder *encoder)
@@ -547,32 +550,43 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	struct drm_display_mode *adjusted_mode =
 		&intel_crtc->config.adjusted_mode;
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	unsigned int bpp = intel_crtc->config.pipe_bpp;
 	u32 val, tmp;
+	u16 mode_hdisplay;
 
 	DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
 
-	/* escape clock divider, 20MHz, shared for A and C. device ready must be
-	 * off when doing this! txclkesc? */
-	tmp = I915_READ(MIPI_CTRL(PORT_A));
-	tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
-	I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
-
-	/* read request priority is per pipe */
-	tmp = I915_READ(MIPI_CTRL(port));
-	tmp &= ~READ_REQUEST_PRIORITY_MASK;
-	I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
+	mode_hdisplay = adjusted_mode->hdisplay;
 
-	/* XXX: why here, why like this? handling in irq handler?! */
-	I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
-	I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
-
-	I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
+	if (intel_dsi->dual_link) {
+		mode_hdisplay /= 2;
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+			mode_hdisplay += intel_dsi->pixel_overlap;
+	}
 
-	I915_WRITE(MIPI_DPI_RESOLUTION(port),
-		   adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
-		   adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* escape clock divider, 20MHz, shared for A and C.
+		 * device ready must be off when doing this! txclkesc? */
+		tmp = I915_READ(MIPI_CTRL(PORT_A));
+		tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+		I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
+
+		/* read request priority is per pipe */
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp &= ~READ_REQUEST_PRIORITY_MASK;
+		I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
+
+		/* XXX: why here, why like this? handling in irq handler?! */
+		I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
+		I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
+
+		I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
+
+		I915_WRITE(MIPI_DPI_RESOLUTION(port),
+			   adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
+			   mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
+	}
 
 	set_dsi_timings(encoder, adjusted_mode);
 
@@ -586,95 +600,105 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 		/* XXX: cross-check bpp vs. pixel format? */
 		val |= intel_dsi->pixel_format;
 	}
-	I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
 
-	/* timeouts for recovery. one frame IIUC. if counter expires, EOT and
-	 * stop state. */
-
-	/*
-	 * In burst mode, value greater than one DPI line Time in byte clock
-	 * (txbyteclkhs) To timeout this timer 1+ of the above said value is
-	 * recommended.
-	 *
-	 * In non-burst mode, Value greater than one DPI frame time in byte
-	 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
-	 * is recommended.
-	 *
-	 * In DBI only mode, value greater than one DBI frame time in byte
-	 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
-	 * is recommended.
-	 */
-
-	if (is_vid_mode(intel_dsi) &&
-	    intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
-		I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
-			   txbyteclkhs(adjusted_mode->htotal, bpp,
-				       intel_dsi->lane_count,
-				       intel_dsi->burst_mode_ratio) + 1);
-	} else {
-		I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
-			   txbyteclkhs(adjusted_mode->vtotal *
-				       adjusted_mode->htotal,
-				       bpp, intel_dsi->lane_count,
-				       intel_dsi->burst_mode_ratio) + 1);
-	}
-	I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
-	I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), intel_dsi->turn_arnd_val);
-	I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), intel_dsi->rst_timer_val);
+	tmp = 0;
+	if (intel_dsi->eotp_pkt == 0)
+		tmp |= EOT_DISABLE;
+	if (intel_dsi->clock_stop)
+		tmp |= CLOCKSTOP;
 
-	/* dphy stuff */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
+
+		/* timeouts for recovery. one frame IIUC. if counter expires,
+		 * EOT and stop state. */
+
+		/*
+		 * In burst mode, value greater than one DPI line Time in byte
+		 * clock (txbyteclkhs) To timeout this timer 1+ of the above
+		 * said value is recommended.
+		 *
+		 * In non-burst mode, Value greater than one DPI frame time in
+		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
+		 * said value is recommended.
+		 *
+		 * In DBI only mode, value greater than one DBI frame time in
+		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
+		 * said value is recommended.
+		 */
 
-	/* in terms of low power clock */
-	I915_WRITE(MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100));
+		if (is_vid_mode(intel_dsi) &&
+		    intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
+			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
+				   txbyteclkhs(adjusted_mode->htotal, bpp,
+					       intel_dsi->lane_count,
+					       intel_dsi->burst_mode_ratio)
+					       + 1);
+		} else {
+			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
+				   txbyteclkhs(adjusted_mode->vtotal *
+				   adjusted_mode->htotal,
+				   bpp, intel_dsi->lane_count,
+				   intel_dsi->burst_mode_ratio) + 1);
+		}
+		I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
+		I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
+			   intel_dsi->turn_arnd_val);
+		I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
+			   intel_dsi->rst_timer_val);
 
-	val = 0;
-	if (intel_dsi->eotp_pkt == 0)
-		val |= EOT_DISABLE;
+		/* dphy stuff */
 
-	if (intel_dsi->clock_stop)
-		val |= CLOCKSTOP;
+		/* in terms of low power clock */
+		I915_WRITE(MIPI_INIT_COUNT(port),
+			   txclkesc(intel_dsi->escape_clk_div, 100));
 
-	/* recovery disables */
-	I915_WRITE(MIPI_EOT_DISABLE(port), val);
 
-	/* in terms of low power clock */
-	I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
+		/* recovery disables */
+		I915_WRITE(MIPI_EOT_DISABLE(port), val);
 
-	/* in terms of txbyteclkhs. actual high to low switch +
-	 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
-	 *
-	 * XXX: write MIPI_STOP_STATE_STALL?
-	 */
-	I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
-		   intel_dsi->hs_to_lp_count);
+		/* in terms of low power clock */
+		I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
 
-	/* XXX: low power clock equivalence in terms of byte clock. the number
-	 * of byte clocks occupied in one low power clock. based on txbyteclkhs
-	 * and txclkesc. txclkesc time / txbyteclk time * (105 +
-	 * MIPI_STOP_STATE_STALL) / 105.???
-	 */
-	I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
-
-	/* the bw essential for transmitting 16 long packets containing 252
-	 * bytes meant for dcs write memory command is programmed in this
-	 * register in terms of byte clocks. based on dsi transfer rate and the
-	 * number of lanes configured the time taken to transmit 16 long packets
-	 * in a dsi stream varies. */
-	I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
-
-	I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
-		   intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
-		   intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
-
-	if (is_vid_mode(intel_dsi))
-		/* Some panels might have resolution which is not a multiple of
-		 * 64 like 1366 x 768. Enable RANDOM resolution support for such
-		 * panels by default */
-		I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
-			   intel_dsi->video_frmt_cfg_bits |
-			   intel_dsi->video_mode_format |
-			   IP_TG_CONFIG |
-			   RANDOM_DPI_DISPLAY_RESOLUTION);
+		/* in terms of txbyteclkhs. actual high to low switch +
+		 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
+		 *
+		 * XXX: write MIPI_STOP_STATE_STALL?
+		 */
+		I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
+			   intel_dsi->hs_to_lp_count);
+
+		/* XXX: low power clock equivalence in terms of byte clock.
+		 * the number of byte clocks occupied in one low power clock.
+		 * based on txbyteclkhs and txclkesc.
+		 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
+		 * ) / 105.???
+		 */
+		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
+
+		/* the bw essential for transmitting 16 long packets containing
+		 * 252 bytes meant for dcs write memory command is programmed in
+		 * this register in terms of byte clocks. based on dsi transfer
+		 * rate and the number of lanes configured the time taken to
+		 * transmit 16 long packets in a dsi stream varies. */
+		I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
+
+		I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
+			   intel_dsi->clk_lp_to_hs_count <<
+			   LP_HS_SSW_CNT_SHIFT |
+			   intel_dsi->clk_hs_to_lp_count <<
+			   HS_LP_PWR_SW_CNT_SHIFT);
+
+		if (is_vid_mode(intel_dsi))
+			/* Some panels might have resolution which is not a
+			 * multiple of 64 like 1366 x 768. Enable RANDOM
+			 * resolution support for such panels by default */
+			I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
+				   intel_dsi->video_frmt_cfg_bits |
+				   intel_dsi->video_mode_format |
+				   IP_TG_CONFIG |
+				   RANDOM_DPI_DISPLAY_RESOLUTION);
+	}
 }
 
 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
-- 
1.7.9.5

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^ permalink raw reply related	[flat|nested] 41+ messages in thread
* Re: [PATCH 02/10] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller
  2014-12-05 14:38         ` Daniel Vetter
@ 2014-12-05 20:35           ` Singh, Gaurav K
  0 siblings, 0 replies; 41+ messages in thread
From: Singh, Gaurav K @ 2014-12-05 20:35 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Shobhit Kumar, intel-gfx


On 12/5/2014 8:08 PM, Daniel Vetter wrote:
> On Fri, Dec 05, 2014 at 06:20:43PM +0530, Singh, Gaurav K wrote:
>> On 12/4/2014 4:52 PM, Daniel Vetter wrote:
>>> On Thu, Dec 04, 2014 at 11:14:01AM +0200, Jani Nikula wrote:
>>>> On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>>>>> This patch is in preparation of DSI dual link panels. For dual link
>>>>> panels, few packets needs to be sent to Port A or Port C or both. Based
>>>>> on the portno from MIPI Sequence Block#53, these sequences needs to be
>>>>> sent accordingly.
>>>>>
>>>>> v2: Addressed review comments by Jani
>>>>>      - port variables named properly
>>>>>
>>>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>>>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>> Merged the first two patches, thanks.
>>> -Daniel
>> Hi Daniel,
>>
>> Thanks. I have addressed Jani's review comments too for the rest of the
>> patches.
> Well looking through the resend patches your changes look a bit minimal.
> Which might be the right thing to do, but review is also about
> communication and sharing expert knowledge. So please follow up to the
> questions from Jani where you didn't adjust the code. And if there's any
> follow-up patches from those discussions please submit them.
>
> Another part: Your editor doesn't seem to align continuation lines quite
> how we usually do that. checkpatch --strict will catch that. Two big
> rules:
> - function paramater lists should be aligned to the opening ( on the next
>    line.
> - Continuations of boolean logic checks (e.g. in if checks) same, with the
>    special rule that && or || should be on the previous line as the last
>    thing.
> - continuation of any other long lines should be indented 1 or two spaces
>    (just to make sure it sticks out without looking jarring).
>
> Especially the first two help readability a lot of you're used to them, so
> please do a follow-up patch to rectify this in intel_dsi*.c.
>
> Thanks, Daniel

Done. Fixed the style related issues and comments also added.

With regards,
Gaurav
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^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 04/10] drm/i915: Pixel Clock changes for DSI dual link
  2014-12-05 17:48           ` Siluvery, Arun
@ 2014-12-05 20:43             ` Singh, Gaurav K
  0 siblings, 0 replies; 41+ messages in thread
From: Singh, Gaurav K @ 2014-12-05 20:43 UTC (permalink / raw)
  To: Siluvery, Arun, Jani Nikula, intel-gfx; +Cc: Shobhit Kumar


On 12/5/2014 11:18 PM, Siluvery, Arun wrote:
> On 05/12/2014 17:36, Jani Nikula wrote:
>> On Fri, 05 Dec 2014, "Siluvery, Arun" <arun.siluvery@linux.intel.com> 
>> wrote:
>>> On 05/12/2014 16:33, Singh, Gaurav K wrote:
>>>>
>>>> On 12/4/2014 2:57 PM, Jani Nikula wrote:
>>>>> On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>>>>>> For dual link MIPI Panels, each port needs half of pixel clock. 
>>>>>> Pixel overlap
>>>>>> can be enabled if needed by panel, then in that case, pixel clock 
>>>>>> will be
>>>>>> increased for extra pixels.
>>>
>>> just a question, why do we need pixel overlap?
>>> I couldn't find more details from spec other than that when overlap is
>>> set some extra pixels are sent.
>>
>>> From the host perspective a dual link (or dual channel) DSI device is
>> two independent peripheral devices. On the peripheral side the display
>> has to combine the input from the two links (which may be two
>> independent DSI blocks on the peripheral as well) into one contiguous
>> display. I don't know the details, but I'm guessing pixel overlap just
>> makes it easier for the peripheral implementation to get it all
>> together.
>
> Thank you for the details.
> I am just wondering how few extra pixels help on the display side 
> unless they are fixed values which act like some kind of markers to 
> synchronize between two halves.
>
> regards
> Arun

Pixel overlap count are fixed values only and it can have values of 0, 1 
or 2. These values will be defined for the particular MIPI DSI panel specs.
These values are programmed in VBT which driver parses and uses it.

With regards,
Gaurav
>
>>
>> BR,
>> Jani.
>>
>>>
>>> regards
>>> Arun
>>>
>>>>>>
>>>>>> v2 : Address review comments by Jani
>>>>>>         - Removed the bit mask used for ->dual_link
>>>>>>         - Used DSI instead of MIPI for #define variables
>>>>>>
>>>>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>>>>>> ---
>>>>>>     drivers/gpu/drm/i915/i915_reg.h            |    4 ++++
>>>>>>     drivers/gpu/drm/i915/intel_bios.h          |    3 ++-
>>>>>>     drivers/gpu/drm/i915/intel_dsi.c           |    8 ++++++++
>>>>>>     drivers/gpu/drm/i915/intel_dsi.h           |    6 ++++++
>>>>>>     drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 
>>>>>> +++++++++++++++++++++
>>>>>>     5 files changed, 41 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>>>>>> b/drivers/gpu/drm/i915/i915_reg.h
>>>>>> index c981f5d..87149ba 100644
>>>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>>>> @@ -6029,6 +6029,10 @@ enum punit_power_well {
>>>>>>     #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
>>>>>>     #define VLV_PWRDWNUPCTL                0xA294
>>>>>>
>>>>>> +#define VLV_CHICKEN_3                0x7040C
>>>>>> +#define  PIXEL_OVERLAP_CNT_MASK            (3 << 30)
>>>>>> +#define  PIXEL_OVERLAP_CNT_SHIFT        30
>>>>> I didn't find this register, but does it not need + VLV_DISPLAY_BASE?
>>>>>
>>>>> Given that I can't find the register my review is pretty shallow, 
>>>>> but I
>>>>> don't spot anything obviously wrong either. With these caveats,
>>>>>
>>>>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>>>>
>>>>> This reg is available in BSpec though the bit definitions have not 
>>>>> been updated in the BSpec. Also, it was communicated by the BIOS 
>>>>> team.
>>>>>> +
>>>>>>     #define GEN6_PMISR                0x44020
>>>>>>     #define GEN6_PMIMR                0x44024 /* rps_lock */
>>>>>>     #define GEN6_PMIIR                0x44028
>>>>>> diff --git a/drivers/gpu/drm/i915/intel_bios.h 
>>>>>> b/drivers/gpu/drm/i915/intel_bios.h
>>>>>> index de01167..a6a8710 100644
>>>>>> --- a/drivers/gpu/drm/i915/intel_bios.h
>>>>>> +++ b/drivers/gpu/drm/i915/intel_bios.h
>>>>>> @@ -818,7 +818,8 @@ struct mipi_config {
>>>>>>     #define DUAL_LINK_PIXEL_ALT    2
>>>>>>         u16 dual_link:2;
>>>>>>         u16 lane_cnt:2;
>>>>>> -    u16 rsvd3:12;
>>>>>> +    u16 pixel_overlap:3;
>>>>>> +    u16 rsvd3:9;
>>>>>>
>>>>>>         u16 rsvd4;
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
>>>>>> b/drivers/gpu/drm/i915/intel_dsi.c
>>>>>> index dbe52e9..4e18abd 100644
>>>>>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>>>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>>>>>> @@ -111,6 +111,14 @@ static void intel_dsi_port_enable(struct 
>>>>>> intel_encoder *encoder)
>>>>>>         enum port port;
>>>>>>         u32 temp;
>>>>>>
>>>>>> +    if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>>>>>> +        temp = I915_READ(VLV_CHICKEN_3);
>>>>>> +        temp &= ~PIXEL_OVERLAP_CNT_MASK |
>>>>>> +                    intel_dsi->pixel_overlap <<
>>>>>> +                    PIXEL_OVERLAP_CNT_SHIFT;
>>>>>> +        I915_WRITE(VLV_CHICKEN_3, temp);
>>>>>> +    }
>>>>>> +
>>>>>>         for_each_dsi_port(port, intel_dsi->ports) {
>>>>>>             temp = I915_READ(MIPI_PORT_CTRL(port));
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h 
>>>>>> b/drivers/gpu/drm/i915/intel_dsi.h
>>>>>> index f2cc2fc..8fe2064 100644
>>>>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>>>>> @@ -28,6 +28,11 @@
>>>>>>     #include <drm/drm_crtc.h>
>>>>>>     #include "intel_drv.h"
>>>>>>
>>>>>> +/* Dual Link support */
>>>>>> +#define DSI_DUAL_LINK_NONE        0
>>>>>> +#define DSI_DUAL_LINK_FRONT_BACK    1
>>>>>> +#define DSI_DUAL_LINK_PIXEL_ALT        2
>>>>>> +
>>>>>>     struct intel_dsi_device {
>>>>>>         unsigned int panel_id;
>>>>>>         const char *name;
>>>>>> @@ -105,6 +110,7 @@ struct intel_dsi {
>>>>>>
>>>>>>         u8 escape_clk_div;
>>>>>>         u8 dual_link;
>>>>>> +    u8 pixel_overlap;
>>>>>>         u32 port_bits;
>>>>>>         u32 bw_timer;
>>>>>>         u32 dphy_reg;
>>>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
>>>>>> b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>>>> index f60146f..f8c2269 100644
>>>>>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>>>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>>>> @@ -288,6 +288,7 @@ static bool generic_init(struct 
>>>>>> intel_dsi_device *dsi)
>>>>>>         intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>>>>>>         intel_dsi->pixel_format = 
>>>>>> mipi_config->videomode_color_format << 7;
>>>>>>         intel_dsi->dual_link = mipi_config->dual_link;
>>>>>> +    intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>>>>>>
>>>>>>         if (intel_dsi->dual_link)
>>>>>>             intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
>>>>>> @@ -310,6 +311,20 @@ static bool generic_init(struct 
>>>>>> intel_dsi_device *dsi)
>>>>>>
>>>>>>         pclk = mode->clock;
>>>>>>
>>>>>> +    /* In dual link mode each port needs half of pixel clock */
>>>>>> +    if (intel_dsi->dual_link) {
>>>>>> +        pclk = pclk / 2;
>>>>>> +
>>>>>> +        /* we can enable pixel_overlap if needed by panel. In this
>>>>>> +         * case we need to increase the pixelclock for extra pixels
>>>>>> +         */
>>>>>> +        if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>>>>>> +            pclk += DIV_ROUND_UP(mode->vtotal *
>>>>>> +                        intel_dsi->pixel_overlap *
>>>>>> +                        60, 1000);
>>>>>> +        }
>>>>>> +    }
>>>>>> +
>>>>>>         /* Burst Mode Ratio
>>>>>>          * Target ddr frequency from VBT / non burst ddr freq
>>>>>>          * multiply by 100 to preserve remainder
>>>>>> @@ -504,6 +519,12 @@ static bool generic_init(struct 
>>>>>> intel_dsi_device *dsi)
>>>>>>         DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
>>>>>>                             "disabled" : "enabled");
>>>>>>         DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? 
>>>>>> "command" : "video");
>>>>>> +    if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
>>>>>> +        DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
>>>>>> +    else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
>>>>>> +        DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
>>>>>> +    else
>>>>>> +        DRM_DEBUG_KMS("Dual link: NONE\n");
>>>>>>         DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
>>>>>>         DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
>>>>>>         DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", 
>>>>>> intel_dsi->lp_rx_timeout);
>>>>>> -- 
>>>>>> 1.7.9.5
>>>>>>
>>>>>> _______________________________________________
>>>>>> Intel-gfx mailing list
>>>>>> Intel-gfx@lists.freedesktop.org
>>>>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>>
>>>
>>
>
>
>

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^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 5/5] drm/i915: Dual link needs Shutdown and Turn on packet for both ports
  2014-12-05 19:10     ` [PATCH 5/5] " Gaurav K Singh
@ 2014-12-05 20:53       ` Daniel Vetter
  0 siblings, 0 replies; 41+ messages in thread
From: Daniel Vetter @ 2014-12-05 20:53 UTC (permalink / raw)
  To: Gaurav K Singh; +Cc: Shobhit Kumar, intel-gfx

On Sat, Dec 06, 2014 at 12:40:39AM +0530, Gaurav K Singh wrote:
> For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports
> A & C during MIPI encoder disabling sequence. Similarly, TURN ON packet
> to be sent to both Ports during MIPI encoder enabling sequence.
> 
> v2: Address review comments by Jani
>     - Used a for loop instead of do-while loop.
> 
> v3: Used for_each_dsi_port macro instead of for loop
> 
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

I've merged this one already, so if you have changes please provide them
as fixups on top of -nightly.

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 41+ messages in thread
end of thread, other threads:[~2014-12-05 20:53 UTC | newest]

Thread overview: 41+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-12-04  5:28 [PATCH 00/10] BYT DSI Dual Link Support Gaurav K Singh
2014-12-04  5:28 ` [PATCH 01/10] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg Gaurav K Singh
2014-12-04  9:13   ` Jani Nikula
2014-12-04  5:28 ` [PATCH 02/10] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller Gaurav K Singh
2014-12-04  9:14   ` Jani Nikula
2014-12-04 11:22     ` Daniel Vetter
2014-12-05 12:50       ` Singh, Gaurav K
2014-12-05 14:38         ` Daniel Vetter
2014-12-05 20:35           ` Singh, Gaurav K
2014-12-04  5:28 ` [PATCH 03/10] drm/i915: Add support for port enable/disable for dual link configuration Gaurav K Singh
2014-12-04  9:17   ` Jani Nikula
2014-12-05  8:39     ` [PATCH v4 " Gaurav K Singh
2014-12-05 12:52       ` Jani Nikula
2014-12-04  5:28 ` [PATCH 04/10] drm/i915: Pixel Clock changes for DSI dual link Gaurav K Singh
2014-12-04  9:27   ` Jani Nikula
2014-12-05  8:43     ` [PATCH v3 " Gaurav K Singh
2014-12-05 16:33     ` [PATCH " Singh, Gaurav K
2014-12-05 16:54       ` Siluvery, Arun
2014-12-05 17:18         ` Singh, Gaurav K
2014-12-05 17:36         ` Jani Nikula
2014-12-05 17:48           ` Siluvery, Arun
2014-12-05 20:43             ` Singh, Gaurav K
2014-12-04  5:28 ` [PATCH 05/10] drm/i915: Dual link needs Shutdown and Turn on packet for both ports Gaurav K Singh
2014-12-04 10:41   ` Jani Nikula
2014-12-05 19:10     ` [PATCH 5/5] " Gaurav K Singh
2014-12-05 20:53       ` Daniel Vetter
2014-12-04  5:28 ` [PATCH 06/10] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link Gaurav K Singh
2014-12-04 11:17   ` Jani Nikula
2014-12-04  5:28 ` [PATCH 07/10] drm/i915: cck reg used for checking DSI Pll locked Gaurav K Singh
2014-12-04 11:22   ` Jani Nikula
2014-12-05  8:46     ` [PATCH v2 " Gaurav K Singh
2014-12-04  5:28 ` [PATCH 08/10] drm/i915: MIPI Timings related changes for dual link Gaurav K Singh
2014-12-04 11:24   ` Jani Nikula
2014-12-04  5:28 ` [PATCH 09/10] drm/i915: Update the DSI disable path to support dual link panel disabling Gaurav K Singh
2014-12-04 11:37   ` Jani Nikula
2014-12-05  8:52     ` [PATCH v4 " Gaurav K Singh
2014-12-04  5:28 ` [PATCH 10/10] drm/i915: Update the DSI enable path to support dual link panel enabling Gaurav K Singh
2014-12-04 11:49   ` Jani Nikula
2014-12-05  8:54     ` [PATCH v4 10/10] drm/i915: Update the DSI enable path to support dual Gaurav K Singh
2014-12-05 20:31       ` [PATCH " Gaurav K Singh
2014-12-05  4:04   ` [PATCH 10/10] drm/i915: Update the DSI enable path to support dual link panel enabling shuang.he

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