[U-Boot] [PATCH v4 0/15] x86: Add Intel Queensbay platform support

[U-Boot] [PATCH v4 0/15] x86: Add Intel Queensbay platform support

[Bin Meng]

This patch series add the Intel Queensbay platform support. The Queensbay
platform includes an Atom E6xx processor (codename Tunnel Creek) and a
Platform Controller Hub EG20T (codename Topcliff). The support depends
on Intel Firmware Support Package (FSP) to initialize the processor and
chipset including system memory. With this patch series, U-Boot boots to
Linux kernel. Validated on an Intel Crown Bay board with kernel 3.17.

Changes in v4:
- Rebase on u-boot-x86/master
- Drop some patches which are already applied
- Switch to use dtsi format microcode
- Use __packed for structure defines
- Fix some typos and print FSP full name in cmd_hob.c
- Minor update to README.x86 per review comments from Pavel Machek

Changes in v3:
- Update to use u-boot coding convention for fsp codes
- Use jnz to jump to the car_init error code at the end of tnc_car.S
  file instead of being in the normal path flow
- Add a TODO comment block to document the fsp_init() call
- Change label xxx_stack to xxx_romstack
- Add a comment block to explain the ROM stack
- Add a commit message for the SPI support

Changes in v2:
- Replace 0xcf9 with macro PORT_RESET from processor.h
- Move FspInit call from start.S to car_init
- Add UART0_BASE and UART1_BASE to ibmpc.h
- Add a comment to explain we don't need check bit0 in GPIO base
  address register
- Add setup_pch_gpios() in crownbay.c
- Fix several typos in queensbay/Kconfig
- Change FSP_FILE and CMC_FILE description to indicate the file is
  in the board directory
- Add help for FSP_TEMP_RAM_ADDR
- Add more help for CMC_FILE
- New patch to use consistent name XXX_ADDR for binary blobs
- Update ifdtool flags to indicate FSP and CMC files are in
  the board directory
- Use consistent XXX_FILE name for binary blob file
- Move PCH_LPC_DEV to arch/x86/include/asm/arch-queensbay/tnc.h
- Check return value of x86_cpu_init_f()
- Use ARRAY_SIZE(mmc_supported) instead of 2
- Check return value of add_sdhci()
- New patch to rename coreboot-serial to x86-serial
- Remove the 'make menuconfig' in the crownbay build instructions
- Indicate all the binary blobs should be put in the board directory
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines

Bin Meng (14):
  x86: Integrate Tunnel Creek processor microcode
  x86: Add basic support to queensbay platform and crownbay board
  x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
  x86: Enable the queensbay cpu directory build
  x86: Add queensbay and crownbay Kconfig files
  x86: Add crownbay defconfig and config.h
  x86: Use consistent name XXX_ADDR for binary blob flash address
  x86: Include FSP and CMC binary in the u-boot.rom build rules
  x86: crownbay: Add SPI flash support
  x86: crownbay: Enable Intel E1000 NIC support
  x86: crownbay: Add SDHCI support
  x86: Rename coreboot-serial to x86-serial
  x86: Add a README.x86 for U-Boot on x86 support
  x86: Clean up the FSP support codes

Simon Glass (1):
  x86: Convert microcode format to device-tree-only

 Makefile                                           |  16 +-
 arch/x86/Kconfig                                   |  13 +
 arch/x86/cpu/Makefile                              |   1 +
 arch/x86/cpu/ivybridge/sdram.c                     |   2 +-
 arch/x86/cpu/queensbay/Kconfig                     |  79 +++++
 arch/x86/cpu/queensbay/Makefile                    |   9 +
 arch/x86/cpu/queensbay/fsp_configs.c               |   2 +-
 arch/x86/cpu/queensbay/fsp_support.c               | 255 +++++++-------
 arch/x86/cpu/queensbay/tnc.c                       |  72 ++++
 arch/x86/cpu/queensbay/tnc_car.S                   | 124 +++++++
 arch/x86/cpu/queensbay/tnc_dram.c                  |  78 +++++
 arch/x86/cpu/queensbay/tnc_pci.c                   |  61 ++++
 arch/x86/cpu/queensbay/topcliff.c                  |  47 +++
 arch/x86/dts/coreboot.dtsi                         |   2 +-
 arch/x86/dts/crownbay.dts                          |   7 +
 arch/x86/dts/microcode/m0220661105_cv.dtsi         | 368 +++++++++++++++++++++
 arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h  |  18 +-
 arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h  |  28 +-
 arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h   |  14 +-
 arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h  | 112 ++++---
 .../asm/arch-queensbay/fsp/fsp_infoheader.h        |   6 +-
 .../include/asm/arch-queensbay/fsp/fsp_platform.h  |   8 +-
 .../include/asm/arch-queensbay/fsp/fsp_support.h   |  63 ++--
 .../x86/include/asm/arch-queensbay/fsp/fsp_types.h |  17 +-
 arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h  |   8 +-
 arch/x86/include/asm/arch-queensbay/gpio.h         |  13 +
 arch/x86/include/asm/arch-queensbay/tnc.h          |  15 +
 arch/x86/include/asm/gpio.h                        |   4 +-
 arch/x86/include/asm/ibmpc.h                       |   3 +
 arch/x86/lib/cmd_hob.c                             |  22 +-
 board/coreboot/coreboot/coreboot.c                 |   2 +-
 board/google/chromebook_link/link.c                |   2 +-
 board/intel/crownbay/Kconfig                       |  20 ++
 board/intel/crownbay/MAINTAINERS                   |   6 +
 board/intel/crownbay/Makefile                      |   7 +
 board/intel/crownbay/crownbay.c                    |  32 ++
 board/intel/crownbay/start.S                       |   9 +
 configs/crownbay_defconfig                         |   6 +
 doc/README.x86                                     | 126 +++++++
 drivers/gpio/intel_ich6_gpio.c                     |  20 +-
 drivers/serial/Makefile                            |   2 +-
 drivers/serial/{serial_coreboot.c => serial_x86.c} |  12 +-
 include/configs/chromebook_link.h                  |   6 +-
 include/configs/coreboot.h                         |   2 +-
 include/configs/crownbay.h                         |  61 ++++
 45 files changed, 1470 insertions(+), 310 deletions(-)
 create mode 100644 arch/x86/cpu/queensbay/Kconfig
 create mode 100644 arch/x86/cpu/queensbay/Makefile
 create mode 100644 arch/x86/cpu/queensbay/tnc.c
 create mode 100644 arch/x86/cpu/queensbay/tnc_car.S
 create mode 100644 arch/x86/cpu/queensbay/tnc_dram.c
 create mode 100644 arch/x86/cpu/queensbay/tnc_pci.c
 create mode 100644 arch/x86/cpu/queensbay/topcliff.c
 create mode 100644 arch/x86/dts/microcode/m0220661105_cv.dtsi
 create mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h
 create mode 100644 arch/x86/include/asm/arch-queensbay/tnc.h
 create mode 100644 board/intel/crownbay/Kconfig
 create mode 100644 board/intel/crownbay/MAINTAINERS
 create mode 100644 board/intel/crownbay/Makefile
 create mode 100644 board/intel/crownbay/crownbay.c
 create mode 100644 board/intel/crownbay/start.S
 create mode 100644 configs/crownbay_defconfig
 create mode 100644 doc/README.x86
 rename drivers/serial/{serial_coreboot.c => serial_x86.c} (67%)
 create mode 100644 include/configs/crownbay.h

-- 
1.8.2.1

[U-Boot] [PATCH v4 01/15] x86: Integrate Tunnel Creek processor microcode

[Bin Meng]

Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v4:
- Switch to use dtsi format microcode

Changes in v3: None
Changes in v2: None

 arch/x86/dts/microcode/m0220661105_cv.dtsi | 368 +++++++++++++++++++++++++++++
 1 file changed, 368 insertions(+)
 create mode 100644 arch/x86/dts/microcode/m0220661105_cv.dtsi

diff --git a/arch/x86/dts/microcode/m0220661105_cv.dtsi b/arch/x86/dts/microcode/m0220661105_cv.dtsi
new file mode 100644
index 0000000..ada8bfc
--- /dev/null
+++ b/arch/x86/dts/microcode/m0220661105_cv.dtsi
@@ -0,0 +1,368 @@
+/*
+ * Copyright (c) <1995-2014>, Intel Corporation.
+ * All rights reserved.
+ * Redistribution. Redistribution and use in binary form, without modification, are
+ * permitted provided that the following conditions are met:
+ *	.Redistributions must reproduce the above copyright notice and the following
+ * disclaimer in the documentation and/or other materials provided with the
+ * distribution.
+ *	.Neither the name of Intel Corporation nor the names of its suppliers may be used
+ * to endorse or promote products derived from this software without specific prior
+ * written permission.
+ *	.No reverse engineering, decompilation, or disassembly of this software is
+ * permitted.
+ *	."Binary form" includes any format commonly used for electronic conveyance
+ * which is a reversible, bit-exact translation of binary representation to ASCII or
+ * ISO text, for example, "uuencode."
+ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date: Sat Sep 13 22:51:38 CST 2014
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x105>;
+intel,date-code = <0x7182011>;
+intel,processor-signature = <0x20661>;
+intel,checksum = <0x52558795>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x2>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x05010000	0x11201807	0x61060200
+	0x95875552	0x01000000	0x02000000	0xd0130000
+	0x00140000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x05010000
+	0x19000000	0x00010500	0x15071120	0x01040000
+	0x01000000	0x61060200	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x9557a557	0x7d7a0fe3	0x8e2fbe53	0x0db9e346
+	0xd35c00d6	0x21bb34b7	0x662b6406	0xa0425035
+	0x3d028208	0xcb843695	0xee06be0a	0x9817efa7
+	0xb86c0d16	0x45f70c93	0x79fdc3af	0xd5f30da7
+	0x460f62b0	0x238a0470	0xf0ec95bf	0x97b9c176
+	0x6d612851	0x69b9b4b6	0x1df769cc	0xe11674df
+	0x1b579adf	0xc8bcc050	0xcdb3e285	0x327592c1
+	0xbeb6047a	0x977f6be5	0xc4854052	0x27f38b66
+	0x4ca5eab3	0xf806decc	0x2be4b409	0x460a3b03
+	0xde2f6e0f	0x53ce08b3	0x3ef0ef93	0x4e013088
+	0x226f8a5c	0x57f7d291	0x8d640bf7	0x8a998907
+	0x40464dd8	0x804ef3e5	0x647e35f3	0xeabee2d1
+	0x3a5ce9c7	0x4d7ee530	0x564321ec	0x9e85107e
+	0xd595581d	0xcbf6efde	0xed3010ed	0x3d607e82
+	0xe32d4b6b	0xd06fec83	0xf39240a6	0xe487988d
+	0xddbefcbe	0xefaf1121	0x96bf9acb	0xacce795c
+	0x7fa5f89b	0xbe440e5d	0xb6d3a3dc	0xcad17290
+	0x503ae748	0x04c80b8d	0xd394ea6a	0x3e4072c3
+	0x11000000	0x0b0ae65d	0xc6c53cbd	0xd52a6c2d
+	0x84cc192f	0x89498e7d	0x89270686	0xe68105e0
+	0x4073a570	0xd3338d8e	0x51193152	0x7266182f
+	0x980553fa	0x51b89c90	0xd13b6151	0xe6e40a91
+	0x0ab997d8	0x2d0a443b	0x9d3d566d	0x820402d1
+	0xdbe79fcc	0x7c5e0b45	0xaf94216d	0xbf717950
+	0x520b3dd4	0x566a3396	0x0b6f794f	0xc5dfeda5
+	0x71ba0f02	0x4839a5ed	0x39a4e4a6	0xe567c652
+	0x0e044997	0x84a0effd	0x09c67178	0x89a815c8
+	0xac821555	0xd6719303	0x582b964e	0xfe3a53f6
+	0x241b9b8b	0xc6e65457	0x623a4e0a	0x590d7d03
+	0xe50e7ce1	0x4bca4700	0xf24f5eff	0x1f1b20d9
+	0x77e3227e	0x699b5e5d	0x9aa5f621	0xff08bba0
+	0xf17ce716	0x0f5336f5	0xbce055a7	0x8cea9dac
+	0x8e09d26c	0x66c3ddf0	0xbec71660	0x75248cd2
+	0x29afcf8d	0xa5ade5ce	0xf68bace5	0x63b513cd
+	0x4736a842	0x4dbf80df	0x4e85fbdf	0x4dce3d56
+	0xf2150fdc	0xc4232709	0xffdc3e3a	0x92b72a3d
+	0x9ffce715	0x682959d1	0x091ba33c	0x0f1dc729
+	0x2f29a924	0x1df72429	0x19b0365d	0x2d5a3cd8
+	0x20617351	0x109074f9	0xf232874a	0x40d79569
+	0x97dbe4c6	0xa3b66845	0xa04d2faa	0x6dce9a96
+	0xd4963c67	0xd4516f76	0x64a0b04d	0x0b87ddfe
+	0xd8a5305d	0x717ecf67	0x77189035	0x40542ed4
+	0x5a180ff1	0xb2042e2c	0x6639819b	0x0f0756c3
+	0xf939bd70	0x25efe0d6	0x3eb65ae9	0x39a057d2
+	0xb2595655	0xf808b4fd	0xe22d0593	0x76256500
+	0x0eeee6ee	0x6895d1cf	0x9fc117a7	0xd19e5f15
+	0xf677f085	0x1ecdb30d	0x704d0975	0x9099f42e
+	0x421be0b2	0xd02548bd	0x3a16e675	0x7d8b051d
+	0x9d24480f	0xbc006432	0x184da9ec	0xbad7abef
+	0x299f58aa	0xc1a249fa	0x8d9d31f3	0xe73cda17
+	0xf41ac993	0x7b88d3bb	0xf349c676	0xb8341361
+	0x1b69bc01	0x98e0bfd2	0xf31db8d9	0xeb49b275
+	0xabc40133	0xfb7d0701	0xcd5ff353	0x4eaceb8d
+	0x67aac555	0x6d81693b	0xe81c555d	0x5d7f3688
+	0xd4347083	0xcd861b1d	0xd332f2cb	0x43130028
+	0x7f1a1c51	0xe2ce3af2	0xdff5076e	0x6ef21237
+	0xf65fc8c4	0xbd28ff14	0xd70f49a3	0x4f559249
+	0xd6fe7530	0x1fe89b4a	0xc1cc8975	0x2fd705c5
+	0xf2993d77	0x60f2e3da	0xe3ca3c44	0xbd0f70b1
+	0x0d333d10	0xa29a6aa1	0x43b5a6d4	0x30d15a08
+	0x6df9564a	0xea09045d	0x54ca3f5a	0xfbcfa037
+	0x6dd64d1b	0xa4a8995c	0x1f4298f0	0x3f4d9a86
+	0x924ee146	0xc2e3f464	0xc247747f	0x8bf5c7d7
+	0xf8f0b05d	0xf65a115f	0x4b1ae4e5	0xe131e187
+	0xfaf713c1	0x5ff88660	0xcd4916b0	0x448028e0
+	0x140711ca	0xffe77575	0x8b7740bd	0x82b6ed95
+	0xd94d9647	0x2623c011	0xd54fba11	0x30a7050b
+	0x28fe4069	0x70b8bf7d	0xf786eb6d	0xe39db734
+	0xa3290669	0x8747e1d6	0x35804a42	0x1c26ed60
+	0x30a8880f	0x8170a277	0xa1d97657	0x6ebcb3ed
+	0x3bb6ce89	0xff808c1b	0xc919fd1e	0x911d8b14
+	0xcbf41a24	0x82abc738	0xfb5e988e	0x328aa123
+	0xf19146e3	0x587baa80	0xd105e811	0x83b09389
+	0xa29fc554	0xe3831a28	0x183f8de7	0x4ef5656e
+	0xcc940baf	0x938bf4b4	0x90627bae	0x14fc3cdb
+	0x75e45681	0xf912c1b3	0x7a5b8a0f	0x3b970524
+	0x6a74d34a	0xb3da9fe6	0x847a3bd8	0xfc4f7dd6
+	0x88fd7f3b	0xbcd74a15	0x3afed836	0x17e31cd0
+	0x5d866dcb	0x0ab69608	0xe334f0fb	0x7181d4a3
+	0x8dc87560	0xd9c94d6f	0x491c2c91	0xca295ed6
+	0xfb8dcd79	0xeb4d3f89	0xec581071	0x0457ebc6
+	0x6b63590b	0x9dde4b79	0x3dc0a0aa	0x41ec8a1e
+	0xfb2ab80e	0x07adc629	0xb8534a4f	0xd0d23901
+	0xcfd024da	0x47c4163a	0xc89d26bb	0xe5cac48c
+	0x17c7fbba	0xd992f42e	0x466f5e35	0xce48304e
+	0x394683c8	0xef6e6b7a	0xb9d1242d	0xb961debd
+	0x432a3dff	0xa4931ea7	0xd9f03907	0xc29e9ce6
+	0x4fccf4c9	0xbf234555	0x0b6a6771	0xb29f29ef
+	0x7edc4bfd	0x781dcf74	0x4ae31020	0x1ab72d9b
+	0x0ac457e2	0xf9291e09	0xd4084918	0xa540d999
+	0x223408d3	0x0bd039aa	0xaf0dd904	0x9cfd6a01
+	0x826c6bca	0x8e41a96d	0xa56fc4ee	0x6a7509fb
+	0x5cd2e6fc	0xb89aa158	0xb1e5d3f5	0x92ccd05e
+	0x995d5acb	0x5ed1dc08	0x75038dac	0x4377c835
+	0x265d66d8	0x3692096f	0xcd69ee59	0x310df351
+	0x087e3133	0xe89e2d58	0x137fd054	0x00f3562b
+	0x2ae304e5	0x9db0316d	0x6868cec6	0xb249ccec
+	0x9f602c90	0xd3715e7c	0x3fcc8a62	0xa1c1e065
+	0x5b4281d4	0x124dfd7e	0xe9d21462	0x77cbc940
+	0xf915f2a5	0x66df82fc	0xa8c67c56	0xac4d461b
+	0x836deb52	0x95fbb48d	0x3454b6bd	0xd87d7a64
+	0xe64d32b8	0xc44c2aa0	0x3e213c1f	0x4d31b94d
+	0x4640be5e	0xe127234b	0x9ca54856	0xac7d093f
+	0x03d0508b	0x30f5121d	0x6e347d91	0x47772312
+	0x318ea26e	0xad3f6902	0xb5598746	0x8be3b65b
+	0xc8bbd31d	0x24691564	0xee77d2e8	0x3581944e
+	0xeff8eed5	0xa29ea86c	0xc2597492	0x23c1c118
+	0x7810c079	0xb966ee47	0x823e9954	0x9e558c0a
+	0x74759c12	0x193c6b4e	0x7544597d	0x65c9bf8a
+	0x68f5e263	0x718c679b	0xc8dc50ba	0x5f5ab841
+	0xc3eaf579	0xc2072358	0x62481939	0xffe7e686
+	0x201f3215	0x1d88dc8e	0x28fb4002	0x40c56ec5
+	0xb7bcce00	0xd52f5042	0x84498e04	0xcc97fb7d
+	0x64035e93	0xcd3478a4	0x15d63309	0xa9e47b85
+	0xe835e45f	0x9de598b7	0x94f569f7	0x56689b0c
+	0x381f9173	0x708b3e52	0xc81f0649	0x12113041
+	0x4694aae2	0x69040fc0	0xe4ba7bf4	0xfadc5729
+	0xc168381f	0x1985f118	0xab0ca720	0xf0150799
+	0x42690e4a	0x71af3be9	0x9325f3b8	0x36575996
+	0x4dc1dca7	0x7e534c37	0x01830a21	0x221eef4f
+	0x18698322	0x57a80837	0x483ae2d8	0xef905b54
+	0xe01827de	0xae9a8ff1	0x0058be7b	0x052632ad
+	0x9df5c90b	0xb763fc7a	0x5535c95c	0x8eb5916a
+	0x75fde5cc	0x57d8eeab	0x0dcc35c6	0xbf11c88f
+	0x69142118	0x4f35c928	0x7966066c	0xb2d13b4b
+	0xdad06d34	0xb5d8f5c7	0xe0bb11e6	0x8a36325d
+	0xc1122d64	0xcf07a1a5	0xfe7ce9b1	0x176b624b
+	0x4de883fd	0x00a9024b	0x3d3f7271	0x5072895d
+	0x2634e158	0x2f3c9a35	0x95e374d1	0x65e66528
+	0x47766433	0x4cb805ff	0xbc8f0319	0x6d5055a5
+	0x4932e8c2	0xa93fbb4d	0x87f08bd9	0xf5e5706e
+	0x409af40e	0x017edf5c	0xc5394c71	0x6fb97b6d
+	0x7b5ddb6b	0x0256adfe	0x76d337e2	0xa3327113
+	0xfbb4cb29	0xea68ca27	0xa76a865e	0x8cdb2dd3
+	0x902642bd	0x16772269	0xb2341eaf	0x858fa943
+	0xb087fac9	0xd17de85b	0x3d9c248a	0x0bdcf2d0
+	0x874fc03c	0xf19f2591	0x190c06a9	0xc6b5c3ea
+	0x472b6245	0xdb9f8201	0x46d27a0d	0x52218ffe
+	0xece78c44	0x3ef6e38a	0xfcf19b65	0x536c840c
+	0x86d363e8	0xaa852826	0xde17e3ec	0xa9c3b45b
+	0xd322302a	0x48f03728	0x2f60d01a	0x3b356752
+	0x8a869fd4	0x055d04f4	0x765074fb	0xb0b5c2d1
+	0x865ad360	0x0cb6c6e8	0x5de9cf99	0x863938d3
+	0xd4d9aeea	0x0babfa86	0x172cfb57	0x972d8f4f
+	0xe9aeeb95	0x6acbe297	0xf2459e42	0x415fdd12
+	0x84b2e67b	0x47d2d466	0x44bc85a4	0x1a55b957
+	0xe4d01142	0xbf4ea387	0x5651e1a2	0x19124703
+	0x8aaed1b2	0x841f3ecd	0xc6d6cc4f	0x1f2d8565
+	0xba08e74a	0x68e5ecf4	0x07af5ef4	0xdd5a43a9
+	0x6086c705	0x37ced045	0x0fb05ca6	0x35f39f3b
+	0xda1ecbef	0x1daf6d76	0x5481d7ed	0xc51e8385
+	0xa705e11e	0x127d2a7f	0x654d4710	0x1a34370e
+	0xf8496ea4	0x4392b6ec	0x2f209933	0x9c5ab017
+	0xa4f7b837	0x33e0a7d0	0x98fb0635	0xdefc042a
+	0xc7a1f6b5	0x47107766	0xd06acfba	0xb8ac2a93
+	0xe21cca44	0xf0150492	0xd4de2e01	0xe0d6e9a5
+	0xa758b5df	0x2e1c31c0	0xc4794495	0x3d9cc157
+	0xf94aa4f7	0xc2325855	0xcf9ddd12	0xaa70e611
+	0x2b2404b8	0x75d87f38	0xa2a6f772	0x61abfa04
+	0x23b61fb0	0x87f4067f	0x355abf99	0x2c4e6c48
+	0x2dc8a3b2	0x119b08b5	0x3f1f6d09	0x374372f0
+	0x24d79d32	0xef2b58be	0x461ab91c	0x1d31267e
+	0x8b1b2c7e	0x27a4f103	0x1686c7c3	0x55af0d87
+	0x61c2503b	0x9ffcca7f	0xc3cbdd07	0xd49a4f3c
+	0x9ddc2ac9	0x335e1b2a	0xd8dcfc08	0x6e83f11c
+	0x53de9e30	0x7b774670	0x15a97571	0x1ecacf66
+	0x26581520	0xeee3496b	0x1fdf8174	0x4ddd3c61
+	0xaa504fc2	0x0b09792e	0x9b81d1c7	0x10765c95
+	0xd3e7b9d1	0xefdb38f9	0x4c44d38e	0xaaf8fd08
+	0xceb22e7c	0x5ac74242	0x6baee02d	0x5c7eaa5b
+	0x27265dca	0x614c3b5e	0x2994874d	0x486d48a3
+	0x5945c4f9	0xe465f343	0x934e55de	0x633199a2
+	0x147222cc	0x9bbb0c16	0x6a7e7ef1	0xb7bce9b5
+	0x13413d18	0x628231af	0x0fd2d58c	0x4cbafba0
+	0xa930fae6	0x91733823	0xe06f99c3	0xda3b57b7
+	0x04b8a9dd	0x53451e33	0x11fde5fd	0x0e35bcb8
+	0x3a5799d4	0x3893f9c0	0x6b9d0e1d	0xf8d948ce
+	0xa33a6628	0x7d09792d	0xd74b3719	0x0afb4de0
+	0xfaa5a685	0xecf7f8ac	0xcf34b855	0x89453b4d
+	0x12f028c3	0x45edc3fd	0x792c43fc	0x2b054962
+	0xb8799a92	0x0ab38d61	0xa6c6a76d	0x7670cdbd
+	0xf878b511	0x9a3474ba	0x478673f0	0x7398bba8
+	0x4fa10ff5	0xf0a1931c	0xd5938e03	0xe9a23c28
+	0x7bea2a5b	0xf7a8db22	0xb94ae0e3	0x2abe6385
+	0x0ef2cc36	0x6b997544	0x1e8cc4f1	0x69a5b182
+	0x54f9b7c7	0x8fe56cba	0xc7c12fcc	0x8d689865
+	0x2d6ef011	0xc6a1b740	0x66af0a76	0x76018cdd
+	0x30661377	0xcf1fcf93	0x08046423	0xdf9371c8
+	0x1795ec3e	0xf5ea09c6	0xe462de69	0xd7da78a1
+	0xd8bda1eb	0x1179f53a	0x2b394767	0x3ba153a7
+	0xf9c85bd7	0x5700c827	0x8478ac99	0x080a2f52
+	0xdd1c18f1	0x579cea67	0x345c56ce	0x4563f16a
+	0xfa1a5b74	0x0b6e233e	0xadc7bd9a	0xbee6d2f0
+	0xa249f3ef	0xcdea9b77	0xeaaed82e	0xcc4448a7
+	0x34f7cafb	0x7621bb44	0x4965b0eb	0xe6d6b8bf
+	0x3c683b25	0x33bcb5fe	0x3f376249	0x5b40dc67
+	0x658bf6aa	0x7f0c5d0d	0x61514591	0xeb3bb83f
+	0xc2e208dd	0xe82f08f2	0x6ef75ae5	0x9c11bc0d
+	0x289c0553	0x1578ce5d	0xb7f05c0e	0x818c5ebd
+	0xe566ec9b	0xc6995b3f	0x0c02aac3	0x2b4264b3
+	0xf9cad304	0x5b0479fb	0xf8ce8d6f	0xb7d80d8b
+	0x41a0d223	0x71ec8a7a	0xc9d74d41	0x245c5988
+	0xf607fc59	0xf1c7b6ab	0x142ef712	0xbf607800
+	0x281e5911	0xad9a3e63	0x87b59384	0x7ebdc04c
+	0x6f47867b	0xb6a304ac	0x289f65e7	0x335fc866
+	0x77eb11b3	0xb70c25b2	0x70b43d52	0x684d46c0
+	0x0940459b	0xde739ede	0x0b438a29	0xb713e77e
+	0x71f539b7	0x8b2f0f7b	0x8d8ab95d	0x42cde8c9
+	0x08c259d1	0x021eda69	0x2af81ddc	0xc7d13028
+	0x05abfa20	0x6a61008b	0xfc62557f	0xd6d731b2
+	0xb080aca3	0x6acae4a3	0xab33d2bc	0x7983c177
+	0xdf0c357d	0xb8dcb956	0x9c214460	0xfeb75d75
+	0x9b3d468b	0xd2c3106c	0xb1bd118e	0xf26df6a8
+	0x11b9c4d2	0x031357f9	0xf7af8a12	0x70fef26c
+	0xe5d8b8d5	0xf6746fd8	0xd6cc3266	0x4158e59f
+	0xa38fbfcb	0x01c61ff6	0x44c7c4e6	0xf26db3aa
+	0x46bb6d84	0x0a794535	0x1d5eab72	0x42345de7
+	0x0c7e6d47	0x8bacc223	0xb7334b8d	0x3d9d951b
+	0x18f4afc4	0x9c0cb708	0x53b71b82	0x603e8350
+	0x6f2df978	0x0c6f3f0f	0x661ebca9	0x30788bd0
+	0x982959c0	0x50aa1351	0x672297c1	0xa490a756
+	0x21c9e911	0x977e172e	0x0446db50	0x49b711c1
+	0xbc6d54c7	0x0fe0adb4	0xc4ec0fe4	0xae6d09b6
+	0x316cfa53	0xba68cc8b	0x104bdbe9	0xc31639a3
+	0x812a97fb	0xa1c6884b	0xc884d473	0xe3057c15
+	0x5ee879a3	0x5abe8262	0xb906bbde	0xfd98fcbd
+	0x6ae15c96	0x44a17e0e	0x28acfa15	0xb345122c
+	0x6ddc4244	0x005eb369	0x22d038bc	0x0d226e4f
+	0x64c7ed6c	0x7964b8d9	0xbc5d668d	0x99155e56
+	0x9979151c	0x65312a00	0x0271d338	0x64867293
+	0xed0d26fb	0xe69c5f02	0x93fd6871	0xf5702656
+	0x4fad1c2b	0x20f8c272	0x438b964a	0x87ff3fa2
+	0x6706537a	0x437b5709	0x6fb797dd	0x85679fab
+	0x00da6b51	0xeecc5540	0x2998791c	0xc36d40ef
+	0xb545e334	0x9ace5e06	0x8a9e6c54	0xc341d0cd
+	0x1478a2d4	0xb81413bd	0x80601f72	0xa1b250b9
+	0x1cb7f5ce	0xefad630c	0x32325fcc	0x29e3474d
+	0x6a7ae043	0x879ee630	0xdc1e8a55	0x7ae794a8
+	0x4ee38039	0x2ff4947a	0x53bb84b1	0x8f0b077d
+	0xaa4c543b	0x9aa88443	0xeb31a017	0xf3485983
+	0xe53b855c	0x6e17aec6	0x726458a6	0x5acf4345
+	0xa1b95c5a	0x30668c67	0x47fb5dc7	0x8aafbff4
+	0x4b94ef01	0x07bd6231	0x544afcf3	0xfdffca2f
+	0xce847471	0xe90abc6e	0xf05e3cc1	0xf602a9c8
+	0x8f104b51	0x1ae3da07	0xd07dfc04	0x561d9373
+	0x6f6cc833	0xac982489	0x3c0f8afd	0xfab974d0
+	0x397e135e	0x8edb3eb4	0x452b9509	0x3972829d
+	0x639e3981	0x1c758ec1	0x11428fa5	0xe8308fa7
+	0x571d71b9	0x94e40c2b	0x1aaaa397	0xce9283ae
+	0x599bbb93	0x51c04bf7	0x556bc74f	0xf6e6e799
+	0xc34191e0	0x5f06bce6	0x9f63ecd1	0x54437905
+	0xf8f9bd50	0xde82cbf6	0xe11a9949	0x9d312bfa
+	0xe712e3db	0xb57eabc9	0x57682068	0xc91c2e3c
+	0x681e4fbd	0x0ecd3452	0xcc893248	0xf13f0600
+	0x9a8a9194	0xb4c1cd29	0xd504d8f2	0xee6c5b8a
+	0x211c9958	0x7a4f9c30	0x32775708	0xda97bf03
+	0xf7035e57	0xbe77d547	0x37accd1e	0x6c537775
+	0x8d63b752	0x7fec4a3c	0x94211d9e	0x60bfeb2a
+	0xebd47130	0x747d52fc	0x8434f487	0xac9091cc
+	0x8f8b228f	0xb77f96a1	0xc21fede9	0xa9e2678a
+	0xbc815194	0x54d677ac	0x66c11faf	0xfb666595
+	0x01e5e973	0x5c990d0c	0xf2cea425	0x5b516ff8
+	0x8c932784	0xd18feb32	0xb5acd3d3	0x1703b89a
+	0x34fb512c	0x0ac83386	0xd58c5728	0x5c018ed6
+	0xbe0908a0	0xd490b0e9	0x0ec94527	0x2f281499
+	0x471df723	0x03eddc08	0x9b99d975	0x11535b70
+	0x5802288c	0xb3512d42	0x415a9c0d	0x52dbd146
+	0x8b0c59bf	0xd8160cc7	0xe37dee6e	0xfd5211cc
+	0x5635ff4d	0x8d783398	0xc11f5d62	0x54ca73b4
+	0xc3ebdf96	0x835e7883	0x9cd03137	0xe4b4f709
+	0xdbde6d86	0x2b562b2d	0xfecc0df5	0x172a5ec2
+	0x568b52b9	0xf542957c	0xd738b325	0x49c49aaf
+	0x6eb4c9ad	0x363f4978	0xac4b0cb3	0x4ec8dca8
+	0x7a2ec2ba	0x10ff39bc	0x8b8748d5	0x6a86e67b
+	0x0d81e2b6	0xf4bde138	0x02249333	0xab0c7acf
+	0x4ce5e894	0x1656dad7	0x46c59329	0xa849fea0
+	0x3d0400be	0x6898c4f7	0xd866ff9a	0x84a5b170
+	0xc997009e	0x80524f6e	0xc80fb5dd	0x5bde0181
+	0x0bb0c8a8	0xe5a6b9e4	0xd4753f0a	0xda9bf0c6
+	0xd6dd041b	0x4c7338f0	0xa223bd71	0x23b58f4a
+	0xf6e127dc	0x1777033d	0x5b057a0f	0xe08af0bf
+	0x17c07032	0xbbc3f27f	0xac6dc98b	0x921e2f12
+	0xcf32236d	0x6cb700a8	0xa3b4e5cc	0xe9b65d73
+	0xca7d6f44	0x7b5917f6	0x7b80dd21	0x5ee87e45
+	0x86799f71	0x0667e036	0x8f97dcca	0xc4bfd5d9
+	0x90737eed	0x41b5a457	0xc6c96301	0xf8933e95
+	0xe51c2456	0x00c661f4	0x8a0e1aaa	0x92aa4181
+	0x1e3f8638	0xd481a14a	0xaf637189	0x91622fb3
+	0x4450865d	0x4202b431	0x5248342b	0x01ff713b
+	0xe33b5ec5	0x912d6856	0x10deb2ac	0x9072c180
+	0x24d792af	0xa39c5dfd	0xb4c94140	0xfeb32004
+	0xa174dae8	0x49da7dfc	0xa4db1090	0x7d2a998b
+	0xb7eba69b	0x9b824871	0x3557bd1d	0xd3a73d9b
+	0xf225310b	0xad1ffcf6	0x2d5f075b	0x592de6f4
+	0x69e438f4	0x4ed8cac4	0xa79c947f	0xb95f9590
+	0xb8ede5c9	0x0b1c9229	0x85a4b30e	0x65149920
+	0x433461a8	0x186fda4f	0xbaee7097	0xd3cac1bd
+	0x8bc32ca2	0x914f1512	0x9b619478	0x582a53c9
+	0x4e624a00	0x77e445ec	0x6f823159	0xa9c4766b
+	0x0dd6ad28	0xfabdadc5	0x704bfd95	0x08645056
+	0xe1939821	0x76650b62	0x8876941a	0xf812239f
+	0x2869ce13	0xa4d292c7	0xecba40fd	0x83d2fd8f
+	0xdd45ccc0	0x7c12b7cb	0xdc0a20bb	0x0d9be34d
+	0x4dd16a9d	0x25835446	0xb94d8c21	0x97ca8010
+	0xddd09324	0x95ffe31f	0xa86136c9	0x828ac571
+	0x9aa7fc00	0x382cc48c	0x015f7186	0xc3fd040d
+	0x505408e0	0x21cdc34c	0xbd266059	0x6e2f673e
+	0xe4523c1b	0x3ba56bb3	0x1c343938	0xabc0df54
+	0x8ba4f1e8	0xfbd4c592	0xb678c884	0xff3be2f1
+	0xca013570	0xfb0598df	0x3cb9cc1d	0xe3ba8ca3
+	0xc3d7ecee	0x0ae84a0b	0x0d70f0c3	0x963110ff
+	>;
-- 
1.8.2.1

[U-Boot] [PATCH v4 02/15] x86: Add basic support to queensbay platform and crownbay board

[Bin Meng]

Implement minimum required functions for the basic support to
queensbay platform and crownbay board.

Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v4: None
Changes in v3:
- Update to use u-boot coding convention for fsp codes
- Use jnz to jump to the car_init error code at the end of tnc_car.S
  file instead of being in the normal path flow
- Add a TODO comment block to document the fsp_init() call
- Change label xxx_stack to xxx_romstack
- Add a comment block to explain the ROM stack

Changes in v2:
- Replace 0xcf9 with macro PORT_RESET from processor.h
- Move FspInit call from start.S to car_init
- Add UART0_BASE and UART1_BASE to ibmpc.h

 arch/x86/cpu/queensbay/Makefile   |   9 +++
 arch/x86/cpu/queensbay/tnc.c      |  48 ++++++++++++++
 arch/x86/cpu/queensbay/tnc_car.S  | 127 ++++++++++++++++++++++++++++++++++++++
 arch/x86/cpu/queensbay/tnc_dram.c |  78 +++++++++++++++++++++++
 arch/x86/cpu/queensbay/tnc_pci.c  |  61 ++++++++++++++++++
 arch/x86/include/asm/ibmpc.h      |   3 +
 board/intel/crownbay/MAINTAINERS  |   6 ++
 board/intel/crownbay/Makefile     |   7 +++
 board/intel/crownbay/crownbay.c   |  21 +++++++
 board/intel/crownbay/start.S      |   9 +++
 10 files changed, 369 insertions(+)
 create mode 100644 arch/x86/cpu/queensbay/Makefile
 create mode 100644 arch/x86/cpu/queensbay/tnc.c
 create mode 100644 arch/x86/cpu/queensbay/tnc_car.S
 create mode 100644 arch/x86/cpu/queensbay/tnc_dram.c
 create mode 100644 arch/x86/cpu/queensbay/tnc_pci.c
 create mode 100644 board/intel/crownbay/MAINTAINERS
 create mode 100644 board/intel/crownbay/Makefile
 create mode 100644 board/intel/crownbay/crownbay.c
 create mode 100644 board/intel/crownbay/start.S

diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
new file mode 100644
index 0000000..ace04ca
--- /dev/null
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += tnc_car.o tnc_dram.o tnc.o
+obj-y += fsp_configs.o fsp_support.o
+obj-$(CONFIG_PCI) += tnc_pci.o
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
new file mode 100644
index 0000000..8b9815f
--- /dev/null
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/post.h>
+#include <asm/arch/fsp/fsp_support.h>
+#include <asm/processor.h>
+
+int arch_cpu_init(void)
+{
+	post_code(POST_CPU_INIT);
+#ifdef CONFIG_SYS_X86_TSC_TIMER
+	timer_set_base(rdtsc());
+#endif
+
+	return x86_cpu_init_f();
+}
+
+int print_cpuinfo(void)
+{
+	post_code(POST_CPU_INFO);
+	return default_print_cpuinfo();
+}
+
+void reset_cpu(ulong addr)
+{
+	/* cold reset */
+	outb(0x06, PORT_RESET);
+}
+
+void board_final_cleanup(void)
+{
+	u32 status;
+
+	/* call into FspNotify */
+	debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
+	status = fsp_notify(NULL, INIT_PHASE_BOOT);
+	if (status != FSP_SUCCESS)
+		debug("fail, error code %x\n", status);
+	else
+		debug("OK\n");
+
+	return;
+}
diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S
new file mode 100644
index 0000000..6834a64
--- /dev/null
+++ b/arch/x86/cpu/queensbay/tnc_car.S
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/post.h>
+
+.globl car_init
+car_init:
+	/*
+	 * Note: ebp holds the BIST value (built-in self test) so far, but ebp
+	 * will be destroyed through the FSP call, thus we have to test the
+	 * BIST value here before we call into FSP.
+	 */
+	test	%ebp, %ebp
+	jz	car_init_start
+	post_code(POST_BIST_FAILURE)
+	jmp	die
+
+car_init_start:
+	post_code(POST_CAR_START)
+	lea	find_fsp_header_romstack, %esp
+	jmp	find_fsp_header
+
+find_fsp_header_ret:
+	/* EAX points to FSP_INFO_HEADER */
+	mov	%eax, %ebp
+
+	/* sanity test */
+	cmp	$CONFIG_FSP_LOCATION, %eax
+	jb	die
+
+	/* calculate TempRamInitEntry address */
+	mov	0x30(%ebp), %eax
+	add	0x1c(%ebp), %eax
+
+	/* call FSP TempRamInitEntry to setup temporary stack */
+	lea	temp_ram_init_romstack, %esp
+	jmp	*%eax
+
+temp_ram_init_ret:
+	addl	$4, %esp
+	cmp	$0, %eax
+	jnz	car_init_fail
+
+	post_code(POST_CAR_CPU_CACHE)
+
+	/*
+	 * The FSP TempRamInit initializes the ecx and edx registers to
+	 * point to a temporary but writable memory range (Cache-As-RAM).
+	 * ecx: the start of this temporary memory range,
+	 * edx: the end of this range.
+	 */
+
+	/* stack grows down from top of CAR */
+	movl	%edx, %esp
+
+	/*
+	 * TODO:
+	 *
+	 * According to FSP architecture spec, the fsp_init() will not return
+	 * to its caller, instead it requires the bootloader to provide a
+	 * so-called continuation function to pass into the FSP as a parameter
+	 * of fsp_init, and fsp_init() will call that continuation function
+	 * directly.
+	 *
+	 * The call to fsp_init() may need to be moved out of the car_init()
+	 * to cpu_init_f() with the help of some inline assembly codes.
+	 * Note there is another issue that fsp_init() will setup another stack
+	 * using the fsp_init parameter stack_top after DRAM is initialized,
+	 * which means any data on the previous stack (on the CAR) gets lost
+	 * (ie: U-Boot global_data). FSP is supposed to support such scenario,
+	 * however it does not work. This should be revisited in the future.
+	 */
+	movl	$CONFIG_FSP_TEMP_RAM_ADDR, %eax
+	xorl	%edx, %edx
+	xorl	%ecx, %ecx
+	call	fsp_init
+
+.global fsp_init_done
+fsp_init_done:
+	/*
+	 * We come here from FspInit with eax pointing to the HOB list.
+	 * Save eax to esi temporarily.
+	 */
+	movl	%eax, %esi
+	/*
+	 * Re-initialize the ebp (BIST) to zero, as we already reach here
+	 * which means we passed BIST testing before.
+	 */
+	xorl	%ebp, %ebp
+	jmp	car_init_ret
+
+car_init_fail:
+	post_code(POST_CAR_FAILURE)
+
+die:
+	hlt
+	jmp	die
+	hlt
+
+	/*
+	 * The function call before CAR initialization is tricky. It cannot
+	 * be called using the 'call' instruction but only the 'jmp' with
+	 * the help of a handcrafted stack in the ROM. The stack needs to
+	 * contain the function return address as well as the parameters.
+	 */
+	.balign	4
+find_fsp_header_romstack:
+	.long	find_fsp_header_ret
+
+	.balign	4
+temp_ram_init_romstack:
+	.long	temp_ram_init_ret
+	.long	temp_ram_init_params
+temp_ram_init_params:
+	.long	ucode_start		/* microcode base */
+	.long	ucode_size		/* microcode size */
+	.long	CONFIG_SYS_MONITOR_BASE	/* code region base */
+	.long	CONFIG_SYS_MONITOR_LEN	/* code region size */
+
+	.balign	4
+ucode_start:
+	.include "arch/x86/cpu/queensbay/M0220661105.inc"
+ucode_size = ( . - ucode_start)
diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/cpu/queensbay/tnc_dram.c
new file mode 100644
index 0000000..dbc1710
--- /dev/null
+++ b/arch/x86/cpu/queensbay/tnc_dram.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsp/fsp_support.h>
+#include <asm/e820.h>
+#include <asm/post.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	phys_size_t ram_size = 0;
+	union hob_pointers_t hob;
+
+	hob.raw = gd->arch.hob_list;
+	while (!END_OF_HOB(hob)) {
+		if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+			if (hob.res_desc->type == RES_SYS_MEM ||
+			    hob.res_desc->type == RES_MEM_RESERVED) {
+				ram_size += hob.res_desc->len;
+			}
+		}
+		hob.raw = GET_NEXT_HOB(hob);
+	}
+
+	gd->ram_size = ram_size;
+	post_code(POST_DRAM);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = 0;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+/*
+ * This function looks for the highest region of memory lower than 4GB which
+ * has enough space for U-Boot where U-Boot is aligned on a page boundary.
+ * It overrides the default implementation found elsewhere which simply
+ * picks the end of ram, wherever that may be. The location of the stack,
+ * the relocation address, and how far U-Boot is moved by relocation are
+ * set in the global data structure.
+ */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	return get_usable_lowmem_top(gd->arch.hob_list);
+}
+
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+	unsigned num_entries = 0;
+
+	union hob_pointers_t hob;
+
+	hob.raw = gd->arch.hob_list;
+
+	while (!END_OF_HOB(hob)) {
+		if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+			entries[num_entries].addr = hob.res_desc->phys_start;
+			entries[num_entries].size = hob.res_desc->len;
+
+			if (hob.res_desc->type == RES_SYS_MEM)
+				entries[num_entries].type = E820_RAM;
+			else if (hob.res_desc->type == RES_MEM_RESERVED)
+				entries[num_entries].type = E820_RESERVED;
+		}
+		hob.raw = GET_NEXT_HOB(hob);
+		num_entries++;
+	}
+
+	return num_entries;
+}
diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c
new file mode 100644
index 0000000..39bff49
--- /dev/null
+++ b/arch/x86/cpu/queensbay/tnc_pci.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/arch/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_pci_setup_hose(struct pci_controller *hose)
+{
+	hose->first_busno = 0;
+	hose->last_busno = 0;
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 0,
+		       CONFIG_PCI_MEM_BUS,
+		       CONFIG_PCI_MEM_PHYS,
+		       CONFIG_PCI_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 1,
+		       CONFIG_PCI_IO_BUS,
+		       CONFIG_PCI_IO_PHYS,
+		       CONFIG_PCI_IO_SIZE,
+		       PCI_REGION_IO);
+
+	pci_set_region(hose->regions + 2,
+		       CONFIG_PCI_PREF_BUS,
+		       CONFIG_PCI_PREF_PHYS,
+		       CONFIG_PCI_PREF_SIZE,
+		       PCI_REGION_PREFETCH);
+
+	pci_set_region(hose->regions + 3,
+		       0,
+		       0,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	hose->region_count = 4;
+}
+
+int board_pci_post_scan(struct pci_controller *hose)
+{
+	u32 status;
+
+	/* call into FspNotify */
+	debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
+	status = fsp_notify(NULL, INIT_PHASE_PCI);
+	if (status != FSP_SUCCESS)
+		debug("fail, error code %x\n", status);
+	else
+		debug("OK\n");
+
+	return 0;
+}
diff --git a/arch/x86/include/asm/ibmpc.h b/arch/x86/include/asm/ibmpc.h
index e6d183b..c3b5187 100644
--- a/arch/x86/include/asm/ibmpc.h
+++ b/arch/x86/include/asm/ibmpc.h
@@ -18,4 +18,7 @@
 #define SYSCTLA         0x92
 #define SLAVE_PIC       0xa0
 
+#define UART0_BASE	0x3f8
+#define UART1_BASE	0x2f8
+
 #endif
diff --git a/board/intel/crownbay/MAINTAINERS b/board/intel/crownbay/MAINTAINERS
new file mode 100644
index 0000000..1eb6869
--- /dev/null
+++ b/board/intel/crownbay/MAINTAINERS
@@ -0,0 +1,6 @@
+INTEL CROWNBAY BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/intel/crownbay/
+F:	include/configs/crownbay.h
+F:	configs/crownbay_defconfig
diff --git a/board/intel/crownbay/Makefile b/board/intel/crownbay/Makefile
new file mode 100644
index 0000000..aeb219b
--- /dev/null
+++ b/board/intel/crownbay/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= crownbay.o start.o
diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
new file mode 100644
index 0000000..8c6df98
--- /dev/null
+++ b/board/intel/crownbay/crownbay.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ibmpc.h>
+#include <asm/pnp_def.h>
+#include <smsc_lpc47m.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, 4)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
+
+	return 0;
+}
diff --git a/board/intel/crownbay/start.S b/board/intel/crownbay/start.S
new file mode 100644
index 0000000..cf92b4c
--- /dev/null
+++ b/board/intel/crownbay/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+	jmp	early_board_init_ret
-- 
1.8.2.1

[U-Boot] [PATCH v4 03/15] x86: Convert microcode format to device-tree-only

[Bin Meng]

From: Simon Glass <sjg@chromium.org>

To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.

Signed-off-by: Simon Glass <sjg@chromium.org>

---

Changes in v4:
- Squash the microcode.dtsi to patch#1 in the v4 series

Changes in v3: None
Changes in v2: None

 Makefile                         |  4 +++-
 arch/x86/cpu/queensbay/tnc_car.S | 11 ++++-------
 arch/x86/dts/crownbay.dts        |  7 +++++++
 3 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/Makefile b/Makefile
index fd24cde..d4e60e8 100644
--- a/Makefile
+++ b/Makefile
@@ -947,7 +947,9 @@ ifneq ($(CONFIG_X86_RESET_VECTOR),)
 rom: u-boot.rom FORCE
 
 IFDTOOL=$(objtree)/tools/ifdtool
-IFDTOOL_FLAGS  = -w $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin
+IFDTOOL_FLAGS  = -f 0:$(objtree)/u-boot.dtb
+IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1)
+IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot.bin
 IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
 
 ifneq ($(CONFIG_HAVE_INTEL_ME),)
diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S
index 6834a64..2e9139e 100644
--- a/arch/x86/cpu/queensbay/tnc_car.S
+++ b/arch/x86/cpu/queensbay/tnc_car.S
@@ -116,12 +116,9 @@ temp_ram_init_romstack:
 	.long	temp_ram_init_ret
 	.long	temp_ram_init_params
 temp_ram_init_params:
-	.long	ucode_start		/* microcode base */
-	.long	ucode_size		/* microcode size */
+_dt_ucode_base_size:
+	/* These next two fields are filled in by ifdtool */
+	.long	0			/* microcode base */
+	.long	0			/* microcode size */
 	.long	CONFIG_SYS_MONITOR_BASE	/* code region base */
 	.long	CONFIG_SYS_MONITOR_LEN	/* code region size */
-
-	.balign	4
-ucode_start:
-	.include "arch/x86/cpu/queensbay/M0220661105.inc"
-ucode_size = ( . - ucode_start)
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 399dafb..3f43f3c 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -50,4 +50,11 @@
 			memory-map = <0xffe00000 0x00200000>;
 		};
 	};
+
+	microcode {
+		update at 0 {
+#include "microcode/m0220661105_cv.dtsi"
+		};
+	};
+
 };
-- 
1.8.2.1

[U-Boot] [PATCH v4 04/15] x86: ich6-gpio: Add Intel Tunnel Creek GPIO support

[Bin Meng]

Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Add a comment to explain we don't need check bit0 in GPIO base
  address register
- Add setup_pch_gpios() in crownbay.c

 arch/x86/include/asm/arch-queensbay/gpio.h | 13 +++++++++++++
 arch/x86/include/asm/gpio.h                |  4 ++--
 board/coreboot/coreboot/coreboot.c         |  2 +-
 board/google/chromebook_link/link.c        |  2 +-
 board/intel/crownbay/crownbay.c            |  5 +++++
 drivers/gpio/intel_ich6_gpio.c             | 20 ++++++++++++--------
 6 files changed, 34 insertions(+), 12 deletions(-)
 create mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h

diff --git a/arch/x86/include/asm/arch-queensbay/gpio.h b/arch/x86/include/asm/arch-queensbay/gpio.h
new file mode 100644
index 0000000..ab4e059
--- /dev/null
+++ b/arch/x86/include/asm/arch-queensbay/gpio.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x44
+
+#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1787e52..1099427 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -11,7 +11,7 @@
 #include <asm-generic/gpio.h>
 
 struct ich6_bank_platdata {
-	uint32_t base_addr;
+	uint16_t base_addr;
 	const char *bank_name;
 };
 
@@ -147,7 +147,7 @@ struct pch_gpio_map {
 	} set3;
 };
 
-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio);
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
 
 #endif /* _X86_GPIO_H_ */
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
index b260f9a..154faf6 100644
--- a/board/coreboot/coreboot/coreboot.c
+++ b/board/coreboot/coreboot/coreboot.c
@@ -16,7 +16,7 @@ int arch_early_init_r(void)
 	return 0;
 }
 
-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
 {
 	return;
 }
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 4d95c1c..9978e92 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -125,7 +125,7 @@ int board_early_init_f(void)
 	return 0;
 }
 
-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
 {
 	/* GPIO Set 1 */
 	if (gpio->set1.level)
diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
index 8c6df98..54670d3 100644
--- a/board/intel/crownbay/crownbay.c
+++ b/board/intel/crownbay/crownbay.c
@@ -19,3 +19,8 @@ int board_early_init_f(void)
 
 	return 0;
 }
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+	return;
+}
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 3433216..7720cc3 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -39,9 +39,9 @@
 
 struct ich6_bank_priv {
 	/* These are I/O addresses */
-	uint32_t use_sel;
-	uint32_t io_sel;
-	uint32_t lvl;
+	uint16_t use_sel;
+	uint16_t io_sel;
+	uint16_t lvl;
 };
 
 /* TODO: Move this to device tree, or platform data */
@@ -57,7 +57,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
 	u8 tmpbyte;
 	u16 tmpword;
 	u32 tmplong;
-	u32 gpiobase;
+	u16 gpiobase;
 	int offset;
 
 	/* Where should it be? */
@@ -116,11 +116,15 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
 	/*
 	 * GPIOBASE moved to its current offset with ICH6, but prior to
 	 * that it was unused (or undocumented). Check that it looks
-	 * okay: not all ones or zeros, and mapped to I/O space (bit 0).
+	 * okay: not all ones or zeros.
+	 *
+	 * Note we don't need check bit0 here, because the Tunnel Creek
+	 * GPIO base address register bit0 is reserved (read returns 0),
+	 * while on the Ivybridge the bit0 is used to indicate it is an
+	 * I/O space.
 	 */
 	tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
-	if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
-	    !(tmplong & 0x00000001)) {
+	if (tmplong == 0x00000000 || tmplong == 0xffffffff) {
 		debug("%s: unexpected GPIOBASE value\n", __func__);
 		return -ENODEV;
 	}
@@ -131,7 +135,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
 	 * at the offset that we just read. Bit 0 indicates that it's
 	 * an I/O address, not a memory address, so mask that off.
 	 */
-	gpiobase = tmplong & 0xfffffffe;
+	gpiobase = tmplong & 0xfffe;
 	offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
 	if (offset == -1) {
 		debug("%s: Invalid register offset %d\n", __func__, offset);
-- 
1.8.2.1

[U-Boot] [PATCH v4 05/15] x86: Enable the queensbay cpu directory build

[Bin Meng]

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/x86/cpu/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 7f09db5..5033d2b 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -15,6 +15,7 @@ obj-y	+= interrupts.o cpu.o call64.o
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
 obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
 obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
+obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
 obj-y += lapic.o
 obj-$(CONFIG_PCI) += pci.o
 obj-y += turbo.o
-- 
1.8.2.1

[U-Boot] [PATCH v4 06/15] x86: Add queensbay and crownbay Kconfig files

[Bin Meng]

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix several typos in queensbay/Kconfig
- Change FSP_FILE and CMC_FILE description to indicate the file is
  in the board directory
- Add help for FSP_TEMP_RAM_ADDR
- Add more help for CMC_FILE

 arch/x86/Kconfig               | 13 +++++++
 arch/x86/cpu/queensbay/Kconfig | 79 ++++++++++++++++++++++++++++++++++++++++++
 board/intel/crownbay/Kconfig   | 20 +++++++++++
 3 files changed, 112 insertions(+)
 create mode 100644 arch/x86/cpu/queensbay/Kconfig
 create mode 100644 board/intel/crownbay/Kconfig

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index fdfb618..ebf72b3 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -32,6 +32,15 @@ config TARGET_CHROMEBOOK_LINK
 	  and it provides a 2560x1700 high resolution touch-enabled LCD
 	  display.
 
+config TARGET_CROWNBAY
+	bool "Support Intel Crown Bay CRB"
+	help
+	  This is the Intel Crown Bay Customer Reference Board. It contains
+	  the Intel Atom Processor E6xx populated on the COM Express module
+	  with 1GB DDR2 soldered down memory and a carrier board with the
+	  Intel Platform Controller Hub EG20T, other system components and
+	  peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+
 endchoice
 
 config RAMBASE
@@ -310,8 +319,12 @@ endmenu
 
 source "arch/x86/cpu/ivybridge/Kconfig"
 
+source "arch/x86/cpu/queensbay/Kconfig"
+
 source "board/coreboot/coreboot/Kconfig"
 
 source "board/google/chromebook_link/Kconfig"
 
+source "board/intel/crownbay/Kconfig"
+
 endmenu
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
new file mode 100644
index 0000000..56fe85c
--- /dev/null
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -0,0 +1,79 @@
+#
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+config INTEL_QUEENSBAY
+	bool
+	select HAVE_FSP
+	select HAVE_CMC
+
+if INTEL_QUEENSBAY
+
+config HAVE_FSP
+	bool "Add an Firmware Support Package binary"
+	help
+	  Select this option to add an Firmware Support Package binary to
+	  the resulting U-Boot image. It is a binary blob which U-Boot uses
+	  to set up SDRAM and other chipset specific initialization.
+
+	  Note: Without this binary U-Boot will not be able to set up its
+	  SDRAM so will not boot.
+
+config FSP_FILE
+	string "Firmware Support Package binary filename"
+	depends on HAVE_FSP
+	default "fsp.bin"
+	help
+	  The filename of the file to use as Firmware Support Package binary
+	  in the board directory.
+
+config FSP_LOCATION
+	hex "Firmware Support Package binary location"
+	depends on HAVE_FSP
+	default 0xfffc0000
+	help
+	  FSP is not Position Independent Code (PIC) and the whole FSP has to
+	  be rebased if it is placed at a location which is different from the
+	  perferred base address specified during the FSP build. Use Intel's
+	  Binary Configuration Tool (BCT) to do the rebase.
+
+	  The default base address of 0xfffc0000 indicates that the binary must
+	  be located at offset 0xc0000 from the beginning of a 1MB flash device.
+
+config FSP_TEMP_RAM_ADDR
+	hex
+	default 0x2000000
+	help
+	  Stack top address which is used in FspInit after DRAM is ready and
+	  CAR is disabled.
+
+config HAVE_CMC
+	bool "Add a Chipset Micro Code state machine binary"
+	help
+	  Select this option to add a Chipset Micro Code state machine binary
+	  to the resulting U-Boot image. It is a 64K data block of machine
+	  specific code which must be put in the flash for the processor to
+	  access when powered up before system BIOS is executed.
+
+config CMC_FILE
+	string "Chipset Micro Code state machine filename"
+	depends on HAVE_CMC
+	default "cmc.bin"
+	help
+	  The filename of the file to use as Chipset Micro Code state machine
+	  binary in the board directory.
+
+config CMC_LOCATION
+	hex "Chipset Micro Code state machine binary location"
+	depends on HAVE_CMC
+	default 0xfffb0000
+	help
+	  The location of the CMC binary is determined by a strap. It must be
+	  put in flash at a location matching the strap-determined base address.
+
+	  The default base address of 0xfffb0000 indicates that the binary must
+	  be located at offset 0xb0000 from the beginning of a 1MB flash device.
+
+endif
diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig
new file mode 100644
index 0000000..4709f9b
--- /dev/null
+++ b/board/intel/crownbay/Kconfig
@@ -0,0 +1,20 @@
+if TARGET_CROWNBAY
+
+config SYS_BOARD
+	default "crownbay"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "queensbay"
+
+config SYS_CONFIG_NAME
+	default "crownbay"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select INTEL_QUEENSBAY
+	select BOARD_ROMSIZE_KB_1024
+
+endif
-- 
1.8.2.1

[U-Boot] [PATCH v4 07/15] x86: Add crownbay defconfig and config.h

[Bin Meng]

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 configs/crownbay_defconfig |  6 ++++++
 include/configs/crownbay.h | 52 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)
 create mode 100644 configs/crownbay_defconfig
 create mode 100644 include/configs/crownbay.h

diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
new file mode 100644
index 0000000..ce90553
--- /dev/null
+++ b/configs/crownbay_defconfig
@@ -0,0 +1,6 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
+CONFIG_X86=y
+CONFIG_TARGET_CROWNBAY=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
+CONFIG_DEFAULT_DEVICE_TREE="crownbay"
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
new file mode 100644
index 0000000..2314e62
--- /dev/null
+++ b/include/configs/crownbay.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+#define CONFIG_SYS_X86_START16		0xfffff800
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_X86_RESET_VECTOR
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_SMSC_LPC47M
+
+#define CONFIG_PCI_MEM_BUS		0x40000000
+#define CONFIG_PCI_MEM_PHYS		CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE		0x80000000
+
+#define CONFIG_PCI_PREF_BUS		0xc0000000
+#define CONFIG_PCI_PREF_PHYS		CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE		0x20000000
+
+#define CONFIG_PCI_IO_BUS		0x2000
+#define CONFIG_PCI_IO_PHYS		CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE		0xe000
+
+#define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_PCI_PNP
+
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial\0" \
+					"stdout=serial\0" \
+					"stderr=serial\0"
+
+#define CONFIG_SCSI_DEV_LIST            \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
+
+/* Video is not supported */
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+
+#endif	/* __CONFIG_H */
-- 
1.8.2.1

[U-Boot] [PATCH v4 08/15] x86: Use consistent name XXX_ADDR for binary blob flash address

[Bin Meng]

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

---

Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to use consistent name XXX_ADDR for binary blobs

 Makefile                             | 2 +-
 arch/x86/cpu/ivybridge/sdram.c       | 2 +-
 arch/x86/cpu/queensbay/Kconfig       | 4 ++--
 arch/x86/cpu/queensbay/fsp_support.c | 2 +-
 arch/x86/cpu/queensbay/tnc_car.S     | 2 +-
 include/configs/chromebook_link.h    | 2 +-
 6 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/Makefile b/Makefile
index d4e60e8..41137a5 100644
--- a/Makefile
+++ b/Makefile
@@ -958,7 +958,7 @@ IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin
 endif
 
 ifneq ($(CONFIG_HAVE_MRC),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin
+IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
 endif
 
 ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index df2b990..b95e781 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -177,7 +177,7 @@ int sdram_initialise(struct pei_data *pei_data)
 
 	debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
 
-	data = (char *)CONFIG_X86_MRC_START;
+	data = (char *)CONFIG_X86_MRC_ADDR;
 	if (data) {
 		int rv;
 		int (*func)(struct pei_data *);
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 56fe85c..f6b5201 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -29,7 +29,7 @@ config FSP_FILE
 	  The filename of the file to use as Firmware Support Package binary
 	  in the board directory.
 
-config FSP_LOCATION
+config FSP_ADDR
 	hex "Firmware Support Package binary location"
 	depends on HAVE_FSP
 	default 0xfffc0000
@@ -65,7 +65,7 @@ config CMC_FILE
 	  The filename of the file to use as Chipset Micro Code state machine
 	  binary in the board directory.
 
-config CMC_LOCATION
+config CMC_ADDR
 	hex "Chipset Micro Code state machine binary location"
 	depends on HAVE_CMC
 	default 0xfffb0000
diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/cpu/queensbay/fsp_support.c
index df3bbd0..f830eeb 100644
--- a/arch/x86/cpu/queensbay/fsp_support.c
+++ b/arch/x86/cpu/queensbay/fsp_support.c
@@ -64,7 +64,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void)
 	volatile register u8 *fsp asm("eax");
 
 	/* Initalize the FSP base */
-	fsp = (u8 *)CONFIG_FSP_LOCATION;
+	fsp = (u8 *)CONFIG_FSP_ADDR;
 
 	/* Check the FV signature, _FVH */
 	if (((struct fv_header_t *)fsp)->sign == 0x4856465F) {
diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S
index 2e9139e..5e09568 100644
--- a/arch/x86/cpu/queensbay/tnc_car.S
+++ b/arch/x86/cpu/queensbay/tnc_car.S
@@ -29,7 +29,7 @@ find_fsp_header_ret:
 	mov	%eax, %ebp
 
 	/* sanity test */
-	cmp	$CONFIG_FSP_LOCATION, %eax
+	cmp	$CONFIG_FSP_ADDR, %eax
 	jb	die
 
 	/* calculate TempRamInitEntry address */
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index 645b31c..c9d84e4 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -25,7 +25,7 @@
 
 #define CONFIG_X86_RESET_VECTOR
 #define CONFIG_NR_DRAM_BANKS			8
-#define CONFIG_X86_MRC_START			0xfffa0000
+#define CONFIG_X86_MRC_ADDR			0xfffa0000
 #define CONFIG_CACHE_MRC_SIZE_KB		512
 
 #define CONFIG_COREBOOT_SERIAL
-- 
1.8.2.1

[U-Boot] [PATCH v4 09/15] x86: Include FSP and CMC binary in the u-boot.rom build rules

[Bin Meng]

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Update ifdtool flags to indicate FSP and CMC files are in
  the board directory
- Use consistent XXX_FILE name for binary blob file

 Makefile                          | 10 +++++++++-
 include/configs/chromebook_link.h |  2 +-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 41137a5..49c4a89 100644
--- a/Makefile
+++ b/Makefile
@@ -961,8 +961,16 @@ ifneq ($(CONFIG_HAVE_MRC),)
 IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
 endif
 
+ifneq ($(CONFIG_HAVE_FSP),)
+IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_CMC),)
+IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
+endif
+
 ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE)
 endif
 
 quiet_cmd_ifdtool = IFDTOOL $@
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index c9d84e4..b311f4c 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -39,7 +39,7 @@
 	{PCI_VENDOR_ID_INTEL,		\
 			PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
 
-#define CONFIG_X86_OPTION_ROM_FILENAME		pci8086,0166.bin
+#define CONFIG_X86_OPTION_ROM_FILE		pci8086,0166.bin
 #define CONFIG_X86_OPTION_ROM_ADDR		0xfff90000
 #define CONFIG_VIDEO_X86
 
-- 
1.8.2.1

[U-Boot] [PATCH v4 10/15] x86: crownbay: Add SPI flash support

[Bin Meng]

The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

---

Changes in v4: None
Changes in v3:
- Add a commit message for the SPI support

Changes in v2:
- Move PCH_LPC_DEV to arch/x86/include/asm/arch-queensbay/tnc.h
- Check return value of x86_cpu_init_f()

 arch/x86/cpu/queensbay/tnc.c              | 26 +++++++++++++++++++++++++-
 arch/x86/include/asm/arch-queensbay/tnc.h | 15 +++++++++++++++
 include/configs/crownbay.h                |  2 ++
 3 files changed, 42 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/include/asm/arch-queensbay/tnc.h

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 8b9815f..8637cdc 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -6,18 +6,42 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/pci.h>
 #include <asm/post.h>
+#include <asm/arch/tnc.h>
 #include <asm/arch/fsp/fsp_support.h>
 #include <asm/processor.h>
 
+static void unprotect_spi_flash(void)
+{
+	u32 bc;
+
+	bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
+	bc |= 0x1;	/* unprotect the flash */
+	pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
+}
+
 int arch_cpu_init(void)
 {
+	struct pci_controller *hose;
+	int ret;
+
 	post_code(POST_CPU_INIT);
 #ifdef CONFIG_SYS_X86_TSC_TIMER
 	timer_set_base(rdtsc());
 #endif
 
-	return x86_cpu_init_f();
+	ret = x86_cpu_init_f();
+	if (ret)
+		return ret;
+
+	ret = pci_early_init_hose(&hose);
+	if (ret)
+		return ret;
+
+	unprotect_spi_flash();
+
+	return 0;
 }
 
 int print_cpuinfo(void)
diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h
new file mode 100644
index 0000000..67c5e05
--- /dev/null
+++ b/arch/x86/include/asm/arch-queensbay/tnc.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_TNC_H_
+#define _X86_ARCH_TNC_H_
+
+#include <pci.h>
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define PCH_LPC_DEV	PCI_BDF(0, 0x1f, 0)
+
+#endif /* _X86_ARCH_TNC_H_ */
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index 2314e62..a051b11 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -45,6 +45,8 @@
 #define CONFIG_SCSI_DEV_LIST            \
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
 
+#define CONFIG_SPI_FLASH_SST
+
 /* Video is not supported */
 #undef CONFIG_VIDEO
 #undef CONFIG_CFB_CONSOLE
-- 
1.8.2.1

[U-Boot] [PATCH v4 11/15] x86: crownbay: Enable Intel E1000 NIC support

[Bin Meng]

We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/intel/crownbay/crownbay.c | 6 ++++++
 include/configs/crownbay.h      | 1 +
 2 files changed, 7 insertions(+)

diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
index 54670d3..2a254ef 100644
--- a/board/intel/crownbay/crownbay.c
+++ b/board/intel/crownbay/crownbay.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <asm/ibmpc.h>
 #include <asm/pnp_def.h>
+#include <netdev.h>
 #include <smsc_lpc47m.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, 4)
@@ -24,3 +25,8 @@ void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
 {
 	return;
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index a051b11..09a52ab 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -37,6 +37,7 @@
 
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP
+#define CONFIG_E1000
 
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial\0" \
 					"stdout=serial\0" \
-- 
1.8.2.1

[U-Boot] [PATCH v4 12/15] x86: crownbay: Add SDHCI support

[Bin Meng]

There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Use ARRAY_SIZE(mmc_supported) instead of 2
- Check return value of add_sdhci()

 arch/x86/cpu/queensbay/Makefile   |  2 +-
 arch/x86/cpu/queensbay/topcliff.c | 47 +++++++++++++++++++++++++++++++++++++++
 include/configs/crownbay.h        |  6 +++++
 3 files changed, 54 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/cpu/queensbay/topcliff.c

diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index ace04ca..2c2ec01 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -4,6 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += tnc_car.o tnc_dram.o tnc.o
+obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
 obj-y += fsp_configs.o fsp_support.o
 obj-$(CONFIG_PCI) += tnc_pci.o
diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c
new file mode 100644
index 0000000..b01422a
--- /dev/null
+++ b/arch/x86/cpu/queensbay/topcliff.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <sdhci.h>
+
+static struct pci_device_id mmc_supported[] = {
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
+	{ }
+};
+
+int cpu_mmc_init(bd_t *bis)
+{
+	struct sdhci_host *mmc_host;
+	pci_dev_t devbusfn;
+	u32 iobase;
+	int ret;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
+		devbusfn =  pci_find_devices(mmc_supported, i);
+		if (devbusfn == -1)
+			return -ENODEV;
+
+		mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
+		if (!mmc_host)
+			return -ENOMEM;
+
+		mmc_host->name = "Topcliff SDHCI";
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
+		mmc_host->ioaddr = (void *)iobase;
+		mmc_host->quirks = 0;
+		ret = add_sdhci(mmc_host, 0, 0);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index 09a52ab..b9db6b7 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -48,6 +48,12 @@
 
 #define CONFIG_SPI_FLASH_SST
 
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_CMD_MMC
+
 /* Video is not supported */
 #undef CONFIG_VIDEO
 #undef CONFIG_CFB_CONSOLE
-- 
1.8.2.1

[U-Boot] [PATCH v4 13/15] x86: Rename coreboot-serial to x86-serial

[Bin Meng]

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

---

Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to rename coreboot-serial to x86-serial

 arch/x86/dts/coreboot.dtsi                         |  2 +-
 drivers/serial/Makefile                            |  2 +-
 drivers/serial/{serial_coreboot.c => serial_x86.c} | 12 ++++++------
 include/configs/chromebook_link.h                  |  2 +-
 include/configs/coreboot.h                         |  2 +-
 include/configs/crownbay.h                         |  2 +-
 6 files changed, 11 insertions(+), 11 deletions(-)
 rename drivers/serial/{serial_coreboot.c => serial_x86.c} (67%)

diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi
index c8dc4ce..65a93ac 100644
--- a/arch/x86/dts/coreboot.dtsi
+++ b/arch/x86/dts/coreboot.dtsi
@@ -6,7 +6,7 @@
 	};
 
 	serial {
-		compatible = "coreboot-uart";
+		compatible = "x86-uart";
 		reg = <0x3f8 0x10>;
 		reg-shift = <0>;
 		io-mapped = <1>;
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 8c84942..4cc00cd 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -43,7 +43,7 @@ obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
-obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
+obj-$(CONFIG_X86_SERIAL) += serial_x86.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_x86.c
similarity index 67%
rename from drivers/serial/serial_coreboot.c
rename to drivers/serial/serial_x86.c
index 5c6a76c..e81e035 100644
--- a/drivers/serial/serial_coreboot.c
+++ b/drivers/serial/serial_x86.c
@@ -9,12 +9,12 @@
 #include <ns16550.h>
 #include <serial.h>
 
-static const struct udevice_id coreboot_serial_ids[] = {
-	{ .compatible = "coreboot-uart" },
+static const struct udevice_id x86_serial_ids[] = {
+	{ .compatible = "x86-uart" },
 	{ }
 };
 
-static int coreboot_serial_ofdata_to_platdata(struct udevice *dev)
+static int x86_serial_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ns16550_platdata *plat = dev_get_platdata(dev);
 	int ret;
@@ -27,10 +27,10 @@ static int coreboot_serial_ofdata_to_platdata(struct udevice *dev)
 	return 0;
 }
 U_BOOT_DRIVER(serial_ns16550) = {
-	.name	= "serial_coreboot",
+	.name	= "serial_x86",
 	.id	= UCLASS_SERIAL,
-	.of_match = coreboot_serial_ids,
-	.ofdata_to_platdata = coreboot_serial_ofdata_to_platdata,
+	.of_match = x86_serial_ids,
+	.ofdata_to_platdata = x86_serial_ofdata_to_platdata,
 	.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
 	.priv_auto_alloc_size = sizeof(struct NS16550),
 	.probe = ns16550_serial_probe,
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index b311f4c..8930210 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -28,7 +28,7 @@
 #define CONFIG_X86_MRC_ADDR			0xfffa0000
 #define CONFIG_CACHE_MRC_SIZE_KB		512
 
-#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_X86_SERIAL
 
 #define CONFIG_SCSI_DEV_LIST		{PCI_VENDOR_ID_INTEL, \
 			PCI_DEVICE_ID_INTEL_NM10_AHCI},	      \
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 2581380..990a2d1 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -49,7 +49,7 @@
 	{PCI_VENDOR_ID_INTEL,		\
 			PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
 
-#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_X86_SERIAL
 
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
 					"stdout=vga,serial,cbmem\0" \
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index b9db6b7..eadb339 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -20,7 +20,7 @@
 #define CONFIG_X86_RESET_VECTOR
 #define CONFIG_NR_DRAM_BANKS		1
 
-#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_X86_SERIAL
 #define CONFIG_SMSC_LPC47M
 
 #define CONFIG_PCI_MEM_BUS		0x40000000
-- 
1.8.2.1

[U-Boot] [PATCH v4 14/15] x86: Add a README.x86 for U-Boot on x86 support

[Bin Meng]

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

---

Changes in v4:
- Minor update per review comments from Pavel Machek

Changes in v3: None
Changes in v2:
- Remove the 'make menuconfig' in the crownbay build instructions
- Indicate all the binary blobs should be put in the board directory

 doc/README.x86 | 126 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 126 insertions(+)
 create mode 100644 doc/README.x86

diff --git a/doc/README.x86 b/doc/README.x86
new file mode 100644
index 0000000..c12dfe5
--- /dev/null
+++ b/doc/README.x86
@@ -0,0 +1,126 @@
+#
+# Copyright (C) 2014, Simon Glass <sjg@chromium.org>
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+U-Boot on x86
+=============
+
+This document describes the information about U-Boot running on x86 targets,
+including supported boards, build instructions, todo list, etc.
+
+Status
+------
+U-Boot supports running as a coreboot [1] payload on x86. So far only link
+(Chromebook pixel) has been tested, but it should work with minimal adjustments
+on other x86 boards since coreboot deals with most of the low-level details.
+
+U-Boot also supports booting directly from x86 reset vector without coreboot,
+aka raw support or bare support. Currently Google Chromebook link and Intel
+Crown Bay board support running U-Boot 'bare metal'.
+
+As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux
+kernel as part of a FIT image. It also supports a compressed zImage.
+
+Build Instructions
+------------------
+Building U-Boot as a coreboot payload is just like building U-Boot for targets
+on other architectures, like below:
+
+$ make coreboot-x86_defconfig
+$ make all
+
+Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
+little bit tricky, as generally it requires several binary blobs which are not
+shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
+not turned on by default in the U-Boot source tree. Firstly, you need turn it
+on by uncommenting the following line in the main U-Boot Makefile:
+
+# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+
+Google Chromebook link specific instructions:
+
+First, you need the following binary blobs:
+
+* descriptor.bin - Intel flash descriptor
+* me.bin - Intel Management Engine
+* mrc.bin - Memory Reference Code, which sets up SDRAM
+* video ROM - sets up the display
+
+You can get these binary blobs by:
+
+$ git clone http://review.coreboot.org/p/blobs.git
+$ cd blobs
+
+Find the following files:
+
+* ./mainboard/google/link/descriptor.bin
+* ./mainboard/google/link/me.bin
+* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin
+
+The 3rd one should be renamed to mrc.bin.
+As for the video ROM, you can get it here [2].
+Make sure all these binary blobs are put in the board directory.
+
+Now you can build U-Boot and obtain u-boot.rom:
+
+$ make chromebook_link_defconfig
+$ make all
+
+Intel Crown Bay specific instructions:
+
+U-Boot support of Intel Crown Bay board [3] relies on a binary blob called
+Firmware Support Package [4] to perform all the necessary initialization steps
+as documented in the BIOS Writer Guide, including initialization of the CPU,
+memory controller, chipset and certain bus interfaces.
+
+Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
+install it on your host and locate the FSP binary blob. Note this platform
+also requires a Chipset Micro Code (CMC) state machine binary to be present in
+the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
+in this FSP package too.
+
+* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
+* ./Microcode/C0_22211.BIN
+
+Rename the first one to fsp.bin and second one to cmc.bin and put them in the
+board directory.
+
+Now you can build U-Boot and obtaim u-boot.rom
+
+$ make crownbay_defconfig
+$ make all
+
+CPU Microcode
+-------------
+Modern CPU usually requires a special bit stream called microcode [5] to be
+loaded on the processor after power up in order to function properly. U-Boot
+has already integrated these as hex dumps in the source tree.
+
+Driver Model
+------------
+x86 has been converted to use driver model for serial and GPIO.
+
+Device Tree
+-----------
+x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
+be turned on. Not every device on the board is configured via devie tree, but
+more and more devices will be added as time goes by. Check out the directory
+arch/x86/dts/ for these device tree source files.
+
+TODO List
+---------
+- MTRR support (for performance)
+- Audio
+- Chrome OS verified boot
+- SMI and ACPI support, to provide platform info and facilities to Linux
+
+References
+----------
+[1] http://www.coreboot.org
+[2] http://www.coreboot.org/~stepan/pci8086,0166.rom
+[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
+[4] http://www.intel.com/fsp
+[5] http://en.wikipedia.org/wiki/Microcode
-- 
1.8.2.1

[U-Boot] [PATCH v4 15/15] x86: Clean up the FSP support codes

[Bin Meng]

This is the follow-on patch to clean up the FSP support codes:

- Remove the _t suffix on the structures defines
- Use __packed for structure defines
- Use U-Boot's assert()
- Use standard bool true/false
- Remove read_unaligned64()
- Use memcmp() in the compare_guid()
- Remove the cast in the memset() call
- Replace some magic numbers with macros
- Use panic() when no valid FSP image header is found
- Change some FSP utility routines to use an fsp_ prefix
- Add comment blocks for asm_continuation and fsp_init_done
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines
- Add comments to mention find_fsp_header() may be called in a
  stackless environment
- Add comments to mention init(&params) in fsp_init() cannot
  be removed

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v4:
- Use __packed for structure defines
- Fix some typos and print FSP full name in cmd_hob.c

Changes in v3: None
Changes in v2:
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines

 arch/x86/cpu/queensbay/fsp_configs.c               |   2 +-
 arch/x86/cpu/queensbay/fsp_support.c               | 253 ++++++++++-----------
 arch/x86/cpu/queensbay/tnc_dram.c                  |  18 +-
 arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h  |  18 +-
 arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h  |  28 +--
 arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h   |  14 +-
 arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h  | 112 +++++----
 .../asm/arch-queensbay/fsp/fsp_infoheader.h        |   6 +-
 .../include/asm/arch-queensbay/fsp/fsp_platform.h  |   8 +-
 .../include/asm/arch-queensbay/fsp/fsp_support.h   |  63 ++---
 .../x86/include/asm/arch-queensbay/fsp/fsp_types.h |  17 +-
 arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h  |   8 +-
 arch/x86/lib/cmd_hob.c                             |  22 +-
 13 files changed, 279 insertions(+), 290 deletions(-)

diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c
index aef18fc..af28e45 100644
--- a/arch/x86/cpu/queensbay/fsp_configs.c
+++ b/arch/x86/cpu/queensbay/fsp_configs.c
@@ -8,7 +8,7 @@
 #include <common.h>
 #include <asm/arch/fsp/fsp_support.h>
 
-void update_fsp_upd(struct upd_region_t *fsp_upd)
+void update_fsp_upd(struct upd_region *fsp_upd)
 {
 	/* Override any UPD setting if required */
 
diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/cpu/queensbay/fsp_support.c
index f830eeb..ef1916b 100644
--- a/arch/x86/cpu/queensbay/fsp_support.c
+++ b/arch/x86/cpu/queensbay/fsp_support.c
@@ -10,67 +10,48 @@
 #include <asm/post.h>
 
 /**
- * Reads a 64-bit value from memory that may be unaligned.
- *
- * This function returns the 64-bit value pointed to by buf. The function
- * guarantees that the read operation does not produce an alignment fault.
- *
- * If the buf is NULL, then ASSERT().
- *
- * @buf: Pointer to a 64-bit value that may be unaligned.
- *
- * @return: The 64-bit value read from buf.
- */
-static u64 read_unaligned64(const u64 *buf)
-{
-	ASSERT(buf != NULL);
-
-	return *buf;
-}
-
-/**
  * Compares two GUIDs
  *
- * If the GUIDs are identical then TRUE is returned.
- * If there are any bit differences in the two GUIDs, then FALSE is returned.
- *
- * If guid1 is NULL, then ASSERT().
- * If guid2 is NULL, then ASSERT().
+ * If the GUIDs are identical then true is returned.
+ * If there are any bit differences in the two GUIDs, then false is returned.
  *
  * @guid1:        A pointer to a 128 bit GUID.
  * @guid2:        A pointer to a 128 bit GUID.
  *
- * @retval TRUE:  guid1 and guid2 are identical.
- * @retval FALSE: guid1 and guid2 are not identical.
+ * @retval true:  guid1 and guid2 are identical.
+ * @retval false: guid1 and guid2 are not identical.
  */
-static unsigned char compare_guid(const struct efi_guid_t *guid1,
-				  const struct efi_guid_t *guid2)
+static bool compare_guid(const struct efi_guid *guid1,
+			 const struct efi_guid *guid2)
 {
-	u64 guid1_low;
-	u64 guid2_low;
-	u64 guid1_high;
-	u64 guid2_high;
-
-	guid1_low  = read_unaligned64((const u64 *)guid1);
-	guid2_low  = read_unaligned64((const u64 *)guid2);
-	guid1_high = read_unaligned64((const u64 *)guid1 + 1);
-	guid2_high = read_unaligned64((const u64 *)guid2 + 1);
-
-	return (unsigned char)(guid1_low == guid2_low && guid1_high == guid2_high);
+	if (memcmp(guid1, guid2, sizeof(struct efi_guid)) == 0)
+		return true;
+	else
+		return false;
 }
 
 u32 __attribute__((optimize("O0"))) find_fsp_header(void)
 {
+	/*
+	 * This function may be called before the a stack is established,
+	 * so special care must be taken. First, it cannot declare any local
+	 * variable using stack. Only register variable can be used here.
+	 * Secondly, some compiler version will add prolog or epilog code
+	 * for the C function. If so the function call may not work before
+	 * stack is ready.
+	 *
+	 * GCC 4.8.1 has been verified to be working for the following codes.
+	 */
 	volatile register u8 *fsp asm("eax");
 
 	/* Initalize the FSP base */
 	fsp = (u8 *)CONFIG_FSP_ADDR;
 
 	/* Check the FV signature, _FVH */
-	if (((struct fv_header_t *)fsp)->sign == 0x4856465F) {
+	if (((struct fv_header *)fsp)->sign == EFI_FVH_SIGNATURE) {
 		/* Go to the end of the FV header and align the address */
-		fsp += ((struct fv_header_t *)fsp)->ext_hdr_off;
-		fsp += ((struct fv_ext_header_t *)fsp)->ext_hdr_size;
+		fsp += ((struct fv_header *)fsp)->ext_hdr_off;
+		fsp += ((struct fv_ext_header *)fsp)->ext_hdr_size;
 		fsp  = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8);
 	} else {
 		fsp  = 0;
@@ -78,20 +59,27 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void)
 
 	/* Check the FFS GUID */
 	if (fsp &&
-	    (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[0] == 0x912740BE) &&
-	    (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[1] == 0x47342284) &&
-	    (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[2] == 0xB08471B9) &&
-	    (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[3] == 0x0C3F3527)) {
+	    ((struct ffs_file_header *)fsp)->name.data1 == FSP_GUID_DATA1 &&
+	    ((struct ffs_file_header *)fsp)->name.data2 == FSP_GUID_DATA2 &&
+	    ((struct ffs_file_header *)fsp)->name.data3 == FSP_GUID_DATA3 &&
+	    ((struct ffs_file_header *)fsp)->name.data4[0] == FSP_GUID_DATA4_0 &&
+	    ((struct ffs_file_header *)fsp)->name.data4[1] == FSP_GUID_DATA4_1 &&
+	    ((struct ffs_file_header *)fsp)->name.data4[2] == FSP_GUID_DATA4_2 &&
+	    ((struct ffs_file_header *)fsp)->name.data4[3] == FSP_GUID_DATA4_3 &&
+	    ((struct ffs_file_header *)fsp)->name.data4[4] == FSP_GUID_DATA4_4 &&
+	    ((struct ffs_file_header *)fsp)->name.data4[5] == FSP_GUID_DATA4_5 &&
+	    ((struct ffs_file_header *)fsp)->name.data4[6] == FSP_GUID_DATA4_6 &&
+	    ((struct ffs_file_header *)fsp)->name.data4[7] == FSP_GUID_DATA4_7) {
 		/* Add the FFS header size to find the raw section header */
-		fsp += sizeof(struct ffs_file_header_t);
+		fsp += sizeof(struct ffs_file_header);
 	} else {
 		fsp = 0;
 	}
 
 	if (fsp &&
-	    ((struct raw_section_t *)fsp)->type == EFI_SECTION_RAW) {
+	    ((struct raw_section *)fsp)->type == EFI_SECTION_RAW) {
 		/* Add the raw section header size to find the FSP header */
-		fsp += sizeof(struct raw_section_t);
+		fsp += sizeof(struct raw_section);
 	} else {
 		fsp = 0;
 	}
@@ -99,7 +87,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void)
 	return (u32)fsp;
 }
 
-void fsp_continue(struct shared_data_t *shared_data, u32 status, void *hob_list)
+void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list)
 {
 	u32 stack_len;
 	u32 stack_base;
@@ -107,18 +95,18 @@ void fsp_continue(struct shared_data_t *shared_data, u32 status, void *hob_list)
 
 	post_code(POST_MRC);
 
-	ASSERT(status == 0);
+	assert(status == 0);
 
 	/* Get the migrated stack in normal memory */
-	stack_base = (u32)get_bootloader_tmp_mem(hob_list, &stack_len);
-	ASSERT(stack_base != 0);
+	stack_base = (u32)fsp_get_bootloader_tmp_mem(hob_list, &stack_len);
+	assert(stack_base != 0);
 	stack_top  = stack_base + stack_len - sizeof(u32);
 
 	/*
 	 * Old stack base is stored at the very end of the stack top,
 	 * use it to calculate the migrated shared data base
 	 */
-	shared_data = (struct shared_data_t *)(stack_base +
+	shared_data = (struct shared_data *)(stack_base +
 			((u32)shared_data - *(u32 *)stack_top));
 
 	/* The boot loader main function entry */
@@ -127,50 +115,50 @@ void fsp_continue(struct shared_data_t *shared_data, u32 status, void *hob_list)
 
 void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
 {
-	struct shared_data_t shared_data;
+	struct shared_data shared_data;
 	fsp_init_f init;
-	struct fsp_init_params_t params;
-	struct fspinit_rtbuf_t rt_buf;
-	struct vpd_region_t *fsp_vpd;
-	struct fsp_header_t *fsp_hdr;
-	struct fsp_init_params_t *params_ptr;
-	struct upd_region_t *fsp_upd;
-
-	fsp_hdr = (struct fsp_header_t *)find_fsp_header();
+	struct fsp_init_params params;
+	struct fspinit_rtbuf rt_buf;
+	struct vpd_region *fsp_vpd;
+	struct fsp_header *fsp_hdr;
+	struct fsp_init_params *params_ptr;
+	struct upd_region *fsp_upd;
+
+	fsp_hdr = (struct fsp_header *)find_fsp_header();
 	if (fsp_hdr == NULL) {
 		/* No valid FSP info header was found */
-		ASSERT(FALSE);
+		panic("Invalid FSP header");
 	}
 
-	fsp_upd = (struct upd_region_t *)&shared_data.fsp_upd;
-	memset((void *)&rt_buf, 0, sizeof(struct fspinit_rtbuf_t));
+	fsp_upd = (struct upd_region *)&shared_data.fsp_upd;
+	memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
 
 	/* Reserve a gap in stack top */
 	rt_buf.common.stack_top = (u32 *)stack_top - 32;
 	rt_buf.common.boot_mode = boot_mode;
-	rt_buf.common.upd_data = (struct upd_region_t *)fsp_upd;
+	rt_buf.common.upd_data = (struct upd_region *)fsp_upd;
 
 	/* Get VPD region start */
-	fsp_vpd = (struct vpd_region_t *)(fsp_hdr->img_base +
+	fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
 			fsp_hdr->cfg_region_off);
 
 	/* Verifify the VPD data region is valid */
-	ASSERT((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
+	assert((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
 	       (fsp_vpd->sign == VPD_IMAGE_ID));
 
 	/* Copy default data from Flash */
 	memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
-	       sizeof(struct upd_region_t));
+	       sizeof(struct upd_region));
 
 	/* Verifify the UPD data region is valid */
-	ASSERT(fsp_upd->terminator == 0x55AA);
+	assert(fsp_upd->terminator == UPD_TERMINATOR);
 
 	/* Override any UPD setting if required */
 	update_fsp_upd(fsp_upd);
 
-	memset((void *)&params, 0, sizeof(struct fsp_init_params_t));
+	memset(&params, 0, sizeof(struct fsp_init_params));
 	params.nvs_buf = nvs_buf;
-	params.rt_buf = (struct fspinit_rtbuf_t *)&rt_buf;
+	params.rt_buf = (struct fspinit_rtbuf *)&rt_buf;
 	params.continuation = (fsp_continuation_f)asm_continuation;
 
 	init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init);
@@ -199,32 +187,28 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
 
 	/*
 	 * Should never get here.
-	 * Control will continue from romstage_main_continue_asm.
+	 * Control will continue from fsp_continue.
 	 * This line below is to prevent the compiler from optimizing
 	 * structure intialization.
+	 *
+	 * DO NOT REMOVE!
 	 */
 	init(&params);
-
-	/*
-	 * Should never return.
-	 * Control will continue from ContinuationFunc
-	 */
-	ASSERT(FALSE);
 }
 
-u32 fsp_notify(struct fsp_header_t *fsp_hdr, u32 phase)
+u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase)
 {
 	fsp_notify_f notify;
-	struct fsp_notify_params_t params;
-	struct fsp_notify_params_t *params_ptr;
+	struct fsp_notify_params params;
+	struct fsp_notify_params *params_ptr;
 	u32 status;
 
 	if (!fsp_hdr)
-		fsp_hdr = (struct fsp_header_t *)find_fsp_header();
+		fsp_hdr = (struct fsp_header *)find_fsp_header();
 
 	if (fsp_hdr == NULL) {
 		/* No valid FSP info header */
-		ASSERT(FALSE);
+		panic("Invalid FSP header");
 	}
 
 	notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify);
@@ -245,9 +229,9 @@ u32 fsp_notify(struct fsp_header_t *fsp_hdr, u32 phase)
 	return status;
 }
 
-u32 get_usable_lowmem_top(const void *hob_list)
+u32 fsp_get_usable_lowmem_top(const void *hob_list)
 {
-	union hob_pointers_t hob;
+	union hob_pointers hob;
 	phys_addr_t phys_start;
 	u32 top;
 
@@ -255,26 +239,26 @@ u32 get_usable_lowmem_top(const void *hob_list)
 	hob.raw = (void *)hob_list;
 
 	/* * Collect memory ranges */
-	top = 0x100000;
-	while (!END_OF_HOB(hob)) {
-		if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+	top = FSP_LOWMEM_BASE;
+	while (!end_of_hob(hob)) {
+		if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
 			if (hob.res_desc->type == RES_SYS_MEM) {
 				phys_start = hob.res_desc->phys_start;
 				/* Need memory above 1MB to be collected here */
-				if (phys_start >= 0x100000 &&
-				    phys_start < (phys_addr_t)0x100000000)
+				if (phys_start >= FSP_LOWMEM_BASE &&
+				    phys_start < (phys_addr_t)FSP_HIGHMEM_BASE)
 					top += (u32)(hob.res_desc->len);
 			}
 		}
-		hob.raw = GET_NEXT_HOB(hob);
+		hob.raw = get_next_hob(hob);
 	}
 
 	return top;
 }
 
-u64 get_usable_highmem_top(const void *hob_list)
+u64 fsp_get_usable_highmem_top(const void *hob_list)
 {
-	union hob_pointers_t hob;
+	union hob_pointers hob;
 	phys_addr_t phys_start;
 	u64 top;
 
@@ -282,33 +266,33 @@ u64 get_usable_highmem_top(const void *hob_list)
 	hob.raw = (void *)hob_list;
 
 	/* Collect memory ranges */
-	top = 0x100000000;
-	while (!END_OF_HOB(hob)) {
-		if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+	top = FSP_HIGHMEM_BASE;
+	while (!end_of_hob(hob)) {
+		if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
 			if (hob.res_desc->type == RES_SYS_MEM) {
 				phys_start = hob.res_desc->phys_start;
 				/* Need memory above 1MB to be collected here */
-				if (phys_start >= (phys_addr_t)0x100000000)
+				if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE)
 					top += (u32)(hob.res_desc->len);
 			}
 		}
-		hob.raw = GET_NEXT_HOB(hob);
+		hob.raw = get_next_hob(hob);
 	}
 
 	return top;
 }
 
-u64 get_fsp_reserved_mem_from_guid(const void *hob_list, u64 *len,
-				   struct efi_guid_t *guid)
+u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len,
+				   struct efi_guid *guid)
 {
-	union hob_pointers_t hob;
+	union hob_pointers hob;
 
 	/* Get the HOB list for processing */
 	hob.raw = (void *)hob_list;
 
 	/* Collect memory ranges */
-	while (!END_OF_HOB(hob)) {
-		if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+	while (!end_of_hob(hob)) {
+		if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
 			if (hob.res_desc->type == RES_MEM_RESERVED) {
 				if (compare_guid(&hob.res_desc->owner, guid)) {
 					if (len)
@@ -318,99 +302,100 @@ u64 get_fsp_reserved_mem_from_guid(const void *hob_list, u64 *len,
 				}
 			}
 		}
-		hob.raw = GET_NEXT_HOB(hob);
+		hob.raw = get_next_hob(hob);
 	}
 
 	return 0;
 }
 
-u32 get_fsp_reserved_mem(const void *hob_list, u32 *len)
+u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len)
 {
-	const struct efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
+	const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
 	u64 length;
 	u32 base;
 
-	base = (u32)get_fsp_reserved_mem_from_guid(hob_list,
-			&length, (struct efi_guid_t *)&guid);
+	base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
+			&length, (struct efi_guid *)&guid);
 	if ((len != 0) && (base != 0))
 		*len = (u32)length;
 
 	return base;
 }
 
-u32 get_tseg_reserved_mem(const void *hob_list, u32 *len)
+u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len)
 {
-	const struct efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
+	const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
 	u64 length;
 	u32 base;
 
-	base = (u32)get_fsp_reserved_mem_from_guid(hob_list,
-			&length, (struct efi_guid_t *)&guid);
+	base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
+			&length, (struct efi_guid *)&guid);
 	if ((len != 0) && (base != 0))
 		*len = (u32)length;
 
 	return base;
 }
 
-void *get_next_hob(u16 type, const void *hob_list)
+void *fsp_get_next_hob(u16 type, const void *hob_list)
 {
-	union hob_pointers_t hob;
+	union hob_pointers hob;
 
-	ASSERT(hob_list != NULL);
+	assert(hob_list != NULL);
 
 	hob.raw = (u8 *)hob_list;
 
 	/* Parse the HOB list until end of list or matching type is found */
-	while (!END_OF_HOB(hob)) {
-		if (hob.hdr->type == type)
+	while (!end_of_hob(hob)) {
+		if (get_hob_type(hob) == type)
 			return hob.raw;
 
-		hob.raw = GET_NEXT_HOB(hob);
+		hob.raw = get_next_hob(hob);
 	}
 
 	return NULL;
 }
 
-void *get_next_guid_hob(const struct efi_guid_t *guid, const void *hob_list)
+void *fsp_get_next_guid_hob(const struct efi_guid *guid, const void *hob_list)
 {
-	union hob_pointers_t hob;
+	union hob_pointers hob;
 
 	hob.raw = (u8 *)hob_list;
-	while ((hob.raw = get_next_hob(HOB_TYPE_GUID_EXT,
+	while ((hob.raw = fsp_get_next_hob(HOB_TYPE_GUID_EXT,
 			hob.raw)) != NULL) {
 		if (compare_guid(guid, &hob.guid->name))
 			break;
-		hob.raw = GET_NEXT_HOB(hob);
+		hob.raw = get_next_hob(hob);
 	}
 
 	return hob.raw;
 }
 
-void *get_guid_hob_data(const void *hob_list, u32 *len, struct efi_guid_t *guid)
+void *fsp_get_guid_hob_data(const void *hob_list, u32 *len,
+			    struct efi_guid *guid)
 {
 	u8 *guid_hob;
 
-	guid_hob = get_next_guid_hob(guid, hob_list);
+	guid_hob = fsp_get_next_guid_hob(guid, hob_list);
 	if (guid_hob == NULL) {
 		return NULL;
 	} else {
 		if (len)
-			*len = GET_GUID_HOB_DATA_SIZE(guid_hob);
+			*len = get_guid_hob_data_size(guid_hob);
 
-		return GET_GUID_HOB_DATA(guid_hob);
+		return get_guid_hob_data(guid_hob);
 	}
 }
 
-void *get_fsp_nvs_data(const void *hob_list, u32 *len)
+void *fsp_get_nvs_data(const void *hob_list, u32 *len)
 {
-	const struct efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
+	const struct efi_guid guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
 
-	return get_guid_hob_data(hob_list, len, (struct efi_guid_t *)&guid);
+	return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
 }
 
-void *get_bootloader_tmp_mem(const void *hob_list, u32 *len)
+void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len)
 {
-	const struct efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;
+	const struct efi_guid guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;
 
-	return get_guid_hob_data(hob_list, len, (struct efi_guid_t *)&guid);
+	return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
 }
diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/cpu/queensbay/tnc_dram.c
index dbc1710..8e97c9b 100644
--- a/arch/x86/cpu/queensbay/tnc_dram.c
+++ b/arch/x86/cpu/queensbay/tnc_dram.c
@@ -14,17 +14,17 @@ DECLARE_GLOBAL_DATA_PTR;
 int dram_init(void)
 {
 	phys_size_t ram_size = 0;
-	union hob_pointers_t hob;
+	union hob_pointers hob;
 
 	hob.raw = gd->arch.hob_list;
-	while (!END_OF_HOB(hob)) {
-		if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+	while (!end_of_hob(hob)) {
+		if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
 			if (hob.res_desc->type == RES_SYS_MEM ||
 			    hob.res_desc->type == RES_MEM_RESERVED) {
 				ram_size += hob.res_desc->len;
 			}
 		}
-		hob.raw = GET_NEXT_HOB(hob);
+		hob.raw = get_next_hob(hob);
 	}
 
 	gd->ram_size = ram_size;
@@ -49,19 +49,19 @@ void dram_init_banksize(void)
  */
 ulong board_get_usable_ram_top(ulong total_size)
 {
-	return get_usable_lowmem_top(gd->arch.hob_list);
+	return fsp_get_usable_lowmem_top(gd->arch.hob_list);
 }
 
 unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
 {
 	unsigned num_entries = 0;
 
-	union hob_pointers_t hob;
+	union hob_pointers hob;
 
 	hob.raw = gd->arch.hob_list;
 
-	while (!END_OF_HOB(hob)) {
-		if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+	while (!end_of_hob(hob)) {
+		if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
 			entries[num_entries].addr = hob.res_desc->phys_start;
 			entries[num_entries].size = hob.res_desc->len;
 
@@ -70,7 +70,7 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
 			else if (hob.res_desc->type == RES_MEM_RESERVED)
 				entries[num_entries].type = E820_RESERVED;
 		}
-		hob.raw = GET_NEXT_HOB(hob);
+		hob.raw = get_next_hob(hob);
 		num_entries++;
 	}
 
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
index 25b938f..a9d7156 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
@@ -14,9 +14,7 @@
  */
 typedef void (*fsp_continuation_f)(u32 status, void *hob_list);
 
-#pragma pack(1)
-
-struct fsp_init_params_t {
+struct fsp_init_params {
 	/* Non-volatile storage buffer pointer */
 	void			*nvs_buf;
 	/* Runtime buffer pointer */
@@ -25,7 +23,7 @@ struct fsp_init_params_t {
 	fsp_continuation_f	continuation;
 };
 
-struct common_buf_t {
+struct common_buf {
 	/*
 	 * Stack top pointer used by the bootloader. The new stack frame will be
 	 * set up at this location after FspInit API call.
@@ -36,24 +34,22 @@ struct common_buf_t {
 	u32	reserved[7];	/* Reserved */
 };
 
-enum fsp_phase_t {
+enum fsp_phase {
 	/* Notification code for post PCI enuermation */
 	INIT_PHASE_PCI	= 0x20,
 	/* Notification code before transfering control to the payload */
 	INIT_PHASE_BOOT	= 0x40
 };
 
-struct fsp_notify_params_t {
+struct fsp_notify_params {
 	/* Notification phase used for NotifyPhase API */
-	enum fsp_phase_t	phase;
+	enum fsp_phase	phase;
 };
 
-#pragma pack()
-
 /* FspInit API function prototype */
-typedef u32 (*fsp_init_f)(struct fsp_init_params_t *param);
+typedef u32 (*fsp_init_f)(struct fsp_init_params *params);
 
 /* FspNotify API function prototype */
-typedef u32 (*fsp_notify_f)(struct fsp_notify_params_t *param);
+typedef u32 (*fsp_notify_f)(struct fsp_notify_params *params);
 
 #endif
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
index 1f73680..eaec2b4 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
@@ -8,10 +8,8 @@
 #ifndef __FSP_FFS_H__
 #define __FSP_FFS_H__
 
-#pragma pack(1)
-
 /* Used to verify the integrity of the file */
-union ffs_integrity_t {
+union __packed ffs_integrity {
 	struct {
 		/*
 		 * The IntegrityCheck.checksum.header field is an 8-bit
@@ -43,14 +41,14 @@ union ffs_integrity_t {
  * Each file begins with the header that describe the
  * contents and state of the files.
  */
-struct ffs_file_header_t {
+struct __packed ffs_file_header {
 	/*
 	 * This GUID is the file name.
 	 * It is used to uniquely identify the file.
 	 */
-	struct efi_guid_t	name;
+	struct efi_guid		name;
 	/* Used to verify the integrity of the file */
-	union ffs_integrity_t	integrity;
+	union ffs_integrity	integrity;
 	/* Identifies the type of file */
 	u8			type;
 	/* Declares various file attribute bits */
@@ -64,16 +62,16 @@ struct ffs_file_header_t {
 	u8			state;
 };
 
-struct ffs_file_header2_t {
+struct __packed ffs_file_header2 {
 	/*
 	 * This GUID is the file name. It is used to uniquely identify the file.
 	 * There may be only one instance of a file with the file name GUID of
 	 * Name in any given firmware volume, except if the file type is
 	 * EFI_FV_FILE_TYPE_FFS_PAD.
 	 */
-	struct efi_guid_t	name;
+	struct efi_guid		name;
 	/* Used to verify the integrity of the file */
-	union ffs_integrity_t	integrity;
+	union ffs_integrity	integrity;
 	/* Identifies the type of file */
 	u8			type;
 	/* Declares various file attribute bits */
@@ -81,9 +79,9 @@ struct ffs_file_header2_t {
 	/*
 	 * The length of the file in bytes, including the FFS header.
 	 * The length of the file data is either
-	 * (size - sizeof(struct ffs_file_header_t)). This calculation means a
+	 * (size - sizeof(struct ffs_file_header)). This calculation means a
 	 * zero-length file has a size of 24 bytes, which is
-	 * sizeof(struct ffs_file_header_t). Size is not required to be a
+	 * sizeof(struct ffs_file_header). Size is not required to be a
 	 * multiple of 8 bytes. Given a file F, the next file header is located
 	 * at the next 8-byte aligned firmware volume offset following the last
 	 * byte of the file F.
@@ -98,7 +96,7 @@ struct ffs_file_header2_t {
 	 * If FFS_ATTRIB_LARGE_FILE is set in attr, then ext_size exists
 	 * and size must be set to zero.
 	 * If FFS_ATTRIB_LARGE_FILE is not set then
-	 * struct ffs_file_header_t is used.
+	 * struct ffs_file_header is used.
 	 */
 	u32			ext_size;
 };
@@ -129,7 +127,7 @@ struct ffs_file_header2_t {
 #define EFI_SECTION_SMM_DEPEX			0x1C
 
 /* Common section header */
-struct raw_section_t {
+struct __packed raw_section {
 	/*
 	 * A 24-bit unsigned integer that contains the total size of
 	 * the section in bytes, including the EFI_COMMON_SECTION_HEADER.
@@ -138,7 +136,7 @@ struct raw_section_t {
 	u8	type;
 };
 
-struct raw_section2_t {
+struct __packed raw_section2 {
 	/*
 	 * A 24-bit unsigned integer that contains the total size of
 	 * the section in bytes, including the EFI_COMMON_SECTION_HEADER.
@@ -153,6 +151,4 @@ struct raw_section2_t {
 	u32	ext_size;
 };
 
-#pragma pack()
-
 #endif
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
index 01300db..a024451 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
@@ -63,7 +63,7 @@
 #define EFI_FVB2_ALIGNMENT_1G		0x001E0000
 #define EFI_FVB2_ALIGNMENT_2G		0x001F0000
 
-struct fv_blkmap_entry_t {
+struct fv_blkmap_entry {
 	/* The number of sequential blocks which are of the same size */
 	u32	num_blocks;
 	/* The size of the blocks */
@@ -71,7 +71,7 @@ struct fv_blkmap_entry_t {
 };
 
 /* Describes the features and layout of the firmware volume */
-struct fv_header_t {
+struct fv_header {
 	/*
 	 * The first 16 bytes are reserved to allow for the reset vector of
 	 * processors whose reset vector is at address 0.
@@ -81,7 +81,7 @@ struct fv_header_t {
 	 * Declares the file system with which the firmware volume
 	 * is formatted.
 	 */
-	struct efi_guid_t	fs_guid;
+	struct efi_guid		fs_guid;
 	/*
 	 * Length in bytes of the complete firmware volume, including
 	 * the header.
@@ -118,18 +118,18 @@ struct fv_header_t {
 	 * An array of run-length encoded FvBlockMapEntry structures.
 	 * The array is terminated with an entry of {0,0}.
 	 */
-	struct fv_blkmap_entry_t	block_map[1];
+	struct fv_blkmap_entry	block_map[1];
 };
 
-#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H')
+#define EFI_FVH_SIGNATURE	SIGNATURE_32('_', 'F', 'V', 'H')
 
 /* Firmware Volume Header Revision definition */
 #define EFI_FVH_REVISION	0x02
 
 /* Extension header pointed by ExtHeaderOffset of volume header */
-struct fv_ext_header_t {
+struct fv_ext_header {
 	/* firmware volume name */
-	struct efi_guid_t	fv_name;
+	struct efi_guid		fv_name;
 	/* Size of the rest of the extension header including this structure */
 	u32			ext_hdr_size;
 };
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
index 44c0f90..380b64e 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
@@ -19,14 +19,14 @@
  * Describes the format and size of the data inside the HOB.
  * All HOBs must contain this generic HOB header.
  */
-struct hob_header_t {
+struct hob_header {
 	u16	type;		/* HOB type */
 	u16	len;		/* HOB length */
 	u32	reserved;	/* always zero */
 };
 
 /* Enumeration of memory types introduced in UEFI */
-enum efi_mem_type_t {
+enum efi_mem_type {
 	EFI_RESERVED_MEMORY_TYPE,
 	/*
 	 * The code portions of a loaded application.
@@ -87,16 +87,16 @@ enum efi_mem_type_t {
  * exist outside the HOB list. This HOB type describes how memory is used,
  * not the physical attributes of memory.
  */
-struct hob_mem_alloc_t {
-	struct hob_header_t	hdr;
+struct hob_mem_alloc {
+	struct hob_header	hdr;
 	/*
 	 * A GUID that defines the memory allocation region's type and purpose,
 	 * as well as other fields within the memory allocation HOB. This GUID
 	 * is used to define the additional data within the HOB that may be
-	 * present for the memory allocation HOB. Type efi_guid_t is defined in
+	 * present for the memory allocation HOB. Type efi_guid is defined in
 	 * InstallProtocolInterface() in the UEFI 2.0 specification.
 	 */
-	struct efi_guid_t	name;
+	struct efi_guid		name;
 	/*
 	 * The base address of memory allocated by this HOB.
 	 * Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0
@@ -111,7 +111,7 @@ struct hob_mem_alloc_t {
 	 * Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0
 	 * specification.
 	 */
-	enum efi_mem_type_t	mem_type;
+	enum efi_mem_type	mem_type;
 	/* padding */
 	u8			reserved[4];
 };
@@ -155,14 +155,14 @@ struct hob_mem_alloc_t {
  * Describes the resource properties of all fixed, nonrelocatable resource
  * ranges found on the processor host bus during the HOB producer phase.
  */
-struct hob_res_desc_t {
-	struct hob_header_t	hdr;
+struct hob_res_desc {
+	struct hob_header	hdr;
 	/*
 	 * A GUID representing the owner of the resource. This GUID is
 	 * used by HOB consumer phase components to correlate device
 	 * ownership of a resource.
 	 */
-	struct efi_guid_t	owner;
+	struct efi_guid		owner;
 	u32			type;
 	u32			attr;
 	/* The physical start address of the resource region */
@@ -175,24 +175,24 @@ struct hob_res_desc_t {
  * Allows writers of executable content in the HOB producer phase to
  * maintain and manage HOBs with specific GUID.
  */
-struct hob_guid_t {
-	struct hob_header_t	hdr;
+struct hob_guid {
+	struct hob_header	hdr;
 	/* A GUID that defines the contents of this HOB */
-	struct efi_guid_t	name;
+	struct efi_guid		name;
 	/* GUID specific data goes here */
 };
 
 /* Union of all the possible HOB Types */
-union hob_pointers_t {
-	struct hob_header_t	*hdr;
-	struct hob_mem_alloc_t	*mem_alloc;
-	struct hob_res_desc_t	*res_desc;
-	struct hob_guid_t	*guid;
+union hob_pointers {
+	struct hob_header	*hdr;
+	struct hob_mem_alloc	*mem_alloc;
+	struct hob_res_desc	*res_desc;
+	struct hob_guid		*guid;
 	u8			*raw;
 };
 
 /**
- * Returns the type of a HOB.
+ * get_hob_type() - return the type of a HOB
  *
  * This macro returns the type field from the HOB header for the
  * HOB specified by hob.
@@ -201,11 +201,13 @@ union hob_pointers_t {
  *
  * @return: HOB type.
  */
-#define GET_HOB_TYPE(hob) \
-	((*(struct hob_header_t **)&(hob))->type)
+static inline u16 get_hob_type(union hob_pointers hob)
+{
+	return hob.hdr->type;
+}
 
 /**
- * Returns the length, in bytes, of a HOB.
+ * get_hob_length() - return the length, in bytes, of a HOB
  *
  * This macro returns the len field from the HOB header for the
  * HOB specified by hob.
@@ -214,11 +216,13 @@ union hob_pointers_t {
  *
  * @return: HOB length.
  */
-#define GET_HOB_LENGTH(hob) \
-	((*(struct hob_header_t **)&(hob))->len)
+static inline u16 get_hob_length(union hob_pointers hob)
+{
+	return hob.hdr->len;
+}
 
 /**
- * Returns a pointer to the next HOB in the HOB list.
+ * get_next_hob() - return a pointer to the next HOB in the HOB list
  *
  * This macro returns a pointer to HOB that follows the HOB specified by hob
  * in the HOB List.
@@ -227,25 +231,31 @@ union hob_pointers_t {
  *
  * @return: A pointer to the next HOB in the HOB list.
  */
-#define GET_NEXT_HOB(hob)	\
-	(void *)(*(u8 **)&(hob) + GET_HOB_LENGTH(hob))
+static inline void *get_next_hob(union hob_pointers hob)
+{
+	return (void *)(*(u8 **)&(hob) + get_hob_length(hob));
+}
 
 /**
- * Determines if a HOB is the last HOB in the HOB list.
+ * end_of_hob() - determine if a HOB is the last HOB in the HOB list
  *
  * This macro determine if the HOB specified by hob is the last HOB in the
- * HOB list.  If hob is last HOB in the HOB list, then TRUE is returned.
- * Otherwise, FALSE is returned.
+ * HOB list.  If hob is last HOB in the HOB list, then true is returned.
+ * Otherwise, false is returned.
  *
  * @hob:          A pointer to a HOB.
  *
- * @retval TRUE:  The HOB specified by hob is the last HOB in the HOB list.
- * @retval FALSE: The HOB specified by hob is not the last HOB in the HOB list.
+ * @retval true:  The HOB specified by hob is the last HOB in the HOB list.
+ * @retval false: The HOB specified by hob is not the last HOB in the HOB list.
  */
-#define END_OF_HOB(hob)	(GET_HOB_TYPE(hob) == (u16)HOB_TYPE_EOH)
+static inline bool end_of_hob(union hob_pointers hob)
+{
+	return get_hob_type(hob) == HOB_TYPE_EOH;
+}
 
 /**
- * Returns a pointer to data buffer from a HOB of type HOB_TYPE_GUID_EXT.
+ * get_guid_hob_data() - return a pointer to data buffer from a HOB of
+ *                       type HOB_TYPE_GUID_EXT
  *
  * This macro returns a pointer to the data buffer in a HOB specified by hob.
  * hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
@@ -254,11 +264,14 @@ union hob_pointers_t {
  *
  * @return: A pointer to the data buffer in a HOB.
  */
-#define GET_GUID_HOB_DATA(hob)	\
-	(void *)(*(u8 **)&(hob) + sizeof(struct hob_guid_t))
+static inline void *get_guid_hob_data(u8 *hob)
+{
+	return (void *)(hob + sizeof(struct hob_guid));
+}
 
 /**
- * Returns the size of the data buffer from a HOB of type HOB_TYPE_GUID_EXT.
+ * get_guid_hob_data_size() - return the size of the data buffer from a HOB
+ *                            of type HOB_TYPE_GUID_EXT
  *
  * This macro returns the size, in bytes, of the data buffer in a HOB
  * specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
@@ -267,14 +280,31 @@ union hob_pointers_t {
  *
  * @return: The size of the data buffer.
  */
-#define GET_GUID_HOB_DATA_SIZE(hob)	\
-	(u16)(GET_HOB_LENGTH(hob) - sizeof(struct hob_guid_t))
+static inline u16 get_guid_hob_data_size(u8 *hob)
+{
+	union hob_pointers hob_p = *(union hob_pointers *)hob;
+	return get_hob_length(hob_p) - sizeof(struct hob_guid);
+}
 
 /* FSP specific GUID HOB definitions */
+#define FSP_GUID_DATA1		0x912740be
+#define FSP_GUID_DATA2		0x2284
+#define FSP_GUID_DATA3		0x4734
+#define FSP_GUID_DATA4_0	0xb9
+#define FSP_GUID_DATA4_1	0x71
+#define FSP_GUID_DATA4_2	0x84
+#define FSP_GUID_DATA4_3	0xb0
+#define FSP_GUID_DATA4_4	0x27
+#define FSP_GUID_DATA4_5	0x35
+#define FSP_GUID_DATA4_6	0x3f
+#define FSP_GUID_DATA4_7	0x0c
+
 #define FSP_HEADER_GUID \
 	{ \
-	0x912740be, 0x2284, 0x4734, \
-	{0xb9, 0x71, 0x84, 0xb0, 0x27, 0x35, 0x3f, 0x0c} \
+	FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \
+	{ FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \
+	  FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \
+	  FSP_GUID_DATA4_6, FSP_GUID_DATA4_7 } \
 	}
 
 #define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h
index ad78bcd..4a4d627 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h
@@ -10,9 +10,7 @@
 
 #define FSP_HEADER_OFF	0x94	/* Fixed FSP header offset in the FSP image */
 
-#pragma pack(1)
-
-struct fsp_header_t {
+struct __packed fsp_header {
 	u32	sign;			/* 'FSPH' */
 	u32	hdr_len;		/* header length */
 	u8	reserved1[3];
@@ -31,6 +29,4 @@ struct fsp_header_t {
 	u32	reserved2;
 };
 
-#pragma pack()
-
 #endif
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h
index a7b6e6b..61286ce 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h
@@ -8,12 +8,8 @@
 #ifndef __FSP_PLATFORM_H__
 #define __FSP_PLATFORM_H__
 
-#pragma pack(1)
-
-struct fspinit_rtbuf_t {
-	struct common_buf_t	common;	/* FSP common runtime data structure */
+struct fspinit_rtbuf {
+	struct common_buf	common;	/* FSP common runtime data structure */
 };
 
-#pragma pack()
-
 #endif
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
index 3296a2b..3ae1b66 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
@@ -18,14 +18,30 @@
 #include "fsp_bootmode.h"
 #include "fsp_vpd.h"
 
-struct shared_data_t {
-	struct fsp_header_t	*fsp_hdr;
+struct shared_data {
+	struct fsp_header	*fsp_hdr;
 	u32			*stack_top;
-	struct upd_region_t	fsp_upd;
+	struct upd_region	fsp_upd;
 };
 
+#define FSP_LOWMEM_BASE		0x100000UL
+#define FSP_HIGHMEM_BASE	0x100000000ULL
+
+/**
+ * FSP Continuation assembly helper routine
+ *
+ * This routine jumps to the C version of FSP continuation function
+ */
 void asm_continuation(void);
 
+/**
+ * FSP initialization complete
+ *
+ * This is the function that indicates FSP initialization is complete and jumps
+ * back to the bootloader with HOB list pointer as the parameter.
+ *
+ * @hob_list:    HOB list pointer
+ */
 void fsp_init_done(void *hob_list);
 
 /**
@@ -37,19 +53,12 @@ void fsp_init_done(void *hob_list);
  *
  * @retval:      Never returns
  */
-void fsp_continue(struct shared_data_t *shared_data, u32 status,
+void fsp_continue(struct shared_data *shared_data, u32 status,
 		  void *hob_list);
 
 /**
  * Find FSP header offset in FSP image
  *
- * If this function is called before the a stack is established, special care
- * must be taken. First, it cannot declare any local variable using stack.
- * Only register variable can be used here. Secondly, some compiler version
- * will add prolog or epilog code for the C function. If so the function call
- * may not work before stack is ready. GCC 4.8.1 has been verified to be
- * working for the following code.
- *
  * @retval: the offset of FSP header. If signature is invalid, returns 0.
  */
 u32 find_fsp_header(void);
@@ -67,11 +76,11 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf);
  * FSP notification wrapper function
  *
  * @fsp_hdr: Pointer to FSP information header
- * @phase:   FSP initialization phase defined in enum fsp_phase_t
+ * @phase:   FSP initialization phase defined in enum fsp_phase
  *
  * @retval:  compatible status code with EFI_STATUS defined in PI spec
  */
-u32 fsp_notify(struct fsp_header_t *fsp_hdr, u32 phase);
+u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
 
 /**
  * This function retrieves the top of usable low memory.
@@ -80,7 +89,7 @@ u32 fsp_notify(struct fsp_header_t *fsp_hdr, u32 phase);
  *
  * @retval:   Usable low memory top.
  */
-u32 get_usable_lowmem_top(const void *hob_list);
+u32 fsp_get_usable_lowmem_top(const void *hob_list);
 
 /**
  * This function retrieves the top of usable high memory.
@@ -89,7 +98,7 @@ u32 get_usable_lowmem_top(const void *hob_list);
  *
  * @retval:   Usable high memory top.
  */
-u64 get_usable_highmem_top(const void *hob_list);
+u64 fsp_get_usable_highmem_top(const void *hob_list);
 
 /**
  * This function retrieves a special reserved memory region.
@@ -102,8 +111,8 @@ u64 get_usable_highmem_top(const void *hob_list);
  * @retval:   Reserved region start address.
  *            0 if this region does not exist.
  */
-u64 get_fsp_reserved_mem_from_guid(const void *hob_list,
-				   u64 *len, struct efi_guid_t *guid);
+u64 fsp_get_reserved_mem_from_guid(const void *hob_list,
+				   u64 *len, struct efi_guid *guid);
 
 /**
  * This function retrieves the FSP reserved normal memory.
@@ -114,7 +123,7 @@ u64 get_fsp_reserved_mem_from_guid(const void *hob_list,
  * @retval:   FSP reserved memory base
  *            0 if this region does not exist.
  */
-u32 get_fsp_reserved_mem(const void *hob_list, u32 *len);
+u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len);
 
 /**
  * This function retrieves the TSEG reserved normal memory.
@@ -126,7 +135,7 @@ u32 get_fsp_reserved_mem(const void *hob_list, u32 *len);
  * @retval NULL:   Failed to find the TSEG reserved memory.
  * @retval others: TSEG reserved memory base.
  */
-u32 get_tseg_reserved_mem(const void *hob_list, u32 *len);
+u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len);
 
 /**
  * Returns the next instance of a HOB type from the starting HOB.
@@ -136,7 +145,7 @@ u32 get_tseg_reserved_mem(const void *hob_list, u32 *len);
  *
  * @retval:   A HOB object with matching type; Otherwise NULL.
  */
-void *get_next_hob(u16 type, const void *hob_list);
+void *fsp_get_next_hob(u16 type, const void *hob_list);
 
 /**
  * Returns the next instance of the matched GUID HOB from the starting HOB.
@@ -146,7 +155,7 @@ void *get_next_hob(u16 type, const void *hob_list);
  *
  * @retval:   A HOB object with matching GUID; Otherwise NULL.
  */
-void *get_next_guid_hob(const struct efi_guid_t *guid, const void *hob_list);
+void *fsp_get_next_guid_hob(const struct efi_guid *guid, const void *hob_list);
 
 /**
  * This function retrieves a GUID HOB data buffer and size.
@@ -159,8 +168,8 @@ void *get_next_guid_hob(const struct efi_guid_t *guid, const void *hob_list);
  * @retval NULL:   Failed to find the GUID HOB.
  * @retval others: GUID HOB data buffer pointer.
  */
-void *get_guid_hob_data(const void *hob_list, u32 *len,
-			struct efi_guid_t *guid);
+void *fsp_get_guid_hob_data(const void *hob_list, u32 *len,
+			    struct efi_guid *guid);
 
 /**
  * This function retrieves FSP Non-volatile Storage HOB buffer and size.
@@ -172,7 +181,7 @@ void *get_guid_hob_data(const void *hob_list, u32 *len,
  * @retval NULL:   Failed to find the NVS HOB.
  * @retval others: FSP NVS data buffer pointer.
  */
-void *get_fsp_nvs_data(const void *hob_list, u32 *len);
+void *fsp_get_nvs_data(const void *hob_list, u32 *len);
 
 /**
  * This function retrieves Bootloader temporary stack buffer and size.
@@ -184,15 +193,15 @@ void *get_fsp_nvs_data(const void *hob_list, u32 *len);
  * @retval NULL:   Failed to find the bootloader temporary stack HOB.
  * @retval others: Bootloader temporary stackbuffer pointer.
  */
-void *get_bootloader_tmp_mem(const void *hob_list, u32 *len);
+void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
 
 /**
  * This function overrides the default configurations in the UPD data region.
  *
- * @fsp_upd: A pointer to the upd_region_t data strcture
+ * @fsp_upd: A pointer to the upd_region data strcture
  *
  * @return:  None
  */
-void update_fsp_upd(struct upd_region_t *fsp_upd);
+void update_fsp_upd(struct upd_region *fsp_upd);
 
 #endif
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h
index 12ebbfd..f32d827 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h
@@ -8,20 +8,8 @@
 #ifndef __FSP_TYPES_H__
 #define __FSP_TYPES_H__
 
-/*
- * Boolean true value.  UEFI Specification defines this value to be 1,
- * but this form is more portable.
- */
-#define TRUE			((unsigned char)(1 == 1))
-
-/*
- * Boolean false value.  UEFI Specification defines this value to be 0,
- * but this form is more portable.
- */
-#define FALSE			((unsigned char)(0 == 1))
-
 /* 128 bit buffer containing a unique identifier value */
-struct efi_guid_t {
+struct efi_guid {
 	u32	data1;
 	u16	data2;
 	u16	data3;
@@ -80,9 +68,6 @@ struct efi_guid_t {
 #define SIGNATURE_64(A, B, C, D, E, F, G, H)	\
 	(SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
 
-/* Assertion for debug */
-#define ASSERT(exp)	do { if (!(exp)) for (;;); } while (FALSE)
-
 /*
  * Define FSP API return status code.
  * Compatiable with EFI_STATUS defined in PI Spec.
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
index 11cc32f..bce58b1 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
@@ -10,9 +10,9 @@
 #ifndef __VPDHEADER_H__
 #define __VPDHEADER_H__
 
-#pragma pack(1)
+#define UPD_TERMINATOR	0x55AA
 
-struct upd_region_t {
+struct __packed upd_region {
 	u64	sign;			/* Offset 0x0000 */
 	u64	reserved;		/* Offset 0x0008 */
 	u8	dummy[240];		/* Offset 0x0010 */
@@ -39,7 +39,7 @@ struct upd_region_t {
 #define VPD_IMAGE_ID	0x445056574F4E4E4D	/* 'MNNOWVPD' */
 #define VPD_IMAGE_REV	0x00000301
 
-struct vpd_region_t {
+struct __packed vpd_region {
 	u64	sign;			/* Offset 0x0000 */
 	u32	img_rev;		/* Offset 0x0008 */
 	u32	upd_offset;		/* Offset 0x000C */
@@ -53,6 +53,4 @@ struct vpd_region_t {
 	u8	pcie_port_ioh;		/* Offset 0x0029 */
 };
 
-#pragma pack()
-
 #endif
diff --git a/arch/x86/lib/cmd_hob.c b/arch/x86/lib/cmd_hob.c
index 2fdff2b..b552fe6 100644
--- a/arch/x86/lib/cmd_hob.c
+++ b/arch/x86/lib/cmd_hob.c
@@ -17,18 +17,18 @@ static char *hob_type[] = {
 	"Memory Allocation",
 	"Resource Descriptor",
 	"GUID Extension",
-	"Firmware Volumn",
+	"Firmware Volume",
 	"CPU",
 	"Memory Pool",
 	"reserved",
-	"Firmware Volumn 2",
+	"Firmware Volume 2",
 	"Load PEIM Unused",
 	"UEFI Capsule",
 };
 
 int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	union hob_pointers_t hob;
+	union hob_pointers hob;
 	u16 type;
 	char *desc;
 	int i = 0;
@@ -39,29 +39,27 @@ int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	printf("No. | Address  | Type                | Length in Bytes\n");
 	printf("----|----------|---------------------|----------------\n");
-	while (!END_OF_HOB(hob)) {
+	while (!end_of_hob(hob)) {
 		printf("%-3d | %08x | ", i, (unsigned int)hob.raw);
-		type = hob.hdr->type;
+		type = get_hob_type(hob);
 		if (type == HOB_TYPE_UNUSED)
 			desc = "*Unused*";
 		else if (type == HOB_TYPE_EOH)
-			desc = "**END OF HOB**";
+			desc = "*END OF HOB*";
 		else if (type >= 0 && type <= ARRAY_SIZE(hob_type))
 			desc = hob_type[type];
 		else
-			desc = "!!!Invalid Type!!!";
-		printf("%-19s | %-15d\n", desc, hob.hdr->len);
-		hob.raw = GET_NEXT_HOB(hob);
+			desc = "*Invalid Type*";
+		printf("%-19s | %-15d\n", desc, get_hob_length(hob));
+		hob.raw = get_next_hob(hob);
 		i++;
 	}
 
 	return 0;
 }
 
-/* -------------------------------------------------------------------- */
-
 U_BOOT_CMD(
 	hob,	1,	1,	do_hob,
-	"print FSP Hand-Off Block information",
+	"print Firmware Support Package (FSP) Hand-Off Block information",
 	""
 );
-- 
1.8.2.1

[U-Boot] [PATCH v4 03/15] x86: Convert microcode format to device-tree-only

[Bin Meng]

Hi,

On Wed, Dec 17, 2014 at 3:50 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> From: Simon Glass <sjg@chromium.org>
>
> To avoid having two microcode formats, adjust the build system to support
> obtaining the microcode from the device tree, even in the case where it
> must be made available before the device tree can be accessed.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4:
> - Squash the microcode.dtsi to patch#1 in the v4 series
>
> Changes in v3: None
> Changes in v2: None
>
>  Makefile                         |  4 +++-
>  arch/x86/cpu/queensbay/tnc_car.S | 11 ++++-------
>  arch/x86/dts/crownbay.dts        |  7 +++++++
>  3 files changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index fd24cde..d4e60e8 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -947,7 +947,9 @@ ifneq ($(CONFIG_X86_RESET_VECTOR),)
>  rom: u-boot.rom FORCE
>
>  IFDTOOL=$(objtree)/tools/ifdtool
> -IFDTOOL_FLAGS  = -w $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin
> +IFDTOOL_FLAGS  = -f 0:$(objtree)/u-boot.dtb
> +IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1)
> +IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot.bin
>  IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
>
>  ifneq ($(CONFIG_HAVE_INTEL_ME),)
> diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S
> index 6834a64..2e9139e 100644
> --- a/arch/x86/cpu/queensbay/tnc_car.S
> +++ b/arch/x86/cpu/queensbay/tnc_car.S
> @@ -116,12 +116,9 @@ temp_ram_init_romstack:
>         .long   temp_ram_init_ret
>         .long   temp_ram_init_params
>  temp_ram_init_params:
> -       .long   ucode_start             /* microcode base */
> -       .long   ucode_size              /* microcode size */
> +_dt_ucode_base_size:
> +       /* These next two fields are filled in by ifdtool */
> +       .long   0                       /* microcode base */
> +       .long   0                       /* microcode size */
>         .long   CONFIG_SYS_MONITOR_BASE /* code region base */
>         .long   CONFIG_SYS_MONITOR_LEN  /* code region size */
> -
> -       .balign 4
> -ucode_start:
> -       .include "arch/x86/cpu/queensbay/M0220661105.inc"
> -ucode_size = ( . - ucode_start)
> diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
> index 399dafb..3f43f3c 100644
> --- a/arch/x86/dts/crownbay.dts
> +++ b/arch/x86/dts/crownbay.dts
> @@ -50,4 +50,11 @@
>                         memory-map = <0xffe00000 0x00200000>;
>                 };
>         };
> +
> +       microcode {
> +               update at 0 {
> +#include "microcode/m0220661105_cv.dtsi"
> +               };
> +       };
> +
>  };
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v4 01/15] x86: Integrate Tunnel Creek processor microcode

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> Integrate the processor microcode version 1.05 for Tunnel Creek,
> CPUID device 20661h.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> Changes in v4:
> - Switch to use dtsi format microcode
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/dts/microcode/m0220661105_cv.dtsi | 368 +++++++++++++++++++++++++++++
>  1 file changed, 368 insertions(+)
>  create mode 100644 arch/x86/dts/microcode/m0220661105_cv.dtsi

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v4 15/15] x86: Clean up the FSP support codes

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> This is the follow-on patch to clean up the FSP support codes:
>
> - Remove the _t suffix on the structures defines
> - Use __packed for structure defines
> - Use U-Boot's assert()
> - Use standard bool true/false
> - Remove read_unaligned64()
> - Use memcmp() in the compare_guid()
> - Remove the cast in the memset() call
> - Replace some magic numbers with macros
> - Use panic() when no valid FSP image header is found
> - Change some FSP utility routines to use an fsp_ prefix
> - Add comment blocks for asm_continuation and fsp_init_done
> - Remove some casts in find_fsp_header()
> - Change HOB access macros to static inline routines
> - Add comments to mention find_fsp_header() may be called in a
>   stackless environment
> - Add comments to mention init(&params) in fsp_init() cannot
>   be removed
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> Changes in v4:
> - Use __packed for structure defines
> - Fix some typos and print FSP full name in cmd_hob.c
>
> Changes in v3: None
> Changes in v2:
> - Remove some casts in find_fsp_header()
> - Change HOB access macros to static inline routines
>
>  arch/x86/cpu/queensbay/fsp_configs.c               |   2 +-
>  arch/x86/cpu/queensbay/fsp_support.c               | 253 ++++++++++-----------
>  arch/x86/cpu/queensbay/tnc_dram.c                  |  18 +-
>  arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h  |  18 +-
>  arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h  |  28 +--
>  arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h   |  14 +-
>  arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h  | 112 +++++----
>  .../asm/arch-queensbay/fsp/fsp_infoheader.h        |   6 +-
>  .../include/asm/arch-queensbay/fsp/fsp_platform.h  |   8 +-
>  .../include/asm/arch-queensbay/fsp/fsp_support.h   |  63 ++---
>  .../x86/include/asm/arch-queensbay/fsp/fsp_types.h |  17 +-
>  arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h  |   8 +-
>  arch/x86/lib/cmd_hob.c                             |  22 +-
>  13 files changed, 279 insertions(+), 290 deletions(-)
>

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v4 02/15] x86: Add basic support to queensbay platform and crownbay board

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> Implement minimum required functions for the basic support to
> queensbay platform and crownbay board.
>
> Currently the implementation is to call fsp_init() in the car_init().
> We may move that call to cpu_init_f() in the future.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> Changes in v4: None
> Changes in v3:
> - Update to use u-boot coding convention for fsp codes
> - Use jnz to jump to the car_init error code at the end of tnc_car.S
>   file instead of being in the normal path flow
> - Add a TODO comment block to document the fsp_init() call
> - Change label xxx_stack to xxx_romstack
> - Add a comment block to explain the ROM stack
>
> Changes in v2:
> - Replace 0xcf9 with macro PORT_RESET from processor.h
> - Move FspInit call from start.S to car_init
> - Add UART0_BASE and UART1_BASE to ibmpc.h
>
>  arch/x86/cpu/queensbay/Makefile   |   9 +++
>  arch/x86/cpu/queensbay/tnc.c      |  48 ++++++++++++++
>  arch/x86/cpu/queensbay/tnc_car.S  | 127 ++++++++++++++++++++++++++++++++++++++
>  arch/x86/cpu/queensbay/tnc_dram.c |  78 +++++++++++++++++++++++
>  arch/x86/cpu/queensbay/tnc_pci.c  |  61 ++++++++++++++++++
>  arch/x86/include/asm/ibmpc.h      |   3 +
>  board/intel/crownbay/MAINTAINERS  |   6 ++
>  board/intel/crownbay/Makefile     |   7 +++
>  board/intel/crownbay/crownbay.c   |  21 +++++++
>  board/intel/crownbay/start.S      |   9 +++
>  10 files changed, 369 insertions(+)
>  create mode 100644 arch/x86/cpu/queensbay/Makefile
>  create mode 100644 arch/x86/cpu/queensbay/tnc.c
>  create mode 100644 arch/x86/cpu/queensbay/tnc_car.S
>  create mode 100644 arch/x86/cpu/queensbay/tnc_dram.c
>  create mode 100644 arch/x86/cpu/queensbay/tnc_pci.c
>  create mode 100644 board/intel/crownbay/MAINTAINERS
>  create mode 100644 board/intel/crownbay/Makefile
>  create mode 100644 board/intel/crownbay/crownbay.c
>  create mode 100644 board/intel/crownbay/start.S

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v4 01/15] x86: Integrate Tunnel Creek processor microcode

[Simon Glass]

On 17 December 2014 at 07:40, Simon Glass <sjg@chromium.org> wrote:
> On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Integrate the processor microcode version 1.05 for Tunnel Creek,
>> CPUID device 20661h.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> ---
>>
>> Changes in v4:
>> - Switch to use dtsi format microcode
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>  arch/x86/dts/microcode/m0220661105_cv.dtsi | 368 +++++++++++++++++++++++++++++
>>  1 file changed, 368 insertions(+)
>>  create mode 100644 arch/x86/dts/microcode/m0220661105_cv.dtsi
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 02/15] x86: Add basic support to queensbay platform and crownbay board

[Simon Glass]

On 17 December 2014 at 07:41, Simon Glass <sjg@chromium.org> wrote:
> On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Implement minimum required functions for the basic support to
>> queensbay platform and crownbay board.
>>
>> Currently the implementation is to call fsp_init() in the car_init().
>> We may move that call to cpu_init_f() in the future.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> ---
>>
>> Changes in v4: None
>> Changes in v3:
>> - Update to use u-boot coding convention for fsp codes
>> - Use jnz to jump to the car_init error code at the end of tnc_car.S
>>   file instead of being in the normal path flow
>> - Add a TODO comment block to document the fsp_init() call
>> - Change label xxx_stack to xxx_romstack
>> - Add a comment block to explain the ROM stack
>>
>> Changes in v2:
>> - Replace 0xcf9 with macro PORT_RESET from processor.h
>> - Move FspInit call from start.S to car_init
>> - Add UART0_BASE and UART1_BASE to ibmpc.h
>>
>>  arch/x86/cpu/queensbay/Makefile   |   9 +++
>>  arch/x86/cpu/queensbay/tnc.c      |  48 ++++++++++++++
>>  arch/x86/cpu/queensbay/tnc_car.S  | 127 ++++++++++++++++++++++++++++++++++++++
>>  arch/x86/cpu/queensbay/tnc_dram.c |  78 +++++++++++++++++++++++
>>  arch/x86/cpu/queensbay/tnc_pci.c  |  61 ++++++++++++++++++
>>  arch/x86/include/asm/ibmpc.h      |   3 +
>>  board/intel/crownbay/MAINTAINERS  |   6 ++
>>  board/intel/crownbay/Makefile     |   7 +++
>>  board/intel/crownbay/crownbay.c   |  21 +++++++
>>  board/intel/crownbay/start.S      |   9 +++
>>  10 files changed, 369 insertions(+)
>>  create mode 100644 arch/x86/cpu/queensbay/Makefile
>>  create mode 100644 arch/x86/cpu/queensbay/tnc.c
>>  create mode 100644 arch/x86/cpu/queensbay/tnc_car.S
>>  create mode 100644 arch/x86/cpu/queensbay/tnc_dram.c
>>  create mode 100644 arch/x86/cpu/queensbay/tnc_pci.c
>>  create mode 100644 board/intel/crownbay/MAINTAINERS
>>  create mode 100644 board/intel/crownbay/Makefile
>>  create mode 100644 board/intel/crownbay/crownbay.c
>>  create mode 100644 board/intel/crownbay/start.S
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 03/15] x86: Convert microcode format to device-tree-only

[Simon Glass]

On 17 December 2014 at 01:05, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi,
>
> On Wed, Dec 17, 2014 at 3:50 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
>> From: Simon Glass <sjg@chromium.org>
>>
>> To avoid having two microcode formats, adjust the build system to support
>> obtaining the microcode from the device tree, even in the case where it
>> must be made available before the device tree can be accessed.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>
>> ---
>>
>> Changes in v4:
>> - Squash the microcode.dtsi to patch#1 in the v4 series
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>  Makefile                         |  4 +++-
>>  arch/x86/cpu/queensbay/tnc_car.S | 11 ++++-------
>>  arch/x86/dts/crownbay.dts        |  7 +++++++
>>  3 files changed, 14 insertions(+), 8 deletions(-)
>>
>> diff --git a/Makefile b/Makefile
>> index fd24cde..d4e60e8 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -947,7 +947,9 @@ ifneq ($(CONFIG_X86_RESET_VECTOR),)
>>  rom: u-boot.rom FORCE
>>
>>  IFDTOOL=$(objtree)/tools/ifdtool
>> -IFDTOOL_FLAGS  = -w $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin
>> +IFDTOOL_FLAGS  = -f 0:$(objtree)/u-boot.dtb
>> +IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1)
>> +IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot.bin
>>  IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
>>
>>  ifneq ($(CONFIG_HAVE_INTEL_ME),)
>> diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S
>> index 6834a64..2e9139e 100644
>> --- a/arch/x86/cpu/queensbay/tnc_car.S
>> +++ b/arch/x86/cpu/queensbay/tnc_car.S
>> @@ -116,12 +116,9 @@ temp_ram_init_romstack:
>>         .long   temp_ram_init_ret
>>         .long   temp_ram_init_params
>>  temp_ram_init_params:
>> -       .long   ucode_start             /* microcode base */
>> -       .long   ucode_size              /* microcode size */
>> +_dt_ucode_base_size:
>> +       /* These next two fields are filled in by ifdtool */
>> +       .long   0                       /* microcode base */
>> +       .long   0                       /* microcode size */
>>         .long   CONFIG_SYS_MONITOR_BASE /* code region base */
>>         .long   CONFIG_SYS_MONITOR_LEN  /* code region size */
>> -
>> -       .balign 4
>> -ucode_start:
>> -       .include "arch/x86/cpu/queensbay/M0220661105.inc"
>> -ucode_size = ( . - ucode_start)
>> diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
>> index 399dafb..3f43f3c 100644
>> --- a/arch/x86/dts/crownbay.dts
>> +++ b/arch/x86/dts/crownbay.dts
>> @@ -50,4 +50,11 @@
>>                         memory-map = <0xffe00000 0x00200000>;
>>                 };
>>         };
>> +
>> +       microcode {
>> +               update at 0 {
>> +#include "microcode/m0220661105_cv.dtsi"
>> +               };
>> +       };
>> +
>>  };
>> --
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 04/15] x86: ich6-gpio: Add Intel Tunnel Creek GPIO support

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> Intel Tunnel Creek GPIO register block is compatible with current
> ich6-gpio driver, except the offset and content of GPIO block base
> address register in the LPC PCI configuration space are different.
>
> Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
> registers so that it could support both Ivybridge and Tunnel Creek.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Add a comment to explain we don't need check bit0 in GPIO base
>   address register
> - Add setup_pch_gpios() in crownbay.c
>
>  arch/x86/include/asm/arch-queensbay/gpio.h | 13 +++++++++++++
>  arch/x86/include/asm/gpio.h                |  4 ++--
>  board/coreboot/coreboot/coreboot.c         |  2 +-
>  board/google/chromebook_link/link.c        |  2 +-
>  board/intel/crownbay/crownbay.c            |  5 +++++
>  drivers/gpio/intel_ich6_gpio.c             | 20 ++++++++++++--------
>  6 files changed, 34 insertions(+), 12 deletions(-)
>  create mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 05/15] x86: Enable the queensbay cpu directory build

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/Makefile | 1 +
>  1 file changed, 1 insertion(+)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 06/15] x86: Add queensbay and crownbay Kconfig files

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Fix several typos in queensbay/Kconfig
> - Change FSP_FILE and CMC_FILE description to indicate the file is
>   in the board directory
> - Add help for FSP_TEMP_RAM_ADDR
> - Add more help for CMC_FILE
>
>  arch/x86/Kconfig               | 13 +++++++
>  arch/x86/cpu/queensbay/Kconfig | 79 ++++++++++++++++++++++++++++++++++++++++++
>  board/intel/crownbay/Kconfig   | 20 +++++++++++
>  3 files changed, 112 insertions(+)
>  create mode 100644 arch/x86/cpu/queensbay/Kconfig
>  create mode 100644 board/intel/crownbay/Kconfig

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 07/15] x86: Add crownbay defconfig and config.h

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  configs/crownbay_defconfig |  6 ++++++
>  include/configs/crownbay.h | 52 ++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 58 insertions(+)
>  create mode 100644 configs/crownbay_defconfig
>  create mode 100644 include/configs/crownbay.h

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 08/15] x86: Use consistent name XXX_ADDR for binary blob flash address

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - New patch to use consistent name XXX_ADDR for binary blobs
>
>  Makefile                             | 2 +-
>  arch/x86/cpu/ivybridge/sdram.c       | 2 +-
>  arch/x86/cpu/queensbay/Kconfig       | 4 ++--
>  arch/x86/cpu/queensbay/fsp_support.c | 2 +-
>  arch/x86/cpu/queensbay/tnc_car.S     | 2 +-
>  include/configs/chromebook_link.h    | 2 +-
>  6 files changed, 7 insertions(+), 7 deletions(-)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 09/15] x86: Include FSP and CMC binary in the u-boot.rom build rules

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Update ifdtool flags to indicate FSP and CMC files are in
>   the board directory
> - Use consistent XXX_FILE name for binary blob file
>
>  Makefile                          | 10 +++++++++-
>  include/configs/chromebook_link.h |  2 +-
>  2 files changed, 10 insertions(+), 2 deletions(-)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 10/15] x86: crownbay: Add SPI flash support

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> The Crown Bay board has an SST25VF016B flash connected to the Tunnel
> Creek processor SPI controller used as the BIOS media where U-Boot
> is stored. Enable this flash support.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4: None
> Changes in v3:
> - Add a commit message for the SPI support
>
> Changes in v2:
> - Move PCH_LPC_DEV to arch/x86/include/asm/arch-queensbay/tnc.h
> - Check return value of x86_cpu_init_f()
>
>  arch/x86/cpu/queensbay/tnc.c              | 26 +++++++++++++++++++++++++-
>  arch/x86/include/asm/arch-queensbay/tnc.h | 15 +++++++++++++++
>  include/configs/crownbay.h                |  2 ++
>  3 files changed, 42 insertions(+), 1 deletion(-)
>  create mode 100644 arch/x86/include/asm/arch-queensbay/tnc.h

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 11/15] x86: crownbay: Enable Intel E1000 NIC support

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
> controller for now, so enable the Intle E1000 NIC support, which
> can be plugged into any PCIe slot on the Crown Bay board.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  board/intel/crownbay/crownbay.c | 6 ++++++
>  include/configs/crownbay.h      | 1 +
>  2 files changed, 7 insertions(+)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 12/15] x86: crownbay: Add SDHCI support

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> There are two standard SD card slots on the Crown Bay board, which
> are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
> support so that we can use them.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Use ARRAY_SIZE(mmc_supported) instead of 2
> - Check return value of add_sdhci()
>
>  arch/x86/cpu/queensbay/Makefile   |  2 +-
>  arch/x86/cpu/queensbay/topcliff.c | 47 +++++++++++++++++++++++++++++++++++++++
>  include/configs/crownbay.h        |  6 +++++
>  3 files changed, 54 insertions(+), 1 deletion(-)
>  create mode 100644 arch/x86/cpu/queensbay/topcliff.c

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 13/15] x86: Rename coreboot-serial to x86-serial

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - New patch to rename coreboot-serial to x86-serial
>
>  arch/x86/dts/coreboot.dtsi                         |  2 +-
>  drivers/serial/Makefile                            |  2 +-
>  drivers/serial/{serial_coreboot.c => serial_x86.c} | 12 ++++++------
>  include/configs/chromebook_link.h                  |  2 +-
>  include/configs/coreboot.h                         |  2 +-
>  include/configs/crownbay.h                         |  2 +-
>  6 files changed, 11 insertions(+), 11 deletions(-)
>  rename drivers/serial/{serial_coreboot.c => serial_x86.c} (67%)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 14/15] x86: Add a README.x86 for U-Boot on x86 support

[Simon Glass]

On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4:
> - Minor update per review comments from Pavel Machek
>
> Changes in v3: None
> Changes in v2:
> - Remove the 'make menuconfig' in the crownbay build instructions
> - Indicate all the binary blobs should be put in the board directory
>
>  doc/README.x86 | 126 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 126 insertions(+)
>  create mode 100644 doc/README.x86

I also fixed up the 'Link' reference.

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 15/15] x86: Clean up the FSP support codes

[Simon Glass]

On 17 December 2014 at 07:41, Simon Glass <sjg@chromium.org> wrote:
> On 17 December 2014 at 00:50, Bin Meng <bmeng.cn@gmail.com> wrote:
>> This is the follow-on patch to clean up the FSP support codes:
>>
>> - Remove the _t suffix on the structures defines
>> - Use __packed for structure defines
>> - Use U-Boot's assert()
>> - Use standard bool true/false
>> - Remove read_unaligned64()
>> - Use memcmp() in the compare_guid()
>> - Remove the cast in the memset() call
>> - Replace some magic numbers with macros
>> - Use panic() when no valid FSP image header is found
>> - Change some FSP utility routines to use an fsp_ prefix
>> - Add comment blocks for asm_continuation and fsp_init_done
>> - Remove some casts in find_fsp_header()
>> - Change HOB access macros to static inline routines
>> - Add comments to mention find_fsp_header() may be called in a
>>   stackless environment
>> - Add comments to mention init(&params) in fsp_init() cannot
>>   be removed
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> ---
>>
>> Changes in v4:
>> - Use __packed for structure defines
>> - Fix some typos and print FSP full name in cmd_hob.c
>>
>> Changes in v3: None
>> Changes in v2:
>> - Remove some casts in find_fsp_header()
>> - Change HOB access macros to static inline routines
>>
>>  arch/x86/cpu/queensbay/fsp_configs.c               |   2 +-
>>  arch/x86/cpu/queensbay/fsp_support.c               | 253 ++++++++++-----------
>>  arch/x86/cpu/queensbay/tnc_dram.c                  |  18 +-
>>  arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h  |  18 +-
>>  arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h  |  28 +--
>>  arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h   |  14 +-
>>  arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h  | 112 +++++----
>>  .../asm/arch-queensbay/fsp/fsp_infoheader.h        |   6 +-
>>  .../include/asm/arch-queensbay/fsp/fsp_platform.h  |   8 +-
>>  .../include/asm/arch-queensbay/fsp/fsp_support.h   |  63 ++---
>>  .../x86/include/asm/arch-queensbay/fsp/fsp_types.h |  17 +-
>>  arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h  |   8 +-
>>  arch/x86/lib/cmd_hob.c                             |  22 +-
>>  13 files changed, 279 insertions(+), 290 deletions(-)
>>
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-x86, thanks!