[PATCH 0/3] Export GT config attributes

[PATCH 0/3] Export GT config attributes

[jeff.mcgee]

From: Jeff McGee <jeff.mcgee@intel.com>

The motivation for this change is that fusing can be used to create
multiple slice, subslice, and EU configuration within the same PCI
ID. CHV is the first such device to do this and thus make an ID-based
lookup table approach unreliable. The best solution is for the kernel
to determine the precise config from fuse registers and share the
required information with userspace. Moving to this approach has the
added benefit of reducing the number of static parameters that
userspace must maintain for current and future devices.

I'll be posting the libdrm and igt components next. I'm in the
process of collecting userspace support for this new interface.
I think the basic idea here is clear. With regards to which
attributes should be included, I am just starting with these 4. I can
add or remove attributes based on the feedback from userspace.
Please provide any comments. Thanks

Jeff McGee (3):
  drm/i915: Export GT config attributes
  drm/i915/chv: Determine CHV GT config attributes
  drm/i915/bdw: Determine BDW GT config attributes

 drivers/gpu/drm/i915/i915_dma.c | 56 +++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |  5 ++++
 drivers/gpu/drm/i915/i915_reg.h | 24 ++++++++++++++++++
 include/uapi/drm/i915_drm.h     |  4 +++
 4 files changed, 89 insertions(+)

-- 
2.2.0

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[PATCH 1/3] drm/i915: Export GT config attributes

[jeff.mcgee]

From: Jeff McGee <jeff.mcgee@intel.com>

Setup new I915_GETPARAM ioctl entries for slice total, subslice
total, EU total, and threads per EU, so that userspace can query
the kernel for the values of these attributes instead of maintaining
individual lookup tables which must be indexed by PCI ID.

The motivation for this change is that fusing can be used to create
multiple slice, subslice, and EU configuration within the same PCI
ID. CHV is the first such device to do this and thus make an ID-based
lookup table approach unreliable. The best solution is for the kernel
to determine the precise config from fuse registers and share the
required information with userspace. Moving to this approach has the
added benefit of reducing the number of static parameters that
userspace must maintain for current and future devices.

The kernel detection of these values is device-specific and not
included in this patch. Because zero is not a valid value for any of
these parameters, a value of zero is interpreted as unknown for the
device.

For: VIZ-4636
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 20 ++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |  5 +++++
 include/uapi/drm/i915_drm.h     |  4 ++++
 3 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 52730ed..a6634e6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -143,6 +143,26 @@ static int i915_getparam(struct drm_device *dev, void *data,
 	case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 		value = 1;
 		break;
+	case I915_PARAM_SLICE_TOTAL:
+		value = INTEL_INFO(dev)->slice_total;
+		if (!value)
+			return -ENODEV;
+		break;
+	case I915_PARAM_SUBSLICE_TOTAL:
+		value = INTEL_INFO(dev)->subslice_total;
+		if (!value)
+			return -ENODEV;
+		break;
+	case I915_PARAM_EU_TOTAL:
+		value = INTEL_INFO(dev)->eu_total;
+		if (!value)
+			return -ENODEV;
+		break;
+	case I915_PARAM_THREADS_PER_EU:
+		value = INTEL_INFO(dev)->threads_per_eu;
+		if (!value)
+			return -ENODEV;
+		break;
 	default:
 		DRM_DEBUG("Unknown parameter %d\n", param->param);
 		return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 921e4c5..02afb29 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -653,6 +653,11 @@ struct intel_device_info {
 	int trans_offsets[I915_MAX_TRANSCODERS];
 	int palette_offsets[I915_MAX_PIPES];
 	int cursor_offsets[I915_MAX_PIPES];
+
+	unsigned int slice_total;
+	unsigned int subslice_total;
+	unsigned int eu_total;
+	unsigned int threads_per_eu;
 };
 
 #undef DEFINE_FLAG
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2502622..5fd37b9 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -341,6 +341,10 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_HAS_WT     	 	 27
 #define I915_PARAM_CMD_PARSER_VERSION	 28
 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
+#define I915_PARAM_SLICE_TOTAL		 30
+#define I915_PARAM_SUBSLICE_TOTAL	 31
+#define I915_PARAM_EU_TOTAL		 32
+#define I915_PARAM_THREADS_PER_EU	 33
 
 typedef struct drm_i915_getparam {
 	int param;
-- 
2.2.0

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[PATCH 2/3] drm/i915/chv: Determine CHV GT config attributes

[jeff.mcgee]

From: Jeff McGee <jeff.mcgee@intel.com>

Cherryview fusing allows for different EU totals within a single
device ID, so fused-based detection is a must. Go ahead and determine
subslice total from fuse as well just in case. Slice total and
threads per EU are fixed for all CHV.

For: VIZ-4636
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a6634e6..0ab8f3a 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -618,6 +618,24 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 			info->num_pipes = 0;
 		}
 	}
+
+	/* Initialize required GT attributes info */
+	if (IS_CHERRYVIEW(dev)) {
+		u32 reg, ss_dis, eu_dis;
+
+		reg = I915_READ(CHV_FUSE_GT);
+		ss_dis = reg & (CHV_FGT_DISABLE_SS0 |
+				CHV_FGT_DISABLE_SS1);
+		eu_dis = reg & (CHV_FGT_EU_DIS_SS0_R0_MASK |
+				CHV_FGT_EU_DIS_SS0_R1_MASK |
+				CHV_FGT_EU_DIS_SS1_R0_MASK |
+				CHV_FGT_EU_DIS_SS1_R1_MASK);
+
+		info->slice_total = 1;
+		info->subslice_total = 2 - hweight32(ss_dis);
+		info->eu_total = 16 - hweight32(eu_dis);
+		info->threads_per_eu = 7;
+	}
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 40ca873..f60119c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6127,6 +6127,19 @@ enum punit_power_well {
 #define GEN7_MISCCPCTL			(0x9424)
 #define   GEN7_DOP_CLOCK_GATE_ENABLE	(1<<0)
 
+/* Fuse readout registers for GT */
+#define CHV_FUSE_GT			0x182168
+#define   CHV_FGT_DISABLE_SS0		10
+#define   CHV_FGT_DISABLE_SS1		11
+#define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
+#define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
+#define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
+#define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
+#define   CHV_FGT_EU_DIS_SS1_R0_SHIFT	24
+#define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
+#define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
+#define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1			0xB008 /* L3CD Error Status 1 */
 #define HSW_L3CDERRST11			0xB208 /* L3CD Error Status register 1 slice 1 */
-- 
2.2.0

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[PATCH 3/3] drm/i915/bdw: Determine BDW GT config attributes

[jeff.mcgee]

From: Jeff McGee <jeff.mcgee@intel.com>

Broadwell values could be tabulated by device ID, but we go ahead
and detect from fuses because it is easier and more flexible.

For: VIZ-4636
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 20 +++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 0ab8f3a..023d010 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -620,7 +620,25 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 	}
 
 	/* Initialize required GT attributes info */
-	if (IS_CHERRYVIEW(dev)) {
+	if (IS_BROADWELL(dev)) {
+		u32 fuse2, eu_dis0, eu_dis1, eu_dis2, s_ena, ss_dis;
+
+		fuse2 = I915_READ(GEN8_FUSE2);
+		eu_dis0 = I915_READ(GEN8_EU_DISABLE0);
+		eu_dis1 = I915_READ(GEN8_EU_DISABLE1);
+		eu_dis2 = I915_READ(GEN8_EU_DISABLE2);
+		s_ena = fuse2 & GEN8_F2_S_ENA_MASK;
+		ss_dis = fuse2 & GEN8_F2_SS_DIS_MASK;
+		eu_dis2 &= GEN8_EU_DIS2_S2_SS2_MASK;
+
+		info->slice_total = hweight32(s_ena);
+		info->subslice_total = (3 - hweight32(ss_dis)) *
+				       info->slice_total;
+		info->eu_total = 72 - (hweight32(eu_dis0) +
+				       hweight32(eu_dis1) +
+				       hweight32(eu_dis2));
+		info->threads_per_eu = 7;
+	} else if (IS_CHERRYVIEW(dev)) {
 		u32 reg, ss_dis, eu_dis;
 
 		reg = I915_READ(CHV_FUSE_GT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f60119c..b08747c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6140,6 +6140,17 @@ enum punit_power_well {
 #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
 #define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
 
+#define GEN8_FUSE2			0x9120
+#define   GEN8_F2_SS_DIS_SHIFT		21
+#define   GEN8_F2_SS_DIS_MASK		(0x7 << GEN8_F2_SS_DIS_SHIFT)
+#define   GEN8_F2_S_ENA_SHIFT		25
+#define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)
+
+#define GEN8_EU_DISABLE0		0x9134
+#define GEN8_EU_DISABLE1		0x9138
+#define GEN8_EU_DISABLE2		0x913c
+#define   GEN8_EU_DIS2_S2_SS2_MASK	(0xff)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1			0xB008 /* L3CD Error Status 1 */
 #define HSW_L3CDERRST11			0xB208 /* L3CD Error Status register 1 slice 1 */
-- 
2.2.0

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Re: [PATCH 0/3] Export GT config attributes

[Jeff McGee]

Link to the libdrm and igt patches corresponding to this change:

http://lists.freedesktop.org/archives/dri-devel/2014-December/074296.html
http://lists.freedesktop.org/archives/intel-gfx/2014-December/057821.html
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