* [RFC PATCHv2 0/8] devfreq: Add generic exynos memory-bus frequency driver
@ 2014-12-31 5:19 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: myungjoo.ham
Cc: kgene.kim, kyungmin.park, rafael.j.wysocki, mark.rutland,
a.kesavan, tomasz.figa, k.kozlowski, b.zolnierkie, cw00.choi,
inki.dae, linux-pm, linux-kernel, linux-arm-kernel,
linux-samsung-soc
This patch-set adds the generic exynos bus frequency driver for memory bus
with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
support the memory bus frequency driver for Exynos SoCs.
Each memory bus block has a clock for memory bus speed and frequency
table which is changed according to the utilization of memory bus on runtime.
And then each memory bus group has the one more memory bus blocks and
OPP table (including frequency and voltage), regulator, devfreq-event
devices.
There are a little difference about the number of memory bus because each Exynos
SoC have the different sub-IP and different memory bus speed. In spite of this
difference among Exynos SoCs, we can support almost Exynos SoC by adding
unique data of memory bus to devicetree file.
This patch-set has the dependency on following patch-set[1]:
[1] [PATCHv6 0/9] devfreq: Add devfreq-event class to provide raw data for devfreq device
- https://lkml.org/lkml/2014/12/28/139
Changes from v1:
- This patchset is rebased on v3.19-rc2.
- Fix bug after wake-up from suspend state. If devfreq device fail to get event,
exynos-busfreq retry to set the event for starting.
- Add memory bus group of Exynos4x12/Exynos4210
- Add divider clock id for Exynos4 memory bus frequency
- Support memory bus frequency driver on Exynos4412-based TRATS2 board
Chanwoo Choi (8):
devfreq: exynos: Add generic exynos memory bus frequency driver
devfreq: exynos: Add documentation for generic exynos memory bus frequency driver
ARM: dts: Add memory bus node for Exynos3250
clk: samsung: exynos4: Add divider clock id for memory bus frequency
ARM: dts: Add memory bus node for Exynos4x12
ARM: dts: Add memory bus node for Exynos4210
ARM: dts: Add memory bus node for Exynos3250-based Rinato board
ARM: dts: Add memory bus node for Exynos4412-based TRATS2 board
.../devicetree/bindings/devfreq/exynos-busfreq.txt | 184 +++++++
arch/arm/boot/dts/exynos3250-rinato.dts | 12 +
arch/arm/boot/dts/exynos3250.dtsi | 125 +++++
arch/arm/boot/dts/exynos4210.dtsi | 93 ++++
arch/arm/boot/dts/exynos4412-trats2.dts | 12 +
arch/arm/boot/dts/exynos4x12.dtsi | 121 +++++
drivers/clk/samsung/clk-exynos4.c | 10 +-
drivers/devfreq/Kconfig | 15 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/exynos-busfreq.c | 588 +++++++++++++++++++++
include/dt-bindings/clock/exynos4.h | 7 +-
11 files changed, 1162 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
create mode 100644 drivers/devfreq/exynos-busfreq.c
--
1.8.5.5
^ permalink raw reply [flat|nested] 20+ messages in thread
* [RFC PATCHv2 0/8] devfreq: Add generic exynos memory-bus frequency driver
@ 2014-12-31 5:19 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: linux-arm-kernel
This patch-set adds the generic exynos bus frequency driver for memory bus
with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
support the memory bus frequency driver for Exynos SoCs.
Each memory bus block has a clock for memory bus speed and frequency
table which is changed according to the utilization of memory bus on runtime.
And then each memory bus group has the one more memory bus blocks and
OPP table (including frequency and voltage), regulator, devfreq-event
devices.
There are a little difference about the number of memory bus because each Exynos
SoC have the different sub-IP and different memory bus speed. In spite of this
difference among Exynos SoCs, we can support almost Exynos SoC by adding
unique data of memory bus to devicetree file.
This patch-set has the dependency on following patch-set[1]:
[1] [PATCHv6 0/9] devfreq: Add devfreq-event class to provide raw data for devfreq device
- https://lkml.org/lkml/2014/12/28/139
Changes from v1:
- This patchset is rebased on v3.19-rc2.
- Fix bug after wake-up from suspend state. If devfreq device fail to get event,
exynos-busfreq retry to set the event for starting.
- Add memory bus group of Exynos4x12/Exynos4210
- Add divider clock id for Exynos4 memory bus frequency
- Support memory bus frequency driver on Exynos4412-based TRATS2 board
Chanwoo Choi (8):
devfreq: exynos: Add generic exynos memory bus frequency driver
devfreq: exynos: Add documentation for generic exynos memory bus frequency driver
ARM: dts: Add memory bus node for Exynos3250
clk: samsung: exynos4: Add divider clock id for memory bus frequency
ARM: dts: Add memory bus node for Exynos4x12
ARM: dts: Add memory bus node for Exynos4210
ARM: dts: Add memory bus node for Exynos3250-based Rinato board
ARM: dts: Add memory bus node for Exynos4412-based TRATS2 board
.../devicetree/bindings/devfreq/exynos-busfreq.txt | 184 +++++++
arch/arm/boot/dts/exynos3250-rinato.dts | 12 +
arch/arm/boot/dts/exynos3250.dtsi | 125 +++++
arch/arm/boot/dts/exynos4210.dtsi | 93 ++++
arch/arm/boot/dts/exynos4412-trats2.dts | 12 +
arch/arm/boot/dts/exynos4x12.dtsi | 121 +++++
drivers/clk/samsung/clk-exynos4.c | 10 +-
drivers/devfreq/Kconfig | 15 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/exynos-busfreq.c | 588 +++++++++++++++++++++
include/dt-bindings/clock/exynos4.h | 7 +-
11 files changed, 1162 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
create mode 100644 drivers/devfreq/exynos-busfreq.c
--
1.8.5.5
^ permalink raw reply [flat|nested] 20+ messages in thread
* [RFC PATCHv2 1/8] devfreq: exynos: Add generic exynos memory bus frequency driver
2014-12-31 5:19 ` Chanwoo Choi
@ 2014-12-31 5:19 ` Chanwoo Choi
-1 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: myungjoo.ham
Cc: kgene.kim, kyungmin.park, rafael.j.wysocki, mark.rutland,
a.kesavan, tomasz.figa, k.kozlowski, b.zolnierkie, cw00.choi,
inki.dae, linux-pm, linux-kernel, linux-arm-kernel,
linux-samsung-soc
This patch adds the generic exynos bus frequency driver for memory bus
with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
support the memory bus frequency driver for Exynos SoCs.
Each memory bus block has a clock for memory bus speed and frequency
table which is changed according to the utilization of memory bus on runtime.
And then each memory bus group has the one more memory bus blocks and
OPP table (including frequency and voltage), regulator, devfreq-event
devices.
There are a little difference about the number of memory bus because each Exynos
SoC have the different sub-IP and different memory bus speed. In spite of this
difference among Exynos SoCs, we can support almost Exynos SoC by adding
unique data of memory bus to devicetree file.
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/devfreq/Kconfig | 15 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/exynos-busfreq.c | 588 +++++++++++++++++++++++++++++++++++++++
3 files changed, 604 insertions(+)
create mode 100644 drivers/devfreq/exynos-busfreq.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 21f8f17..f1003eb 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -65,6 +65,21 @@ config DEVFREQ_GOV_USERSPACE
comment "DEVFREQ Drivers"
+config ARM_EXYNOS_BUS_DEVFREQ
+ bool "EXYNOS Memory Bus DEVFREQ Driver"
+ depends on ARCH_EXYNOS
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
+ select DEVFREQ_EVENT_EXYNOS_PPMU
+ select PM_DEVFREQ_EVENT
+ select PM_OPP
+ help
+ This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
+ Memory bus has one more group of memory bus (e.g, MIF and INT block).
+ Each memory bus group could contain many memoby bus block. It reads
+ PPMU counters of memory controllers by using DEVFREQ-event device
+ and adjusts the operating frequencies and voltages with OPP support.
+ This does not yet operate with optimal voltages.
+
config ARM_EXYNOS4_BUS_DEVFREQ
bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index c449336..2b82a4c 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o
# DEVFREQ Drivers
+obj-$(CONFIG_ARCH_EXYNOS) += exynos-busfreq.o
obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/
obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/
diff --git a/drivers/devfreq/exynos-busfreq.c b/drivers/devfreq/exynos-busfreq.c
new file mode 100644
index 0000000..3c92541
--- /dev/null
+++ b/drivers/devfreq/exynos-busfreq.c
@@ -0,0 +1,588 @@
+/*
+ * Generic Exynos Memory Bus Frequency driver with DEVFREQ Framework
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author : Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This driver is based on exynos4_bus.c, which was written
+ * by MyungJoo Ham <myungjoo.ham@samsung.com>, Samsung Electronics.
+ *
+ * This driver support Exynos Memory Bus frequency feature by using in DEVFREQ
+ * framework. This version supprots Exynos3250/Exynos4 series/Exynos5260 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq.h>
+#include <linux/devfreq-event.h>
+#include <linux/device.h>
+#include <linux/export.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_opp.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+
+#define BUS_SATURATION_RATIO 40
+#define SAFEVOLT 50000
+
+struct exynos_memory_bus_opp_info {
+ unsigned long rate;
+ unsigned long volt;
+};
+
+struct exynos_memory_bus_block {
+ struct clk *clk;
+ struct exynos_memory_bus_opp_info *freq_table;
+};
+
+struct exynos_memory_bus_data {
+ /* devfreq device to monitor and control memory bus group */
+ struct device *dev;
+ struct devfreq *devfreq;
+
+ struct exynos_memory_bus_opp_info *freq_table;
+ unsigned int freq_count;
+ struct regulator *regulator;
+ struct mutex lock;
+
+ struct exynos_memory_bus_opp_info curr_opp;
+
+ struct exynos_memory_bus_block *block;
+ unsigned int block_count;
+
+ /* devfreq-event device to get current state of memory bus group */
+ struct devfreq_event_dev **edev;
+ unsigned int edev_count;
+};
+
+/*
+ * Initialize the memory bus group/block by parsing dt node in the devicetree
+ */
+static int of_init_memory_bus(struct device_node *np,
+ struct exynos_memory_bus_data *data)
+{
+ struct device *dev = data->dev;
+ struct dev_pm_opp *opp;
+ unsigned long rate, volt;
+ int i, ret, count, size;
+
+ /* Get the freq/voltage OPP table to scale memory bus frequency */
+ ret = of_init_opp_table(dev);
+ if (ret < 0) {
+ dev_err(dev, "failed to get OPP table\n");
+ return ret;
+ }
+
+ rcu_read_lock();
+
+ data->freq_count = dev_pm_opp_get_opp_count(dev);
+ if (data->freq_count <= 0) {
+ dev_err(dev, "failed to get the count of OPP entry\n");
+ rcu_read_unlock();
+ return -EINVAL;
+ }
+
+ size = sizeof(*data->freq_table) * data->freq_count;
+ data->freq_table = devm_kzalloc(dev, size, GFP_KERNEL);
+ if (!data->freq_table) {
+ rcu_read_unlock();
+ return -ENOMEM;
+ }
+
+ for (i = 0, rate = 0; i < data->freq_count; i++, rate++) {
+ opp = dev_pm_opp_find_freq_ceil(dev, &rate);
+ if (IS_ERR(opp)) {
+ dev_err(dev, "failed to find dev_pm_opp\n");
+ rcu_read_unlock();
+ return PTR_ERR(opp);
+ }
+
+ volt = dev_pm_opp_get_voltage(opp);
+
+ data->freq_table[i].rate = rate;
+ data->freq_table[i].volt = volt;
+
+ dev_dbg(dev, "%d : frequency(%ld), voltage(%ld)\n",
+ i, rate, volt);
+ }
+
+ rcu_read_unlock();
+
+ /* Get the regulator to provide memory bus group with the power */
+ data->regulator = devm_regulator_get(dev, "vdd-mem");
+ if (IS_ERR(data->regulator)) {
+ dev_err(dev, "failed to get vdd-memory regulator\n");
+ return PTR_ERR(data->regulator);
+ }
+
+ ret = regulator_enable(data->regulator);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable vdd-memory regulator\n");
+ return ret;
+ }
+
+ /*
+ * Get the devfreq-event devices to get the current state of
+ * memory bus group. This raw data will be used in devfreq governor.
+ */
+ count = devfreq_event_get_edev_count(dev);
+ if (count < 0) {
+ dev_err(dev, "failed to get the count of devfreq-event dev\n");
+ return count;
+ }
+ data->edev_count = count;
+
+ size = sizeof(*data->edev) * count;
+ data->edev = devm_kzalloc(dev, size, GFP_KERNEL);
+ if (!data->edev)
+ return -ENOMEM;
+
+ for (i = 0; i < count; i++) {
+ data->edev[i] = devfreq_event_get_edev_by_phandle(dev, i);
+ if (IS_ERR(data->edev[i])) {
+ of_free_opp_table(dev);
+ return -EPROBE_DEFER;
+ }
+ }
+
+ return 0;
+}
+
+static int of_init_memory_bus_block(struct device_node *np,
+ struct exynos_memory_bus_data *data)
+{
+ struct exynos_memory_bus_block *block;
+ struct device *dev = data->dev;
+ struct device_node *buses_np, *node;
+ int i, count;
+
+ buses_np = of_get_child_by_name(np, "blocks");
+ if (!buses_np) {
+ dev_err(dev,
+ "failed to get child node of memory bus\n");
+ return -EINVAL;
+ }
+
+ count = of_get_child_count(buses_np);
+ block = devm_kzalloc(dev, sizeof(*block) * count, GFP_KERNEL);
+ if (!block)
+ return -ENOMEM;
+ data->block = block;
+ data->block_count = count;
+
+ /* Parse the information of memory bus block */
+ i = 0;
+ for_each_child_of_node(buses_np, node) {
+ const struct property *prop;
+ const __be32 *val;
+ int j, nr, size;
+
+ block = &data->block[i++];
+
+ /* Get the frequency table of each memory bus block */
+ prop = of_find_property(node, "frequency", NULL);
+ if (!prop)
+ return -ENODEV;
+ if (!prop->value)
+ return -ENODATA;
+
+ nr = prop->length / sizeof(u32);
+ if (!nr)
+ return -EINVAL;
+
+ if (nr != data->freq_count) {
+ dev_err(dev, "the size of frequency table is different \
+ from OPP table\n");
+ return -EINVAL;
+ }
+
+ size = sizeof(*block->freq_table) * nr;
+ block->freq_table = devm_kzalloc(dev, size, GFP_KERNEL);
+ if (!block->freq_table)
+ return -ENOMEM;
+
+ val = prop->value;
+ for (j = nr - 1; j >= 0; j--)
+ block->freq_table[j].rate = be32_to_cpup(val++) * 1000;
+
+ for (j = 0; j < nr; j++)
+ dev_dbg(dev, "%s: %d : frequency(%ld)\n",
+ node->name, j, block->freq_table[j].rate);
+ dev_dbg(dev, "\n");
+
+ /* Get the clock of each memory bus block */
+ block->clk = of_clk_get_by_name(node, "memory-bus");
+ if (IS_ERR(block->clk)) {
+ dev_err(dev, "failed to get memory-bus clock in %s\n",
+ node->name);
+ return PTR_ERR(block->clk);
+ }
+ clk_prepare_enable(block->clk);
+
+ of_node_put(node);
+ }
+
+ of_node_put(buses_np);
+
+ return 0;
+}
+
+/*
+ * Control the devfreq-event device to get the current state of memory bus
+ */
+static int exynos_busfreq_enable_edev(struct exynos_memory_bus_data *data)
+{
+ int i, ret;
+
+ for (i = 0; i < data->edev_count; i++) {
+ ret = devfreq_event_enable_edev(data->edev[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int exynos_busfreq_disable_edev(struct exynos_memory_bus_data *data)
+{
+ int i, ret;
+
+ for (i = 0; i < data->edev_count; i++) {
+ ret = devfreq_event_disable_edev(data->edev[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+
+static int exynos_busfreq_set_event(struct exynos_memory_bus_data *data)
+{
+ int i, ret;
+
+ for (i = 0; i < data->edev_count; i++) {
+ ret = devfreq_event_set_event(data->edev[i],
+ DEVFREQ_EVENT_TYPE_RAW_DATA);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int exynos_busfreq_get_event(struct exynos_memory_bus_data *data,
+ struct devfreq_event_data *edata)
+{
+ struct devfreq_event_data curr_edata;
+ unsigned long event, total_event;
+ int i, ret = 0;
+
+ for (i = 0; i < data->edev_count; i++) {
+ ret = devfreq_event_get_event(data->edev[i],
+ DEVFREQ_EVENT_TYPE_RAW_DATA,
+ &curr_edata);
+ if (ret < 0)
+ return ret;
+
+ if (i == 0 || curr_edata.event > event) {
+ event = curr_edata.event;
+ total_event = curr_edata.total_event;
+ }
+ }
+
+ edata->event = event;
+ edata->total_event = total_event;
+
+ return ret;
+}
+
+/*
+ * Must necessary function for devfreq governor
+ */
+
+static int exynos_busfreq_set_frequency(struct exynos_memory_bus_data *data,
+ struct exynos_memory_bus_opp_info *new_opp)
+{
+ int i, j;
+
+ for (i = 0; i < data->freq_count; i++)
+ if (new_opp->rate == data->freq_table[i].rate)
+ break;
+
+ if (i == data->freq_count)
+ i = data->freq_count - 1;
+
+ for (j = 0; j < data->block_count; j++)
+ clk_set_rate(data->block[j].clk,
+ data->block[j].freq_table[i].rate);
+
+ return 0;
+}
+
+static int exynos_busfreq_target(struct device *dev, unsigned long *freq,
+ u32 flags)
+{
+ struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
+ struct exynos_memory_bus_opp_info new_opp;
+ unsigned long new_freq, old_freq;
+ struct dev_pm_opp *opp;
+ int ret = 0;
+
+ /* Get new opp-info instance according to new busfreq clock */
+ rcu_read_lock();
+ opp = devfreq_recommended_opp(dev, freq, flags);
+ if (IS_ERR_OR_NULL(opp)) {
+ dev_err(dev, "failed to get recommed opp instance\n");
+ rcu_read_unlock();
+ return PTR_ERR(opp);
+ }
+ new_opp.rate = dev_pm_opp_get_freq(opp);
+ new_opp.volt = dev_pm_opp_get_voltage(opp);
+ rcu_read_unlock();
+
+ old_freq = data->curr_opp.rate;
+ new_freq = new_opp.rate;
+ if (old_freq == new_freq)
+ return 0;
+
+ dev_dbg(dev, "Change the frequency of memory bus (%ld kHz -> %ld kHz)\n",
+ old_freq / 1000, new_freq / 1000);
+
+ /* Change voltage/clock according to new busfreq level */
+ mutex_lock(&data->lock);
+
+ if (old_freq < new_freq) {
+ ret = regulator_set_voltage(data->regulator, new_opp.volt,
+ new_opp.volt + SAFEVOLT);
+ if (ret < 0) {
+ dev_err(data->dev, "failed to set voltage\n");
+ regulator_set_voltage(data->regulator,
+ data->curr_opp.rate,
+ data->curr_opp.rate + SAFEVOLT);
+ goto out;
+ }
+ }
+
+ exynos_busfreq_set_frequency(data, &new_opp);
+ if (ret < 0) {
+ dev_err(dev, "failed to change clock of memory bus\n");
+ goto out;
+ }
+
+ if (old_freq > new_freq) {
+ ret = regulator_set_voltage(data->regulator, new_opp.volt,
+ new_opp.volt + SAFEVOLT);
+ if (ret < 0) {
+ dev_err(data->dev, "failed to set voltage\n");
+ regulator_set_voltage(data->regulator,
+ data->curr_opp.rate,
+ data->curr_opp.rate + SAFEVOLT);
+ goto out;
+ }
+ }
+
+ data->curr_opp = new_opp;
+
+out:
+ mutex_unlock(&data->lock);
+
+ return ret;
+}
+
+static int exynos_busfreq_get_dev_status(struct device *dev,
+ struct devfreq_dev_status *stat)
+{
+ struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
+ struct devfreq_event_data edata;
+ int ret;
+
+ stat->current_frequency = data->curr_opp.rate;
+
+ ret = exynos_busfreq_get_event(data, &edata);
+ if (ret < 0) {
+ stat->total_time = stat->busy_time = 0;
+ goto err;
+ }
+
+ stat->busy_time = (edata.event * 100) / BUS_SATURATION_RATIO;
+ stat->total_time = edata.total_event;
+
+err:
+ ret = exynos_busfreq_set_event(data);
+ if (ret < 0) {
+ dev_err(dev, "failed to set event to devfreq-event devices\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+static void exynos_busfreq_exit(struct device *dev)
+{
+ struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
+ int i, ret;
+
+ ret = exynos_busfreq_disable_edev(data);
+ if (ret < 0)
+ dev_warn(dev, "failed to disable the devfreq-event devices\n");
+
+ for (i = 0; i < data->block_count; i++)
+ clk_disable_unprepare(data->block[i].clk);
+
+ if (regulator_is_enabled(data->regulator))
+ regulator_disable(data->regulator);
+
+ of_free_opp_table(dev);
+}
+
+static struct devfreq_dev_profile exynos_memory_bus_profile = {
+ .polling_ms = 100,
+ .target = exynos_busfreq_target,
+ .get_dev_status = exynos_busfreq_get_dev_status,
+ .exit = exynos_busfreq_exit,
+};
+
+static struct devfreq_simple_ondemand_data exynos_memory_bus_ondemand_data = {
+ .upthreshold = 40,
+ .downdifferential = 5,
+};
+
+static int exynos_busfreq_probe(struct platform_device *pdev)
+{
+ struct exynos_memory_bus_data *data;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ if (!np) {
+ dev_err(dev, "failed to find devicetree node\n");
+ return -EINVAL;
+ }
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+ mutex_init(&data->lock);
+ data->dev = &pdev->dev;
+ platform_set_drvdata(pdev, data);
+
+ /* Initialize */
+ ret = of_init_memory_bus(np, data);
+ if (ret < 0) {
+ dev_err(dev, "failed to initialize memory-bus\n");
+ return ret;
+ }
+
+ ret = of_init_memory_bus_block(np, data);
+ if (ret < 0) {
+ dev_err(dev, "failed to initialize memory-bus block\n");
+ return ret;
+ }
+
+ /* Add devfreq device for DVFS of memory bus */
+ data->devfreq = devm_devfreq_add_device(dev,
+ &exynos_memory_bus_profile,
+ "simple_ondemand",
+ &exynos_memory_bus_ondemand_data);
+ if (IS_ERR_OR_NULL(data->devfreq)) {
+ dev_err(dev, "failed to add devfreq device\n");
+ return PTR_ERR(data->devfreq);
+ }
+
+ /* Register opp_notifier to catch the change of OPP */
+ ret = devm_devfreq_register_opp_notifier(dev, data->devfreq);
+ if (ret < 0) {
+ dev_err(dev, "failed to register opp notifier\n");
+ return ret;
+ }
+
+ /*
+ * Enable devfreq-event to get raw data which is used to determine
+ * current memory bus load.
+ */
+ ret = exynos_busfreq_enable_edev(data);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable devfreq-event devices\n");
+ return ret;
+ }
+
+ ret = exynos_busfreq_set_event(data);
+ if (ret < 0) {
+ dev_err(dev, "failed to set event to devfreq-event devices\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int exynos_busfreq_remove(struct platform_device *pdev)
+{
+ /*
+ * devfreq_dev_profile.exit() have to free the resource of this
+ * device driver.
+ */
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos_busfreq_resume(struct device *dev)
+{
+ struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
+ int ret;
+
+ ret = exynos_busfreq_enable_edev(data);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable the devfreq-event devices\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int exynos_busfreq_suspend(struct device *dev)
+{
+ struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
+ int ret;
+
+ ret = exynos_busfreq_disable_edev(data);
+ if (ret < 0) {
+ dev_err(dev, "failed to disable the devfreq-event devices\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops exynos_busfreq_pm = {
+ SET_SYSTEM_SLEEP_PM_OPS(exynos_busfreq_suspend, exynos_busfreq_resume)
+};
+
+static const struct of_device_id exynos_busfreq_of_match[] = {
+ { .compatible = "samsung,exynos-memory-bus", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, exynos_busfreq_of_match);
+
+static struct platform_driver exynos_busfreq_platdrv = {
+ .probe = exynos_busfreq_probe,
+ .remove = exynos_busfreq_remove,
+ .driver = {
+ .name = "exynos-memory-bus",
+ .owner = THIS_MODULE,
+ .pm = &exynos_busfreq_pm,
+ .of_match_table = of_match_ptr(exynos_busfreq_of_match),
+ },
+};
+module_platform_driver(exynos_busfreq_platdrv);
+
+MODULE_DESCRIPTION("Generic Exynos Memory Bus Frequency driver");
+MODULE_AUTHOR("Chanwoo Choi <cw00.choi@samsung.com>");
+MODULE_LICENSE("GPL v2");
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 1/8] devfreq: exynos: Add generic exynos memory bus frequency driver
@ 2014-12-31 5:19 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the generic exynos bus frequency driver for memory bus
with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
support the memory bus frequency driver for Exynos SoCs.
Each memory bus block has a clock for memory bus speed and frequency
table which is changed according to the utilization of memory bus on runtime.
And then each memory bus group has the one more memory bus blocks and
OPP table (including frequency and voltage), regulator, devfreq-event
devices.
There are a little difference about the number of memory bus because each Exynos
SoC have the different sub-IP and different memory bus speed. In spite of this
difference among Exynos SoCs, we can support almost Exynos SoC by adding
unique data of memory bus to devicetree file.
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/devfreq/Kconfig | 15 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/exynos-busfreq.c | 588 +++++++++++++++++++++++++++++++++++++++
3 files changed, 604 insertions(+)
create mode 100644 drivers/devfreq/exynos-busfreq.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 21f8f17..f1003eb 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -65,6 +65,21 @@ config DEVFREQ_GOV_USERSPACE
comment "DEVFREQ Drivers"
+config ARM_EXYNOS_BUS_DEVFREQ
+ bool "EXYNOS Memory Bus DEVFREQ Driver"
+ depends on ARCH_EXYNOS
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
+ select DEVFREQ_EVENT_EXYNOS_PPMU
+ select PM_DEVFREQ_EVENT
+ select PM_OPP
+ help
+ This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
+ Memory bus has one more group of memory bus (e.g, MIF and INT block).
+ Each memory bus group could contain many memoby bus block. It reads
+ PPMU counters of memory controllers by using DEVFREQ-event device
+ and adjusts the operating frequencies and voltages with OPP support.
+ This does not yet operate with optimal voltages.
+
config ARM_EXYNOS4_BUS_DEVFREQ
bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index c449336..2b82a4c 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o
# DEVFREQ Drivers
+obj-$(CONFIG_ARCH_EXYNOS) += exynos-busfreq.o
obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/
obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/
diff --git a/drivers/devfreq/exynos-busfreq.c b/drivers/devfreq/exynos-busfreq.c
new file mode 100644
index 0000000..3c92541
--- /dev/null
+++ b/drivers/devfreq/exynos-busfreq.c
@@ -0,0 +1,588 @@
+/*
+ * Generic Exynos Memory Bus Frequency driver with DEVFREQ Framework
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author : Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This driver is based on exynos4_bus.c, which was written
+ * by MyungJoo Ham <myungjoo.ham@samsung.com>, Samsung Electronics.
+ *
+ * This driver support Exynos Memory Bus frequency feature by using in DEVFREQ
+ * framework. This version supprots Exynos3250/Exynos4 series/Exynos5260 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq.h>
+#include <linux/devfreq-event.h>
+#include <linux/device.h>
+#include <linux/export.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_opp.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+
+#define BUS_SATURATION_RATIO 40
+#define SAFEVOLT 50000
+
+struct exynos_memory_bus_opp_info {
+ unsigned long rate;
+ unsigned long volt;
+};
+
+struct exynos_memory_bus_block {
+ struct clk *clk;
+ struct exynos_memory_bus_opp_info *freq_table;
+};
+
+struct exynos_memory_bus_data {
+ /* devfreq device to monitor and control memory bus group */
+ struct device *dev;
+ struct devfreq *devfreq;
+
+ struct exynos_memory_bus_opp_info *freq_table;
+ unsigned int freq_count;
+ struct regulator *regulator;
+ struct mutex lock;
+
+ struct exynos_memory_bus_opp_info curr_opp;
+
+ struct exynos_memory_bus_block *block;
+ unsigned int block_count;
+
+ /* devfreq-event device to get current state of memory bus group */
+ struct devfreq_event_dev **edev;
+ unsigned int edev_count;
+};
+
+/*
+ * Initialize the memory bus group/block by parsing dt node in the devicetree
+ */
+static int of_init_memory_bus(struct device_node *np,
+ struct exynos_memory_bus_data *data)
+{
+ struct device *dev = data->dev;
+ struct dev_pm_opp *opp;
+ unsigned long rate, volt;
+ int i, ret, count, size;
+
+ /* Get the freq/voltage OPP table to scale memory bus frequency */
+ ret = of_init_opp_table(dev);
+ if (ret < 0) {
+ dev_err(dev, "failed to get OPP table\n");
+ return ret;
+ }
+
+ rcu_read_lock();
+
+ data->freq_count = dev_pm_opp_get_opp_count(dev);
+ if (data->freq_count <= 0) {
+ dev_err(dev, "failed to get the count of OPP entry\n");
+ rcu_read_unlock();
+ return -EINVAL;
+ }
+
+ size = sizeof(*data->freq_table) * data->freq_count;
+ data->freq_table = devm_kzalloc(dev, size, GFP_KERNEL);
+ if (!data->freq_table) {
+ rcu_read_unlock();
+ return -ENOMEM;
+ }
+
+ for (i = 0, rate = 0; i < data->freq_count; i++, rate++) {
+ opp = dev_pm_opp_find_freq_ceil(dev, &rate);
+ if (IS_ERR(opp)) {
+ dev_err(dev, "failed to find dev_pm_opp\n");
+ rcu_read_unlock();
+ return PTR_ERR(opp);
+ }
+
+ volt = dev_pm_opp_get_voltage(opp);
+
+ data->freq_table[i].rate = rate;
+ data->freq_table[i].volt = volt;
+
+ dev_dbg(dev, "%d : frequency(%ld), voltage(%ld)\n",
+ i, rate, volt);
+ }
+
+ rcu_read_unlock();
+
+ /* Get the regulator to provide memory bus group with the power */
+ data->regulator = devm_regulator_get(dev, "vdd-mem");
+ if (IS_ERR(data->regulator)) {
+ dev_err(dev, "failed to get vdd-memory regulator\n");
+ return PTR_ERR(data->regulator);
+ }
+
+ ret = regulator_enable(data->regulator);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable vdd-memory regulator\n");
+ return ret;
+ }
+
+ /*
+ * Get the devfreq-event devices to get the current state of
+ * memory bus group. This raw data will be used in devfreq governor.
+ */
+ count = devfreq_event_get_edev_count(dev);
+ if (count < 0) {
+ dev_err(dev, "failed to get the count of devfreq-event dev\n");
+ return count;
+ }
+ data->edev_count = count;
+
+ size = sizeof(*data->edev) * count;
+ data->edev = devm_kzalloc(dev, size, GFP_KERNEL);
+ if (!data->edev)
+ return -ENOMEM;
+
+ for (i = 0; i < count; i++) {
+ data->edev[i] = devfreq_event_get_edev_by_phandle(dev, i);
+ if (IS_ERR(data->edev[i])) {
+ of_free_opp_table(dev);
+ return -EPROBE_DEFER;
+ }
+ }
+
+ return 0;
+}
+
+static int of_init_memory_bus_block(struct device_node *np,
+ struct exynos_memory_bus_data *data)
+{
+ struct exynos_memory_bus_block *block;
+ struct device *dev = data->dev;
+ struct device_node *buses_np, *node;
+ int i, count;
+
+ buses_np = of_get_child_by_name(np, "blocks");
+ if (!buses_np) {
+ dev_err(dev,
+ "failed to get child node of memory bus\n");
+ return -EINVAL;
+ }
+
+ count = of_get_child_count(buses_np);
+ block = devm_kzalloc(dev, sizeof(*block) * count, GFP_KERNEL);
+ if (!block)
+ return -ENOMEM;
+ data->block = block;
+ data->block_count = count;
+
+ /* Parse the information of memory bus block */
+ i = 0;
+ for_each_child_of_node(buses_np, node) {
+ const struct property *prop;
+ const __be32 *val;
+ int j, nr, size;
+
+ block = &data->block[i++];
+
+ /* Get the frequency table of each memory bus block */
+ prop = of_find_property(node, "frequency", NULL);
+ if (!prop)
+ return -ENODEV;
+ if (!prop->value)
+ return -ENODATA;
+
+ nr = prop->length / sizeof(u32);
+ if (!nr)
+ return -EINVAL;
+
+ if (nr != data->freq_count) {
+ dev_err(dev, "the size of frequency table is different \
+ from OPP table\n");
+ return -EINVAL;
+ }
+
+ size = sizeof(*block->freq_table) * nr;
+ block->freq_table = devm_kzalloc(dev, size, GFP_KERNEL);
+ if (!block->freq_table)
+ return -ENOMEM;
+
+ val = prop->value;
+ for (j = nr - 1; j >= 0; j--)
+ block->freq_table[j].rate = be32_to_cpup(val++) * 1000;
+
+ for (j = 0; j < nr; j++)
+ dev_dbg(dev, "%s: %d : frequency(%ld)\n",
+ node->name, j, block->freq_table[j].rate);
+ dev_dbg(dev, "\n");
+
+ /* Get the clock of each memory bus block */
+ block->clk = of_clk_get_by_name(node, "memory-bus");
+ if (IS_ERR(block->clk)) {
+ dev_err(dev, "failed to get memory-bus clock in %s\n",
+ node->name);
+ return PTR_ERR(block->clk);
+ }
+ clk_prepare_enable(block->clk);
+
+ of_node_put(node);
+ }
+
+ of_node_put(buses_np);
+
+ return 0;
+}
+
+/*
+ * Control the devfreq-event device to get the current state of memory bus
+ */
+static int exynos_busfreq_enable_edev(struct exynos_memory_bus_data *data)
+{
+ int i, ret;
+
+ for (i = 0; i < data->edev_count; i++) {
+ ret = devfreq_event_enable_edev(data->edev[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int exynos_busfreq_disable_edev(struct exynos_memory_bus_data *data)
+{
+ int i, ret;
+
+ for (i = 0; i < data->edev_count; i++) {
+ ret = devfreq_event_disable_edev(data->edev[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+
+static int exynos_busfreq_set_event(struct exynos_memory_bus_data *data)
+{
+ int i, ret;
+
+ for (i = 0; i < data->edev_count; i++) {
+ ret = devfreq_event_set_event(data->edev[i],
+ DEVFREQ_EVENT_TYPE_RAW_DATA);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int exynos_busfreq_get_event(struct exynos_memory_bus_data *data,
+ struct devfreq_event_data *edata)
+{
+ struct devfreq_event_data curr_edata;
+ unsigned long event, total_event;
+ int i, ret = 0;
+
+ for (i = 0; i < data->edev_count; i++) {
+ ret = devfreq_event_get_event(data->edev[i],
+ DEVFREQ_EVENT_TYPE_RAW_DATA,
+ &curr_edata);
+ if (ret < 0)
+ return ret;
+
+ if (i == 0 || curr_edata.event > event) {
+ event = curr_edata.event;
+ total_event = curr_edata.total_event;
+ }
+ }
+
+ edata->event = event;
+ edata->total_event = total_event;
+
+ return ret;
+}
+
+/*
+ * Must necessary function for devfreq governor
+ */
+
+static int exynos_busfreq_set_frequency(struct exynos_memory_bus_data *data,
+ struct exynos_memory_bus_opp_info *new_opp)
+{
+ int i, j;
+
+ for (i = 0; i < data->freq_count; i++)
+ if (new_opp->rate == data->freq_table[i].rate)
+ break;
+
+ if (i == data->freq_count)
+ i = data->freq_count - 1;
+
+ for (j = 0; j < data->block_count; j++)
+ clk_set_rate(data->block[j].clk,
+ data->block[j].freq_table[i].rate);
+
+ return 0;
+}
+
+static int exynos_busfreq_target(struct device *dev, unsigned long *freq,
+ u32 flags)
+{
+ struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
+ struct exynos_memory_bus_opp_info new_opp;
+ unsigned long new_freq, old_freq;
+ struct dev_pm_opp *opp;
+ int ret = 0;
+
+ /* Get new opp-info instance according to new busfreq clock */
+ rcu_read_lock();
+ opp = devfreq_recommended_opp(dev, freq, flags);
+ if (IS_ERR_OR_NULL(opp)) {
+ dev_err(dev, "failed to get recommed opp instance\n");
+ rcu_read_unlock();
+ return PTR_ERR(opp);
+ }
+ new_opp.rate = dev_pm_opp_get_freq(opp);
+ new_opp.volt = dev_pm_opp_get_voltage(opp);
+ rcu_read_unlock();
+
+ old_freq = data->curr_opp.rate;
+ new_freq = new_opp.rate;
+ if (old_freq == new_freq)
+ return 0;
+
+ dev_dbg(dev, "Change the frequency of memory bus (%ld kHz -> %ld kHz)\n",
+ old_freq / 1000, new_freq / 1000);
+
+ /* Change voltage/clock according to new busfreq level */
+ mutex_lock(&data->lock);
+
+ if (old_freq < new_freq) {
+ ret = regulator_set_voltage(data->regulator, new_opp.volt,
+ new_opp.volt + SAFEVOLT);
+ if (ret < 0) {
+ dev_err(data->dev, "failed to set voltage\n");
+ regulator_set_voltage(data->regulator,
+ data->curr_opp.rate,
+ data->curr_opp.rate + SAFEVOLT);
+ goto out;
+ }
+ }
+
+ exynos_busfreq_set_frequency(data, &new_opp);
+ if (ret < 0) {
+ dev_err(dev, "failed to change clock of memory bus\n");
+ goto out;
+ }
+
+ if (old_freq > new_freq) {
+ ret = regulator_set_voltage(data->regulator, new_opp.volt,
+ new_opp.volt + SAFEVOLT);
+ if (ret < 0) {
+ dev_err(data->dev, "failed to set voltage\n");
+ regulator_set_voltage(data->regulator,
+ data->curr_opp.rate,
+ data->curr_opp.rate + SAFEVOLT);
+ goto out;
+ }
+ }
+
+ data->curr_opp = new_opp;
+
+out:
+ mutex_unlock(&data->lock);
+
+ return ret;
+}
+
+static int exynos_busfreq_get_dev_status(struct device *dev,
+ struct devfreq_dev_status *stat)
+{
+ struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
+ struct devfreq_event_data edata;
+ int ret;
+
+ stat->current_frequency = data->curr_opp.rate;
+
+ ret = exynos_busfreq_get_event(data, &edata);
+ if (ret < 0) {
+ stat->total_time = stat->busy_time = 0;
+ goto err;
+ }
+
+ stat->busy_time = (edata.event * 100) / BUS_SATURATION_RATIO;
+ stat->total_time = edata.total_event;
+
+err:
+ ret = exynos_busfreq_set_event(data);
+ if (ret < 0) {
+ dev_err(dev, "failed to set event to devfreq-event devices\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+static void exynos_busfreq_exit(struct device *dev)
+{
+ struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
+ int i, ret;
+
+ ret = exynos_busfreq_disable_edev(data);
+ if (ret < 0)
+ dev_warn(dev, "failed to disable the devfreq-event devices\n");
+
+ for (i = 0; i < data->block_count; i++)
+ clk_disable_unprepare(data->block[i].clk);
+
+ if (regulator_is_enabled(data->regulator))
+ regulator_disable(data->regulator);
+
+ of_free_opp_table(dev);
+}
+
+static struct devfreq_dev_profile exynos_memory_bus_profile = {
+ .polling_ms = 100,
+ .target = exynos_busfreq_target,
+ .get_dev_status = exynos_busfreq_get_dev_status,
+ .exit = exynos_busfreq_exit,
+};
+
+static struct devfreq_simple_ondemand_data exynos_memory_bus_ondemand_data = {
+ .upthreshold = 40,
+ .downdifferential = 5,
+};
+
+static int exynos_busfreq_probe(struct platform_device *pdev)
+{
+ struct exynos_memory_bus_data *data;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ if (!np) {
+ dev_err(dev, "failed to find devicetree node\n");
+ return -EINVAL;
+ }
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+ mutex_init(&data->lock);
+ data->dev = &pdev->dev;
+ platform_set_drvdata(pdev, data);
+
+ /* Initialize */
+ ret = of_init_memory_bus(np, data);
+ if (ret < 0) {
+ dev_err(dev, "failed to initialize memory-bus\n");
+ return ret;
+ }
+
+ ret = of_init_memory_bus_block(np, data);
+ if (ret < 0) {
+ dev_err(dev, "failed to initialize memory-bus block\n");
+ return ret;
+ }
+
+ /* Add devfreq device for DVFS of memory bus */
+ data->devfreq = devm_devfreq_add_device(dev,
+ &exynos_memory_bus_profile,
+ "simple_ondemand",
+ &exynos_memory_bus_ondemand_data);
+ if (IS_ERR_OR_NULL(data->devfreq)) {
+ dev_err(dev, "failed to add devfreq device\n");
+ return PTR_ERR(data->devfreq);
+ }
+
+ /* Register opp_notifier to catch the change of OPP */
+ ret = devm_devfreq_register_opp_notifier(dev, data->devfreq);
+ if (ret < 0) {
+ dev_err(dev, "failed to register opp notifier\n");
+ return ret;
+ }
+
+ /*
+ * Enable devfreq-event to get raw data which is used to determine
+ * current memory bus load.
+ */
+ ret = exynos_busfreq_enable_edev(data);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable devfreq-event devices\n");
+ return ret;
+ }
+
+ ret = exynos_busfreq_set_event(data);
+ if (ret < 0) {
+ dev_err(dev, "failed to set event to devfreq-event devices\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int exynos_busfreq_remove(struct platform_device *pdev)
+{
+ /*
+ * devfreq_dev_profile.exit() have to free the resource of this
+ * device driver.
+ */
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos_busfreq_resume(struct device *dev)
+{
+ struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
+ int ret;
+
+ ret = exynos_busfreq_enable_edev(data);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable the devfreq-event devices\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int exynos_busfreq_suspend(struct device *dev)
+{
+ struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
+ int ret;
+
+ ret = exynos_busfreq_disable_edev(data);
+ if (ret < 0) {
+ dev_err(dev, "failed to disable the devfreq-event devices\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops exynos_busfreq_pm = {
+ SET_SYSTEM_SLEEP_PM_OPS(exynos_busfreq_suspend, exynos_busfreq_resume)
+};
+
+static const struct of_device_id exynos_busfreq_of_match[] = {
+ { .compatible = "samsung,exynos-memory-bus", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, exynos_busfreq_of_match);
+
+static struct platform_driver exynos_busfreq_platdrv = {
+ .probe = exynos_busfreq_probe,
+ .remove = exynos_busfreq_remove,
+ .driver = {
+ .name = "exynos-memory-bus",
+ .owner = THIS_MODULE,
+ .pm = &exynos_busfreq_pm,
+ .of_match_table = of_match_ptr(exynos_busfreq_of_match),
+ },
+};
+module_platform_driver(exynos_busfreq_platdrv);
+
+MODULE_DESCRIPTION("Generic Exynos Memory Bus Frequency driver");
+MODULE_AUTHOR("Chanwoo Choi <cw00.choi@samsung.com>");
+MODULE_LICENSE("GPL v2");
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 2/8] devfreq: exynos: Add documentation for generic exynos memory bus frequency driver
2014-12-31 5:19 ` Chanwoo Choi
(?)
@ 2014-12-31 5:19 ` Chanwoo Choi
-1 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: myungjoo.ham
Cc: kgene.kim, kyungmin.park, rafael.j.wysocki, mark.rutland,
a.kesavan, tomasz.figa, k.kozlowski, b.zolnierkie, cw00.choi,
inki.dae, linux-pm, linux-kernel, linux-arm-kernel,
linux-samsung-soc
This patch adds the documentation for generic exynos memory bus frequency
driver.
Cc: MyungJoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
.../devicetree/bindings/devfreq/exynos-busfreq.txt | 184 +++++++++++++++++++++
1 file changed, 184 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt b/Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
new file mode 100644
index 0000000..c601e88
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
@@ -0,0 +1,184 @@
+
+* Generic Exynos Memory Bus device
+
+The Samsung Exynos SoCs have many memory buses for data transfer between DRAM
+memory and MMC/sub-IP in SoC. Almost Exynos SoCs have the common architecture
+for memory buses. Generally, Exynos SoC express the memory bus by using memory
+bus group and block. The memory bus group has one more memory bus blocks and
+OPP table (including frequency and voltage for DVFS), regulator, devfreq-event
+devices. Each memory bus block has a clock for own memory bus speen and
+frequency table for DVFS. There are a little different among Exynos SoCs
+because each Exynos SoC has the different sub-IP and differnt memory bus.
+So, this difference should be specified in devicetree file.
+
+Required properties for memory bus group:
+- compatible: Should be "samsung,exynos-memory-bus".
+- operating-points: the OPP table including frequency/voltage information to
+ support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+- devfreq-events: the devfreq-event device to monitor the curret state of
+ memory bus group.
+- vdd-mem-supply: the regulator to provide memory bus group with the voltage.
+
+Required properties for memory bus block:
+- clock-names : the name of clock used by the memory bus, "memory-bus".
+- clocks : phandles for clock specified in "clock-names" property.
+- #clock-cells: should be 1.
+- frequency: the frequency table to support DVFS feature.
+
+Example1 : Memory bus group/block in exynos3250.dtsi are listed below.
+ Exynos3250 has two memory bus group (MIF, INT group). MIF memory bus
+ group includes one memory bus block between DRAM and eMMC. Also, INT
+ memory bus group includes eight memory bus blocks which support each
+ sub-IPs between DRAM and sub-IPs.
+
+ memory_bus_mif: memory_bus@0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 875000
+ 200000 800000
+ 133000 800000
+ 100000 800000
+ 50000 800000>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <&cmu_dmc CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 133000
+ 100000
+ 50000>;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus@1 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 950000
+ 200000 950000
+ 133000 925000
+ 100000 850000
+ 80000 850000
+ 50000 850000>;
+
+ status = "disabled";
+
+ blocks {
+ peri_block: memory_bus_block1 {
+ clocks = <&cmu CLK_DIV_ACLK_100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 100000
+ 100000
+ 100000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ display_block: memory_bus_block2 {
+ clocks = <&cmu CLK_DIV_ACLK_160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000
+ 80000
+ 80000
+ 50000>;
+ };
+
+ isp_block: memory_bus_block3 {
+ clocks = <&cmu CLK_DIV_ACLK_200>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 100000
+ 80000
+ 50000
+ 50000>;
+ };
+
+ gps_block: memory_bus_block4 {
+ clocks = <&cmu CLK_DIV_ACLK_266>;
+ clock-names = "memory-bus";
+ frequency = <
+ 300000
+ 200000
+ 133000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ mcuisp_block: memory_bus_block5 {
+ clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 50000
+ 50000
+ 50000
+ 50000>;
+ };
+
+ leftbus_block: memory_bus_block6 {
+ clocks = <&cmu CLK_DIV_GDL>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ rightbus_block: memory_bus_block7 {
+ clocks = <&cmu CLK_DIV_GDR>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ mfc_block: memory_bus_block8 {
+ clocks = <&cmu CLK_SCLK_MFC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 200000
+ 133000
+ 100000
+ 80000>;
+ };
+ };
+ };
+
+Example2 : Usage case to handle the frequency/voltage of memory bus on runtime
+ in exynos3250-rinato.dts are listed below.
+
+ &memory_bus_mif {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-mem-supply = <&buck1_reg>;
+ status = "okay";
+ };
+
+ &memory_bus_int {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-mem-supply = <&buck3_reg>;
+ status = "okay";
+ };
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 2/8] devfreq: exynos: Add documentation for generic exynos memory bus frequency driver
@ 2014-12-31 5:19 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: myungjoo.ham
Cc: mark.rutland, k.kozlowski, kgene.kim, b.zolnierkie, linux-pm,
rafael.j.wysocki, tomasz.figa, linux-kernel, inki.dae, cw00.choi,
kyungmin.park, linux-samsung-soc, a.kesavan, linux-arm-kernel
This patch adds the documentation for generic exynos memory bus frequency
driver.
Cc: MyungJoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
.../devicetree/bindings/devfreq/exynos-busfreq.txt | 184 +++++++++++++++++++++
1 file changed, 184 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt b/Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
new file mode 100644
index 0000000..c601e88
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
@@ -0,0 +1,184 @@
+
+* Generic Exynos Memory Bus device
+
+The Samsung Exynos SoCs have many memory buses for data transfer between DRAM
+memory and MMC/sub-IP in SoC. Almost Exynos SoCs have the common architecture
+for memory buses. Generally, Exynos SoC express the memory bus by using memory
+bus group and block. The memory bus group has one more memory bus blocks and
+OPP table (including frequency and voltage for DVFS), regulator, devfreq-event
+devices. Each memory bus block has a clock for own memory bus speen and
+frequency table for DVFS. There are a little different among Exynos SoCs
+because each Exynos SoC has the different sub-IP and differnt memory bus.
+So, this difference should be specified in devicetree file.
+
+Required properties for memory bus group:
+- compatible: Should be "samsung,exynos-memory-bus".
+- operating-points: the OPP table including frequency/voltage information to
+ support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+- devfreq-events: the devfreq-event device to monitor the curret state of
+ memory bus group.
+- vdd-mem-supply: the regulator to provide memory bus group with the voltage.
+
+Required properties for memory bus block:
+- clock-names : the name of clock used by the memory bus, "memory-bus".
+- clocks : phandles for clock specified in "clock-names" property.
+- #clock-cells: should be 1.
+- frequency: the frequency table to support DVFS feature.
+
+Example1 : Memory bus group/block in exynos3250.dtsi are listed below.
+ Exynos3250 has two memory bus group (MIF, INT group). MIF memory bus
+ group includes one memory bus block between DRAM and eMMC. Also, INT
+ memory bus group includes eight memory bus blocks which support each
+ sub-IPs between DRAM and sub-IPs.
+
+ memory_bus_mif: memory_bus@0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 875000
+ 200000 800000
+ 133000 800000
+ 100000 800000
+ 50000 800000>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <&cmu_dmc CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 133000
+ 100000
+ 50000>;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus@1 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 950000
+ 200000 950000
+ 133000 925000
+ 100000 850000
+ 80000 850000
+ 50000 850000>;
+
+ status = "disabled";
+
+ blocks {
+ peri_block: memory_bus_block1 {
+ clocks = <&cmu CLK_DIV_ACLK_100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 100000
+ 100000
+ 100000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ display_block: memory_bus_block2 {
+ clocks = <&cmu CLK_DIV_ACLK_160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000
+ 80000
+ 80000
+ 50000>;
+ };
+
+ isp_block: memory_bus_block3 {
+ clocks = <&cmu CLK_DIV_ACLK_200>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 100000
+ 80000
+ 50000
+ 50000>;
+ };
+
+ gps_block: memory_bus_block4 {
+ clocks = <&cmu CLK_DIV_ACLK_266>;
+ clock-names = "memory-bus";
+ frequency = <
+ 300000
+ 200000
+ 133000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ mcuisp_block: memory_bus_block5 {
+ clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 50000
+ 50000
+ 50000
+ 50000>;
+ };
+
+ leftbus_block: memory_bus_block6 {
+ clocks = <&cmu CLK_DIV_GDL>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ rightbus_block: memory_bus_block7 {
+ clocks = <&cmu CLK_DIV_GDR>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ mfc_block: memory_bus_block8 {
+ clocks = <&cmu CLK_SCLK_MFC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 200000
+ 133000
+ 100000
+ 80000>;
+ };
+ };
+ };
+
+Example2 : Usage case to handle the frequency/voltage of memory bus on runtime
+ in exynos3250-rinato.dts are listed below.
+
+ &memory_bus_mif {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-mem-supply = <&buck1_reg>;
+ status = "okay";
+ };
+
+ &memory_bus_int {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-mem-supply = <&buck3_reg>;
+ status = "okay";
+ };
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 2/8] devfreq: exynos: Add documentation for generic exynos memory bus frequency driver
@ 2014-12-31 5:19 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the documentation for generic exynos memory bus frequency
driver.
Cc: MyungJoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
.../devicetree/bindings/devfreq/exynos-busfreq.txt | 184 +++++++++++++++++++++
1 file changed, 184 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt b/Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
new file mode 100644
index 0000000..c601e88
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt
@@ -0,0 +1,184 @@
+
+* Generic Exynos Memory Bus device
+
+The Samsung Exynos SoCs have many memory buses for data transfer between DRAM
+memory and MMC/sub-IP in SoC. Almost Exynos SoCs have the common architecture
+for memory buses. Generally, Exynos SoC express the memory bus by using memory
+bus group and block. The memory bus group has one more memory bus blocks and
+OPP table (including frequency and voltage for DVFS), regulator, devfreq-event
+devices. Each memory bus block has a clock for own memory bus speen and
+frequency table for DVFS. There are a little different among Exynos SoCs
+because each Exynos SoC has the different sub-IP and differnt memory bus.
+So, this difference should be specified in devicetree file.
+
+Required properties for memory bus group:
+- compatible: Should be "samsung,exynos-memory-bus".
+- operating-points: the OPP table including frequency/voltage information to
+ support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+- devfreq-events: the devfreq-event device to monitor the curret state of
+ memory bus group.
+- vdd-mem-supply: the regulator to provide memory bus group with the voltage.
+
+Required properties for memory bus block:
+- clock-names : the name of clock used by the memory bus, "memory-bus".
+- clocks : phandles for clock specified in "clock-names" property.
+- #clock-cells: should be 1.
+- frequency: the frequency table to support DVFS feature.
+
+Example1 : Memory bus group/block in exynos3250.dtsi are listed below.
+ Exynos3250 has two memory bus group (MIF, INT group). MIF memory bus
+ group includes one memory bus block between DRAM and eMMC. Also, INT
+ memory bus group includes eight memory bus blocks which support each
+ sub-IPs between DRAM and sub-IPs.
+
+ memory_bus_mif: memory_bus at 0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 875000
+ 200000 800000
+ 133000 800000
+ 100000 800000
+ 50000 800000>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <&cmu_dmc CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 133000
+ 100000
+ 50000>;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus at 1 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 950000
+ 200000 950000
+ 133000 925000
+ 100000 850000
+ 80000 850000
+ 50000 850000>;
+
+ status = "disabled";
+
+ blocks {
+ peri_block: memory_bus_block1 {
+ clocks = <&cmu CLK_DIV_ACLK_100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 100000
+ 100000
+ 100000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ display_block: memory_bus_block2 {
+ clocks = <&cmu CLK_DIV_ACLK_160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000
+ 80000
+ 80000
+ 50000>;
+ };
+
+ isp_block: memory_bus_block3 {
+ clocks = <&cmu CLK_DIV_ACLK_200>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 100000
+ 80000
+ 50000
+ 50000>;
+ };
+
+ gps_block: memory_bus_block4 {
+ clocks = <&cmu CLK_DIV_ACLK_266>;
+ clock-names = "memory-bus";
+ frequency = <
+ 300000
+ 200000
+ 133000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ mcuisp_block: memory_bus_block5 {
+ clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 50000
+ 50000
+ 50000
+ 50000>;
+ };
+
+ leftbus_block: memory_bus_block6 {
+ clocks = <&cmu CLK_DIV_GDL>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ rightbus_block: memory_bus_block7 {
+ clocks = <&cmu CLK_DIV_GDR>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ mfc_block: memory_bus_block8 {
+ clocks = <&cmu CLK_SCLK_MFC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 200000
+ 133000
+ 100000
+ 80000>;
+ };
+ };
+ };
+
+Example2 : Usage case to handle the frequency/voltage of memory bus on runtime
+ in exynos3250-rinato.dts are listed below.
+
+ &memory_bus_mif {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-mem-supply = <&buck1_reg>;
+ status = "okay";
+ };
+
+ &memory_bus_int {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-mem-supply = <&buck3_reg>;
+ status = "okay";
+ };
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 3/8] ARM: dts: Add memory bus node for Exynos3250
2014-12-31 5:19 ` Chanwoo Choi
@ 2014-12-31 5:19 ` Chanwoo Choi
-1 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: myungjoo.ham
Cc: kgene.kim, kyungmin.park, rafael.j.wysocki, mark.rutland,
a.kesavan, tomasz.figa, k.kozlowski, b.zolnierkie, cw00.choi,
inki.dae, linux-pm, linux-kernel, linux-arm-kernel,
linux-samsung-soc
This patch adds the memory bus node for Exynos3250 SoC. Exynos3250 has
following memory buses to translate data between DRAM and eMMC/sub-IPs.
Following list specifies the detailed relation between memory bus clock and DMC
IP in MIF (Memory Interface) block:
- DMC clock : DMC (Dynamic Memory Controller)
Following list specifies the detailed relation between memory bus clock and
sub-IPs in INT (Internal) block:
- ACLK100 clock : PERIL
- ACLK160 clock : LCD0
- ACLK200 clock : FSYS
- ACLK266 clock : ISP
- GDL/GDR clock : leftbus/rightbus
- SCLK_MFC clock : MFC
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
arch/arm/boot/dts/exynos3250.dtsi | 125 ++++++++++++++++++++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 9ed1260..3eaed53 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -99,6 +99,131 @@
};
};
+ memory_bus_mif: memory_bus@0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 875000
+ 200000 800000
+ 133000 800000
+ 100000 800000
+ 50000 800000>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <&cmu_dmc CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 133000
+ 100000
+ 50000>;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus@1 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 950000
+ 200000 950000
+ 133000 925000
+ 100000 850000
+ 80000 850000
+ 50000 850000>;
+
+ status = "disabled";
+
+ blocks {
+ peril_block: memory_bus_block1 {
+ clocks = <&cmu CLK_DIV_ACLK_100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 100000
+ 100000
+ 100000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ lcd0_block: memory_bus_block2 {
+ clocks = <&cmu CLK_DIV_ACLK_160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000
+ 80000
+ 80000
+ 50000>;
+ };
+
+ fsys_block: memory_bus_block3 {
+ clocks = <&cmu CLK_DIV_ACLK_200>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 100000
+ 80000
+ 50000
+ 50000>;
+ };
+
+ isp_block: memory_bus_block4 {
+ clocks = <&cmu CLK_DIV_ACLK_266>;
+ clock-names = "memory-bus";
+ frequency = <
+ 300000
+ 200000
+ 133000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ leftbus_block: memory_bus_block5 {
+ clocks = <&cmu CLK_DIV_GDL>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ rightbus_block: memory_bus_block6 {
+ clocks = <&cmu CLK_DIV_GDR>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ mfc_block: memory_bus_block7 {
+ clocks = <&cmu CLK_SCLK_MFC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 200000
+ 133000
+ 100000
+ 80000>;
+ };
+ };
+ };
+
sysram@02020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 3/8] ARM: dts: Add memory bus node for Exynos3250
@ 2014-12-31 5:19 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the memory bus node for Exynos3250 SoC. Exynos3250 has
following memory buses to translate data between DRAM and eMMC/sub-IPs.
Following list specifies the detailed relation between memory bus clock and DMC
IP in MIF (Memory Interface) block:
- DMC clock : DMC (Dynamic Memory Controller)
Following list specifies the detailed relation between memory bus clock and
sub-IPs in INT (Internal) block:
- ACLK100 clock : PERIL
- ACLK160 clock : LCD0
- ACLK200 clock : FSYS
- ACLK266 clock : ISP
- GDL/GDR clock : leftbus/rightbus
- SCLK_MFC clock : MFC
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
arch/arm/boot/dts/exynos3250.dtsi | 125 ++++++++++++++++++++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 9ed1260..3eaed53 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -99,6 +99,131 @@
};
};
+ memory_bus_mif: memory_bus at 0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 875000
+ 200000 800000
+ 133000 800000
+ 100000 800000
+ 50000 800000>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <&cmu_dmc CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 133000
+ 100000
+ 50000>;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus at 1 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 950000
+ 200000 950000
+ 133000 925000
+ 100000 850000
+ 80000 850000
+ 50000 850000>;
+
+ status = "disabled";
+
+ blocks {
+ peril_block: memory_bus_block1 {
+ clocks = <&cmu CLK_DIV_ACLK_100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 100000
+ 100000
+ 100000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ lcd0_block: memory_bus_block2 {
+ clocks = <&cmu CLK_DIV_ACLK_160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000
+ 80000
+ 80000
+ 50000>;
+ };
+
+ fsys_block: memory_bus_block3 {
+ clocks = <&cmu CLK_DIV_ACLK_200>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 100000
+ 80000
+ 50000
+ 50000>;
+ };
+
+ isp_block: memory_bus_block4 {
+ clocks = <&cmu CLK_DIV_ACLK_266>;
+ clock-names = "memory-bus";
+ frequency = <
+ 300000
+ 200000
+ 133000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ leftbus_block: memory_bus_block5 {
+ clocks = <&cmu CLK_DIV_GDL>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ rightbus_block: memory_bus_block6 {
+ clocks = <&cmu CLK_DIV_GDR>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ mfc_block: memory_bus_block7 {
+ clocks = <&cmu CLK_SCLK_MFC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 200000
+ 133000
+ 100000
+ 80000>;
+ };
+ };
+ };
+
sysram at 02020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 4/8] clk: samsung: exynos4: Add divider clock id for memory bus frequency
2014-12-31 5:19 ` Chanwoo Choi
(?)
@ 2014-12-31 5:19 ` Chanwoo Choi
-1 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: myungjoo.ham
Cc: kgene.kim, kyungmin.park, rafael.j.wysocki, mark.rutland,
a.kesavan, tomasz.figa, k.kozlowski, b.zolnierkie, cw00.choi,
inki.dae, linux-pm, linux-kernel, linux-arm-kernel,
linux-samsung-soc, Sylwester Nawrocki
This patch adds the divider clock id for Exynos4 memory bus frequency.
The clock id is used fo DVFS (Dynamic Voltage/Frequency Scaling)
feature of exynos memory bus frequency.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/clk/samsung/clk-exynos4.c | 10 +++++-----
include/dt-bindings/clock/exynos4.h | 7 ++++++-
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 88e8c6b..51462e8 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -703,12 +703,12 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
/* list of divider clocks supported in all exynos4 soc's */
static struct samsung_div_clock exynos4_div_clks[] __initdata = {
- DIV(0, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
+ DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
CLKOUT_CMU_LEFTBUS, 8, 6),
- DIV(0, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
+ DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
CLKOUT_CMU_RIGHTBUS, 8, 6),
@@ -781,10 +781,10 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
CLK_SET_RATE_PARENT, 0),
DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
- DIV(0, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
+ DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
- DIV(0, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
+ DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
@@ -829,7 +829,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
8, 3, CLK_GET_RATE_NOCACHE, 0),
DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
- DIV(0, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
+ DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
};
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 34fe28c..c4b1676 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -262,8 +262,13 @@
#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
+#define CLK_DIV_ACP 456
+#define CLK_DIV_DMC 457
+#define CLK_DIV_C2C 458 /* Exynos4x12 only */
+#define CLK_DIV_GDL 459
+#define CLK_DIV_GDR 460
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 456
+#define CLK_NR_CLKS 461
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 4/8] clk: samsung: exynos4: Add divider clock id for memory bus frequency
@ 2014-12-31 5:19 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: myungjoo.ham
Cc: mark.rutland, k.kozlowski, kgene.kim, b.zolnierkie, linux-pm,
rafael.j.wysocki, tomasz.figa, linux-kernel, inki.dae, cw00.choi,
kyungmin.park, linux-samsung-soc, Sylwester Nawrocki, a.kesavan,
linux-arm-kernel
This patch adds the divider clock id for Exynos4 memory bus frequency.
The clock id is used fo DVFS (Dynamic Voltage/Frequency Scaling)
feature of exynos memory bus frequency.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/clk/samsung/clk-exynos4.c | 10 +++++-----
include/dt-bindings/clock/exynos4.h | 7 ++++++-
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 88e8c6b..51462e8 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -703,12 +703,12 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
/* list of divider clocks supported in all exynos4 soc's */
static struct samsung_div_clock exynos4_div_clks[] __initdata = {
- DIV(0, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
+ DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
CLKOUT_CMU_LEFTBUS, 8, 6),
- DIV(0, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
+ DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
CLKOUT_CMU_RIGHTBUS, 8, 6),
@@ -781,10 +781,10 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
CLK_SET_RATE_PARENT, 0),
DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
- DIV(0, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
+ DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
- DIV(0, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
+ DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
@@ -829,7 +829,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
8, 3, CLK_GET_RATE_NOCACHE, 0),
DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
- DIV(0, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
+ DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
};
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 34fe28c..c4b1676 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -262,8 +262,13 @@
#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
+#define CLK_DIV_ACP 456
+#define CLK_DIV_DMC 457
+#define CLK_DIV_C2C 458 /* Exynos4x12 only */
+#define CLK_DIV_GDL 459
+#define CLK_DIV_GDR 460
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 456
+#define CLK_NR_CLKS 461
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 4/8] clk: samsung: exynos4: Add divider clock id for memory bus frequency
@ 2014-12-31 5:19 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the divider clock id for Exynos4 memory bus frequency.
The clock id is used fo DVFS (Dynamic Voltage/Frequency Scaling)
feature of exynos memory bus frequency.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/clk/samsung/clk-exynos4.c | 10 +++++-----
include/dt-bindings/clock/exynos4.h | 7 ++++++-
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 88e8c6b..51462e8 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -703,12 +703,12 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
/* list of divider clocks supported in all exynos4 soc's */
static struct samsung_div_clock exynos4_div_clks[] __initdata = {
- DIV(0, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
+ DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
CLKOUT_CMU_LEFTBUS, 8, 6),
- DIV(0, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
+ DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
CLKOUT_CMU_RIGHTBUS, 8, 6),
@@ -781,10 +781,10 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
CLK_SET_RATE_PARENT, 0),
DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
- DIV(0, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
+ DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
- DIV(0, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
+ DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
@@ -829,7 +829,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
8, 3, CLK_GET_RATE_NOCACHE, 0),
DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
- DIV(0, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
+ DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
};
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 34fe28c..c4b1676 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -262,8 +262,13 @@
#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
+#define CLK_DIV_ACP 456
+#define CLK_DIV_DMC 457
+#define CLK_DIV_C2C 458 /* Exynos4x12 only */
+#define CLK_DIV_GDL 459
+#define CLK_DIV_GDR 460
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 456
+#define CLK_NR_CLKS 461
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 5/8] ARM: dts: Add memory bus node for Exynos4x12
2014-12-31 5:19 ` Chanwoo Choi
@ 2014-12-31 5:19 ` Chanwoo Choi
-1 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: myungjoo.ham
Cc: kgene.kim, kyungmin.park, rafael.j.wysocki, mark.rutland,
a.kesavan, tomasz.figa, k.kozlowski, b.zolnierkie, cw00.choi,
inki.dae, linux-pm, linux-kernel, linux-arm-kernel,
linux-samsung-soc
This patch adds the memory bus node for Exynos4x12 SoC. Exynos4x12 SoC has
two memory bus to translate data between DRAM and eMMC/sub-IPs.
Following list specifies the detailed relation between memory bus clock and DMC
IP in MIF (Memory Interface) block:
- DMC/ACP clock : DMC (Dynamic Memory Controller)
Following list specifies the detailed relation between memory bus clock and
sub-IPs in INT (Internal) block:
- ACLK100 clock : PERIL/PERIR/MFC(PCLK)
- ACLK160 clock : CAM/TV/LCD
- ACLK133 clock : FSYS
- GDL/GDR clock : leftbus/rightbus
- SCLK_MFC clock : MFC
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm/boot/dts/exynos4x12.dtsi | 121 ++++++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 93b7040..44f6272 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -31,6 +31,127 @@
mshc0 = &mshc_0;
};
+ memory_bus_mif: memory_bus@0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 1100000
+ 200000 1000000
+ 160000 950000
+ 133000 950000
+ 100000 950000>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <&clock CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 160000
+ 133000
+ 100000>;
+ };
+
+ acp_block: memory_bus_block2 {
+ clocks = <&clock CLK_DIV_ACP>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 133000
+ 133000
+ 100000>;
+ };
+
+ c2c_block: memory_bus_block3 {
+ clocks = <&clock CLK_DIV_C2C>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 160000
+ 133000
+ 100000>;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus@1 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 200000 1000000
+ 160000 950000
+ 133000 925000
+ 100000 900000>;
+
+ status = "disabled";
+
+ blocks {
+ peri_block: memory_bus_block1 {
+ clocks = <&clock CLK_ACLK100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 100000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ fsys_block: memory_bus_block2 {
+ clocks = <&clock CLK_ACLK133>;
+ clock-names = "memory-bus";
+ frequency = <
+ 133000
+ 133000
+ 100000
+ 100000>;
+ };
+
+ display_block: memory_bus_block3 {
+ clocks = <&clock CLK_ACLK160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 160000
+ 160000
+ 133000
+ 100000>;
+ };
+
+ leftbus_block: memory_bus_block4 {
+ clocks = <&clock CLK_DIV_GDL>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 133000
+ 100000>;
+ };
+
+ rightbus_block: memory_bus_block5 {
+ clocks = <&clock CLK_DIV_GDR>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 133000
+ 100000>;
+ };
+
+ mfc_block: memory_bus_block6 {
+ clocks = <&clock CLK_SCLK_MFC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 133000
+ 100000>;
+ };
+ };
+ };
+
sysram@02020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 5/8] ARM: dts: Add memory bus node for Exynos4x12
@ 2014-12-31 5:19 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the memory bus node for Exynos4x12 SoC. Exynos4x12 SoC has
two memory bus to translate data between DRAM and eMMC/sub-IPs.
Following list specifies the detailed relation between memory bus clock and DMC
IP in MIF (Memory Interface) block:
- DMC/ACP clock : DMC (Dynamic Memory Controller)
Following list specifies the detailed relation between memory bus clock and
sub-IPs in INT (Internal) block:
- ACLK100 clock : PERIL/PERIR/MFC(PCLK)
- ACLK160 clock : CAM/TV/LCD
- ACLK133 clock : FSYS
- GDL/GDR clock : leftbus/rightbus
- SCLK_MFC clock : MFC
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm/boot/dts/exynos4x12.dtsi | 121 ++++++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 93b7040..44f6272 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -31,6 +31,127 @@
mshc0 = &mshc_0;
};
+ memory_bus_mif: memory_bus at 0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 1100000
+ 200000 1000000
+ 160000 950000
+ 133000 950000
+ 100000 950000>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <&clock CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 160000
+ 133000
+ 100000>;
+ };
+
+ acp_block: memory_bus_block2 {
+ clocks = <&clock CLK_DIV_ACP>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 133000
+ 133000
+ 100000>;
+ };
+
+ c2c_block: memory_bus_block3 {
+ clocks = <&clock CLK_DIV_C2C>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 160000
+ 133000
+ 100000>;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus at 1 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 200000 1000000
+ 160000 950000
+ 133000 925000
+ 100000 900000>;
+
+ status = "disabled";
+
+ blocks {
+ peri_block: memory_bus_block1 {
+ clocks = <&clock CLK_ACLK100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 100000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ fsys_block: memory_bus_block2 {
+ clocks = <&clock CLK_ACLK133>;
+ clock-names = "memory-bus";
+ frequency = <
+ 133000
+ 133000
+ 100000
+ 100000>;
+ };
+
+ display_block: memory_bus_block3 {
+ clocks = <&clock CLK_ACLK160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 160000
+ 160000
+ 133000
+ 100000>;
+ };
+
+ leftbus_block: memory_bus_block4 {
+ clocks = <&clock CLK_DIV_GDL>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 133000
+ 100000>;
+ };
+
+ rightbus_block: memory_bus_block5 {
+ clocks = <&clock CLK_DIV_GDR>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 133000
+ 100000>;
+ };
+
+ mfc_block: memory_bus_block6 {
+ clocks = <&clock CLK_SCLK_MFC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 133000
+ 100000>;
+ };
+ };
+ };
+
sysram at 02020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 6/8] ARM: dts: Add memory bus node for Exynos4210
2014-12-31 5:19 ` Chanwoo Choi
@ 2014-12-31 5:19 ` Chanwoo Choi
-1 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: myungjoo.ham
Cc: kgene.kim, kyungmin.park, rafael.j.wysocki, mark.rutland,
a.kesavan, tomasz.figa, k.kozlowski, b.zolnierkie, cw00.choi,
inki.dae, linux-pm, linux-kernel, linux-arm-kernel,
linux-samsung-soc
This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has
one memory bus to translate data between DRAM and eMMC/sub-IPs because
Exynos4210 must need only one regulator for memory bus.
Following list specifies the detailed relation between memory bus clock and
sub-IPs:
- DMC/ACP clock : DMC (Dynamic Memory Controller)
- ACLK200 clock : LCD0
- ACLK100 clock : PERIL/PERIR/MFC(PCLK)
- ACLK160 clock : CAM/TV/LCD0/LCD1
- ACLK133 clock : FSYS/GPS
- GDL/GDR clock : leftbus/rightbus
- SCLK_MFC clock : MFC
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm/boot/dts/exynos4210.dtsi | 93 +++++++++++++++++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index b2598de..c039409 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -48,6 +48,99 @@
};
};
+ memory_bus: memory_bus@0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 1150000
+ 267000 1050000
+ 133000 1025000>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <&clock CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 267000
+ 133000>;
+ };
+
+ acp_block: memory_bus_block2 {
+ clocks = <&clock CLK_DIV_ACP>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 133000>;
+ };
+
+ peri_block: memory_bus_block3 {
+ clocks = <&clock CLK_ACLK100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 100000
+ 100000
+ 100000>;
+ };
+
+ fsys_block: memory_bus_block4 {
+ clocks = <&clock CLK_ACLK133>;
+ clock-names = "memory-bus";
+ frequency = <
+ 133000
+ 133000
+ 100000>;
+ };
+
+ display_block: memory_bus_block5 {
+ clocks = <&clock CLK_ACLK160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 160000
+ 133000
+ 100000>;
+ };
+
+ lcd0_block: memory_bus_block6 {
+ clocks = <&clock CLK_ACLK200>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000>;
+ };
+
+ leftbus_block: memory_bus_block7 {
+ clocks = <&clock CLK_DIV_GDL>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000>;
+ };
+
+ rightbus_block: memory_bus_block8 {
+ clocks = <&clock CLK_DIV_GDR>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000>;
+ };
+
+ mfc_block: memory_bus_block9 {
+ clocks = <&clock CLK_SCLK_MFC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000>;
+ };
+ };
+ };
+
pmu_system_controller: system-controller@10020000 {
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
"clkout4", "clkout8", "clkout9";
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 6/8] ARM: dts: Add memory bus node for Exynos4210
@ 2014-12-31 5:19 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has
one memory bus to translate data between DRAM and eMMC/sub-IPs because
Exynos4210 must need only one regulator for memory bus.
Following list specifies the detailed relation between memory bus clock and
sub-IPs:
- DMC/ACP clock : DMC (Dynamic Memory Controller)
- ACLK200 clock : LCD0
- ACLK100 clock : PERIL/PERIR/MFC(PCLK)
- ACLK160 clock : CAM/TV/LCD0/LCD1
- ACLK133 clock : FSYS/GPS
- GDL/GDR clock : leftbus/rightbus
- SCLK_MFC clock : MFC
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm/boot/dts/exynos4210.dtsi | 93 +++++++++++++++++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index b2598de..c039409 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -48,6 +48,99 @@
};
};
+ memory_bus: memory_bus at 0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 1150000
+ 267000 1050000
+ 133000 1025000>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <&clock CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 267000
+ 133000>;
+ };
+
+ acp_block: memory_bus_block2 {
+ clocks = <&clock CLK_DIV_ACP>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 133000>;
+ };
+
+ peri_block: memory_bus_block3 {
+ clocks = <&clock CLK_ACLK100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 100000
+ 100000
+ 100000>;
+ };
+
+ fsys_block: memory_bus_block4 {
+ clocks = <&clock CLK_ACLK133>;
+ clock-names = "memory-bus";
+ frequency = <
+ 133000
+ 133000
+ 100000>;
+ };
+
+ display_block: memory_bus_block5 {
+ clocks = <&clock CLK_ACLK160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 160000
+ 133000
+ 100000>;
+ };
+
+ lcd0_block: memory_bus_block6 {
+ clocks = <&clock CLK_ACLK200>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000>;
+ };
+
+ leftbus_block: memory_bus_block7 {
+ clocks = <&clock CLK_DIV_GDL>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000>;
+ };
+
+ rightbus_block: memory_bus_block8 {
+ clocks = <&clock CLK_DIV_GDR>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000>;
+ };
+
+ mfc_block: memory_bus_block9 {
+ clocks = <&clock CLK_SCLK_MFC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000>;
+ };
+ };
+ };
+
pmu_system_controller: system-controller at 10020000 {
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
"clkout4", "clkout8", "clkout9";
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 7/8] ARM: dts: Add memory bus node for Exynos3250-based Rinato board
2014-12-31 5:19 ` Chanwoo Choi
@ 2014-12-31 5:19 ` Chanwoo Choi
-1 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: myungjoo.ham
Cc: kgene.kim, kyungmin.park, rafael.j.wysocki, mark.rutland,
a.kesavan, tomasz.figa, k.kozlowski, b.zolnierkie, cw00.choi,
inki.dae, linux-pm, linux-kernel, linux-arm-kernel,
linux-samsung-soc
This patch adds the Exynos3250 memory-bus node which includes the regulator
and devfreq-event phandle. The devfreq-event phandle is used for the
governor of devfreq device and provide the current usage state of
MIF (Memory Interface) / INT (Internal) memory bus group.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
arch/arm/boot/dts/exynos3250-rinato.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 60948ae..6722555 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -564,6 +564,18 @@
};
};
+&memory_bus_mif {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-mem-supply = <&buck1_reg>;
+ status = "okay";
+};
+
+&memory_bus_int {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-mem-supply = <&buck3_reg>;
+ status = "okay";
+};
+
&xusbxti {
clock-frequency = <24000000>;
};
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 7/8] ARM: dts: Add memory bus node for Exynos3250-based Rinato board
@ 2014-12-31 5:19 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the Exynos3250 memory-bus node which includes the regulator
and devfreq-event phandle. The devfreq-event phandle is used for the
governor of devfreq device and provide the current usage state of
MIF (Memory Interface) / INT (Internal) memory bus group.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
arch/arm/boot/dts/exynos3250-rinato.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 60948ae..6722555 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -564,6 +564,18 @@
};
};
+&memory_bus_mif {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-mem-supply = <&buck1_reg>;
+ status = "okay";
+};
+
+&memory_bus_int {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-mem-supply = <&buck3_reg>;
+ status = "okay";
+};
+
&xusbxti {
clock-frequency = <24000000>;
};
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 8/8] ARM: dts: Add memory bus node for Exynos4412-based TRATS2 board
2014-12-31 5:19 ` Chanwoo Choi
@ 2014-12-31 5:19 ` Chanwoo Choi
-1 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: myungjoo.ham
Cc: kgene.kim, kyungmin.park, rafael.j.wysocki, mark.rutland,
a.kesavan, tomasz.figa, k.kozlowski, b.zolnierkie, cw00.choi,
inki.dae, linux-pm, linux-kernel, linux-arm-kernel,
linux-samsung-soc
This patch adds the Exynos4412 memory-bus node which includes the regulator
and devfreq-event phandle. The devfreq-event phandle is used for the
governor of devfreq device and provide the current usage state of
MIF (Memory Interface) / INT (Internal) memory bus group.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm/boot/dts/exynos4412-trats2.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index bee0eed..21ba25e 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -917,6 +917,18 @@
};
};
+&memory_bus_mif {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-mem-supply = <&buck1_reg>;
+ status = "okay";
+};
+
+&memory_bus_int {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-mem-supply = <&buck3_reg>;
+ status = "okay";
+};
+
&pinctrl_0 {
pinctrl-names = "default";
pinctrl-0 = <&sleep0>;
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [RFC PATCHv2 8/8] ARM: dts: Add memory bus node for Exynos4412-based TRATS2 board
@ 2014-12-31 5:19 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2014-12-31 5:19 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the Exynos4412 memory-bus node which includes the regulator
and devfreq-event phandle. The devfreq-event phandle is used for the
governor of devfreq device and provide the current usage state of
MIF (Memory Interface) / INT (Internal) memory bus group.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm/boot/dts/exynos4412-trats2.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index bee0eed..21ba25e 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -917,6 +917,18 @@
};
};
+&memory_bus_mif {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-mem-supply = <&buck1_reg>;
+ status = "okay";
+};
+
+&memory_bus_int {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-mem-supply = <&buck3_reg>;
+ status = "okay";
+};
+
&pinctrl_0 {
pinctrl-names = "default";
pinctrl-0 = <&sleep0>;
--
1.8.5.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
end of thread, other threads:[~2014-12-31 5:22 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-12-31 5:19 [RFC PATCHv2 0/8] devfreq: Add generic exynos memory-bus frequency driver Chanwoo Choi
2014-12-31 5:19 ` Chanwoo Choi
2014-12-31 5:19 ` [RFC PATCHv2 1/8] devfreq: exynos: Add generic exynos memory bus " Chanwoo Choi
2014-12-31 5:19 ` Chanwoo Choi
2014-12-31 5:19 ` [RFC PATCHv2 2/8] devfreq: exynos: Add documentation for " Chanwoo Choi
2014-12-31 5:19 ` Chanwoo Choi
2014-12-31 5:19 ` Chanwoo Choi
2014-12-31 5:19 ` [RFC PATCHv2 3/8] ARM: dts: Add memory bus node for Exynos3250 Chanwoo Choi
2014-12-31 5:19 ` Chanwoo Choi
2014-12-31 5:19 ` [RFC PATCHv2 4/8] clk: samsung: exynos4: Add divider clock id for memory bus frequency Chanwoo Choi
2014-12-31 5:19 ` Chanwoo Choi
2014-12-31 5:19 ` Chanwoo Choi
2014-12-31 5:19 ` [RFC PATCHv2 5/8] ARM: dts: Add memory bus node for Exynos4x12 Chanwoo Choi
2014-12-31 5:19 ` Chanwoo Choi
2014-12-31 5:19 ` [RFC PATCHv2 6/8] ARM: dts: Add memory bus node for Exynos4210 Chanwoo Choi
2014-12-31 5:19 ` Chanwoo Choi
2014-12-31 5:19 ` [RFC PATCHv2 7/8] ARM: dts: Add memory bus node for Exynos3250-based Rinato board Chanwoo Choi
2014-12-31 5:19 ` Chanwoo Choi
2014-12-31 5:19 ` [RFC PATCHv2 8/8] ARM: dts: Add memory bus node for Exynos4412-based TRATS2 board Chanwoo Choi
2014-12-31 5:19 ` Chanwoo Choi
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