* [RFC v01] Driver for Toshiba TC358743 CSI-2 to HDMI bridge
@ 2014-12-15 18:21 matrandg
2014-12-17 10:32 ` Hans Verkuil
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: matrandg @ 2014-12-15 18:21 UTC (permalink / raw)
To: linux-media; +Cc: hansverk, Mats Randgaard
From: Mats Randgaard <matrandg@cisco.com>
The driver is tested on our hardware and all the implemented features
works as expected.
Missing features:
- CEC support
- HDCP repeater support
- IR support
Signed-off-by: Mats Randgaard <matrandg@cisco.com>
---
MAINTAINERS | 6 +
drivers/media/i2c/Kconfig | 12 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/tc358743.c | 1768 ++++++++++++++++++++++++++++++++++++
drivers/media/i2c/tc358743_regs.h | 670 ++++++++++++++
include/media/tc358743.h | 89 ++
include/uapi/linux/v4l2-controls.h | 4 +
7 files changed, 2550 insertions(+)
create mode 100644 drivers/media/i2c/tc358743.c
create mode 100644 drivers/media/i2c/tc358743_regs.h
create mode 100644 include/media/tc358743.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 9c49eb6..7608a83 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9448,6 +9448,12 @@ L: platform-driver-x86@vger.kernel.org
S: Orphan
F: drivers/platform/x86/toshiba_acpi.c
+TOSHIBA TC358743 DRIVER
+M: Mats Randgaard <matrandg@cisco.com>
+L: linux-media@vger.kernel.org
+S: Maintained
+F: drivers/media/i2c/tc358743*
+
TOSHIBA SMM DRIVER
M: Jonathan Buzzard <jonathan@buzzard.org.uk>
L: tlinux-users@tce.toshiba-dme.co.jp
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index f40b4cf..0103cdf 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -293,6 +293,18 @@ config VIDEO_SAA7191
To compile this driver as a module, choose M here: the
module will be called saa7191.
+config VIDEO_TC358743
+ tristate "Toshiba TC358743 decoder"
+ depends on VIDEO_V4L2 && I2C
+ ---help---
+ Support for the Toshiba TC358743 HDMI to MIPI CSI-2 bridge
+
+ This is a Analog Devices Component/Graphics Digitizer
+ with 4:1 Multiplexed HDMI Receiver.
+
+ To compile this driver as a module, choose M here: the
+ module will be called tc358743.
+
config VIDEO_TVP514X
tristate "Texas Instruments TVP514x video decoder"
depends on VIDEO_V4L2 && I2C
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index 01ae932..b4dea43 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -78,3 +78,4 @@ obj-$(CONFIG_VIDEO_SMIAPP_PLL) += smiapp-pll.o
obj-$(CONFIG_VIDEO_AK881X) += ak881x.o
obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
obj-$(CONFIG_VIDEO_ML86V7667) += ml86v7667.o
+obj-$(CONFIG_VIDEO_TC358743) += tc358743.o
diff --git a/drivers/media/i2c/tc358743.c b/drivers/media/i2c/tc358743.c
new file mode 100644
index 0000000..a86cbe0
--- /dev/null
+++ b/drivers/media/i2c/tc358743.c
@@ -0,0 +1,1768 @@
+/*
+ * tc358743 - Toshiba HDMI to CSI-2 bridge
+ *
+ * Copyright 2014 Cisco Systems, Inc. and/or its affiliates. All rights
+ * reserved.
+ *
+ * This program is free software; you may redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+/*
+ * References (c = chapter, p = page):
+ * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
+ * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/videodev2.h>
+#include <linux/workqueue.h>
+#include <linux/v4l2-dv-timings.h>
+#include <media/v4l2-dv-timings.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ctrls.h>
+#include <media/tc358743.h>
+
+#include "tc358743_regs.h"
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "debug level (0-3)");
+
+MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
+MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
+MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
+MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
+MODULE_LICENSE("GPL");
+
+static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
+ .type = V4L2_DV_BT_656_1120,
+ /* keep this initialization for compatibility with GCC < 4.4.6 */
+ .reserved = { 0 },
+ /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
+ V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000,
+ V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
+ V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
+ V4L2_DV_BT_CAP_PROGRESSIVE |
+ V4L2_DV_BT_CAP_REDUCED_BLANKING |
+ V4L2_DV_BT_CAP_CUSTOM)
+};
+
+struct tc358743_state {
+ struct tc358743_platform_data pdata;
+ struct v4l2_subdev sd;
+ struct media_pad pad;
+ struct v4l2_ctrl_handler hdl;
+ struct i2c_client *i2c_client;
+
+ /* controls */
+ struct v4l2_ctrl *detect_tx_5v_ctrl;
+ struct v4l2_ctrl *audio_sampling_rate_ctrl;
+ struct v4l2_ctrl *audio_present_ctrl;
+
+ /* work queues */
+ struct workqueue_struct *work_queues;
+ struct delayed_work delayed_work_enable_hotplug;
+
+ /* edid */
+ bool edid_written;
+
+ struct v4l2_dv_timings timings;
+ u32 mbus_fmt_code;
+};
+
+static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct tc358743_state, sd);
+}
+
+/* --------------- I2C --------------- */
+
+static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
+{
+ struct tc358743_state *state = to_state(sd);
+ struct i2c_client *client = state->i2c_client;
+ int err;
+ u8 buf[2] = { reg >> 8, reg & 0xff };
+ struct i2c_msg msgs[] = {
+ {
+ .addr = client->addr,
+ .flags = 0,
+ .len = 2,
+ .buf = buf,
+ },
+ {
+ .addr = client->addr,
+ .flags = I2C_M_RD,
+ .len = n,
+ .buf = values,
+ },
+ };
+
+ err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+ if (err != ARRAY_SIZE(msgs)) {
+ v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
+ __func__, reg, client->addr);
+ }
+}
+
+static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
+{
+ struct tc358743_state *state = to_state(sd);
+ struct i2c_client *client = state->i2c_client;
+ int err, i;
+ struct i2c_msg msg;
+ u8 data[2 + n];
+
+ msg.addr = client->addr;
+ msg.buf = data;
+ msg.len = 2 + n;
+ msg.flags = 0;
+
+ data[0] = reg >> 8;
+ data[1] = reg & 0xff;
+
+ for (i = 0; i < n; i++)
+ data[2 + i] = values[i];
+
+ err = i2c_transfer(client->adapter, &msg, 1);
+ if (err != 1) {
+ v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
+ __func__, reg, client->addr);
+ return;
+ }
+
+ if (debug < 3)
+ return;
+
+ switch (n) {
+ case 1:
+ v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
+ reg, data[2]);
+ break;
+ case 2:
+ v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
+ reg, data[3], data[2]);
+ break;
+ case 4:
+ v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
+ reg, data[5], data[4], data[3], data[2]);
+ break;
+ default:
+ v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
+ n, reg);
+ }
+}
+
+static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
+{
+ u8 val;
+
+ i2c_rd(sd, reg, &val, 1);
+
+ return val;
+}
+
+static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
+{
+ i2c_wr(sd, reg, &val, 1);
+}
+
+static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
+ u8 mask, u8 val)
+{
+ i2c_wr8(sd, reg, (i2c_rd8(sd, reg) & mask) | val);
+}
+
+static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
+{
+ u16 val;
+
+ i2c_rd(sd, reg, (u8 *)&val, 2);
+
+ return val;
+}
+
+static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
+{
+ i2c_wr(sd, reg, (u8 *)&val, 2);
+}
+
+static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
+{
+ i2c_wr16(sd, reg, (i2c_rd16(sd, reg) & mask) | val);
+}
+
+static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
+{
+ u32 val;
+
+ i2c_rd(sd, reg, (u8 *)&val, 4);
+
+ return val;
+}
+
+static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
+{
+ i2c_wr(sd, reg, (u8 *)&val, 4);
+}
+
+/* --------------- STATUS --------------- */
+
+static inline bool is_hdmi(struct v4l2_subdev *sd)
+{
+ return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
+}
+
+static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
+{
+ return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
+}
+
+static inline bool no_signal(struct v4l2_subdev *sd)
+{
+ return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
+}
+
+static inline bool no_sync(struct v4l2_subdev *sd)
+{
+ return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
+}
+
+static inline bool audio_present(struct v4l2_subdev *sd)
+{
+ return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
+}
+
+static int get_audio_sampling_rate(struct v4l2_subdev *sd)
+{
+ static const int code_to_rate[] = {
+ 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
+ 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
+ };
+
+ /* Register FS_SET is not cleared when the cable is disconnected */
+ if (no_signal(sd))
+ return 0;
+
+ return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
+}
+
+static unsigned tc358743_num_csi_lanes_in_use(struct v4l2_subdev *sd)
+{
+ return ((i2c_rd32(sd, CSI_CONTROL) & MASK_NOL) >> 1) + 1;
+}
+
+/* --------------- TIMINGS --------------- */
+
+static inline unsigned fps(const struct v4l2_bt_timings *t)
+{
+ if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
+ return 0;
+
+ return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
+ V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
+}
+
+static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
+ struct v4l2_dv_timings *timings)
+{
+ struct v4l2_bt_timings *bt = &timings->bt;
+ unsigned width, height, frame_width, frame_height, frame_interval, fps;
+
+ memset(timings, 0, sizeof(struct v4l2_dv_timings));
+
+ if (no_signal(sd)) {
+ v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
+ return -ENOLINK;
+ }
+ if (no_sync(sd))
+ v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
+
+ timings->type = V4L2_DV_BT_656_1120;
+ bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
+ V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
+
+ width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
+ i2c_rd8(sd, DE_WIDTH_H_LO);
+ height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
+ i2c_rd8(sd, DE_WIDTH_V_LO);
+ frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
+ i2c_rd8(sd, H_SIZE_LO);
+ frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
+ i2c_rd8(sd, V_SIZE_LO)) / 2;
+ /* frame interval in milliseconds * 10
+ * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
+ frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
+ i2c_rd8(sd, FV_CNT_LO);
+ fps = (frame_interval > 0) ?
+ DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
+
+ bt->width = width;
+ bt->height = height;
+ bt->vsync = frame_height - height;
+ bt->hsync = frame_width - width;
+ bt->pixelclock = frame_width * frame_height * fps;
+
+ return 0;
+}
+
+/* --------------- HOTPLUG / HDCP / EDID --------------- */
+
+static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
+{
+ struct delayed_work *dwork = to_delayed_work(work);
+ struct tc358743_state *state = container_of(dwork,
+ struct tc358743_state, delayed_work_enable_hotplug);
+ struct v4l2_subdev *sd = &state->sd;
+
+ v4l2_dbg(2, debug, sd, "%s:\n", __func__);
+
+ i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
+}
+
+static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
+{
+ v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
+ "enable" : "disable");
+
+ i2c_wr8_and_or(sd, HDCP_REG1,
+ ~(MASK_AUTH_UNAUTH_SEL | MASK_AUTH_UNAUTH),
+ MASK_AUTH_UNAUTH_SEL_16_FRAMES | MASK_AUTH_UNAUTH_AUTO);
+
+ i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
+ SET_AUTO_P3_RESET_FRAMES(0x0f));
+
+ /* HDCP is disabled by configuring the receiver as HDCP repeater.
+ * The repeater mode require software support to work, so
+ * HDCP authentication will fail. Set Ready and MAX_EXCED bits
+ * to avoid problems on MacBook Pro gen.8.
+ */
+ i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, enable ? KEY_RD_CMD : 0);
+
+ i2c_wr8_and_or(sd, HDCP_MODE, ~(MASK_AUTO_CLR | MASK_MODE_RST_TN),
+ enable ? (MASK_AUTO_CLR | MASK_MODE_RST_TN) : 0);
+
+ i2c_wr8_and_or(sd, BSTATUS1, ~MASK_MAX_EXCED,
+ enable ? 0 : MASK_MAX_EXCED);
+
+ i2c_wr8_and_or(sd, BCAPS, ~(MASK_REPEATER | MASK_READY),
+ enable ? 0 : MASK_REPEATER | MASK_READY);
+}
+
+static void tc358743_disable_edid(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+
+ v4l2_dbg(2, debug, sd, "%s:\n", __func__);
+
+ cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
+
+ /* DDC access to EDID is also disabled when hotplug is disabled. See
+ * register DDC_CTL */
+ i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
+}
+
+static void tc358743_enable_edid(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+
+ if (!state->edid_written) {
+ v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
+ return;
+ }
+
+ v4l2_dbg(2, debug, sd, "%s:\n", __func__);
+
+ /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
+ * hotplug is enabled. See register DDC_CTL */
+ queue_delayed_work(state->work_queues,
+ &state->delayed_work_enable_hotplug, HZ / 10);
+}
+
+/* --------------- AVI --------------- */
+/* TODO move to common library */
+
+struct aviInfoFrame {
+ u8 f17;
+ u8 y10;
+ u8 a0;
+ u8 b10;
+ u8 s10;
+ u8 c10;
+ u8 m10;
+ u8 r3210;
+ u8 itc;
+ u8 ec210;
+ u8 q10;
+ u8 sc10;
+ u8 f47;
+ u8 vic;
+ u8 yq10;
+ u8 cn10;
+ u8 pr3210;
+ u16 etb;
+ u16 sbb;
+ u16 elb;
+ u16 srb;
+};
+
+static const char *y10Text[4] = {
+ "RGB",
+ "YCbCr 4:2:2",
+ "YCbCr 4:4:4",
+ "Future",
+};
+
+static const char *c10Text[4] = {
+ "No Data",
+ "SMPTE 170M",
+ "ITU-R 709",
+ "Extended Colorimetry information valied",
+};
+
+static const char *itcText[2] = {
+ "No Data",
+ "IT content",
+};
+
+static const char *ec210Text[8] = {
+ "xvYCC601",
+ "xvYCC709",
+ "sYCC601",
+ "AdobeYCC601",
+ "AdobeRGB",
+ "5 reserved",
+ "6 reserved",
+ "7 reserved",
+};
+
+static const char *q10Text[4] = {
+ "Default",
+ "Limited Range",
+ "Full Range",
+ "Reserved",
+};
+
+static void parse_avi_infoframe(struct v4l2_subdev *sd, u8 *buf,
+ struct aviInfoFrame *avi)
+{
+ avi->f17 = (buf[1] >> 7) & 0x1;
+ avi->y10 = (buf[1] >> 5) & 0x3;
+ avi->a0 = (buf[1] >> 4) & 0x1;
+ avi->b10 = (buf[1] >> 2) & 0x3;
+ avi->s10 = buf[1] & 0x3;
+ avi->c10 = (buf[2] >> 6) & 0x3;
+ avi->m10 = (buf[2] >> 4) & 0x3;
+ avi->r3210 = buf[2] & 0xf;
+ avi->itc = (buf[3] >> 7) & 0x1;
+ avi->ec210 = (buf[3] >> 4) & 0x7;
+ avi->q10 = (buf[3] >> 2) & 0x3;
+ avi->sc10 = buf[3] & 0x3;
+ avi->f47 = (buf[4] >> 7) & 0x1;
+ avi->vic = buf[4] & 0x7f;
+ avi->yq10 = (buf[5] >> 6) & 0x3;
+ avi->cn10 = (buf[5] >> 4) & 0x3;
+ avi->pr3210 = buf[5] & 0xf;
+ avi->etb = buf[6] + 256 * buf[7];
+ avi->sbb = buf[8] + 256 * buf[9];
+ avi->elb = buf[10] + 256 * buf[11];
+ avi->srb = buf[12] + 256 * buf[13];
+}
+
+static void print_avi_infoframe(struct v4l2_subdev *sd)
+{
+ u8 buf[14];
+ u8 avi_len;
+ u8 avi_ver;
+ struct aviInfoFrame avi;
+
+ if (!is_hdmi(sd)) {
+ v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
+ return;
+ }
+
+ avi_ver = i2c_rd8(sd, PK_AVI_1HEAD);
+ avi_len = i2c_rd8(sd, PK_AVI_2HEAD);
+ v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", avi_ver, avi_len);
+
+ if (avi_ver != 0x02)
+ return;
+
+ i2c_rd(sd, PK_AVI_0BYTE, buf, ARRAY_SIZE(buf));
+
+ v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+ buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
+ buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
+ buf[13]);
+
+ parse_avi_infoframe(sd, buf, &avi);
+
+ if (avi.vic)
+ v4l2_info(sd, "\tVIC: %d\n", avi.vic);
+ if (avi.itc)
+ v4l2_info(sd, "\t%s\n", itcText[avi.itc]);
+
+ if (avi.y10)
+ v4l2_info(sd, "\t%s %s\n", y10Text[avi.y10],
+ !avi.c10 ? "" :
+ (avi.c10 == 0x3 ? ec210Text[avi.ec210] :
+ c10Text[avi.c10]));
+ else
+ v4l2_info(sd, "\t%s %s\n", y10Text[avi.y10], q10Text[avi.q10]);
+}
+
+/* --------------- CTRLS --------------- */
+
+static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+
+ return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
+ tx_5v_power_present(sd));
+}
+
+static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+
+ return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
+ get_audio_sampling_rate(sd));
+}
+
+static int tc358743_s_audio_present_ctrl(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+
+ return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
+ audio_present(sd));
+}
+
+static int tc358743_update_controls(struct v4l2_subdev *sd)
+{
+ int ret = 0;
+
+ ret |= tc358743_s_ctrl_detect_tx_5v(sd);
+ ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
+ ret |= tc358743_s_audio_present_ctrl(sd);
+
+ return ret;
+}
+
+/* --------------- INIT --------------- */
+
+static void tc358743_reset_phy(struct v4l2_subdev *sd)
+{
+ v4l2_dbg(1, debug, sd, "%s:\n", __func__);
+
+ i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
+ i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
+}
+
+static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
+{
+ u16 sysctl = i2c_rd16(sd, SYSCTL);
+
+ i2c_wr16(sd, SYSCTL, sysctl | mask);
+ i2c_wr16(sd, SYSCTL, sysctl & ~mask);
+}
+
+static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
+{
+ i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
+ enable ? MASK_SLEEP : 0);
+}
+
+static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
+{
+ v4l2_dbg(3, debug, sd, "%s: %sable\n",
+ __func__, enable ? "en" : "dis");
+
+ i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
+ enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
+}
+
+static void tc358743_set_pll(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+ struct tc358743_platform_data *pdata = &state->pdata;
+ u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
+ u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
+ SET_PLL_FBD(pdata->pll_fbd);
+
+ v4l2_dbg(2, debug, sd, "%s:\n", __func__);
+
+ /* Only rewrite when needed, since rewriting triggers another format
+ * change event. */
+ if (pllctl0 != pllctl0_new) {
+ u32 hsck = (pdata->refclk_hz * pdata->pll_prd) / pdata->pll_fbd;
+ u16 pll_frs;
+
+ if (hsck > 500000000)
+ pll_frs = 0x0;
+ else if (hsck > 250000000)
+ pll_frs = 0x1;
+ else if (hsck > 125000000)
+ pll_frs = 0x2;
+ else
+ pll_frs = 0x3;
+
+ v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
+ tc358743_sleep_mode(sd, true);
+ i2c_wr16(sd, PLLCTL0, pllctl0_new);
+ i2c_wr16_and_or(sd, PLLCTL1,
+ ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
+ (SET_PLL_FRS(pll_frs) | MASK_RESETB |
+ MASK_PLL_EN));
+ udelay(10); /* REF_02, Sheet "Source HDMI" */
+ i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
+ tc358743_sleep_mode(sd, false);
+ }
+}
+
+static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+ struct tc358743_platform_data *pdata = &state->pdata;
+ u32 sys_freq;
+ u32 lockdet_ref;
+ u16 fh_min;
+ u16 fh_max;
+
+ BUG_ON(!(pdata->refclk_hz == 26000000 ||
+ pdata->refclk_hz == 27000000 ||
+ pdata->refclk_hz == 42000000));
+
+ sys_freq = pdata->refclk_hz / 10000;
+ i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
+ i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
+
+ i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
+ (pdata->refclk_hz == 42000000) ?
+ MASK_PHY_SYSCLK_IND : 0x0);
+
+ fh_min = pdata->refclk_hz / 100000;
+ i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
+ i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
+
+ fh_max = (fh_min * 66) / 10;
+ i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
+ i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
+
+ lockdet_ref = pdata->refclk_hz / 100;
+ i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
+ i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
+ i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
+
+ i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
+ (pdata->refclk_hz == 27000000) ?
+ MASK_NCO_F0_MOD_27MHZ : 0x0);
+}
+
+static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+
+ switch (state->mbus_fmt_code) {
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
+ i2c_wr8_and_or(sd, VOUT_SET2,
+ ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
+ MASK_SEL422 | MASK_VOUT_422FIL_100);
+ i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
+ MASK_VOUT_COLOR_601_YCBCR_LIMITED);
+ i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
+ MASK_YCBCRFMT_422_8_BIT);
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
+ i2c_wr8_and_or(sd, VOUT_SET2,
+ ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
+ 0x00);
+ i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
+ MASK_VOUT_COLOR_RGB_FULL);
+ i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
+ break;
+ default:
+ v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
+ __func__, state->mbus_fmt_code);
+ }
+}
+
+static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+ struct v4l2_bt_timings *bt = &state->timings.bt;
+ u32 bits_pr_pixel =
+ (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
+ u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
+
+ return DIV_ROUND_UP(bps, state->pdata.bps_pr_lane);
+}
+
+static void tc358743_set_csi(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+ struct tc358743_platform_data *pdata = &state->pdata;
+ unsigned lanes = tc358743_num_csi_lanes_needed(sd);
+
+ v4l2_dbg(3, debug, sd, "%s:\n", __func__);
+
+ tc358743_reset(sd, MASK_CTXRST);
+
+ if (lanes < 1)
+ i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
+ if (lanes < 1)
+ i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
+ if (lanes < 2)
+ i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
+ if (lanes < 3)
+ i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
+ if (lanes < 4)
+ i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
+
+ i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
+ i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
+ i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
+ i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
+ i2c_wr32(sd, TWAKEUP, pdata->twakeup);
+ i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
+ i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
+
+ i2c_wr32(sd, HSTXVREGEN,
+ ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
+ ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
+ ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
+ ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
+ ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
+
+ i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
+ i2c_wr32(sd, STARTCNTRL, MASK_START);
+ i2c_wr32(sd, CSI_START, MASK_STRT);
+
+ i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
+ MASK_ADDRESS_CSI_CONTROL |
+ MASK_CSI_MODE |
+ MASK_TXHSMD |
+ ((lanes == 4) ? MASK_NOL_4 :
+ (lanes == 3) ? MASK_NOL_3 :
+ (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
+
+ i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
+ MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
+ MASK_WCER | MASK_INER);
+
+ i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
+ MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
+
+ i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
+ MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
+}
+
+static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+ struct tc358743_platform_data *pdata = &state->pdata;
+
+ /* Default settings from REF_02, sheet "Source HDMI"
+ * and custom settings as platform data */
+ i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
+ i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
+ SET_FREQ_RANGE_MODE_CYCLES(1));
+ i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn, pdata->phy_auto_rst);
+ i2c_wr8(sd, PHY_BIAS, 0x40);
+ i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
+ i2c_wr8(sd, AVM_CTL, 45);
+ i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
+ pdata->hdmi_det_v);
+ i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
+ (pdata->h_pi_rst ? MASK_H_PI_RST : 0) |
+ (pdata->v_pi_rst ? MASK_V_PI_RST : 0));
+ i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
+}
+
+static void tc358743_erase_bksv(struct v4l2_subdev *sd)
+{
+ int i;
+
+ for (i = 0; i < 5; i++)
+ i2c_wr8(sd, BKSV + i, 0);
+}
+
+static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
+{
+ /* Default settings from REF_02, sheet "Source HDMI" */
+ i2c_wr8(sd, FORCE_MUTE, 0x00);
+ i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
+ MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
+ MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
+ i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
+ i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
+ i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
+ i2c_wr8(sd, FS_MUTE, 0x00);
+ i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
+ i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
+ i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
+ i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
+ i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
+ i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
+ i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
+ MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
+}
+
+static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
+{
+ /* Default settings from REF_02, sheet "Source HDMI" */
+ i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
+ MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
+ MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
+ MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
+ i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
+ i2c_wr8(sd, NO_PKT_CLR, 0x53);
+ i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
+ i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
+ i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
+}
+
+static void tc358743_initial_setup(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+ struct tc358743_platform_data *pdata = &state->pdata;
+
+ /* Keep CEC and IR in reset since driver support is missing */
+ i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST),
+ (MASK_CECRST | MASK_IRRST));
+
+ tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
+ tc358743_sleep_mode(sd, false);
+
+ i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
+
+ tc358743_set_ref_clk(sd);
+
+ i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
+ pdata->ddc5v_delay & MASK_DDC5V_MODE);
+ i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
+
+ tc358743_set_hdmi_phy(sd);
+ tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
+ tc358743_set_hdmi_audio(sd);
+ tc358743_set_hdmi_info_frame_mode(sd);
+
+ i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
+ MASK_VOUTCOLORMODE_AUTO);
+ i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
+}
+
+/* --------------- IRQ --------------- */
+
+static void tc358743_enable_interrupts(struct v4l2_subdev *sd)
+{
+ u16 i;
+
+ /* clear interrupt status registers */
+ for (i = SYS_INT; i <= KEY_INT; i++)
+ i2c_wr8(sd, i, 0xff);
+
+ i2c_wr16(sd, INTSTATUS, 0xffff);
+
+ /* enable interrupts */
+ i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_HDMI_DET) & 0xff);
+
+ i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
+
+ i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
+
+ i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
+ MASK_M_AF_UNLOCK) & 0xff);
+
+ i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff);
+}
+
+static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
+{
+ v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
+
+ i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
+}
+
+static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
+ bool *handled)
+{
+ u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
+ u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
+
+ i2c_wr8(sd, MISC_INT, misc_int);
+
+ v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
+
+ if (misc_int & MASK_I_SYNC_CHG) {
+
+ v4l2_dbg(1, debug, sd, "%s: Format changed\n", __func__);
+
+ if (no_sync(sd) || no_signal(sd)) {
+ tc358743_reset_phy(sd);
+ tc358743_erase_bksv(sd);
+ }
+
+ v4l2_subdev_notify(sd, TC358743_FMT_CHANGE, NULL);
+
+ misc_int &= ~MASK_I_SYNC_CHG;
+ if (handled)
+ *handled = true;
+ }
+
+ if (misc_int) {
+ v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
+ __func__, misc_int);
+ }
+}
+
+static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
+ bool *handled)
+{
+ u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
+ u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
+
+ i2c_wr8(sd, CBIT_INT, cbit_int);
+
+ v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
+
+ if (cbit_int & MASK_I_CBIT_FS) {
+
+ v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
+ __func__);
+ tc358743_s_ctrl_audio_sampling_rate(sd);
+
+ cbit_int &= ~MASK_I_CBIT_FS;
+ if (handled)
+ *handled = true;
+ }
+
+ if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
+
+ v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
+ __func__);
+ tc358743_s_audio_present_ctrl(sd);
+
+ cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
+ if (handled)
+ *handled = true;
+ }
+
+ if (cbit_int) {
+ v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
+ __func__, cbit_int);
+ }
+}
+
+static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
+{
+ u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
+ u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
+
+ /* Bit 7 and bit 6 are set even when they are masked */
+ i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
+
+ v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
+
+ if (clk_int & (MASK_I_IN_DE_CHG)) {
+
+ v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
+ __func__);
+
+ /* If the source switch to a new resolution with the same pixel
+ * frequency as the existing (ie. 1080p25 -> 720p50), the
+ * I_SYNC_CHG interrupt is not always triggered, while the
+ * I_IN_DE_CHG interrupt seems to work fine. FMT_CHANGE
+ * notifications are only sent when the signal is stable to
+ * reduce the number of notifications. */
+ if (!no_signal(sd) && !no_sync(sd))
+ v4l2_subdev_notify(sd, TC358743_FMT_CHANGE, NULL);
+
+ clk_int &= ~(MASK_I_IN_DE_CHG);
+ if (handled)
+ *handled = true;
+ }
+
+ if (clk_int) {
+ v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
+ __func__, clk_int);
+ }
+}
+
+static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
+{
+ struct tc358743_state *state = to_state(sd);
+ u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
+ u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
+
+ i2c_wr8(sd, SYS_INT, sys_int);
+
+ v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
+
+ if (sys_int & MASK_I_DDC) {
+ bool tx_5v = tx_5v_power_present(sd);
+
+ v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
+ __func__, tx_5v ? "yes" : "no");
+
+ if (tx_5v) {
+ tc358743_enable_edid(sd);
+ } else {
+ tc358743_disable_edid(sd);
+ memset(&state->timings, 0, sizeof(state->timings));
+ tc358743_erase_bksv(sd);
+ }
+
+ tc358743_update_controls(sd);
+
+ sys_int &= ~MASK_I_DDC;
+ if (handled)
+ *handled = true;
+ }
+
+ if (sys_int & MASK_I_HDMI) {
+ v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
+ __func__);
+
+ /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
+ i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
+
+ sys_int &= ~MASK_I_HDMI;
+ if (handled)
+ *handled = true;
+ }
+
+ if (sys_int) {
+ v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
+ __func__, sys_int);
+ }
+}
+
+/* --------------- CORE OPS --------------- */
+
+static int tc358743_log_status(struct v4l2_subdev *sd)
+{
+ struct tc358743_state *state = to_state(sd);
+ struct v4l2_dv_timings timings;
+ uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
+ uint16_t sysctl = i2c_rd16(sd, SYSCTL);
+ u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
+ const int deep_color_mode[4] = { 8, 10, 12, 16 };
+ static const char * const input_color_space[] = {
+ "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
+ "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
+ "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
+
+ v4l2_info(sd, "-----Chip status-----\n");
+ v4l2_info(sd, "Chip ID: %d\n", i2c_rd16(sd, CHIPID) &
+ MASK_CHIPID);
+ v4l2_info(sd, "Chip revision: %d\n",
+ i2c_rd16(sd, CHIPID) & MASK_REVID);
+ v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
+ !!(sysctl & MASK_IRRST),
+ !!(sysctl & MASK_CECRST),
+ !!(sysctl & MASK_CTXRST),
+ !!(sysctl & MASK_HDMIRST));
+ v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
+ v4l2_info(sd, "Cable detected (+5V power): %s\n",
+ hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
+ v4l2_info(sd, "DDC lines enabled: %s\n",
+ (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
+ "yes" : "no");
+ v4l2_info(sd, "Hotplug enabled: %s\n",
+ (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
+ "yes" : "no");
+ v4l2_info(sd, "CEC enabled: %s\n",
+ (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
+ v4l2_info(sd, "-----Signal status-----\n");
+ v4l2_info(sd, "TMDS signal detected: %s\n",
+ hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
+ v4l2_info(sd, "Stable sync signal: %s\n",
+ hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
+ v4l2_info(sd, "PHY PLL locked: %s\n",
+ hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
+ v4l2_info(sd, "PHY DE detected: %s\n",
+ hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
+
+ if (tc358743_get_detected_timings(sd, &timings)) {
+ v4l2_info(sd, "No video detected\n");
+ } else {
+ v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
+ true);
+ }
+ v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
+ true);
+
+ v4l2_info(sd, "-----CSI-TX status-----\n");
+ v4l2_info(sd, "Lanes needed: %d\n",
+ tc358743_num_csi_lanes_needed(sd));
+ v4l2_info(sd, "Lanes in use: %d\n",
+ tc358743_num_csi_lanes_in_use(sd));
+ v4l2_info(sd, "Waiting for particular sync signal: %s\n",
+ (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
+ "yes" : "no");
+ v4l2_info(sd, "Transmit mode: %s\n",
+ (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
+ "yes" : "no");
+ v4l2_info(sd, "Receive mode: %s\n",
+ (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
+ "yes" : "no");
+ v4l2_info(sd, "Stopped: %s\n",
+ (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
+ "yes" : "no");
+ v4l2_info(sd, "Color space: %s\n",
+ state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
+ "YCbCr 422 16-bit" :
+ state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
+ "RGB 888 24-bit" : "Unsupported");
+
+ v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
+ v4l2_info(sd, "HDCP encrypted content: %s\n",
+ hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
+ v4l2_info(sd, "Input color space: %s %s range\n",
+ input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
+ (vi_status3 & MASK_LIMITED) ? "limited" : "full");
+ if (!is_hdmi(sd))
+ return 0;
+ v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
+ "off");
+ v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
+ deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
+ MASK_S_DEEPCOLOR) >> 2]);
+ print_avi_infoframe(sd);
+
+ return 0;
+}
+
+static long tc358743_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
+{
+ switch (cmd) {
+ case TC358743_CSI_RESET:
+ {
+ /*
+ * This function is called often with CSI overflow. It should
+ * run as fast as possible for quick recovery. I2C operations
+ * are slow. This function takes about 20 ms. Stop stream first,
+ * reset CSI and enable stream. Avoid calling enable_stream
+ * twice which add an extra I2C read.
+ */
+ unsigned short confctl = i2c_rd16(sd, CONFCTL);
+
+ v4l2_dbg(3, debug, sd, "%s: TC358743_CSI_RESET\n", __func__);
+
+ i2c_wr16(sd, CONFCTL, confctl &
+ (~(MASK_VBUFEN | MASK_ABUFEN)));
+ tc358743_set_csi(sd);
+ i2c_wr16(sd, CONFCTL, confctl |
+ (MASK_VBUFEN | MASK_ABUFEN));
+ return 0;
+ }
+ }
+
+ v4l2_dbg(1, debug, sd, "%s: unknown ioctl %08x\n", __func__, cmd);
+
+ return -ENOTTY;
+}
+
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+static void tc358743_print_register_map(struct v4l2_subdev *sd)
+{
+ v4l2_info(sd, "0x0000–0x00FF: Global Control Register\n");
+ v4l2_info(sd, "0x0100–0x01FF: CSI2-TX PHY Register\n");
+ v4l2_info(sd, "0x0200–0x03FF: CSI2-TX PPI Register\n");
+ v4l2_info(sd, "0x0400–0x05FF: Reserved\n");
+ v4l2_info(sd, "0x0600–0x06FF: CEC Register\n");
+ v4l2_info(sd, "0x0700–0x84FF: Reserved\n");
+ v4l2_info(sd, "0x8500–0x85FF: HDMIRX System Control Register\n");
+ v4l2_info(sd, "0x8600–0x86FF: HDMIRX Audio Control Register\n");
+ v4l2_info(sd, "0x8700–0x87FF: HDMIRX InfoFrame packet data Register\n");
+ v4l2_info(sd, "0x8800–0x88FF: HDMIRX HDCP Port Register\n");
+ v4l2_info(sd, "0x8900–0x89FF: HDMIRX Video Output Port & 3D Register\n");
+ v4l2_info(sd, "0x8A00–0x8BFF: Reserved\n");
+ v4l2_info(sd, "0x8C00–0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
+ v4l2_info(sd, "0x9000–0x90FF: HDMIRX GBD Extraction Control\n");
+ v4l2_info(sd, "0x9100–0x92FF: HDMIRX GBD RAM read\n");
+ v4l2_info(sd, "0x9300- : Reserved\n");
+}
+
+static int tc358743_get_reg_size(u16 address)
+{
+ /* REF_01 p. 66-72 */
+ if (address <= 0x00ff)
+ return 2;
+ else if ((address >= 0x0100) && (address <= 0x06FF))
+ return 4;
+ else if ((address >= 0x0700) && (address <= 0x84ff))
+ return 2;
+ else
+ return 1;
+}
+
+static int tc358743_g_register(struct v4l2_subdev *sd,
+ struct v4l2_dbg_register *reg)
+{
+ if (reg->reg > 0xffff) {
+ tc358743_print_register_map(sd);
+ return -EINVAL;
+ }
+
+ reg->size = tc358743_get_reg_size(reg->reg);
+
+ i2c_rd(sd, reg->reg, (u8 *)®->val, reg->size);
+
+ return 0;
+}
+
+static int tc358743_s_register(struct v4l2_subdev *sd,
+ const struct v4l2_dbg_register *reg)
+{
+ if (reg->reg > 0xffff) {
+ tc358743_print_register_map(sd);
+ return -EINVAL;
+ }
+
+ /* It should not be possible for the user to enable HDCP with a simple
+ * v4l2-dbg command.
+ *
+ * DO NOT REMOVE THIS unless all other issues with HDCP have been
+ * resolved.
+ */
+ if (reg->reg == HDCP_MODE ||
+ reg->reg == HDCP_REG1 ||
+ reg->reg == HDCP_REG2 ||
+ reg->reg == HDCP_REG3 ||
+ reg->reg == BCAPS)
+ return 0;
+
+ i2c_wr(sd, (u16)reg->reg, (u8 *)®->val,
+ tc358743_get_reg_size(reg->reg));
+
+ return 0;
+}
+#endif
+
+static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
+{
+ u16 intstatus = i2c_rd16(sd, INTSTATUS);
+
+ v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
+
+ if (intstatus & MASK_HDMI_INT) {
+ u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
+ u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
+
+ if (hdmi_int0 & MASK_I_MISC)
+ tc358743_hdmi_misc_int_handler(sd, handled);
+ if (hdmi_int1 & MASK_I_CBIT)
+ tc358743_hdmi_cbit_int_handler(sd, handled);
+ if (hdmi_int1 & MASK_I_CLK)
+ tc358743_hdmi_clk_int_handler(sd, handled);
+ if (hdmi_int1 & MASK_I_SYS)
+ tc358743_hdmi_sys_int_handler(sd, handled);
+
+ i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
+ intstatus &= ~MASK_HDMI_INT;
+ }
+
+ if (intstatus & MASK_CSI_INT) {
+ u32 csi_int = i2c_rd32(sd, CSI_INT);
+
+ if (csi_int & MASK_INTER)
+ tc358743_csi_err_int_handler(sd, handled);
+
+ i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
+ intstatus &= ~MASK_CSI_INT;
+ }
+
+ intstatus = i2c_rd16(sd, INTSTATUS);
+ if (intstatus) {
+ v4l2_dbg(1, debug, sd,
+ "%s: Unhandled IntStatus interrupts: 0x%02x\n",
+ __func__, intstatus);
+ }
+
+ return 0;
+}
+
+/* --------------- VIDEO OPS --------------- */
+
+static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
+{
+ *status = 0;
+ *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
+ *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
+
+ v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
+
+ return 0;
+}
+
+static int tc358743_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_format *format)
+{
+ struct tc358743_state *state = to_state(sd);
+
+ if (format->pad != 0)
+ return -EINVAL;
+
+ switch (format->format.code) {
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ state->mbus_fmt_code = format->format.code;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ enable_stream(sd, false);
+ tc358743_set_pll(sd);
+ tc358743_set_csi(sd);
+ tc358743_set_csi_color_space(sd);
+
+ return 0;
+}
+
+static int tc358743_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_format *format)
+{
+ struct tc358743_state *state = to_state(sd);
+ u8 vi_rep = i2c_rd8(sd, VI_REP);
+
+ if (format->pad != 0)
+ return -EINVAL;
+
+ format->format.code = state->mbus_fmt_code;
+ format->format.width = state->timings.bt.width;
+ format->format.height = state->timings.bt.height;
+ format->format.field = V4L2_FIELD_NONE;
+
+ switch (vi_rep & MASK_VOUT_COLOR_SEL) {
+ case MASK_VOUT_COLOR_RGB_FULL:
+ case MASK_VOUT_COLOR_RGB_LIMITED:
+ format->format.colorspace = V4L2_COLORSPACE_SRGB;
+ break;
+ case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
+ case MASK_VOUT_COLOR_601_YCBCR_FULL:
+ format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
+ break;
+ case MASK_VOUT_COLOR_709_YCBCR_FULL:
+ case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
+ format->format.colorspace = V4L2_COLORSPACE_REC709;
+ break;
+ default:
+ format->format.colorspace = 0;
+ break;
+ }
+
+ return 0;
+}
+
+static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
+ struct v4l2_dv_timings *timings)
+{
+ struct tc358743_state *state = to_state(sd);
+ struct v4l2_bt_timings *bt;
+
+ if (!timings)
+ return -EINVAL;
+
+ if (debug)
+ v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
+ timings, false);
+
+ if (!memcmp(&state->timings, timings, sizeof(struct v4l2_dv_timings))) {
+ v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
+ return 0;
+ }
+
+ bt = &timings->bt;
+
+ if (!v4l2_valid_dv_timings(timings,
+ &tc358743_timings_cap, NULL, NULL)) {
+ v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
+ return -ERANGE;
+ }
+
+ /* Fill the optional fields .standards and .flags in struct
+ * v4l2_dv_timings if the format is one of the CEA or DMT timings */
+ v4l2_find_dv_timings_cap(timings,
+ &tc358743_timings_cap, 250000, NULL, NULL);
+
+ state->timings = *timings;
+
+ enable_stream(sd, false);
+ tc358743_set_pll(sd);
+ tc358743_set_csi(sd);
+
+ return 0;
+}
+
+static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
+ struct v4l2_dv_timings *timings)
+{
+ struct tc358743_state *state = to_state(sd);
+
+ *timings = state->timings;
+
+ return 0;
+}
+
+static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
+ struct v4l2_enum_dv_timings *timings)
+{
+ if (timings->pad != 0)
+ return -EINVAL;
+
+ return v4l2_enum_dv_timings_cap(timings,
+ &tc358743_timings_cap, NULL, NULL);
+}
+
+static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
+ struct v4l2_dv_timings *timings)
+{
+ int ret;
+
+ ret = tc358743_get_detected_timings(sd, timings);
+ if (ret)
+ return ret;
+
+ if (debug)
+ v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
+ timings, false);
+
+ if (!v4l2_valid_dv_timings(timings,
+ &tc358743_timings_cap, NULL, NULL)) {
+ v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
+ return -ERANGE;
+ }
+
+ return 0;
+}
+
+static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
+ struct v4l2_dv_timings_cap *cap)
+{
+ if (cap->pad != 0)
+ return -EINVAL;
+
+ *cap = tc358743_timings_cap;
+
+ return 0;
+}
+
+static int tc358743_g_mbus_config(struct v4l2_subdev *sd,
+ struct v4l2_mbus_config *cfg)
+{
+ cfg->type = V4L2_MBUS_CSI2;
+
+ cfg->flags = i2c_rd16(sd, TXOPTIONCNTRL) & MASK_CONTCLKMODE ?
+ V4L2_MBUS_CSI2_CONTINUOUS_CLOCK :
+ V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK;
+
+ switch (tc358743_num_csi_lanes_in_use(sd)) {
+ case 1:
+ cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
+ break;
+ case 2:
+ cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
+ break;
+ case 3:
+ cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
+ break;
+ case 4:
+ cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ enable_stream(sd, enable);
+
+ return 0;
+}
+
+/* --------------- PAD OPS --------------- */
+
+static int tc358743_g_edid(struct v4l2_subdev *sd,
+ struct v4l2_subdev_edid *edid)
+{
+ struct tc358743_state *state = to_state(sd);
+
+ if (edid->pad != 0)
+ return -EINVAL;
+
+ if (!state->edid_written)
+ return -ENODATA;
+
+ if (edid->blocks == 0)
+ return -EINVAL;
+
+ if (edid->start_block + edid->blocks > 8) {
+ edid->blocks = 8;
+ return -E2BIG;
+ }
+
+ if (!edid->edid)
+ return -EINVAL;
+
+ i2c_rd(sd, EDID_RAM + (edid->start_block * 128), edid->edid,
+ edid->blocks * 128);
+
+ return 0;
+}
+
+static int tc358743_s_edid(struct v4l2_subdev *sd,
+ struct v4l2_subdev_edid *edid)
+{
+ struct tc358743_state *state = to_state(sd);
+ u16 edid_len = edid->blocks * 128;
+
+ v4l2_dbg(2, debug, sd, "%s\n", __func__);
+
+ if (edid->pad != 0)
+ return -EINVAL;
+
+ if (edid->start_block != 0)
+ return -EINVAL;
+
+ if (edid->blocks > 8) {
+ edid->blocks = 8;
+ return -E2BIG;
+ }
+
+ if (edid->blocks != 0 && !edid->edid)
+ return -EINVAL;
+
+ tc358743_disable_edid(sd);
+
+ i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
+ i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
+
+ if (edid->blocks == 0) {
+ state->edid_written = false;
+ return 0;
+ }
+
+ i2c_wr(sd, EDID_RAM, edid->edid, edid_len);
+
+ state->edid_written = true;
+
+ if (tx_5v_power_present(sd))
+ tc358743_enable_edid(sd);
+
+ return 0;
+}
+
+/* -------------------------------------------------------------------------- */
+
+static const struct v4l2_subdev_core_ops tc358743_core_ops = {
+ .log_status = tc358743_log_status,
+ .ioctl = tc358743_ioctl,
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+ .g_register = tc358743_g_register,
+ .s_register = tc358743_s_register,
+#endif
+ .interrupt_service_routine = tc358743_isr,
+};
+
+static const struct v4l2_subdev_video_ops tc358743_video_ops = {
+ .g_input_status = tc358743_g_input_status,
+ .s_dv_timings = tc358743_s_dv_timings,
+ .g_dv_timings = tc358743_g_dv_timings,
+ .query_dv_timings = tc358743_query_dv_timings,
+ .g_mbus_config = tc358743_g_mbus_config,
+ .s_stream = tc358743_s_stream,
+};
+
+static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
+ .set_fmt = tc358743_set_fmt,
+ .get_fmt = tc358743_get_fmt,
+ .get_edid = tc358743_g_edid,
+ .set_edid = tc358743_s_edid,
+ .enum_dv_timings = tc358743_enum_dv_timings,
+ .dv_timings_cap = tc358743_dv_timings_cap,
+};
+
+static const struct v4l2_subdev_ops tc358743_ops = {
+ .core = &tc358743_core_ops,
+ .video = &tc358743_video_ops,
+ .pad = &tc358743_pad_ops,
+};
+
+/* --------------- CUSTOM CTRLS --------------- */
+
+static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
+ .id = TC358743_CID_AUDIO_SAMPLING_RATE,
+ .name = "Audio sampling rate",
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .min = 0,
+ .max = 768000,
+ .step = 1,
+ .def = 0,
+ .flags = V4L2_CTRL_FLAG_READ_ONLY,
+};
+
+static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
+ .id = TC358743_CID_AUDIO_PRESENT,
+ .name = "Audio present",
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .def = 0,
+ .flags = V4L2_CTRL_FLAG_READ_ONLY,
+};
+
+/* --------------- PROBE / REMOVE --------------- */
+
+static int tc358743_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ static struct v4l2_dv_timings default_timing =
+ V4L2_DV_BT_CEA_640X480P59_94;
+ struct tc358743_state *state;
+ struct tc358743_platform_data *pdata = client->dev.platform_data;
+ struct v4l2_subdev *sd;
+ int err;
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+ return -EIO;
+ v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
+ client->addr << 1, client->adapter->name);
+
+ state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
+ GFP_KERNEL);
+ if (!state) {
+ v4l_err(client, "Could not allocate tc358743_state memory!\n");
+ return -ENOMEM;
+ }
+
+ /* platform data */
+ if (!pdata) {
+ v4l_err(client, "No platform data!\n");
+ return -ENODEV;
+ }
+ state->pdata = *pdata;
+
+ state->i2c_client = client;
+ sd = &state->sd;
+ v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
+ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
+
+ /* i2c access */
+ /* read the interrupt mask register, it should carry the
+ * default values, as it hasn't been touched at this point.
+ */
+ if (i2c_rd16(sd, INTMASK) != 0x0400) {
+ v4l2_info(sd, "not a TC358743 on address 0x%x\n",
+ client->addr << 1);
+ return -ENODEV;
+ }
+
+ /* control handlers */
+ v4l2_ctrl_handler_init(&state->hdl, 3);
+
+ /* private controls */
+ state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
+ V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
+
+ /* custom controls */
+ state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
+ &tc358743_ctrl_audio_sampling_rate, NULL);
+
+ state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
+ &tc358743_ctrl_audio_present, NULL);
+
+ sd->ctrl_handler = &state->hdl;
+ if (state->hdl.error) {
+ err = state->hdl.error;
+ goto err_hdl;
+ }
+
+ if (tc358743_update_controls(sd)) {
+ err = -ENODEV;
+ goto err_hdl;
+ }
+
+ /* work queues */
+ state->work_queues = create_singlethread_workqueue(client->name);
+ if (!state->work_queues) {
+ v4l2_err(sd, "Could not create work queue\n");
+ err = -ENOMEM;
+ goto err_hdl;
+ }
+
+ INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
+ tc358743_delayed_work_enable_hotplug);
+
+ tc358743_initial_setup(sd);
+
+ tc358743_s_dv_timings(sd, &default_timing);
+
+ state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
+ tc358743_set_csi_color_space(sd);
+
+ tc358743_enable_interrupts(sd);
+
+ v4l2_ctrl_handler_setup(sd->ctrl_handler);
+
+ v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
+ client->addr << 1, client->adapter->name);
+
+ return 0;
+
+err_hdl:
+ v4l2_ctrl_handler_free(&state->hdl);
+ return err;
+}
+
+static int tc358743_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct tc358743_state *state = to_state(sd);
+
+ cancel_delayed_work(&state->delayed_work_enable_hotplug);
+ destroy_workqueue(state->work_queues);
+ v4l2_device_unregister_subdev(sd);
+ v4l2_ctrl_handler_free(&state->hdl);
+
+ return 0;
+}
+
+static struct i2c_device_id tc358743_id[] = {
+ {"tc358743", 0},
+ {}
+};
+
+MODULE_DEVICE_TABLE(i2c, tc358743_id);
+
+static struct i2c_driver tc358743_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "tc358743",
+ },
+ .probe = tc358743_probe,
+ .remove = tc358743_remove,
+ .id_table = tc358743_id,
+};
+
+module_i2c_driver(tc358743_driver);
diff --git a/drivers/media/i2c/tc358743_regs.h b/drivers/media/i2c/tc358743_regs.h
new file mode 100644
index 0000000..30a8537
--- /dev/null
+++ b/drivers/media/i2c/tc358743_regs.h
@@ -0,0 +1,670 @@
+/*
+ * tc358743 - Toshiba HDMI to CSI-2 bridge - register names and bit masks
+ *
+ * Copyright 2014 Cisco Systems, Inc. and/or its affiliates. All rights
+ * reserved.
+ *
+ * This program is free software; you may redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+/*
+ * References (c = chapter, p = page):
+ * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
+ */
+
+/* Bit masks has prefix 'MASK_' and options after '_'. */
+
+#ifndef __TC358743_REGS_H
+#define __TC358743_REGS_H
+
+#define CHIPID 0x0000
+#define MASK_CHIPID 0xff00
+#define MASK_REVID 0x00ff
+
+#define SYSCTL 0x0002
+#define MASK_IRRST 0x0800
+#define MASK_CECRST 0x0400
+#define MASK_CTXRST 0x0200
+#define MASK_HDMIRST 0x0100
+#define MASK_SLEEP 0x0001
+
+#define CONFCTL 0x0004
+#define MASK_PWRISO 0x8000
+#define MASK_ACLKOPT 0x1000
+#define MASK_AUDCHNUM 0x0c00
+#define MASK_AUDCHNUM_8 0x0000
+#define MASK_AUDCHNUM_6 0x0400
+#define MASK_AUDCHNUM_4 0x0800
+#define MASK_AUDCHNUM_2 0x0c00
+#define MASK_AUDCHSEL 0x0200
+#define MASK_I2SDLYOPT 0x0100
+#define MASK_YCBCRFMT 0x00c0
+#define MASK_YCBCRFMT_444 0x0000
+#define MASK_YCBCRFMT_422_12_BIT 0x0040
+#define MASK_YCBCRFMT_COLORBAR 0x0080
+#define MASK_YCBCRFMT_422_8_BIT 0x00c0
+#define MASK_INFRMEN 0x0020
+#define MASK_AUDOUTSEL 0x0018
+#define MASK_AUDOUTSEL_CSI 0x0000
+#define MASK_AUDOUTSEL_I2S 0x0010
+#define MASK_AUDOUTSEL_TDM 0x0018
+#define MASK_AUTOINDEX 0x0004
+#define MASK_ABUFEN 0x0002
+#define MASK_VBUFEN 0x0001
+
+#define FIFOCTL 0x0006
+
+#define INTSTATUS 0x0014
+#define MASK_AMUTE_INT 0x0400
+#define MASK_HDMI_INT 0x0200
+#define MASK_CSI_INT 0x0100
+#define MASK_SYS_INT 0x0020
+#define MASK_CEC_EINT 0x0010
+#define MASK_CEC_TINT 0x0008
+#define MASK_CEC_RINT 0x0004
+#define MASK_IR_EINT 0x0002
+#define MASK_IR_DINT 0x0001
+
+#define INTMASK 0x0016
+#define MASK_AMUTE_MSK 0x0400
+#define MASK_HDMI_MSK 0x0200
+#define MASK_CSI_MSK 0x0100
+#define MASK_SYS_MSK 0x0020
+#define MASK_CEC_EMSK 0x0010
+#define MASK_CEC_TMSK 0x0008
+#define MASK_CEC_RMSK 0x0004
+#define MASK_IR_EMSK 0x0002
+#define MASK_IR_DMSK 0x0001
+
+#define INTFLAG 0x0018
+#define INTSYSSTATUS 0x001A
+
+#define PLLCTL0 0x0020
+#define MASK_PLL_PRD 0xf000
+#define SET_PLL_PRD(prd) ((((prd) - 1) << 12) &\
+ MASK_PLL_PRD)
+#define MASK_PLL_FBD 0x01ff
+#define SET_PLL_FBD(fbd) (((fbd) - 1) & MASK_PLL_FBD)
+
+#define PLLCTL1 0x0022
+#define MASK_PLL_FRS 0x0c00
+#define SET_PLL_FRS(frs) (((frs) << 10) & MASK_PLL_PRD)
+#define MASK_PLL_LBWS 0x0300
+#define MASK_LFBREN 0x0040
+#define MASK_BYPCKEN 0x0020
+#define MASK_CKEN 0x0010
+#define MASK_RESETB 0x0002
+#define MASK_PLL_EN 0x0001
+
+#define CLW_CNTRL 0x0140
+#define MASK_CLW_LANEDISABLE 0x0001
+
+#define D0W_CNTRL 0x0144
+#define MASK_D0W_LANEDISABLE 0x0001
+
+#define D1W_CNTRL 0x0148
+#define MASK_D1W_LANEDISABLE 0x0001
+
+#define D2W_CNTRL 0x014C
+#define MASK_D2W_LANEDISABLE 0x0001
+
+#define D3W_CNTRL 0x0150
+#define MASK_D3W_LANEDISABLE 0x0001
+
+#define STARTCNTRL 0x0204
+#define MASK_START 0x00000001
+
+#define LINEINITCNT 0x0210
+#define LPTXTIMECNT 0x0214
+#define TCLK_HEADERCNT 0x0218
+#define TCLK_TRAILCNT 0x021C
+#define THS_HEADERCNT 0x0220
+#define TWAKEUP 0x0224
+#define TCLK_POSTCNT 0x0228
+#define THS_TRAILCNT 0x022C
+#define HSTXVREGCNT 0x0230
+
+#define HSTXVREGEN 0x0234
+#define MASK_D3M_HSTXVREGEN 0x0010
+#define MASK_D2M_HSTXVREGEN 0x0008
+#define MASK_D1M_HSTXVREGEN 0x0004
+#define MASK_D0M_HSTXVREGEN 0x0002
+#define MASK_CLM_HSTXVREGEN 0x0001
+
+
+#define TXOPTIONCNTRL 0x0238
+#define MASK_CONTCLKMODE 0x00000001
+
+#define CSI_CONTROL 0x040C
+#define MASK_CSI_MODE 0x8000
+#define MASK_HTXTOEN 0x0400
+#define MASK_TXHSMD 0x0080
+#define MASK_HSCKMD 0x0020
+#define MASK_NOL 0x0006
+#define MASK_NOL_1 0x0000
+#define MASK_NOL_2 0x0002
+#define MASK_NOL_3 0x0004
+#define MASK_NOL_4 0x0006
+#define MASK_EOTDIS 0x0001
+
+#define CSI_INT 0x0414
+#define MASK_INTHLT 0x00000008
+#define MASK_INTER 0x00000004
+
+#define CSI_INT_ENA 0x0418
+#define MASK_IENHLT 0x00000008
+#define MASK_IENER 0x00000004
+
+#define CSI_ERR 0x044C
+#define MASK_INER 0x00000200
+#define MASK_WCER 0x00000100
+#define MASK_QUNK 0x00000010
+#define MASK_TXBRK 0x00000002
+
+#define CSI_ERR_INTENA 0x0450
+#define CSI_ERR_HALT 0x0454
+
+#define CSI_CONFW 0x0500
+#define MASK_MODE 0xe0000000
+#define MASK_MODE_SET 0xa0000000
+#define MASK_MODE_CLEAR 0xc0000000
+#define MASK_ADDRESS 0x1f000000
+#define MASK_ADDRESS_CSI_CONTROL 0x03000000
+#define MASK_ADDRESS_CSI_INT_ENA 0x06000000
+#define MASK_ADDRESS_CSI_ERR_INTENA 0x14000000
+#define MASK_ADDRESS_CSI_ERR_HALT 0x15000000
+#define MASK_DATA 0x0000ffff
+
+#define CSI_INT_CLR 0x050C
+#define MASK_ICRER 0x00000004
+
+#define CSI_START 0x0518
+#define MASK_STRT 0x00000001
+
+#define CECEN 0x0600
+#define MASK_CECEN 0x0001
+
+#define HDMI_INT0 0x8500
+#define MASK_I_KEY 0x80
+#define MASK_I_MISC 0x02
+#define MASK_I_PHYERR 0x01
+
+#define HDMI_INT1 0x8501
+#define MASK_I_GBD 0x80
+#define MASK_I_HDCP 0x40
+#define MASK_I_ERR 0x20
+#define MASK_I_AUD 0x10
+#define MASK_I_CBIT 0x08
+#define MASK_I_PACKET 0x04
+#define MASK_I_CLK 0x02
+#define MASK_I_SYS 0x01
+
+#define SYS_INT 0x8502
+#define MASK_I_ACR_CTS 0x80
+#define MASK_I_ACRN 0x40
+#define MASK_I_DVI 0x20
+#define MASK_I_HDMI 0x10
+#define MASK_I_NOPMBDET 0x08
+#define MASK_I_DPMBDET 0x04
+#define MASK_I_TMDS 0x02
+#define MASK_I_DDC 0x01
+
+#define CLK_INT 0x8503
+#define MASK_I_OUT_H_CHG 0x40
+#define MASK_I_IN_DE_CHG 0x20
+#define MASK_I_IN_HV_CHG 0x10
+#define MASK_I_DC_CHG 0x08
+#define MASK_I_PXCLK_CHG 0x04
+#define MASK_I_PHYCLK_CHG 0x02
+#define MASK_I_TMDSCLK_CHG 0x01
+
+#define CBIT_INT 0x8505
+#define MASK_I_AF_LOCK 0x80
+#define MASK_I_AF_UNLOCK 0x40
+#define MASK_I_CBIT_FS 0x02
+
+#define ERR_INT 0x8507
+#define MASK_I_EESS_ERR 0x80
+
+#define HDCP_INT 0x8508
+#define MASK_I_AVM_SET 0x80
+#define MASK_I_AVM_CLR 0x40
+#define MASK_I_LINKERR 0x20
+#define MASK_I_SHA_END 0x10
+#define MASK_I_R0_END 0x08
+#define MASK_I_KM_END 0x04
+#define MASK_I_AKSV_END 0x02
+#define MASK_I_AN_END 0x01
+
+#define MISC_INT 0x850B
+#define MASK_I_AS_LAYOUT 0x10
+#define MASK_I_NO_SPD 0x08
+#define MASK_I_NO_VS 0x03
+#define MASK_I_SYNC_CHG 0x02
+#define MASK_I_AUDIO_MUTE 0x01
+
+#define KEY_INT 0x850F
+
+#define SYS_INTM 0x8512
+#define MASK_M_ACR_CTS 0x80
+#define MASK_M_ACR_N 0x40
+#define MASK_M_DVI_DET 0x20
+#define MASK_M_HDMI_DET 0x10
+#define MASK_M_NOPMBDET 0x08
+#define MASK_M_BPMBDET 0x04
+#define MASK_M_TMDS 0x02
+#define MASK_M_DDC 0x01
+
+#define CLK_INTM 0x8513
+#define MASK_M_OUT_H_CHG 0x40
+#define MASK_M_IN_DE_CHG 0x20
+#define MASK_M_IN_HV_CHG 0x10
+#define MASK_M_DC_CHG 0x08
+#define MASK_M_PXCLK_CHG 0x04
+#define MASK_M_PHYCLK_CHG 0x02
+#define MASK_M_TMDS_CHG 0x01
+
+#define PACKET_INTM 0x8514
+
+#define CBIT_INTM 0x8515
+#define MASK_M_AF_LOCK 0x80
+#define MASK_M_AF_UNLOCK 0x40
+#define MASK_M_CBIT_FS 0x02
+
+#define AUDIO_INTM 0x8516
+
+#define ERR_INTM 0x8517
+#define MASK_M_EESS_ERR 0x80
+
+#define HDCP_INTM 0x8518
+#define MASK_M_AVM_SET 0x80
+#define MASK_M_AVM_CLR 0x40
+#define MASK_M_LINKERR 0x20
+#define MASK_M_SHA_END 0x10
+#define MASK_M_R0_END 0x08
+#define MASK_M_KM_END 0x04
+#define MASK_M_AKSV_END 0x02
+#define MASK_M_AN_END 0x01
+
+#define MISC_INTM 0x851B
+#define MASK_M_AS_LAYOUT 0x10
+#define MASK_M_NO_SPD 0x08
+#define MASK_M_NO_VS 0x03
+#define MASK_M_SYNC_CHG 0x02
+#define MASK_M_AUDIO_MUTE 0x01
+
+#define KEY_INTM 0x851F
+
+#define SYS_STATUS 0x8520
+#define MASK_S_SYNC 0x80
+#define MASK_S_AVMUTE 0x40
+#define MASK_S_HDCP 0x20
+#define MASK_S_HDMI 0x10
+#define MASK_S_PHY_SCDT 0x08
+#define MASK_S_PHY_PLL 0x04
+#define MASK_S_TMDS 0x02
+#define MASK_S_DDC5V 0x01
+
+#define CSI_STATUS 0x0410
+#define MASK_S_WSYNC 0x0400
+#define MASK_S_TXACT 0x0200
+#define MASK_S_RXACT 0x0100
+#define MASK_S_HLT 0x0001
+
+#define VI_STATUS1 0x8522
+#define MASK_S_V_GBD 0x08
+#define MASK_S_DEEPCOLOR 0x0c
+#define MASK_S_V_422 0x02
+#define MASK_S_V_INTERLACE 0x01
+
+#define AU_STATUS0 0x8523
+#define MASK_S_A_SAMPLE 0x01
+
+#define VI_STATUS3 0x8528
+#define MASK_S_V_COLOR 0x1e
+#define MASK_LIMITED 0x01
+
+#define PHY_CTL0 0x8531
+#define MASK_PHY_SYSCLK_IND 0x02
+#define MASK_PHY_CTL 0x01
+
+
+#define PHY_CTL1 0x8532 /* Not in REF_01 */
+#define MASK_PHY_AUTO_RST1 0xf0
+#define MASK_PHY_AUTO_RST1_OFF 0x00
+#define SET_PHY_AUTO_RST1_US(us) ((((us) / 200) << 4) & \
+ MASK_PHY_AUTO_RST1)
+#define MASK_FREQ_RANGE_MODE 0x0f
+#define SET_FREQ_RANGE_MODE_CYCLES(cycles) (((cycles) - 1) & \
+ MASK_FREQ_RANGE_MODE)
+
+#define PHY_CTL2 0x8533 /* Not in REF_01 */
+#define MASK_PHY_AUTO_RST4 0x04
+#define MASK_PHY_AUTO_RST3 0x02
+#define MASK_PHY_AUTO_RST2 0x01
+#define MASK_PHY_AUTO_RSTn (MASK_PHY_AUTO_RST4 | \
+ MASK_PHY_AUTO_RST3 | \
+ MASK_PHY_AUTO_RST2)
+
+#define PHY_EN 0x8534
+#define MASK_ENABLE_PHY 0x01
+
+#define PHY_RST 0x8535
+#define MASK_RESET_CTRL 0x01 /* Reset active low */
+
+#define PHY_BIAS 0x8536 /* Not in REF_01 */
+
+#define PHY_CSQ 0x853F /* Not in REF_01 */
+#define MASK_CSQ_CNT 0x0f
+#define SET_CSQ_CNT_LEVEL(n) (n & MASK_CSQ_CNT)
+
+#define SYS_FREQ0 0x8540
+#define SYS_FREQ1 0x8541
+
+#define SYS_CLK 0x8542 /* Not in REF_01 */
+#define MASK_CLK_DIFF 0x0C
+#define MASK_CLK_DIV 0x03
+
+#define DDC_CTL 0x8543
+#define MASK_DDC_ACK_POL 0x08
+#define MASK_DDC_ACTION 0x04
+#define MASK_DDC5V_MODE 0x03
+#define MASK_DDC5V_MODE_0MS 0x00
+#define MASK_DDC5V_MODE_50MS 0x01
+#define MASK_DDC5V_MODE_100MS 0x02
+#define MASK_DDC5V_MODE_200MS 0x03
+
+#define HPD_CTL 0x8544
+#define MASK_HPD_CTL0 0x10
+#define MASK_HPD_OUT0 0x01
+
+#define ANA_CTL 0x8545
+#define MASK_APPL_PCSX 0x30
+#define MASK_APPL_PCSX_HIZ 0x00
+#define MASK_APPL_PCSX_L_FIX 0x10
+#define MASK_APPL_PCSX_H_FIX 0x20
+#define MASK_APPL_PCSX_NORMAL 0x30
+#define MASK_ANALOG_ON 0x01
+
+#define AVM_CTL 0x8546
+
+#define INIT_END 0x854A
+#define MASK_INIT_END 0x01
+
+#define HDMI_DET 0x8552
+#define MASK_HDMI_DET_MOD1 0x80
+#define MASK_HDMI_DET_MOD0 0x40
+#define MASK_HDMI_DET_V 0x30
+#define MASK_HDMI_DET_V_SYNC 0x00
+#define MASK_HDMI_DET_V_ASYNC_25MS 0x10
+#define MASK_HDMI_DET_V_ASYNC_50MS 0x20
+#define MASK_HDMI_DET_V_ASYNC_100MS 0x30
+#define MASK_HDMI_DET_NUM 0x0f
+
+#define HDCP_MODE 0x8560
+#define MASK_MODE_RST_TN 0x20
+#define MASK_LINE_REKEY 0x10
+#define MASK_AUTO_CLR 0x04
+
+#define HDCP_REG1 0x8563 /* Not in REF_01 */
+#define MASK_AUTH_UNAUTH_SEL 0x70
+#define MASK_AUTH_UNAUTH_SEL_12_FRAMES 0x70
+#define MASK_AUTH_UNAUTH_SEL_8_FRAMES 0x60
+#define MASK_AUTH_UNAUTH_SEL_4_FRAMES 0x50
+#define MASK_AUTH_UNAUTH_SEL_2_FRAMES 0x40
+#define MASK_AUTH_UNAUTH_SEL_64_FRAMES 0x30
+#define MASK_AUTH_UNAUTH_SEL_32_FRAMES 0x20
+#define MASK_AUTH_UNAUTH_SEL_16_FRAMES 0x10
+#define MASK_AUTH_UNAUTH_SEL_ONCE 0x00
+#define MASK_AUTH_UNAUTH 0x01
+#define MASK_AUTH_UNAUTH_AUTO 0x01
+
+#define HDCP_REG2 0x8564 /* Not in REF_01 */
+#define MASK_AUTO_P3_RESET 0x0F
+#define SET_AUTO_P3_RESET_FRAMES(n) (n & MASK_AUTO_P3_RESET)
+#define MASK_AUTO_P3_RESET_OFF 0x00
+
+#define VOUT_SET2 0x8573
+#define MASK_SEL422 0x80
+#define MASK_VOUT_422FIL_100 0x40
+#define MASK_VOUTCOLORMODE 0x03
+#define MASK_VOUTCOLORMODE_THROUGH 0x00
+#define MASK_VOUTCOLORMODE_AUTO 0x01
+#define MASK_VOUTCOLORMODE_MANUAL 0x03
+
+#define VOUT_SET3 0x8574
+#define MASK_VOUT_EXTCNT 0x08
+
+#define VI_REP 0x8576
+#define MASK_VOUT_COLOR_SEL 0xe0
+#define MASK_VOUT_COLOR_RGB_FULL 0x00
+#define MASK_VOUT_COLOR_RGB_LIMITED 0x20
+#define MASK_VOUT_COLOR_601_YCBCR_FULL 0x40
+#define MASK_VOUT_COLOR_601_YCBCR_LIMITED 0x60
+#define MASK_VOUT_COLOR_709_YCBCR_FULL 0x80
+#define MASK_VOUT_COLOR_709_YCBCR_LIMITED 0xa0
+#define MASK_VOUT_COLOR_FULL_TO_LIMITED 0xc0
+#define MASK_VOUT_COLOR_LIMITED_TO_FULL 0xe0
+#define MASK_IN_REP_HEN 0x10
+#define MASK_IN_REP 0x0f
+
+#define DE_WIDTH_H_LO 0x8582 /* Not in REF_01 */
+#define DE_WIDTH_H_HI 0x8583 /* Not in REF_01 */
+#define DE_WIDTH_V_LO 0x8588 /* Not in REF_01 */
+#define DE_WIDTH_V_HI 0x8589 /* Not in REF_01 */
+#define H_SIZE_LO 0x858A /* Not in REF_01 */
+#define H_SIZE_HI 0x858B /* Not in REF_01 */
+#define V_SIZE_LO 0x858C /* Not in REF_01 */
+#define V_SIZE_HI 0x858D /* Not in REF_01 */
+#define FV_CNT_LO 0x85A1 /* Not in REF_01 */
+#define FV_CNT_HI 0x85A2 /* Not in REF_01 */
+
+#define FH_MIN0 0x85AA /* Not in REF_01 */
+#define FH_MIN1 0x85AB /* Not in REF_01 */
+#define FH_MAX0 0x85AC /* Not in REF_01 */
+#define FH_MAX1 0x85AD /* Not in REF_01 */
+#define HV_RST 0x85AF /* Not in REF_01 */
+#define MASK_H_PI_RST 0x20
+#define MASK_V_PI_RST 0x10
+
+#define EDID_MODE 0x85C7
+#define MASK_EDID_SPEED 0x40
+#define MASK_EDID_MODE 0x03
+#define MASK_EDID_MODE_DISABLE 0x00
+#define MASK_EDID_MODE_DDC2B 0x01
+#define MASK_EDID_MODE_E_DDC 0x02
+
+#define EDID_LEN1 0x85CA
+#define EDID_LEN2 0x85CB
+
+#define HDCP_REG3 0x85D1 /* Not in REF_01 */
+#define KEY_RD_CMD 0x01
+
+#define FORCE_MUTE 0x8600
+#define MASK_FORCE_AMUTE 0x10
+#define MASK_FORCE_DMUTE 0x01
+
+#define CMD_AUD 0x8601
+#define MASK_CMD_BUFINIT 0x04
+#define MASK_CMD_LOCKDET 0x02
+#define MASK_CMD_MUTE 0x01
+
+#define AUTO_CMD0 0x8602
+#define MASK_AUTO_MUTE7 0x80
+#define MASK_AUTO_MUTE6 0x40
+#define MASK_AUTO_MUTE5 0x20
+#define MASK_AUTO_MUTE4 0x10
+#define MASK_AUTO_MUTE3 0x08
+#define MASK_AUTO_MUTE2 0x04
+#define MASK_AUTO_MUTE1 0x02
+#define MASK_AUTO_MUTE0 0x01
+
+#define AUTO_CMD1 0x8603
+#define MASK_AUTO_MUTE10 0x04
+#define MASK_AUTO_MUTE9 0x02
+#define MASK_AUTO_MUTE8 0x01
+
+#define AUTO_CMD2 0x8604
+#define MASK_AUTO_PLAY3 0x08
+#define MASK_AUTO_PLAY2 0x04
+
+#define BUFINIT_START 0x8606
+#define SET_BUFINIT_START_MS(milliseconds) ((milliseconds) / 100)
+
+#define FS_MUTE 0x8607
+#define MASK_FS_ELSE_MUTE 0x80
+#define MASK_FS22_MUTE 0x40
+#define MASK_FS24_MUTE 0x20
+#define MASK_FS88_MUTE 0x10
+#define MASK_FS96_MUTE 0x08
+#define MASK_FS176_MUTE 0x04
+#define MASK_FS192_MUTE 0x02
+#define MASK_FS_NO_MUTE 0x01
+
+#define FS_IMODE 0x8620
+#define MASK_NLPCM_HMODE 0x40
+#define MASK_NLPCM_SMODE 0x20
+#define MASK_NLPCM_IMODE 0x10
+#define MASK_FS_HMODE 0x08
+#define MASK_FS_AMODE 0x04
+#define MASK_FS_SMODE 0x02
+#define MASK_FS_IMODE 0x01
+
+#define FS_SET 0x8621
+#define MASK_FS 0x0f
+
+#define LOCKDET_REF0 0x8630
+#define LOCKDET_REF1 0x8631
+#define LOCKDET_REF2 0x8632
+
+#define ACR_MODE 0x8640
+#define MASK_ACR_LOAD 0x10
+#define MASK_N_MODE 0x04
+#define MASK_CTS_MODE 0x01
+
+#define ACR_MDF0 0x8641
+#define MASK_ACR_L2MDF 0x70
+#define MASK_ACR_L2MDF_0_PPM 0x00
+#define MASK_ACR_L2MDF_61_PPM 0x10
+#define MASK_ACR_L2MDF_122_PPM 0x20
+#define MASK_ACR_L2MDF_244_PPM 0x30
+#define MASK_ACR_L2MDF_488_PPM 0x40
+#define MASK_ACR_L2MDF_976_PPM 0x50
+#define MASK_ACR_L2MDF_1976_PPM 0x60
+#define MASK_ACR_L2MDF_3906_PPM 0x70
+#define MASK_ACR_L1MDF 0x07
+#define MASK_ACR_L1MDF_0_PPM 0x00
+#define MASK_ACR_L1MDF_61_PPM 0x01
+#define MASK_ACR_L1MDF_122_PPM 0x02
+#define MASK_ACR_L1MDF_244_PPM 0x03
+#define MASK_ACR_L1MDF_488_PPM 0x04
+#define MASK_ACR_L1MDF_976_PPM 0x05
+#define MASK_ACR_L1MDF_1976_PPM 0x06
+#define MASK_ACR_L1MDF_3906_PPM 0x07
+
+#define ACR_MDF1 0x8642
+#define MASK_ACR_L3MDF 0x07
+#define MASK_ACR_L3MDF_0_PPM 0x00
+#define MASK_ACR_L3MDF_61_PPM 0x01
+#define MASK_ACR_L3MDF_122_PPM 0x02
+#define MASK_ACR_L3MDF_244_PPM 0x03
+#define MASK_ACR_L3MDF_488_PPM 0x04
+#define MASK_ACR_L3MDF_976_PPM 0x05
+#define MASK_ACR_L3MDF_1976_PPM 0x06
+#define MASK_ACR_L3MDF_3906_PPM 0x07
+
+#define SDO_MODE1 0x8652
+#define MASK_SDO_BIT_LENG 0x70
+#define MASK_SDO_FMT 0x03
+#define MASK_SDO_FMT_RIGHT 0x00
+#define MASK_SDO_FMT_LEFT 0x01
+#define MASK_SDO_FMT_I2S 0x02
+
+#define DIV_MODE 0x8665 /* Not in REF_01 */
+#define MASK_DIV_DLY 0xf0
+#define SET_DIV_DLY_MS(milliseconds) ((((milliseconds) / 100) << 4) & \
+ MASK_DIV_DLY)
+#define MASK_DIV_MODE 0x01
+
+#define NCO_F0_MOD 0x8670
+#define MASK_NCO_F0_MOD 0x03
+#define MASK_NCO_F0_MOD_42MHZ 0x00
+#define MASK_NCO_F0_MOD_27MHZ 0x01
+
+#define PK_INT_MODE 0x8709
+#define MASK_ISRC2_INT_MODE 0x80
+#define MASK_ISRC_INT_MODE 0x40
+#define MASK_ACP_INT_MODE 0x20
+#define MASK_VS_INT_MODE 0x10
+#define MASK_SPD_INT_MODE 0x08
+#define MASK_MS_INT_MODE 0x04
+#define MASK_AUD_INT_MODE 0x02
+#define MASK_AVI_INT_MODE 0x01
+
+#define NO_PKT_LIMIT 0x870B
+#define MASK_NO_ACP_LIMIT 0xf0
+#define SET_NO_ACP_LIMIT_MS(milliseconds) ((((milliseconds) / 80) << 4) & \
+ MASK_NO_ACP_LIMIT)
+#define MASK_NO_AVI_LIMIT 0x0f
+#define SET_NO_AVI_LIMIT_MS(milliseconds) (((milliseconds) / 80) & \
+ MASK_NO_AVI_LIMIT)
+
+#define NO_PKT_CLR 0x870C
+#define MASK_NO_VS_CLR 0x40
+#define MASK_NO_SPD_CLR 0x20
+#define MASK_NO_ACP_CLR 0x10
+#define MASK_NO_AVI_CLR1 0x02
+#define MASK_NO_AVI_CLR0 0x01
+
+#define ERR_PK_LIMIT 0x870D
+#define NO_PKT_LIMIT2 0x870E
+#define PK_AVI_0HEAD 0x8710
+#define PK_AVI_1HEAD 0x8711
+#define PK_AVI_2HEAD 0x8712
+#define PK_AVI_0BYTE 0x8713
+#define PK_AVI_1BYTE 0x8714
+#define PK_AVI_2BYTE 0x8715
+#define PK_AVI_3BYTE 0x8716
+#define PK_AVI_4BYTE 0x8717
+#define PK_AVI_5BYTE 0x8718
+#define PK_AVI_6BYTE 0x8719
+#define PK_AVI_7BYTE 0x871A
+#define PK_AVI_8BYTE 0x871B
+#define PK_AVI_9BYTE 0x871C
+#define PK_AVI_10BYTE 0x871D
+#define PK_AVI_11BYTE 0x871E
+#define PK_AVI_12BYTE 0x871F
+#define PK_AVI_13BYTE 0x8720
+#define PK_AVI_14BYTE 0x8721
+#define PK_AVI_15BYTE 0x8722
+#define PK_AVI_16BYTE 0x8723
+
+#define BKSV 0x8800
+
+#define BCAPS 0x8840
+#define MASK_HDMI_RSVD 0x80
+#define MASK_REPEATER 0x40
+#define MASK_READY 0x20
+#define MASK_FASTI2C 0x10
+#define MASK_1_1_FEA 0x02
+#define MASK_FAST_REAU 0x01
+
+#define BSTATUS1 0x8842
+#define MASK_MAX_EXCED 0x08
+
+#define EDID_RAM 0x8C00
+#define NO_GDB_LIMIT 0x9007
+
+#endif
diff --git a/include/media/tc358743.h b/include/media/tc358743.h
new file mode 100644
index 0000000..c552a65
--- /dev/null
+++ b/include/media/tc358743.h
@@ -0,0 +1,89 @@
+/*
+ * tc358743 - Toshiba HDMI to CSI-2 bridge
+ *
+ * Copyright 2014 Cisco Systems, Inc. and/or its affiliates. All rights
+ * reserved.
+ *
+ * This program is free software; you may redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+/*
+ * References (c = chapter, p = page):
+ * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
+ * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
+ */
+
+#ifndef _TC358743_
+#define _TC358743_
+
+enum tc358743_ddc5v_delays {
+ DDC5V_DELAY_0MS,
+ DDC5V_DELAY_50MS,
+ DDC5V_DELAY_100MS,
+ DDC5V_DELAY_200MS,
+};
+
+struct tc358743_platform_data {
+ u32 refclk_hz; /* System clock connected to REFCLK (pin H5) */
+ enum tc358743_ddc5v_delays ddc5v_delay; /* DDC +5V debounce delay */
+ bool enable_hdcp;
+ /*
+ * The FIFO size is 512x32, so Toshiba recommend to set the default FIFO
+ * level to somewhere in the middle (eg. 200), so it can cover speed
+ * mismatches in input and output ports.
+ */
+ u16 fifo_level;
+ u16 pll_prd; /* PLLCTL0 */
+ u16 pll_fbd; /*PLLCTL0 */
+
+ /* CSI
+ * Calculate CSI parameters with REF_02 for the highest resolution your
+ * CSI interface can handle. The driver will adjust the number of CSI
+ * lanes in use according to the pixel clock.
+ */
+ u32 bps_pr_lane;
+ u32 lineinitcnt;
+ u32 lptxtimecnt;
+ u32 tclk_headercnt;
+ u32 tclk_trailcnt;
+ u32 ths_headercnt;
+ u32 twakeup;
+ u32 tclk_postcnt;
+ u32 ths_trailcnt;
+ u32 hstxvregcnt;
+
+ /* HDMI PHY */
+ u8 phy_auto_rst; /* PHY_CTL2, default = 0 */
+ u8 hdmi_det_v; /* HDMI_DET, default = 0 */
+ u8 h_pi_rst; /* HV_RST, default = 0 */
+ u8 v_pi_rst; /* HV_RST, default = 0 */
+};
+
+enum tc358743_cable_connection {
+ TC358743_CABLE_PLUGGED,
+ TC358743_CABLE_UNPLUGGED,
+};
+
+/* notify events */
+#define TC358743_FMT_CHANGE 1
+
+/* ioctls */
+#define TC358743_CSI_RESET _IO('a', 1)
+
+/* custom controls */
+#define TC358743_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC358743_BASE + 0)
+#define TC358743_CID_AUDIO_PRESENT (V4L2_CID_USER_TC358743_BASE + 1)
+
+#endif
diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
index 661f119..1bee69c 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h
@@ -170,6 +170,10 @@ enum v4l2_colorfx {
* We reserve 16 controls for this driver. */
#define V4L2_CID_USER_SAA7134_BASE (V4L2_CID_USER_BASE + 0x1060)
+/* The base for the tc358743 driver controls.
+ * We reserve 16 controls for this driver. */
+#define V4L2_CID_USER_TC358743_BASE (V4L2_CID_USER_BASE + 0x1070)
+
/* MPEG-class control IDs */
/* The MPEG controls are applicable to all codec controls
* and the 'MPEG' part of the define is historical */
--
2.1.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [RFC v01] Driver for Toshiba TC358743 CSI-2 to HDMI bridge
2014-12-15 18:21 [RFC v01] Driver for Toshiba TC358743 CSI-2 to HDMI bridge matrandg
@ 2014-12-17 10:32 ` Hans Verkuil
2015-01-08 17:12 ` Philipp Zabel
2015-02-17 8:50 ` Philipp Zabel
2 siblings, 0 replies; 7+ messages in thread
From: Hans Verkuil @ 2014-12-17 10:32 UTC (permalink / raw)
To: matrandg, linux-media; +Cc: hansverk
Hi Mats,
Some review comments...
On 12/15/14 19:21, matrandg@cisco.com wrote:
> From: Mats Randgaard <matrandg@cisco.com>
>
> The driver is tested on our hardware and all the implemented features
> works as expected.
>
> Missing features:
> - CEC support
> - HDCP repeater support
> - IR support
>
> Signed-off-by: Mats Randgaard <matrandg@cisco.com>
> ---
> MAINTAINERS | 6 +
> drivers/media/i2c/Kconfig | 12 +
> drivers/media/i2c/Makefile | 1 +
> drivers/media/i2c/tc358743.c | 1768 ++++++++++++++++++++++++++++++++++++
> drivers/media/i2c/tc358743_regs.h | 670 ++++++++++++++
> include/media/tc358743.h | 89 ++
> include/uapi/linux/v4l2-controls.h | 4 +
> 7 files changed, 2550 insertions(+)
> create mode 100644 drivers/media/i2c/tc358743.c
> create mode 100644 drivers/media/i2c/tc358743_regs.h
> create mode 100644 include/media/tc358743.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9c49eb6..7608a83 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -9448,6 +9448,12 @@ L: platform-driver-x86@vger.kernel.org
> S: Orphan
> F: drivers/platform/x86/toshiba_acpi.c
>
> +TOSHIBA TC358743 DRIVER
> +M: Mats Randgaard <matrandg@cisco.com>
> +L: linux-media@vger.kernel.org
> +S: Maintained
> +F: drivers/media/i2c/tc358743*
> +
> TOSHIBA SMM DRIVER
> M: Jonathan Buzzard <jonathan@buzzard.org.uk>
> L: tlinux-users@tce.toshiba-dme.co.jp
> diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
> index f40b4cf..0103cdf 100644
> --- a/drivers/media/i2c/Kconfig
> +++ b/drivers/media/i2c/Kconfig
> @@ -293,6 +293,18 @@ config VIDEO_SAA7191
> To compile this driver as a module, choose M here: the
> module will be called saa7191.
>
> +config VIDEO_TC358743
> + tristate "Toshiba TC358743 decoder"
> + depends on VIDEO_V4L2 && I2C
> + ---help---
> + Support for the Toshiba TC358743 HDMI to MIPI CSI-2 bridge
> +
> + This is a Analog Devices Component/Graphics Digitizer
> + with 4:1 Multiplexed HDMI Receiver.
Copy-and-paste leftover :-)
> +
> + To compile this driver as a module, choose M here: the
> + module will be called tc358743.
> +
> config VIDEO_TVP514X
> tristate "Texas Instruments TVP514x video decoder"
> depends on VIDEO_V4L2 && I2C
> diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
> index 01ae932..b4dea43 100644
> --- a/drivers/media/i2c/Makefile
> +++ b/drivers/media/i2c/Makefile
> @@ -78,3 +78,4 @@ obj-$(CONFIG_VIDEO_SMIAPP_PLL) += smiapp-pll.o
> obj-$(CONFIG_VIDEO_AK881X) += ak881x.o
> obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
> obj-$(CONFIG_VIDEO_ML86V7667) += ml86v7667.o
> +obj-$(CONFIG_VIDEO_TC358743) += tc358743.o
> diff --git a/drivers/media/i2c/tc358743.c b/drivers/media/i2c/tc358743.c
> new file mode 100644
> index 0000000..a86cbe0
> --- /dev/null
> +++ b/drivers/media/i2c/tc358743.c
> @@ -0,0 +1,1768 @@
> +/*
> + * tc358743 - Toshiba HDMI to CSI-2 bridge
> + *
> + * Copyright 2014 Cisco Systems, Inc. and/or its affiliates. All rights
> + * reserved.
> + *
> + * This program is free software; you may redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + *
> + */
> +
> +/*
> + * References (c = chapter, p = page):
> + * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
> + * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/i2c.h>
> +#include <linux/delay.h>
> +#include <linux/videodev2.h>
> +#include <linux/workqueue.h>
> +#include <linux/v4l2-dv-timings.h>
> +#include <media/v4l2-dv-timings.h>
> +#include <media/v4l2-device.h>
> +#include <media/v4l2-ctrls.h>
> +#include <media/tc358743.h>
> +
> +#include "tc358743_regs.h"
> +
> +static int debug;
> +module_param(debug, int, 0644);
> +MODULE_PARM_DESC(debug, "debug level (0-3)");
> +
> +MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
> +MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
> +MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
> +MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
> +MODULE_LICENSE("GPL");
> +
> +static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
> + .type = V4L2_DV_BT_656_1120,
> + /* keep this initialization for compatibility with GCC < 4.4.6 */
> + .reserved = { 0 },
> + /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
> + V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000,
> + V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
> + V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
> + V4L2_DV_BT_CAP_PROGRESSIVE |
> + V4L2_DV_BT_CAP_REDUCED_BLANKING |
> + V4L2_DV_BT_CAP_CUSTOM)
> +};
> +
> +struct tc358743_state {
> + struct tc358743_platform_data pdata;
> + struct v4l2_subdev sd;
> + struct media_pad pad;
> + struct v4l2_ctrl_handler hdl;
> + struct i2c_client *i2c_client;
> +
> + /* controls */
> + struct v4l2_ctrl *detect_tx_5v_ctrl;
> + struct v4l2_ctrl *audio_sampling_rate_ctrl;
> + struct v4l2_ctrl *audio_present_ctrl;
> +
> + /* work queues */
> + struct workqueue_struct *work_queues;
> + struct delayed_work delayed_work_enable_hotplug;
> +
> + /* edid */
> + bool edid_written;
> +
> + struct v4l2_dv_timings timings;
> + u32 mbus_fmt_code;
> +};
> +
> +static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
> +{
> + return container_of(sd, struct tc358743_state, sd);
> +}
> +
> +/* --------------- I2C --------------- */
> +
> +static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct i2c_client *client = state->i2c_client;
> + int err;
> + u8 buf[2] = { reg >> 8, reg & 0xff };
> + struct i2c_msg msgs[] = {
> + {
> + .addr = client->addr,
> + .flags = 0,
> + .len = 2,
> + .buf = buf,
> + },
> + {
> + .addr = client->addr,
> + .flags = I2C_M_RD,
> + .len = n,
> + .buf = values,
> + },
> + };
> +
> + err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
> + if (err != ARRAY_SIZE(msgs)) {
> + v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
> + __func__, reg, client->addr);
> + }
> +}
> +
> +static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct i2c_client *client = state->i2c_client;
> + int err, i;
> + struct i2c_msg msg;
> + u8 data[2 + n];
> +
> + msg.addr = client->addr;
> + msg.buf = data;
> + msg.len = 2 + n;
> + msg.flags = 0;
> +
> + data[0] = reg >> 8;
> + data[1] = reg & 0xff;
> +
> + for (i = 0; i < n; i++)
> + data[2 + i] = values[i];
> +
> + err = i2c_transfer(client->adapter, &msg, 1);
> + if (err != 1) {
> + v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
> + __func__, reg, client->addr);
> + return;
> + }
> +
> + if (debug < 3)
> + return;
> +
> + switch (n) {
> + case 1:
> + v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
> + reg, data[2]);
> + break;
> + case 2:
> + v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
> + reg, data[3], data[2]);
> + break;
> + case 4:
> + v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
> + reg, data[5], data[4], data[3], data[2]);
> + break;
> + default:
> + v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
> + n, reg);
> + }
> +}
> +
> +static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
> +{
> + u8 val;
> +
> + i2c_rd(sd, reg, &val, 1);
> +
> + return val;
> +}
> +
> +static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
> +{
> + i2c_wr(sd, reg, &val, 1);
> +}
> +
> +static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
> + u8 mask, u8 val)
> +{
> + i2c_wr8(sd, reg, (i2c_rd8(sd, reg) & mask) | val);
> +}
> +
> +static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
> +{
> + u16 val;
> +
> + i2c_rd(sd, reg, (u8 *)&val, 2);
> +
> + return val;
> +}
> +
> +static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
> +{
> + i2c_wr(sd, reg, (u8 *)&val, 2);
> +}
> +
> +static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
> +{
> + i2c_wr16(sd, reg, (i2c_rd16(sd, reg) & mask) | val);
> +}
> +
> +static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
> +{
> + u32 val;
> +
> + i2c_rd(sd, reg, (u8 *)&val, 4);
> +
> + return val;
> +}
> +
> +static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
> +{
> + i2c_wr(sd, reg, (u8 *)&val, 4);
> +}
> +
> +/* --------------- STATUS --------------- */
> +
> +static inline bool is_hdmi(struct v4l2_subdev *sd)
> +{
> + return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
> +}
> +
> +static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
> +{
> + return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
> +}
> +
> +static inline bool no_signal(struct v4l2_subdev *sd)
> +{
> + return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
> +}
> +
> +static inline bool no_sync(struct v4l2_subdev *sd)
> +{
> + return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
> +}
> +
> +static inline bool audio_present(struct v4l2_subdev *sd)
> +{
> + return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
> +}
> +
> +static int get_audio_sampling_rate(struct v4l2_subdev *sd)
> +{
> + static const int code_to_rate[] = {
> + 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
> + 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
> + };
> +
> + /* Register FS_SET is not cleared when the cable is disconnected */
> + if (no_signal(sd))
> + return 0;
> +
> + return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
> +}
> +
> +static unsigned tc358743_num_csi_lanes_in_use(struct v4l2_subdev *sd)
> +{
> + return ((i2c_rd32(sd, CSI_CONTROL) & MASK_NOL) >> 1) + 1;
> +}
> +
> +/* --------------- TIMINGS --------------- */
> +
> +static inline unsigned fps(const struct v4l2_bt_timings *t)
> +{
> + if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
> + return 0;
> +
> + return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
> + V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
> +}
> +
> +static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
> + struct v4l2_dv_timings *timings)
> +{
> + struct v4l2_bt_timings *bt = &timings->bt;
> + unsigned width, height, frame_width, frame_height, frame_interval, fps;
> +
> + memset(timings, 0, sizeof(struct v4l2_dv_timings));
> +
> + if (no_signal(sd)) {
> + v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
> + return -ENOLINK;
> + }
> + if (no_sync(sd))
> + v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
Shouldn't this return -ENOLCK?
> +
> + timings->type = V4L2_DV_BT_656_1120;
> + bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
> + V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
> +
> + width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
> + i2c_rd8(sd, DE_WIDTH_H_LO);
> + height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
> + i2c_rd8(sd, DE_WIDTH_V_LO);
> + frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
> + i2c_rd8(sd, H_SIZE_LO);
> + frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
> + i2c_rd8(sd, V_SIZE_LO)) / 2;
> + /* frame interval in milliseconds * 10
> + * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
> + frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
> + i2c_rd8(sd, FV_CNT_LO);
> + fps = (frame_interval > 0) ?
> + DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
> +
> + bt->width = width;
> + bt->height = height;
> + bt->vsync = frame_height - height;
Is 'height' the height of a field or of a frame for interlaced formats?
Remember that bt->height is the *frame* height, not the field height.
Also, for interlaced formats bt->il_vsync should be set as well.
> + bt->hsync = frame_width - width;
> + bt->pixelclock = frame_width * frame_height * fps;
> +
> + return 0;
> +}
> +
> +/* --------------- HOTPLUG / HDCP / EDID --------------- */
> +
> +static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
> +{
> + struct delayed_work *dwork = to_delayed_work(work);
> + struct tc358743_state *state = container_of(dwork,
> + struct tc358743_state, delayed_work_enable_hotplug);
> + struct v4l2_subdev *sd = &state->sd;
> +
> + v4l2_dbg(2, debug, sd, "%s:\n", __func__);
> +
> + i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
> +}
> +
> +static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
> +{
> + v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
> + "enable" : "disable");
> +
> + i2c_wr8_and_or(sd, HDCP_REG1,
> + ~(MASK_AUTH_UNAUTH_SEL | MASK_AUTH_UNAUTH),
> + MASK_AUTH_UNAUTH_SEL_16_FRAMES | MASK_AUTH_UNAUTH_AUTO);
> +
> + i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
> + SET_AUTO_P3_RESET_FRAMES(0x0f));
> +
> + /* HDCP is disabled by configuring the receiver as HDCP repeater.
> + * The repeater mode require software support to work, so
> + * HDCP authentication will fail. Set Ready and MAX_EXCED bits
> + * to avoid problems on MacBook Pro gen.8.
Can you elaborate a bit more what those problems are?
> + */
> + i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, enable ? KEY_RD_CMD : 0);
> +
> + i2c_wr8_and_or(sd, HDCP_MODE, ~(MASK_AUTO_CLR | MASK_MODE_RST_TN),
> + enable ? (MASK_AUTO_CLR | MASK_MODE_RST_TN) : 0);
> +
> + i2c_wr8_and_or(sd, BSTATUS1, ~MASK_MAX_EXCED,
> + enable ? 0 : MASK_MAX_EXCED);
> +
> + i2c_wr8_and_or(sd, BCAPS, ~(MASK_REPEATER | MASK_READY),
> + enable ? 0 : MASK_REPEATER | MASK_READY);
> +}
> +
> +static void tc358743_disable_edid(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> +
> + v4l2_dbg(2, debug, sd, "%s:\n", __func__);
> +
> + cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
> +
> + /* DDC access to EDID is also disabled when hotplug is disabled. See
> + * register DDC_CTL */
> + i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
> +}
> +
> +static void tc358743_enable_edid(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> +
> + if (!state->edid_written) {
> + v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
> + return;
> + }
> +
> + v4l2_dbg(2, debug, sd, "%s:\n", __func__);
> +
> + /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
> + * hotplug is enabled. See register DDC_CTL */
> + queue_delayed_work(state->work_queues,
> + &state->delayed_work_enable_hotplug, HZ / 10);
> +}
> +
> +/* --------------- AVI --------------- */
> +/* TODO move to common library */
> +
> +struct aviInfoFrame {
> + u8 f17;
> + u8 y10;
> + u8 a0;
> + u8 b10;
> + u8 s10;
> + u8 c10;
> + u8 m10;
> + u8 r3210;
> + u8 itc;
> + u8 ec210;
> + u8 q10;
> + u8 sc10;
> + u8 f47;
> + u8 vic;
> + u8 yq10;
> + u8 cn10;
> + u8 pr3210;
> + u16 etb;
> + u16 sbb;
> + u16 elb;
> + u16 srb;
> +};
> +
> +static const char *y10Text[4] = {
> + "RGB",
> + "YCbCr 4:2:2",
> + "YCbCr 4:4:4",
> + "Future",
> +};
> +
> +static const char *c10Text[4] = {
> + "No Data",
> + "SMPTE 170M",
> + "ITU-R 709",
> + "Extended Colorimetry information valied",
Typo: valid
> +};
> +
> +static const char *itcText[2] = {
> + "No Data",
> + "IT content",
> +};
> +
> +static const char *ec210Text[8] = {
> + "xvYCC601",
> + "xvYCC709",
> + "sYCC601",
> + "AdobeYCC601",
> + "AdobeRGB",
> + "5 reserved",
> + "6 reserved",
> + "7 reserved",
> +};
> +
> +static const char *q10Text[4] = {
> + "Default",
> + "Limited Range",
> + "Full Range",
> + "Reserved",
> +};
> +
> +static void parse_avi_infoframe(struct v4l2_subdev *sd, u8 *buf,
> + struct aviInfoFrame *avi)
> +{
> + avi->f17 = (buf[1] >> 7) & 0x1;
> + avi->y10 = (buf[1] >> 5) & 0x3;
> + avi->a0 = (buf[1] >> 4) & 0x1;
> + avi->b10 = (buf[1] >> 2) & 0x3;
> + avi->s10 = buf[1] & 0x3;
> + avi->c10 = (buf[2] >> 6) & 0x3;
> + avi->m10 = (buf[2] >> 4) & 0x3;
> + avi->r3210 = buf[2] & 0xf;
> + avi->itc = (buf[3] >> 7) & 0x1;
> + avi->ec210 = (buf[3] >> 4) & 0x7;
> + avi->q10 = (buf[3] >> 2) & 0x3;
> + avi->sc10 = buf[3] & 0x3;
> + avi->f47 = (buf[4] >> 7) & 0x1;
> + avi->vic = buf[4] & 0x7f;
> + avi->yq10 = (buf[5] >> 6) & 0x3;
> + avi->cn10 = (buf[5] >> 4) & 0x3;
> + avi->pr3210 = buf[5] & 0xf;
> + avi->etb = buf[6] + 256 * buf[7];
> + avi->sbb = buf[8] + 256 * buf[9];
> + avi->elb = buf[10] + 256 * buf[11];
> + avi->srb = buf[12] + 256 * buf[13];
> +}
> +
> +static void print_avi_infoframe(struct v4l2_subdev *sd)
> +{
> + u8 buf[14];
> + u8 avi_len;
> + u8 avi_ver;
> + struct aviInfoFrame avi;
> +
> + if (!is_hdmi(sd)) {
> + v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
> + return;
> + }
> +
> + avi_ver = i2c_rd8(sd, PK_AVI_1HEAD);
> + avi_len = i2c_rd8(sd, PK_AVI_2HEAD);
> + v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", avi_ver, avi_len);
> +
> + if (avi_ver != 0x02)
> + return;
> +
> + i2c_rd(sd, PK_AVI_0BYTE, buf, ARRAY_SIZE(buf));
> +
> + v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
> + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
> + buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
> + buf[13]);
> +
> + parse_avi_infoframe(sd, buf, &avi);
> +
> + if (avi.vic)
> + v4l2_info(sd, "\tVIC: %d\n", avi.vic);
> + if (avi.itc)
> + v4l2_info(sd, "\t%s\n", itcText[avi.itc]);
> +
> + if (avi.y10)
> + v4l2_info(sd, "\t%s %s\n", y10Text[avi.y10],
> + !avi.c10 ? "" :
> + (avi.c10 == 0x3 ? ec210Text[avi.ec210] :
> + c10Text[avi.c10]));
> + else
> + v4l2_info(sd, "\t%s %s\n", y10Text[avi.y10], q10Text[avi.q10]);
> +}
> +
> +/* --------------- CTRLS --------------- */
> +
> +static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> +
> + return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
> + tx_5v_power_present(sd));
> +}
> +
> +static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> +
> + return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
> + get_audio_sampling_rate(sd));
> +}
> +
> +static int tc358743_s_audio_present_ctrl(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> +
> + return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
> + audio_present(sd));
> +}
> +
> +static int tc358743_update_controls(struct v4l2_subdev *sd)
> +{
> + int ret = 0;
> +
> + ret |= tc358743_s_ctrl_detect_tx_5v(sd);
> + ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
> + ret |= tc358743_s_audio_present_ctrl(sd);
> +
> + return ret;
> +}
> +
> +/* --------------- INIT --------------- */
> +
> +static void tc358743_reset_phy(struct v4l2_subdev *sd)
> +{
> + v4l2_dbg(1, debug, sd, "%s:\n", __func__);
> +
> + i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
> + i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
> +}
> +
> +static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
> +{
> + u16 sysctl = i2c_rd16(sd, SYSCTL);
> +
> + i2c_wr16(sd, SYSCTL, sysctl | mask);
> + i2c_wr16(sd, SYSCTL, sysctl & ~mask);
> +}
> +
> +static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
> +{
> + i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
> + enable ? MASK_SLEEP : 0);
> +}
> +
> +static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
> +{
> + v4l2_dbg(3, debug, sd, "%s: %sable\n",
> + __func__, enable ? "en" : "dis");
> +
> + i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
> + enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
> +}
> +
> +static void tc358743_set_pll(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct tc358743_platform_data *pdata = &state->pdata;
> + u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
> + u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
> + SET_PLL_FBD(pdata->pll_fbd);
> +
> + v4l2_dbg(2, debug, sd, "%s:\n", __func__);
> +
> + /* Only rewrite when needed, since rewriting triggers another format
> + * change event. */
> + if (pllctl0 != pllctl0_new) {
> + u32 hsck = (pdata->refclk_hz * pdata->pll_prd) / pdata->pll_fbd;
> + u16 pll_frs;
> +
> + if (hsck > 500000000)
> + pll_frs = 0x0;
> + else if (hsck > 250000000)
> + pll_frs = 0x1;
> + else if (hsck > 125000000)
> + pll_frs = 0x2;
> + else
> + pll_frs = 0x3;
> +
> + v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
> + tc358743_sleep_mode(sd, true);
> + i2c_wr16(sd, PLLCTL0, pllctl0_new);
> + i2c_wr16_and_or(sd, PLLCTL1,
> + ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
> + (SET_PLL_FRS(pll_frs) | MASK_RESETB |
> + MASK_PLL_EN));
> + udelay(10); /* REF_02, Sheet "Source HDMI" */
> + i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
> + tc358743_sleep_mode(sd, false);
> + }
> +}
> +
> +static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct tc358743_platform_data *pdata = &state->pdata;
> + u32 sys_freq;
> + u32 lockdet_ref;
> + u16 fh_min;
> + u16 fh_max;
> +
> + BUG_ON(!(pdata->refclk_hz == 26000000 ||
> + pdata->refclk_hz == 27000000 ||
> + pdata->refclk_hz == 42000000));
> +
> + sys_freq = pdata->refclk_hz / 10000;
> + i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
> + i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
> +
> + i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
> + (pdata->refclk_hz == 42000000) ?
> + MASK_PHY_SYSCLK_IND : 0x0);
> +
> + fh_min = pdata->refclk_hz / 100000;
> + i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
> + i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
> +
> + fh_max = (fh_min * 66) / 10;
> + i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
> + i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
> +
> + lockdet_ref = pdata->refclk_hz / 100;
> + i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
> + i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
> + i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
> +
> + i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
> + (pdata->refclk_hz == 27000000) ?
> + MASK_NCO_F0_MOD_27MHZ : 0x0);
> +}
> +
> +static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> +
> + switch (state->mbus_fmt_code) {
> + case MEDIA_BUS_FMT_UYVY8_1X16:
> + v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
> + i2c_wr8_and_or(sd, VOUT_SET2,
> + ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
> + MASK_SEL422 | MASK_VOUT_422FIL_100);
> + i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
> + MASK_VOUT_COLOR_601_YCBCR_LIMITED);
> + i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
> + MASK_YCBCRFMT_422_8_BIT);
> + break;
> + case MEDIA_BUS_FMT_RGB888_1X24:
> + v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
> + i2c_wr8_and_or(sd, VOUT_SET2,
> + ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
> + 0x00);
> + i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
> + MASK_VOUT_COLOR_RGB_FULL);
> + i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
> + break;
> + default:
> + v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
> + __func__, state->mbus_fmt_code);
> + }
> +}
> +
> +static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct v4l2_bt_timings *bt = &state->timings.bt;
> + u32 bits_pr_pixel =
> + (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
> + u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
> +
> + return DIV_ROUND_UP(bps, state->pdata.bps_pr_lane);
> +}
> +
> +static void tc358743_set_csi(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct tc358743_platform_data *pdata = &state->pdata;
> + unsigned lanes = tc358743_num_csi_lanes_needed(sd);
> +
> + v4l2_dbg(3, debug, sd, "%s:\n", __func__);
> +
> + tc358743_reset(sd, MASK_CTXRST);
> +
> + if (lanes < 1)
> + i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
> + if (lanes < 1)
> + i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
> + if (lanes < 2)
> + i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
> + if (lanes < 3)
> + i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
> + if (lanes < 4)
> + i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
> +
> + i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
> + i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
> + i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
> + i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
> + i2c_wr32(sd, TWAKEUP, pdata->twakeup);
> + i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
> + i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
> +
> + i2c_wr32(sd, HSTXVREGEN,
> + ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
> + ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
> + ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
> + ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
> + ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
> +
> + i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
> + i2c_wr32(sd, STARTCNTRL, MASK_START);
> + i2c_wr32(sd, CSI_START, MASK_STRT);
> +
> + i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
> + MASK_ADDRESS_CSI_CONTROL |
> + MASK_CSI_MODE |
> + MASK_TXHSMD |
> + ((lanes == 4) ? MASK_NOL_4 :
> + (lanes == 3) ? MASK_NOL_3 :
> + (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
> +
> + i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
> + MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
> + MASK_WCER | MASK_INER);
> +
> + i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
> + MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
> +
> + i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
> + MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
> +}
> +
> +static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct tc358743_platform_data *pdata = &state->pdata;
> +
> + /* Default settings from REF_02, sheet "Source HDMI"
> + * and custom settings as platform data */
> + i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
> + i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
> + SET_FREQ_RANGE_MODE_CYCLES(1));
> + i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn, pdata->phy_auto_rst);
> + i2c_wr8(sd, PHY_BIAS, 0x40);
> + i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
> + i2c_wr8(sd, AVM_CTL, 45);
> + i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
> + pdata->hdmi_det_v);
> + i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
> + (pdata->h_pi_rst ? MASK_H_PI_RST : 0) |
> + (pdata->v_pi_rst ? MASK_V_PI_RST : 0));
> + i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
> +}
> +
> +static void tc358743_erase_bksv(struct v4l2_subdev *sd)
> +{
> + int i;
> +
> + for (i = 0; i < 5; i++)
> + i2c_wr8(sd, BKSV + i, 0);
> +}
> +
> +static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
> +{
> + /* Default settings from REF_02, sheet "Source HDMI" */
> + i2c_wr8(sd, FORCE_MUTE, 0x00);
> + i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
> + MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
> + MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
> + i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
> + i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
> + i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
> + i2c_wr8(sd, FS_MUTE, 0x00);
> + i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
> + i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
> + i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
> + i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
> + i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
> + i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
> + i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
> + MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
> +}
> +
> +static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
> +{
> + /* Default settings from REF_02, sheet "Source HDMI" */
> + i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
> + MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
> + MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
> + MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
> + i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
> + i2c_wr8(sd, NO_PKT_CLR, 0x53);
> + i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
> + i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
> + i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
> +}
> +
> +static void tc358743_initial_setup(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct tc358743_platform_data *pdata = &state->pdata;
> +
> + /* Keep CEC and IR in reset since driver support is missing */
> + i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST),
> + (MASK_CECRST | MASK_IRRST));
> +
> + tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
> + tc358743_sleep_mode(sd, false);
> +
> + i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
> +
> + tc358743_set_ref_clk(sd);
> +
> + i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
> + pdata->ddc5v_delay & MASK_DDC5V_MODE);
> + i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
> +
> + tc358743_set_hdmi_phy(sd);
> + tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
> + tc358743_set_hdmi_audio(sd);
> + tc358743_set_hdmi_info_frame_mode(sd);
> +
> + i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
> + MASK_VOUTCOLORMODE_AUTO);
> + i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
> +}
> +
> +/* --------------- IRQ --------------- */
> +
> +static void tc358743_enable_interrupts(struct v4l2_subdev *sd)
> +{
> + u16 i;
> +
> + /* clear interrupt status registers */
> + for (i = SYS_INT; i <= KEY_INT; i++)
> + i2c_wr8(sd, i, 0xff);
> +
> + i2c_wr16(sd, INTSTATUS, 0xffff);
> +
> + /* enable interrupts */
> + i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_HDMI_DET) & 0xff);
> +
> + i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
> +
> + i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
> +
> + i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
> + MASK_M_AF_UNLOCK) & 0xff);
> +
> + i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff);
> +}
> +
> +static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
> +{
> + v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
> +
> + i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
> +}
> +
> +static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
> + bool *handled)
> +{
> + u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
> + u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
> +
> + i2c_wr8(sd, MISC_INT, misc_int);
> +
> + v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
> +
> + if (misc_int & MASK_I_SYNC_CHG) {
> +
> + v4l2_dbg(1, debug, sd, "%s: Format changed\n", __func__);
> +
> + if (no_sync(sd) || no_signal(sd)) {
> + tc358743_reset_phy(sd);
> + tc358743_erase_bksv(sd);
> + }
> +
> + v4l2_subdev_notify(sd, TC358743_FMT_CHANGE, NULL);
> +
> + misc_int &= ~MASK_I_SYNC_CHG;
> + if (handled)
> + *handled = true;
> + }
> +
> + if (misc_int) {
> + v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
> + __func__, misc_int);
> + }
> +}
> +
> +static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
> + bool *handled)
> +{
> + u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
> + u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
> +
> + i2c_wr8(sd, CBIT_INT, cbit_int);
> +
> + v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
> +
> + if (cbit_int & MASK_I_CBIT_FS) {
> +
> + v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
> + __func__);
> + tc358743_s_ctrl_audio_sampling_rate(sd);
> +
> + cbit_int &= ~MASK_I_CBIT_FS;
> + if (handled)
> + *handled = true;
> + }
> +
> + if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
> +
> + v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
> + __func__);
> + tc358743_s_audio_present_ctrl(sd);
> +
> + cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
> + if (handled)
> + *handled = true;
> + }
> +
> + if (cbit_int) {
> + v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
> + __func__, cbit_int);
> + }
> +}
> +
> +static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
> +{
> + u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
> + u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
> +
> + /* Bit 7 and bit 6 are set even when they are masked */
> + i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
> +
> + v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
> +
> + if (clk_int & (MASK_I_IN_DE_CHG)) {
> +
> + v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
> + __func__);
> +
> + /* If the source switch to a new resolution with the same pixel
> + * frequency as the existing (ie. 1080p25 -> 720p50), the
> + * I_SYNC_CHG interrupt is not always triggered, while the
> + * I_IN_DE_CHG interrupt seems to work fine. FMT_CHANGE
> + * notifications are only sent when the signal is stable to
> + * reduce the number of notifications. */
> + if (!no_signal(sd) && !no_sync(sd))
> + v4l2_subdev_notify(sd, TC358743_FMT_CHANGE, NULL);
> +
> + clk_int &= ~(MASK_I_IN_DE_CHG);
> + if (handled)
> + *handled = true;
> + }
> +
> + if (clk_int) {
> + v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
> + __func__, clk_int);
> + }
> +}
> +
> +static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
> +{
> + struct tc358743_state *state = to_state(sd);
> + u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
> + u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
> +
> + i2c_wr8(sd, SYS_INT, sys_int);
> +
> + v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
> +
> + if (sys_int & MASK_I_DDC) {
> + bool tx_5v = tx_5v_power_present(sd);
> +
> + v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
> + __func__, tx_5v ? "yes" : "no");
> +
> + if (tx_5v) {
> + tc358743_enable_edid(sd);
> + } else {
> + tc358743_disable_edid(sd);
> + memset(&state->timings, 0, sizeof(state->timings));
> + tc358743_erase_bksv(sd);
> + }
> +
> + tc358743_update_controls(sd);
> +
> + sys_int &= ~MASK_I_DDC;
> + if (handled)
> + *handled = true;
> + }
> +
> + if (sys_int & MASK_I_HDMI) {
> + v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
> + __func__);
> +
> + /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
> + i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
> +
> + sys_int &= ~MASK_I_HDMI;
> + if (handled)
> + *handled = true;
> + }
> +
> + if (sys_int) {
> + v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
> + __func__, sys_int);
> + }
> +}
> +
> +/* --------------- CORE OPS --------------- */
> +
> +static int tc358743_log_status(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct v4l2_dv_timings timings;
> + uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
> + uint16_t sysctl = i2c_rd16(sd, SYSCTL);
> + u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
> + const int deep_color_mode[4] = { 8, 10, 12, 16 };
> + static const char * const input_color_space[] = {
> + "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
> + "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
> + "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
> +
> + v4l2_info(sd, "-----Chip status-----\n");
> + v4l2_info(sd, "Chip ID: %d\n", i2c_rd16(sd, CHIPID) &
> + MASK_CHIPID);
> + v4l2_info(sd, "Chip revision: %d\n",
> + i2c_rd16(sd, CHIPID) & MASK_REVID);
> + v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
> + !!(sysctl & MASK_IRRST),
> + !!(sysctl & MASK_CECRST),
> + !!(sysctl & MASK_CTXRST),
> + !!(sysctl & MASK_HDMIRST));
> + v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
> + v4l2_info(sd, "Cable detected (+5V power): %s\n",
> + hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
> + v4l2_info(sd, "DDC lines enabled: %s\n",
> + (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
> + "yes" : "no");
> + v4l2_info(sd, "Hotplug enabled: %s\n",
> + (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
> + "yes" : "no");
> + v4l2_info(sd, "CEC enabled: %s\n",
> + (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
> + v4l2_info(sd, "-----Signal status-----\n");
> + v4l2_info(sd, "TMDS signal detected: %s\n",
> + hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
> + v4l2_info(sd, "Stable sync signal: %s\n",
> + hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
> + v4l2_info(sd, "PHY PLL locked: %s\n",
> + hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
> + v4l2_info(sd, "PHY DE detected: %s\n",
> + hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
> +
> + if (tc358743_get_detected_timings(sd, &timings)) {
> + v4l2_info(sd, "No video detected\n");
> + } else {
> + v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
> + true);
> + }
> + v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
> + true);
> +
> + v4l2_info(sd, "-----CSI-TX status-----\n");
> + v4l2_info(sd, "Lanes needed: %d\n",
> + tc358743_num_csi_lanes_needed(sd));
> + v4l2_info(sd, "Lanes in use: %d\n",
> + tc358743_num_csi_lanes_in_use(sd));
> + v4l2_info(sd, "Waiting for particular sync signal: %s\n",
> + (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
> + "yes" : "no");
> + v4l2_info(sd, "Transmit mode: %s\n",
> + (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
> + "yes" : "no");
> + v4l2_info(sd, "Receive mode: %s\n",
> + (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
> + "yes" : "no");
> + v4l2_info(sd, "Stopped: %s\n",
> + (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
> + "yes" : "no");
> + v4l2_info(sd, "Color space: %s\n",
> + state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
> + "YCbCr 422 16-bit" :
> + state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
> + "RGB 888 24-bit" : "Unsupported");
> +
> + v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
> + v4l2_info(sd, "HDCP encrypted content: %s\n",
> + hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
> + v4l2_info(sd, "Input color space: %s %s range\n",
> + input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
> + (vi_status3 & MASK_LIMITED) ? "limited" : "full");
> + if (!is_hdmi(sd))
> + return 0;
> + v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
> + "off");
> + v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
> + deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
> + MASK_S_DEEPCOLOR) >> 2]);
> + print_avi_infoframe(sd);
> +
> + return 0;
> +}
> +
> +static long tc358743_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
> +{
> + switch (cmd) {
> + case TC358743_CSI_RESET:
> + {
> + /*
> + * This function is called often with CSI overflow. It should
> + * run as fast as possible for quick recovery. I2C operations
> + * are slow. This function takes about 20 ms. Stop stream first,
> + * reset CSI and enable stream. Avoid calling enable_stream
> + * twice which add an extra I2C read.
> + */
> + unsigned short confctl = i2c_rd16(sd, CONFCTL);
> +
> + v4l2_dbg(3, debug, sd, "%s: TC358743_CSI_RESET\n", __func__);
> +
> + i2c_wr16(sd, CONFCTL, confctl &
> + (~(MASK_VBUFEN | MASK_ABUFEN)));
> + tc358743_set_csi(sd);
> + i2c_wr16(sd, CONFCTL, confctl |
> + (MASK_VBUFEN | MASK_ABUFEN));
> + return 0;
> + }
> + }
> +
> + v4l2_dbg(1, debug, sd, "%s: unknown ioctl %08x\n", __func__, cmd);
> +
> + return -ENOTTY;
> +}
> +
> +#ifdef CONFIG_VIDEO_ADV_DEBUG
> +static void tc358743_print_register_map(struct v4l2_subdev *sd)
> +{
> + v4l2_info(sd, "0x0000–0x00FF: Global Control Register\n");
> + v4l2_info(sd, "0x0100–0x01FF: CSI2-TX PHY Register\n");
> + v4l2_info(sd, "0x0200–0x03FF: CSI2-TX PPI Register\n");
> + v4l2_info(sd, "0x0400–0x05FF: Reserved\n");
> + v4l2_info(sd, "0x0600–0x06FF: CEC Register\n");
> + v4l2_info(sd, "0x0700–0x84FF: Reserved\n");
> + v4l2_info(sd, "0x8500–0x85FF: HDMIRX System Control Register\n");
> + v4l2_info(sd, "0x8600–0x86FF: HDMIRX Audio Control Register\n");
> + v4l2_info(sd, "0x8700–0x87FF: HDMIRX InfoFrame packet data Register\n");
> + v4l2_info(sd, "0x8800–0x88FF: HDMIRX HDCP Port Register\n");
> + v4l2_info(sd, "0x8900–0x89FF: HDMIRX Video Output Port & 3D Register\n");
> + v4l2_info(sd, "0x8A00–0x8BFF: Reserved\n");
> + v4l2_info(sd, "0x8C00–0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
> + v4l2_info(sd, "0x9000–0x90FF: HDMIRX GBD Extraction Control\n");
> + v4l2_info(sd, "0x9100–0x92FF: HDMIRX GBD RAM read\n");
> + v4l2_info(sd, "0x9300- : Reserved\n");
> +}
> +
> +static int tc358743_get_reg_size(u16 address)
> +{
> + /* REF_01 p. 66-72 */
> + if (address <= 0x00ff)
> + return 2;
> + else if ((address >= 0x0100) && (address <= 0x06FF))
> + return 4;
> + else if ((address >= 0x0700) && (address <= 0x84ff))
> + return 2;
> + else
> + return 1;
> +}
> +
> +static int tc358743_g_register(struct v4l2_subdev *sd,
> + struct v4l2_dbg_register *reg)
> +{
> + if (reg->reg > 0xffff) {
> + tc358743_print_register_map(sd);
> + return -EINVAL;
> + }
> +
> + reg->size = tc358743_get_reg_size(reg->reg);
> +
> + i2c_rd(sd, reg->reg, (u8 *)®->val, reg->size);
> +
> + return 0;
> +}
> +
> +static int tc358743_s_register(struct v4l2_subdev *sd,
> + const struct v4l2_dbg_register *reg)
> +{
> + if (reg->reg > 0xffff) {
> + tc358743_print_register_map(sd);
> + return -EINVAL;
> + }
> +
> + /* It should not be possible for the user to enable HDCP with a simple
> + * v4l2-dbg command.
> + *
> + * DO NOT REMOVE THIS unless all other issues with HDCP have been
> + * resolved.
> + */
> + if (reg->reg == HDCP_MODE ||
> + reg->reg == HDCP_REG1 ||
> + reg->reg == HDCP_REG2 ||
> + reg->reg == HDCP_REG3 ||
> + reg->reg == BCAPS)
> + return 0;
> +
> + i2c_wr(sd, (u16)reg->reg, (u8 *)®->val,
> + tc358743_get_reg_size(reg->reg));
> +
> + return 0;
> +}
> +#endif
> +
> +static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
> +{
> + u16 intstatus = i2c_rd16(sd, INTSTATUS);
> +
> + v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
> +
> + if (intstatus & MASK_HDMI_INT) {
> + u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
> + u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
> +
> + if (hdmi_int0 & MASK_I_MISC)
> + tc358743_hdmi_misc_int_handler(sd, handled);
> + if (hdmi_int1 & MASK_I_CBIT)
> + tc358743_hdmi_cbit_int_handler(sd, handled);
> + if (hdmi_int1 & MASK_I_CLK)
> + tc358743_hdmi_clk_int_handler(sd, handled);
> + if (hdmi_int1 & MASK_I_SYS)
> + tc358743_hdmi_sys_int_handler(sd, handled);
> +
> + i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
> + intstatus &= ~MASK_HDMI_INT;
> + }
> +
> + if (intstatus & MASK_CSI_INT) {
> + u32 csi_int = i2c_rd32(sd, CSI_INT);
> +
> + if (csi_int & MASK_INTER)
> + tc358743_csi_err_int_handler(sd, handled);
> +
> + i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
> + intstatus &= ~MASK_CSI_INT;
> + }
> +
> + intstatus = i2c_rd16(sd, INTSTATUS);
> + if (intstatus) {
> + v4l2_dbg(1, debug, sd,
> + "%s: Unhandled IntStatus interrupts: 0x%02x\n",
> + __func__, intstatus);
> + }
> +
> + return 0;
> +}
> +
> +/* --------------- VIDEO OPS --------------- */
> +
> +static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
> +{
> + *status = 0;
> + *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
> + *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
> +
> + v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
> +
> + return 0;
> +}
> +
> +static int tc358743_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
> + struct v4l2_subdev_format *format)
> +{
> + struct tc358743_state *state = to_state(sd);
> +
> + if (format->pad != 0)
> + return -EINVAL;
> +
> + switch (format->format.code) {
> + case MEDIA_BUS_FMT_RGB888_1X24:
> + case MEDIA_BUS_FMT_UYVY8_1X16:
> + state->mbus_fmt_code = format->format.code;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + enable_stream(sd, false);
> + tc358743_set_pll(sd);
> + tc358743_set_csi(sd);
> + tc358743_set_csi_color_space(sd);
> +
> + return 0;
> +}
> +
> +static int tc358743_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
> + struct v4l2_subdev_format *format)
> +{
> + struct tc358743_state *state = to_state(sd);
> + u8 vi_rep = i2c_rd8(sd, VI_REP);
> +
> + if (format->pad != 0)
> + return -EINVAL;
> +
> + format->format.code = state->mbus_fmt_code;
> + format->format.width = state->timings.bt.width;
> + format->format.height = state->timings.bt.height;
> + format->format.field = V4L2_FIELD_NONE;
> +
> + switch (vi_rep & MASK_VOUT_COLOR_SEL) {
> + case MASK_VOUT_COLOR_RGB_FULL:
> + case MASK_VOUT_COLOR_RGB_LIMITED:
> + format->format.colorspace = V4L2_COLORSPACE_SRGB;
> + break;
> + case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
> + case MASK_VOUT_COLOR_601_YCBCR_FULL:
> + format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
> + break;
> + case MASK_VOUT_COLOR_709_YCBCR_FULL:
> + case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
> + format->format.colorspace = V4L2_COLORSPACE_REC709;
> + break;
> + default:
> + format->format.colorspace = 0;
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
> + struct v4l2_dv_timings *timings)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct v4l2_bt_timings *bt;
> +
> + if (!timings)
> + return -EINVAL;
> +
> + if (debug)
> + v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
> + timings, false);
> +
> + if (!memcmp(&state->timings, timings, sizeof(struct v4l2_dv_timings))) {
Use v4l2_match_dv_timings() instead of memcmp. v4l2_match_dv_timings will
ignore differences that are irrelevant, such as different 'standards' field
values.
> + v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
> + return 0;
> + }
> +
> + bt = &timings->bt;
> +
> + if (!v4l2_valid_dv_timings(timings,
> + &tc358743_timings_cap, NULL, NULL)) {
> + v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
> + return -ERANGE;
> + }
> +
> + /* Fill the optional fields .standards and .flags in struct
> + * v4l2_dv_timings if the format is one of the CEA or DMT timings */
> + v4l2_find_dv_timings_cap(timings,
> + &tc358743_timings_cap, 250000, NULL, NULL);
> +
> + state->timings = *timings;
> +
> + enable_stream(sd, false);
> + tc358743_set_pll(sd);
> + tc358743_set_csi(sd);
> +
> + return 0;
> +}
> +
> +static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
> + struct v4l2_dv_timings *timings)
> +{
> + struct tc358743_state *state = to_state(sd);
> +
> + *timings = state->timings;
> +
> + return 0;
> +}
> +
> +static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
> + struct v4l2_enum_dv_timings *timings)
> +{
> + if (timings->pad != 0)
> + return -EINVAL;
> +
> + return v4l2_enum_dv_timings_cap(timings,
> + &tc358743_timings_cap, NULL, NULL);
> +}
> +
> +static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
> + struct v4l2_dv_timings *timings)
> +{
> + int ret;
> +
> + ret = tc358743_get_detected_timings(sd, timings);
> + if (ret)
> + return ret;
> +
> + if (debug)
> + v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
> + timings, false);
> +
> + if (!v4l2_valid_dv_timings(timings,
> + &tc358743_timings_cap, NULL, NULL)) {
> + v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
> + return -ERANGE;
> + }
> +
> + return 0;
> +}
> +
> +static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
> + struct v4l2_dv_timings_cap *cap)
> +{
> + if (cap->pad != 0)
> + return -EINVAL;
> +
> + *cap = tc358743_timings_cap;
> +
> + return 0;
> +}
> +
> +static int tc358743_g_mbus_config(struct v4l2_subdev *sd,
> + struct v4l2_mbus_config *cfg)
> +{
> + cfg->type = V4L2_MBUS_CSI2;
> +
> + cfg->flags = i2c_rd16(sd, TXOPTIONCNTRL) & MASK_CONTCLKMODE ?
> + V4L2_MBUS_CSI2_CONTINUOUS_CLOCK :
> + V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK;
> +
> + switch (tc358743_num_csi_lanes_in_use(sd)) {
> + case 1:
> + cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
> + break;
> + case 2:
> + cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
> + break;
> + case 3:
> + cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
> + break;
> + case 4:
> + cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
> +{
> + enable_stream(sd, enable);
> +
> + return 0;
> +}
> +
> +/* --------------- PAD OPS --------------- */
> +
> +static int tc358743_g_edid(struct v4l2_subdev *sd,
> + struct v4l2_subdev_edid *edid)
> +{
> + struct tc358743_state *state = to_state(sd);
> +
> + if (edid->pad != 0)
> + return -EINVAL;
> +
Add:
if (edid->start_block == 0 && edid->blocks == 0) {
edid->blocks = state->edid_written ? 8 : 0;
return 0;
}
Actually, it would be better if s_edid would remember the size
of the EDID and return that here instead of hardcoding to 8.
> + if (!state->edid_written)
> + return -ENODATA;
> +
> + if (edid->blocks == 0)
> + return -EINVAL;
> +
> + if (edid->start_block + edid->blocks > 8) {
> + edid->blocks = 8;
> + return -E2BIG;
Just return -EINVAL here.
> + }
> +
> + if (!edid->edid)
> + return -EINVAL;
No need to test for this, it can't happen.
> +
> + i2c_rd(sd, EDID_RAM + (edid->start_block * 128), edid->edid,
> + edid->blocks * 128);
> +
> + return 0;
> +}
> +
> +static int tc358743_s_edid(struct v4l2_subdev *sd,
> + struct v4l2_subdev_edid *edid)
> +{
> + struct tc358743_state *state = to_state(sd);
> + u16 edid_len = edid->blocks * 128;
> +
> + v4l2_dbg(2, debug, sd, "%s\n", __func__);
> +
> + if (edid->pad != 0)
> + return -EINVAL;
> +
> + if (edid->start_block != 0)
> + return -EINVAL;
> +
> + if (edid->blocks > 8) {
> + edid->blocks = 8;
'8' should be a #define.
> + return -E2BIG;
> + }
> +
> + if (edid->blocks != 0 && !edid->edid)
> + return -EINVAL;
> +
> + tc358743_disable_edid(sd);
> +
> + i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
> + i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
> +
> + if (edid->blocks == 0) {
> + state->edid_written = false;
> + return 0;
> + }
> +
> + i2c_wr(sd, EDID_RAM, edid->edid, edid_len);
> +
> + state->edid_written = true;
Instead of true and false, store the number of blocks in edid_written.
> +
> + if (tx_5v_power_present(sd))
> + tc358743_enable_edid(sd);
> +
> + return 0;
> +}
> +
> +/* -------------------------------------------------------------------------- */
> +
> +static const struct v4l2_subdev_core_ops tc358743_core_ops = {
> + .log_status = tc358743_log_status,
> + .ioctl = tc358743_ioctl,
> +#ifdef CONFIG_VIDEO_ADV_DEBUG
> + .g_register = tc358743_g_register,
> + .s_register = tc358743_s_register,
> +#endif
> + .interrupt_service_routine = tc358743_isr,
> +};
> +
> +static const struct v4l2_subdev_video_ops tc358743_video_ops = {
> + .g_input_status = tc358743_g_input_status,
> + .s_dv_timings = tc358743_s_dv_timings,
> + .g_dv_timings = tc358743_g_dv_timings,
> + .query_dv_timings = tc358743_query_dv_timings,
> + .g_mbus_config = tc358743_g_mbus_config,
> + .s_stream = tc358743_s_stream,
> +};
> +
> +static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
> + .set_fmt = tc358743_set_fmt,
> + .get_fmt = tc358743_get_fmt,
> + .get_edid = tc358743_g_edid,
> + .set_edid = tc358743_s_edid,
> + .enum_dv_timings = tc358743_enum_dv_timings,
> + .dv_timings_cap = tc358743_dv_timings_cap,
> +};
> +
> +static const struct v4l2_subdev_ops tc358743_ops = {
> + .core = &tc358743_core_ops,
> + .video = &tc358743_video_ops,
> + .pad = &tc358743_pad_ops,
> +};
> +
> +/* --------------- CUSTOM CTRLS --------------- */
> +
> +static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
> + .id = TC358743_CID_AUDIO_SAMPLING_RATE,
> + .name = "Audio sampling rate",
> + .type = V4L2_CTRL_TYPE_INTEGER,
> + .min = 0,
> + .max = 768000,
> + .step = 1,
> + .def = 0,
> + .flags = V4L2_CTRL_FLAG_READ_ONLY,
> +};
> +
> +static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
> + .id = TC358743_CID_AUDIO_PRESENT,
> + .name = "Audio present",
> + .type = V4L2_CTRL_TYPE_BOOLEAN,
> + .def = 0,
> + .flags = V4L2_CTRL_FLAG_READ_ONLY,
> +};
> +
> +/* --------------- PROBE / REMOVE --------------- */
> +
> +static int tc358743_probe(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + static struct v4l2_dv_timings default_timing =
> + V4L2_DV_BT_CEA_640X480P59_94;
> + struct tc358743_state *state;
> + struct tc358743_platform_data *pdata = client->dev.platform_data;
> + struct v4l2_subdev *sd;
> + int err;
> +
> + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
> + return -EIO;
> + v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
> + client->addr << 1, client->adapter->name);
> +
> + state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
> + GFP_KERNEL);
> + if (!state) {
> + v4l_err(client, "Could not allocate tc358743_state memory!\n");
> + return -ENOMEM;
> + }
> +
> + /* platform data */
> + if (!pdata) {
> + v4l_err(client, "No platform data!\n");
> + return -ENODEV;
> + }
> + state->pdata = *pdata;
> +
> + state->i2c_client = client;
> + sd = &state->sd;
> + v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
> + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
> +
> + /* i2c access */
> + /* read the interrupt mask register, it should carry the
> + * default values, as it hasn't been touched at this point.
> + */
> + if (i2c_rd16(sd, INTMASK) != 0x0400) {
> + v4l2_info(sd, "not a TC358743 on address 0x%x\n",
> + client->addr << 1);
> + return -ENODEV;
> + }
> +
> + /* control handlers */
> + v4l2_ctrl_handler_init(&state->hdl, 3);
> +
> + /* private controls */
> + state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
> + V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
> +
> + /* custom controls */
> + state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
> + &tc358743_ctrl_audio_sampling_rate, NULL);
> +
> + state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
> + &tc358743_ctrl_audio_present, NULL);
> +
> + sd->ctrl_handler = &state->hdl;
> + if (state->hdl.error) {
> + err = state->hdl.error;
> + goto err_hdl;
> + }
> +
> + if (tc358743_update_controls(sd)) {
> + err = -ENODEV;
> + goto err_hdl;
> + }
> +
> + /* work queues */
> + state->work_queues = create_singlethread_workqueue(client->name);
> + if (!state->work_queues) {
> + v4l2_err(sd, "Could not create work queue\n");
> + err = -ENOMEM;
> + goto err_hdl;
> + }
> +
> + INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
> + tc358743_delayed_work_enable_hotplug);
> +
> + tc358743_initial_setup(sd);
> +
> + tc358743_s_dv_timings(sd, &default_timing);
> +
> + state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
> + tc358743_set_csi_color_space(sd);
> +
> + tc358743_enable_interrupts(sd);
> +
> + v4l2_ctrl_handler_setup(sd->ctrl_handler);
> +
> + v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
> + client->addr << 1, client->adapter->name);
> +
> + return 0;
> +
> +err_hdl:
> + v4l2_ctrl_handler_free(&state->hdl);
> + return err;
> +}
> +
> +static int tc358743_remove(struct i2c_client *client)
> +{
> + struct v4l2_subdev *sd = i2c_get_clientdata(client);
> + struct tc358743_state *state = to_state(sd);
> +
> + cancel_delayed_work(&state->delayed_work_enable_hotplug);
> + destroy_workqueue(state->work_queues);
> + v4l2_device_unregister_subdev(sd);
> + v4l2_ctrl_handler_free(&state->hdl);
> +
> + return 0;
> +}
> +
> +static struct i2c_device_id tc358743_id[] = {
> + {"tc358743", 0},
> + {}
> +};
> +
> +MODULE_DEVICE_TABLE(i2c, tc358743_id);
> +
> +static struct i2c_driver tc358743_driver = {
> + .driver = {
> + .owner = THIS_MODULE,
> + .name = "tc358743",
> + },
> + .probe = tc358743_probe,
> + .remove = tc358743_remove,
> + .id_table = tc358743_id,
> +};
> +
> +module_i2c_driver(tc358743_driver);
> diff --git a/drivers/media/i2c/tc358743_regs.h b/drivers/media/i2c/tc358743_regs.h
> new file mode 100644
> index 0000000..30a8537
> --- /dev/null
> +++ b/drivers/media/i2c/tc358743_regs.h
> @@ -0,0 +1,670 @@
> +/*
> + * tc358743 - Toshiba HDMI to CSI-2 bridge - register names and bit masks
> + *
> + * Copyright 2014 Cisco Systems, Inc. and/or its affiliates. All rights
> + * reserved.
> + *
> + * This program is free software; you may redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + *
> + */
> +
> +/*
> + * References (c = chapter, p = page):
> + * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
> + */
> +
> +/* Bit masks has prefix 'MASK_' and options after '_'. */
> +
> +#ifndef __TC358743_REGS_H
> +#define __TC358743_REGS_H
> +
> +#define CHIPID 0x0000
> +#define MASK_CHIPID 0xff00
> +#define MASK_REVID 0x00ff
> +
> +#define SYSCTL 0x0002
> +#define MASK_IRRST 0x0800
> +#define MASK_CECRST 0x0400
> +#define MASK_CTXRST 0x0200
> +#define MASK_HDMIRST 0x0100
> +#define MASK_SLEEP 0x0001
> +
> +#define CONFCTL 0x0004
> +#define MASK_PWRISO 0x8000
> +#define MASK_ACLKOPT 0x1000
> +#define MASK_AUDCHNUM 0x0c00
> +#define MASK_AUDCHNUM_8 0x0000
> +#define MASK_AUDCHNUM_6 0x0400
> +#define MASK_AUDCHNUM_4 0x0800
> +#define MASK_AUDCHNUM_2 0x0c00
> +#define MASK_AUDCHSEL 0x0200
> +#define MASK_I2SDLYOPT 0x0100
> +#define MASK_YCBCRFMT 0x00c0
> +#define MASK_YCBCRFMT_444 0x0000
> +#define MASK_YCBCRFMT_422_12_BIT 0x0040
> +#define MASK_YCBCRFMT_COLORBAR 0x0080
> +#define MASK_YCBCRFMT_422_8_BIT 0x00c0
> +#define MASK_INFRMEN 0x0020
> +#define MASK_AUDOUTSEL 0x0018
> +#define MASK_AUDOUTSEL_CSI 0x0000
> +#define MASK_AUDOUTSEL_I2S 0x0010
> +#define MASK_AUDOUTSEL_TDM 0x0018
> +#define MASK_AUTOINDEX 0x0004
> +#define MASK_ABUFEN 0x0002
> +#define MASK_VBUFEN 0x0001
> +
> +#define FIFOCTL 0x0006
> +
> +#define INTSTATUS 0x0014
> +#define MASK_AMUTE_INT 0x0400
> +#define MASK_HDMI_INT 0x0200
> +#define MASK_CSI_INT 0x0100
> +#define MASK_SYS_INT 0x0020
> +#define MASK_CEC_EINT 0x0010
> +#define MASK_CEC_TINT 0x0008
> +#define MASK_CEC_RINT 0x0004
> +#define MASK_IR_EINT 0x0002
> +#define MASK_IR_DINT 0x0001
> +
> +#define INTMASK 0x0016
> +#define MASK_AMUTE_MSK 0x0400
> +#define MASK_HDMI_MSK 0x0200
> +#define MASK_CSI_MSK 0x0100
> +#define MASK_SYS_MSK 0x0020
> +#define MASK_CEC_EMSK 0x0010
> +#define MASK_CEC_TMSK 0x0008
> +#define MASK_CEC_RMSK 0x0004
> +#define MASK_IR_EMSK 0x0002
> +#define MASK_IR_DMSK 0x0001
> +
> +#define INTFLAG 0x0018
> +#define INTSYSSTATUS 0x001A
> +
> +#define PLLCTL0 0x0020
> +#define MASK_PLL_PRD 0xf000
> +#define SET_PLL_PRD(prd) ((((prd) - 1) << 12) &\
> + MASK_PLL_PRD)
> +#define MASK_PLL_FBD 0x01ff
> +#define SET_PLL_FBD(fbd) (((fbd) - 1) & MASK_PLL_FBD)
> +
> +#define PLLCTL1 0x0022
> +#define MASK_PLL_FRS 0x0c00
> +#define SET_PLL_FRS(frs) (((frs) << 10) & MASK_PLL_PRD)
> +#define MASK_PLL_LBWS 0x0300
> +#define MASK_LFBREN 0x0040
> +#define MASK_BYPCKEN 0x0020
> +#define MASK_CKEN 0x0010
> +#define MASK_RESETB 0x0002
> +#define MASK_PLL_EN 0x0001
> +
> +#define CLW_CNTRL 0x0140
> +#define MASK_CLW_LANEDISABLE 0x0001
> +
> +#define D0W_CNTRL 0x0144
> +#define MASK_D0W_LANEDISABLE 0x0001
> +
> +#define D1W_CNTRL 0x0148
> +#define MASK_D1W_LANEDISABLE 0x0001
> +
> +#define D2W_CNTRL 0x014C
> +#define MASK_D2W_LANEDISABLE 0x0001
> +
> +#define D3W_CNTRL 0x0150
> +#define MASK_D3W_LANEDISABLE 0x0001
> +
> +#define STARTCNTRL 0x0204
> +#define MASK_START 0x00000001
> +
> +#define LINEINITCNT 0x0210
> +#define LPTXTIMECNT 0x0214
> +#define TCLK_HEADERCNT 0x0218
> +#define TCLK_TRAILCNT 0x021C
> +#define THS_HEADERCNT 0x0220
> +#define TWAKEUP 0x0224
> +#define TCLK_POSTCNT 0x0228
> +#define THS_TRAILCNT 0x022C
> +#define HSTXVREGCNT 0x0230
> +
> +#define HSTXVREGEN 0x0234
> +#define MASK_D3M_HSTXVREGEN 0x0010
> +#define MASK_D2M_HSTXVREGEN 0x0008
> +#define MASK_D1M_HSTXVREGEN 0x0004
> +#define MASK_D0M_HSTXVREGEN 0x0002
> +#define MASK_CLM_HSTXVREGEN 0x0001
> +
> +
> +#define TXOPTIONCNTRL 0x0238
> +#define MASK_CONTCLKMODE 0x00000001
> +
> +#define CSI_CONTROL 0x040C
> +#define MASK_CSI_MODE 0x8000
> +#define MASK_HTXTOEN 0x0400
> +#define MASK_TXHSMD 0x0080
> +#define MASK_HSCKMD 0x0020
> +#define MASK_NOL 0x0006
> +#define MASK_NOL_1 0x0000
> +#define MASK_NOL_2 0x0002
> +#define MASK_NOL_3 0x0004
> +#define MASK_NOL_4 0x0006
> +#define MASK_EOTDIS 0x0001
> +
> +#define CSI_INT 0x0414
> +#define MASK_INTHLT 0x00000008
> +#define MASK_INTER 0x00000004
> +
> +#define CSI_INT_ENA 0x0418
> +#define MASK_IENHLT 0x00000008
> +#define MASK_IENER 0x00000004
> +
> +#define CSI_ERR 0x044C
> +#define MASK_INER 0x00000200
> +#define MASK_WCER 0x00000100
> +#define MASK_QUNK 0x00000010
> +#define MASK_TXBRK 0x00000002
> +
> +#define CSI_ERR_INTENA 0x0450
> +#define CSI_ERR_HALT 0x0454
> +
> +#define CSI_CONFW 0x0500
> +#define MASK_MODE 0xe0000000
> +#define MASK_MODE_SET 0xa0000000
> +#define MASK_MODE_CLEAR 0xc0000000
> +#define MASK_ADDRESS 0x1f000000
> +#define MASK_ADDRESS_CSI_CONTROL 0x03000000
> +#define MASK_ADDRESS_CSI_INT_ENA 0x06000000
> +#define MASK_ADDRESS_CSI_ERR_INTENA 0x14000000
> +#define MASK_ADDRESS_CSI_ERR_HALT 0x15000000
> +#define MASK_DATA 0x0000ffff
> +
> +#define CSI_INT_CLR 0x050C
> +#define MASK_ICRER 0x00000004
> +
> +#define CSI_START 0x0518
> +#define MASK_STRT 0x00000001
> +
> +#define CECEN 0x0600
> +#define MASK_CECEN 0x0001
> +
> +#define HDMI_INT0 0x8500
> +#define MASK_I_KEY 0x80
> +#define MASK_I_MISC 0x02
> +#define MASK_I_PHYERR 0x01
> +
> +#define HDMI_INT1 0x8501
> +#define MASK_I_GBD 0x80
> +#define MASK_I_HDCP 0x40
> +#define MASK_I_ERR 0x20
> +#define MASK_I_AUD 0x10
> +#define MASK_I_CBIT 0x08
> +#define MASK_I_PACKET 0x04
> +#define MASK_I_CLK 0x02
> +#define MASK_I_SYS 0x01
> +
> +#define SYS_INT 0x8502
> +#define MASK_I_ACR_CTS 0x80
> +#define MASK_I_ACRN 0x40
> +#define MASK_I_DVI 0x20
> +#define MASK_I_HDMI 0x10
> +#define MASK_I_NOPMBDET 0x08
> +#define MASK_I_DPMBDET 0x04
> +#define MASK_I_TMDS 0x02
> +#define MASK_I_DDC 0x01
> +
> +#define CLK_INT 0x8503
> +#define MASK_I_OUT_H_CHG 0x40
> +#define MASK_I_IN_DE_CHG 0x20
> +#define MASK_I_IN_HV_CHG 0x10
> +#define MASK_I_DC_CHG 0x08
> +#define MASK_I_PXCLK_CHG 0x04
> +#define MASK_I_PHYCLK_CHG 0x02
> +#define MASK_I_TMDSCLK_CHG 0x01
> +
> +#define CBIT_INT 0x8505
> +#define MASK_I_AF_LOCK 0x80
> +#define MASK_I_AF_UNLOCK 0x40
> +#define MASK_I_CBIT_FS 0x02
> +
> +#define ERR_INT 0x8507
> +#define MASK_I_EESS_ERR 0x80
> +
> +#define HDCP_INT 0x8508
> +#define MASK_I_AVM_SET 0x80
> +#define MASK_I_AVM_CLR 0x40
> +#define MASK_I_LINKERR 0x20
> +#define MASK_I_SHA_END 0x10
> +#define MASK_I_R0_END 0x08
> +#define MASK_I_KM_END 0x04
> +#define MASK_I_AKSV_END 0x02
> +#define MASK_I_AN_END 0x01
> +
> +#define MISC_INT 0x850B
> +#define MASK_I_AS_LAYOUT 0x10
> +#define MASK_I_NO_SPD 0x08
> +#define MASK_I_NO_VS 0x03
> +#define MASK_I_SYNC_CHG 0x02
> +#define MASK_I_AUDIO_MUTE 0x01
> +
> +#define KEY_INT 0x850F
> +
> +#define SYS_INTM 0x8512
> +#define MASK_M_ACR_CTS 0x80
> +#define MASK_M_ACR_N 0x40
> +#define MASK_M_DVI_DET 0x20
> +#define MASK_M_HDMI_DET 0x10
> +#define MASK_M_NOPMBDET 0x08
> +#define MASK_M_BPMBDET 0x04
> +#define MASK_M_TMDS 0x02
> +#define MASK_M_DDC 0x01
> +
> +#define CLK_INTM 0x8513
> +#define MASK_M_OUT_H_CHG 0x40
> +#define MASK_M_IN_DE_CHG 0x20
> +#define MASK_M_IN_HV_CHG 0x10
> +#define MASK_M_DC_CHG 0x08
> +#define MASK_M_PXCLK_CHG 0x04
> +#define MASK_M_PHYCLK_CHG 0x02
> +#define MASK_M_TMDS_CHG 0x01
> +
> +#define PACKET_INTM 0x8514
> +
> +#define CBIT_INTM 0x8515
> +#define MASK_M_AF_LOCK 0x80
> +#define MASK_M_AF_UNLOCK 0x40
> +#define MASK_M_CBIT_FS 0x02
> +
> +#define AUDIO_INTM 0x8516
> +
> +#define ERR_INTM 0x8517
> +#define MASK_M_EESS_ERR 0x80
> +
> +#define HDCP_INTM 0x8518
> +#define MASK_M_AVM_SET 0x80
> +#define MASK_M_AVM_CLR 0x40
> +#define MASK_M_LINKERR 0x20
> +#define MASK_M_SHA_END 0x10
> +#define MASK_M_R0_END 0x08
> +#define MASK_M_KM_END 0x04
> +#define MASK_M_AKSV_END 0x02
> +#define MASK_M_AN_END 0x01
> +
> +#define MISC_INTM 0x851B
> +#define MASK_M_AS_LAYOUT 0x10
> +#define MASK_M_NO_SPD 0x08
> +#define MASK_M_NO_VS 0x03
> +#define MASK_M_SYNC_CHG 0x02
> +#define MASK_M_AUDIO_MUTE 0x01
> +
> +#define KEY_INTM 0x851F
> +
> +#define SYS_STATUS 0x8520
> +#define MASK_S_SYNC 0x80
> +#define MASK_S_AVMUTE 0x40
> +#define MASK_S_HDCP 0x20
> +#define MASK_S_HDMI 0x10
> +#define MASK_S_PHY_SCDT 0x08
> +#define MASK_S_PHY_PLL 0x04
> +#define MASK_S_TMDS 0x02
> +#define MASK_S_DDC5V 0x01
> +
> +#define CSI_STATUS 0x0410
> +#define MASK_S_WSYNC 0x0400
> +#define MASK_S_TXACT 0x0200
> +#define MASK_S_RXACT 0x0100
> +#define MASK_S_HLT 0x0001
> +
> +#define VI_STATUS1 0x8522
> +#define MASK_S_V_GBD 0x08
> +#define MASK_S_DEEPCOLOR 0x0c
> +#define MASK_S_V_422 0x02
> +#define MASK_S_V_INTERLACE 0x01
> +
> +#define AU_STATUS0 0x8523
> +#define MASK_S_A_SAMPLE 0x01
> +
> +#define VI_STATUS3 0x8528
> +#define MASK_S_V_COLOR 0x1e
> +#define MASK_LIMITED 0x01
> +
> +#define PHY_CTL0 0x8531
> +#define MASK_PHY_SYSCLK_IND 0x02
> +#define MASK_PHY_CTL 0x01
> +
> +
> +#define PHY_CTL1 0x8532 /* Not in REF_01 */
> +#define MASK_PHY_AUTO_RST1 0xf0
> +#define MASK_PHY_AUTO_RST1_OFF 0x00
> +#define SET_PHY_AUTO_RST1_US(us) ((((us) / 200) << 4) & \
> + MASK_PHY_AUTO_RST1)
> +#define MASK_FREQ_RANGE_MODE 0x0f
> +#define SET_FREQ_RANGE_MODE_CYCLES(cycles) (((cycles) - 1) & \
> + MASK_FREQ_RANGE_MODE)
> +
> +#define PHY_CTL2 0x8533 /* Not in REF_01 */
> +#define MASK_PHY_AUTO_RST4 0x04
> +#define MASK_PHY_AUTO_RST3 0x02
> +#define MASK_PHY_AUTO_RST2 0x01
> +#define MASK_PHY_AUTO_RSTn (MASK_PHY_AUTO_RST4 | \
> + MASK_PHY_AUTO_RST3 | \
> + MASK_PHY_AUTO_RST2)
> +
> +#define PHY_EN 0x8534
> +#define MASK_ENABLE_PHY 0x01
> +
> +#define PHY_RST 0x8535
> +#define MASK_RESET_CTRL 0x01 /* Reset active low */
> +
> +#define PHY_BIAS 0x8536 /* Not in REF_01 */
> +
> +#define PHY_CSQ 0x853F /* Not in REF_01 */
> +#define MASK_CSQ_CNT 0x0f
> +#define SET_CSQ_CNT_LEVEL(n) (n & MASK_CSQ_CNT)
> +
> +#define SYS_FREQ0 0x8540
> +#define SYS_FREQ1 0x8541
> +
> +#define SYS_CLK 0x8542 /* Not in REF_01 */
> +#define MASK_CLK_DIFF 0x0C
> +#define MASK_CLK_DIV 0x03
> +
> +#define DDC_CTL 0x8543
> +#define MASK_DDC_ACK_POL 0x08
> +#define MASK_DDC_ACTION 0x04
> +#define MASK_DDC5V_MODE 0x03
> +#define MASK_DDC5V_MODE_0MS 0x00
> +#define MASK_DDC5V_MODE_50MS 0x01
> +#define MASK_DDC5V_MODE_100MS 0x02
> +#define MASK_DDC5V_MODE_200MS 0x03
> +
> +#define HPD_CTL 0x8544
> +#define MASK_HPD_CTL0 0x10
> +#define MASK_HPD_OUT0 0x01
> +
> +#define ANA_CTL 0x8545
> +#define MASK_APPL_PCSX 0x30
> +#define MASK_APPL_PCSX_HIZ 0x00
> +#define MASK_APPL_PCSX_L_FIX 0x10
> +#define MASK_APPL_PCSX_H_FIX 0x20
> +#define MASK_APPL_PCSX_NORMAL 0x30
> +#define MASK_ANALOG_ON 0x01
> +
> +#define AVM_CTL 0x8546
> +
> +#define INIT_END 0x854A
> +#define MASK_INIT_END 0x01
> +
> +#define HDMI_DET 0x8552
> +#define MASK_HDMI_DET_MOD1 0x80
> +#define MASK_HDMI_DET_MOD0 0x40
> +#define MASK_HDMI_DET_V 0x30
> +#define MASK_HDMI_DET_V_SYNC 0x00
> +#define MASK_HDMI_DET_V_ASYNC_25MS 0x10
> +#define MASK_HDMI_DET_V_ASYNC_50MS 0x20
> +#define MASK_HDMI_DET_V_ASYNC_100MS 0x30
> +#define MASK_HDMI_DET_NUM 0x0f
> +
> +#define HDCP_MODE 0x8560
> +#define MASK_MODE_RST_TN 0x20
> +#define MASK_LINE_REKEY 0x10
> +#define MASK_AUTO_CLR 0x04
> +
> +#define HDCP_REG1 0x8563 /* Not in REF_01 */
> +#define MASK_AUTH_UNAUTH_SEL 0x70
> +#define MASK_AUTH_UNAUTH_SEL_12_FRAMES 0x70
> +#define MASK_AUTH_UNAUTH_SEL_8_FRAMES 0x60
> +#define MASK_AUTH_UNAUTH_SEL_4_FRAMES 0x50
> +#define MASK_AUTH_UNAUTH_SEL_2_FRAMES 0x40
> +#define MASK_AUTH_UNAUTH_SEL_64_FRAMES 0x30
> +#define MASK_AUTH_UNAUTH_SEL_32_FRAMES 0x20
> +#define MASK_AUTH_UNAUTH_SEL_16_FRAMES 0x10
> +#define MASK_AUTH_UNAUTH_SEL_ONCE 0x00
> +#define MASK_AUTH_UNAUTH 0x01
> +#define MASK_AUTH_UNAUTH_AUTO 0x01
> +
> +#define HDCP_REG2 0x8564 /* Not in REF_01 */
> +#define MASK_AUTO_P3_RESET 0x0F
> +#define SET_AUTO_P3_RESET_FRAMES(n) (n & MASK_AUTO_P3_RESET)
> +#define MASK_AUTO_P3_RESET_OFF 0x00
> +
> +#define VOUT_SET2 0x8573
> +#define MASK_SEL422 0x80
> +#define MASK_VOUT_422FIL_100 0x40
> +#define MASK_VOUTCOLORMODE 0x03
> +#define MASK_VOUTCOLORMODE_THROUGH 0x00
> +#define MASK_VOUTCOLORMODE_AUTO 0x01
> +#define MASK_VOUTCOLORMODE_MANUAL 0x03
> +
> +#define VOUT_SET3 0x8574
> +#define MASK_VOUT_EXTCNT 0x08
> +
> +#define VI_REP 0x8576
> +#define MASK_VOUT_COLOR_SEL 0xe0
> +#define MASK_VOUT_COLOR_RGB_FULL 0x00
> +#define MASK_VOUT_COLOR_RGB_LIMITED 0x20
> +#define MASK_VOUT_COLOR_601_YCBCR_FULL 0x40
> +#define MASK_VOUT_COLOR_601_YCBCR_LIMITED 0x60
> +#define MASK_VOUT_COLOR_709_YCBCR_FULL 0x80
> +#define MASK_VOUT_COLOR_709_YCBCR_LIMITED 0xa0
> +#define MASK_VOUT_COLOR_FULL_TO_LIMITED 0xc0
> +#define MASK_VOUT_COLOR_LIMITED_TO_FULL 0xe0
> +#define MASK_IN_REP_HEN 0x10
> +#define MASK_IN_REP 0x0f
> +
> +#define DE_WIDTH_H_LO 0x8582 /* Not in REF_01 */
> +#define DE_WIDTH_H_HI 0x8583 /* Not in REF_01 */
> +#define DE_WIDTH_V_LO 0x8588 /* Not in REF_01 */
> +#define DE_WIDTH_V_HI 0x8589 /* Not in REF_01 */
> +#define H_SIZE_LO 0x858A /* Not in REF_01 */
> +#define H_SIZE_HI 0x858B /* Not in REF_01 */
> +#define V_SIZE_LO 0x858C /* Not in REF_01 */
> +#define V_SIZE_HI 0x858D /* Not in REF_01 */
> +#define FV_CNT_LO 0x85A1 /* Not in REF_01 */
> +#define FV_CNT_HI 0x85A2 /* Not in REF_01 */
> +
> +#define FH_MIN0 0x85AA /* Not in REF_01 */
> +#define FH_MIN1 0x85AB /* Not in REF_01 */
> +#define FH_MAX0 0x85AC /* Not in REF_01 */
> +#define FH_MAX1 0x85AD /* Not in REF_01 */
> +#define HV_RST 0x85AF /* Not in REF_01 */
> +#define MASK_H_PI_RST 0x20
> +#define MASK_V_PI_RST 0x10
> +
> +#define EDID_MODE 0x85C7
> +#define MASK_EDID_SPEED 0x40
> +#define MASK_EDID_MODE 0x03
> +#define MASK_EDID_MODE_DISABLE 0x00
> +#define MASK_EDID_MODE_DDC2B 0x01
> +#define MASK_EDID_MODE_E_DDC 0x02
> +
> +#define EDID_LEN1 0x85CA
> +#define EDID_LEN2 0x85CB
> +
> +#define HDCP_REG3 0x85D1 /* Not in REF_01 */
> +#define KEY_RD_CMD 0x01
> +
> +#define FORCE_MUTE 0x8600
> +#define MASK_FORCE_AMUTE 0x10
> +#define MASK_FORCE_DMUTE 0x01
> +
> +#define CMD_AUD 0x8601
> +#define MASK_CMD_BUFINIT 0x04
> +#define MASK_CMD_LOCKDET 0x02
> +#define MASK_CMD_MUTE 0x01
> +
> +#define AUTO_CMD0 0x8602
> +#define MASK_AUTO_MUTE7 0x80
> +#define MASK_AUTO_MUTE6 0x40
> +#define MASK_AUTO_MUTE5 0x20
> +#define MASK_AUTO_MUTE4 0x10
> +#define MASK_AUTO_MUTE3 0x08
> +#define MASK_AUTO_MUTE2 0x04
> +#define MASK_AUTO_MUTE1 0x02
> +#define MASK_AUTO_MUTE0 0x01
> +
> +#define AUTO_CMD1 0x8603
> +#define MASK_AUTO_MUTE10 0x04
> +#define MASK_AUTO_MUTE9 0x02
> +#define MASK_AUTO_MUTE8 0x01
> +
> +#define AUTO_CMD2 0x8604
> +#define MASK_AUTO_PLAY3 0x08
> +#define MASK_AUTO_PLAY2 0x04
> +
> +#define BUFINIT_START 0x8606
> +#define SET_BUFINIT_START_MS(milliseconds) ((milliseconds) / 100)
> +
> +#define FS_MUTE 0x8607
> +#define MASK_FS_ELSE_MUTE 0x80
> +#define MASK_FS22_MUTE 0x40
> +#define MASK_FS24_MUTE 0x20
> +#define MASK_FS88_MUTE 0x10
> +#define MASK_FS96_MUTE 0x08
> +#define MASK_FS176_MUTE 0x04
> +#define MASK_FS192_MUTE 0x02
> +#define MASK_FS_NO_MUTE 0x01
> +
> +#define FS_IMODE 0x8620
> +#define MASK_NLPCM_HMODE 0x40
> +#define MASK_NLPCM_SMODE 0x20
> +#define MASK_NLPCM_IMODE 0x10
> +#define MASK_FS_HMODE 0x08
> +#define MASK_FS_AMODE 0x04
> +#define MASK_FS_SMODE 0x02
> +#define MASK_FS_IMODE 0x01
> +
> +#define FS_SET 0x8621
> +#define MASK_FS 0x0f
> +
> +#define LOCKDET_REF0 0x8630
> +#define LOCKDET_REF1 0x8631
> +#define LOCKDET_REF2 0x8632
> +
> +#define ACR_MODE 0x8640
> +#define MASK_ACR_LOAD 0x10
> +#define MASK_N_MODE 0x04
> +#define MASK_CTS_MODE 0x01
> +
> +#define ACR_MDF0 0x8641
> +#define MASK_ACR_L2MDF 0x70
> +#define MASK_ACR_L2MDF_0_PPM 0x00
> +#define MASK_ACR_L2MDF_61_PPM 0x10
> +#define MASK_ACR_L2MDF_122_PPM 0x20
> +#define MASK_ACR_L2MDF_244_PPM 0x30
> +#define MASK_ACR_L2MDF_488_PPM 0x40
> +#define MASK_ACR_L2MDF_976_PPM 0x50
> +#define MASK_ACR_L2MDF_1976_PPM 0x60
> +#define MASK_ACR_L2MDF_3906_PPM 0x70
> +#define MASK_ACR_L1MDF 0x07
> +#define MASK_ACR_L1MDF_0_PPM 0x00
> +#define MASK_ACR_L1MDF_61_PPM 0x01
> +#define MASK_ACR_L1MDF_122_PPM 0x02
> +#define MASK_ACR_L1MDF_244_PPM 0x03
> +#define MASK_ACR_L1MDF_488_PPM 0x04
> +#define MASK_ACR_L1MDF_976_PPM 0x05
> +#define MASK_ACR_L1MDF_1976_PPM 0x06
> +#define MASK_ACR_L1MDF_3906_PPM 0x07
> +
> +#define ACR_MDF1 0x8642
> +#define MASK_ACR_L3MDF 0x07
> +#define MASK_ACR_L3MDF_0_PPM 0x00
> +#define MASK_ACR_L3MDF_61_PPM 0x01
> +#define MASK_ACR_L3MDF_122_PPM 0x02
> +#define MASK_ACR_L3MDF_244_PPM 0x03
> +#define MASK_ACR_L3MDF_488_PPM 0x04
> +#define MASK_ACR_L3MDF_976_PPM 0x05
> +#define MASK_ACR_L3MDF_1976_PPM 0x06
> +#define MASK_ACR_L3MDF_3906_PPM 0x07
> +
> +#define SDO_MODE1 0x8652
> +#define MASK_SDO_BIT_LENG 0x70
> +#define MASK_SDO_FMT 0x03
> +#define MASK_SDO_FMT_RIGHT 0x00
> +#define MASK_SDO_FMT_LEFT 0x01
> +#define MASK_SDO_FMT_I2S 0x02
> +
> +#define DIV_MODE 0x8665 /* Not in REF_01 */
> +#define MASK_DIV_DLY 0xf0
> +#define SET_DIV_DLY_MS(milliseconds) ((((milliseconds) / 100) << 4) & \
> + MASK_DIV_DLY)
> +#define MASK_DIV_MODE 0x01
> +
> +#define NCO_F0_MOD 0x8670
> +#define MASK_NCO_F0_MOD 0x03
> +#define MASK_NCO_F0_MOD_42MHZ 0x00
> +#define MASK_NCO_F0_MOD_27MHZ 0x01
> +
> +#define PK_INT_MODE 0x8709
> +#define MASK_ISRC2_INT_MODE 0x80
> +#define MASK_ISRC_INT_MODE 0x40
> +#define MASK_ACP_INT_MODE 0x20
> +#define MASK_VS_INT_MODE 0x10
> +#define MASK_SPD_INT_MODE 0x08
> +#define MASK_MS_INT_MODE 0x04
> +#define MASK_AUD_INT_MODE 0x02
> +#define MASK_AVI_INT_MODE 0x01
> +
> +#define NO_PKT_LIMIT 0x870B
> +#define MASK_NO_ACP_LIMIT 0xf0
> +#define SET_NO_ACP_LIMIT_MS(milliseconds) ((((milliseconds) / 80) << 4) & \
> + MASK_NO_ACP_LIMIT)
> +#define MASK_NO_AVI_LIMIT 0x0f
> +#define SET_NO_AVI_LIMIT_MS(milliseconds) (((milliseconds) / 80) & \
> + MASK_NO_AVI_LIMIT)
> +
> +#define NO_PKT_CLR 0x870C
> +#define MASK_NO_VS_CLR 0x40
> +#define MASK_NO_SPD_CLR 0x20
> +#define MASK_NO_ACP_CLR 0x10
> +#define MASK_NO_AVI_CLR1 0x02
> +#define MASK_NO_AVI_CLR0 0x01
> +
> +#define ERR_PK_LIMIT 0x870D
> +#define NO_PKT_LIMIT2 0x870E
> +#define PK_AVI_0HEAD 0x8710
> +#define PK_AVI_1HEAD 0x8711
> +#define PK_AVI_2HEAD 0x8712
> +#define PK_AVI_0BYTE 0x8713
> +#define PK_AVI_1BYTE 0x8714
> +#define PK_AVI_2BYTE 0x8715
> +#define PK_AVI_3BYTE 0x8716
> +#define PK_AVI_4BYTE 0x8717
> +#define PK_AVI_5BYTE 0x8718
> +#define PK_AVI_6BYTE 0x8719
> +#define PK_AVI_7BYTE 0x871A
> +#define PK_AVI_8BYTE 0x871B
> +#define PK_AVI_9BYTE 0x871C
> +#define PK_AVI_10BYTE 0x871D
> +#define PK_AVI_11BYTE 0x871E
> +#define PK_AVI_12BYTE 0x871F
> +#define PK_AVI_13BYTE 0x8720
> +#define PK_AVI_14BYTE 0x8721
> +#define PK_AVI_15BYTE 0x8722
> +#define PK_AVI_16BYTE 0x8723
> +
> +#define BKSV 0x8800
> +
> +#define BCAPS 0x8840
> +#define MASK_HDMI_RSVD 0x80
> +#define MASK_REPEATER 0x40
> +#define MASK_READY 0x20
> +#define MASK_FASTI2C 0x10
> +#define MASK_1_1_FEA 0x02
> +#define MASK_FAST_REAU 0x01
> +
> +#define BSTATUS1 0x8842
> +#define MASK_MAX_EXCED 0x08
> +
> +#define EDID_RAM 0x8C00
> +#define NO_GDB_LIMIT 0x9007
> +
> +#endif
> diff --git a/include/media/tc358743.h b/include/media/tc358743.h
> new file mode 100644
> index 0000000..c552a65
> --- /dev/null
> +++ b/include/media/tc358743.h
> @@ -0,0 +1,89 @@
> +/*
> + * tc358743 - Toshiba HDMI to CSI-2 bridge
> + *
> + * Copyright 2014 Cisco Systems, Inc. and/or its affiliates. All rights
> + * reserved.
> + *
> + * This program is free software; you may redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + *
> + */
> +
> +/*
> + * References (c = chapter, p = page):
> + * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
> + * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
> + */
> +
> +#ifndef _TC358743_
> +#define _TC358743_
> +
> +enum tc358743_ddc5v_delays {
> + DDC5V_DELAY_0MS,
> + DDC5V_DELAY_50MS,
> + DDC5V_DELAY_100MS,
> + DDC5V_DELAY_200MS,
> +};
> +
> +struct tc358743_platform_data {
> + u32 refclk_hz; /* System clock connected to REFCLK (pin H5) */
> + enum tc358743_ddc5v_delays ddc5v_delay; /* DDC +5V debounce delay */
> + bool enable_hdcp;
> + /*
> + * The FIFO size is 512x32, so Toshiba recommend to set the default FIFO
> + * level to somewhere in the middle (eg. 200), so it can cover speed
> + * mismatches in input and output ports.
> + */
> + u16 fifo_level;
Shouldn't the driver just set this to the recommended value instead of
adding this to the platform data?
> + u16 pll_prd; /* PLLCTL0 */
> + u16 pll_fbd; /*PLLCTL0 */
> +
> + /* CSI
> + * Calculate CSI parameters with REF_02 for the highest resolution your
> + * CSI interface can handle. The driver will adjust the number of CSI
> + * lanes in use according to the pixel clock.
> + */
I assume that REF_02 explains how to set these CSI parameters. But if this
is based on the highest resolution (and/or pixelclock), wouldn't it make
more sense if the platform data sets those higher level parameters and
leaves it to this driver to calculate the CSI parameters?
Now every bridge driver that want to use this driver has to do the
calculation.
> + u32 bps_pr_lane;
> + u32 lineinitcnt;
> + u32 lptxtimecnt;
> + u32 tclk_headercnt;
> + u32 tclk_trailcnt;
> + u32 ths_headercnt;
> + u32 twakeup;
> + u32 tclk_postcnt;
> + u32 ths_trailcnt;
> + u32 hstxvregcnt;
> +
> + /* HDMI PHY */
> + u8 phy_auto_rst; /* PHY_CTL2, default = 0 */
> + u8 hdmi_det_v; /* HDMI_DET, default = 0 */
> + u8 h_pi_rst; /* HV_RST, default = 0 */
> + u8 v_pi_rst; /* HV_RST, default = 0 */
> +};
> +
> +enum tc358743_cable_connection {
> + TC358743_CABLE_PLUGGED,
> + TC358743_CABLE_UNPLUGGED,
> +};
Unused?
> +
> +/* notify events */
> +#define TC358743_FMT_CHANGE 1
> +
> +/* ioctls */
> +#define TC358743_CSI_RESET _IO('a', 1)
Document this ioctl here.
> +
> +/* custom controls */
> +#define TC358743_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC358743_BASE + 0)
> +#define TC358743_CID_AUDIO_PRESENT (V4L2_CID_USER_TC358743_BASE + 1)
Document these controls here.
Regards,
Hans
> +
> +#endif
> diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
> index 661f119..1bee69c 100644
> --- a/include/uapi/linux/v4l2-controls.h
> +++ b/include/uapi/linux/v4l2-controls.h
> @@ -170,6 +170,10 @@ enum v4l2_colorfx {
> * We reserve 16 controls for this driver. */
> #define V4L2_CID_USER_SAA7134_BASE (V4L2_CID_USER_BASE + 0x1060)
>
> +/* The base for the tc358743 driver controls.
> + * We reserve 16 controls for this driver. */
> +#define V4L2_CID_USER_TC358743_BASE (V4L2_CID_USER_BASE + 0x1070)
> +
> /* MPEG-class control IDs */
> /* The MPEG controls are applicable to all codec controls
> * and the 'MPEG' part of the define is historical */
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RFC v01] Driver for Toshiba TC358743 CSI-2 to HDMI bridge
2014-12-15 18:21 [RFC v01] Driver for Toshiba TC358743 CSI-2 to HDMI bridge matrandg
2014-12-17 10:32 ` Hans Verkuil
@ 2015-01-08 17:12 ` Philipp Zabel
2015-01-09 7:50 ` Mats Randgaard (matrandg)
2015-02-17 8:50 ` Philipp Zabel
2 siblings, 1 reply; 7+ messages in thread
From: Philipp Zabel @ 2015-01-08 17:12 UTC (permalink / raw)
To: matrandg; +Cc: linux-media, hansverk
Hi Mats,
Am Montag, den 15.12.2014, 19:21 +0100 schrieb matrandg@cisco.com:
> From: Mats Randgaard <matrandg@cisco.com>
>
> The driver is tested on our hardware and all the implemented features
> works as expected.
>
> Missing features:
> - CEC support
> - HDCP repeater support
> - IR support
>
> Signed-off-by: Mats Randgaard <matrandg@cisco.com>
> ---
> MAINTAINERS | 6 +
> drivers/media/i2c/Kconfig | 12 +
> drivers/media/i2c/Makefile | 1 +
> drivers/media/i2c/tc358743.c | 1768 ++++++++++++++++++++++++++++++++++++
> drivers/media/i2c/tc358743_regs.h | 670 ++++++++++++++
> include/media/tc358743.h | 89 ++
> include/uapi/linux/v4l2-controls.h | 4 +
> 7 files changed, 2550 insertions(+)
> create mode 100644 drivers/media/i2c/tc358743.c
> create mode 100644 drivers/media/i2c/tc358743_regs.h
> create mode 100644 include/media/tc358743.h
>
[...]
> diff --git a/drivers/media/i2c/tc358743.c b/drivers/media/i2c/tc358743.c
> new file mode 100644
> index 0000000..a86cbe0
> --- /dev/null
> +++ b/drivers/media/i2c/tc358743.c
[...]
> +/* --------------- CUSTOM CTRLS --------------- */
> +
> +static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
> + .id = TC358743_CID_AUDIO_SAMPLING_RATE,
> + .name = "Audio sampling rate",
> + .type = V4L2_CTRL_TYPE_INTEGER,
> + .min = 0,
> + .max = 768000,
> + .step = 1,
> + .def = 0,
> + .flags = V4L2_CTRL_FLAG_READ_ONLY,
> +};
> +
> +static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
> + .id = TC358743_CID_AUDIO_PRESENT,
> + .name = "Audio present",
> + .type = V4L2_CTRL_TYPE_BOOLEAN,
If I don't add
+ .max = 1,
+ .step = 1,
here, I get -ERANGE from v4l2_ctrl_new_custom for this control.
regards
Philipp
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RFC v01] Driver for Toshiba TC358743 CSI-2 to HDMI bridge
2015-01-08 17:12 ` Philipp Zabel
@ 2015-01-09 7:50 ` Mats Randgaard (matrandg)
0 siblings, 0 replies; 7+ messages in thread
From: Mats Randgaard (matrandg) @ 2015-01-09 7:50 UTC (permalink / raw)
To: Philipp Zabel; +Cc: linux-media, hansverk
Thanks for testing the driver!
On 01/08/2015 06:12 PM, Philipp Zabel wrote:
> Hi Mats,
>
> Am Montag, den 15.12.2014, 19:21 +0100 schrieb matrandg@cisco.com:
>> From: Mats Randgaard <matrandg@cisco.com>
>>
>> The driver is tested on our hardware and all the implemented features
>> works as expected.
>>
>> Missing features:
>> - CEC support
>> - HDCP repeater support
>> - IR support
>>
>> Signed-off-by: Mats Randgaard <matrandg@cisco.com>
>> ---
>> MAINTAINERS | 6 +
>> drivers/media/i2c/Kconfig | 12 +
>> drivers/media/i2c/Makefile | 1 +
>> drivers/media/i2c/tc358743.c | 1768 ++++++++++++++++++++++++++++++++++++
>> drivers/media/i2c/tc358743_regs.h | 670 ++++++++++++++
>> include/media/tc358743.h | 89 ++
>> include/uapi/linux/v4l2-controls.h | 4 +
>> 7 files changed, 2550 insertions(+)
>> create mode 100644 drivers/media/i2c/tc358743.c
>> create mode 100644 drivers/media/i2c/tc358743_regs.h
>> create mode 100644 include/media/tc358743.h
>>
> [...]
>> diff --git a/drivers/media/i2c/tc358743.c b/drivers/media/i2c/tc358743.c
>> new file mode 100644
>> index 0000000..a86cbe0
>> --- /dev/null
>> +++ b/drivers/media/i2c/tc358743.c
> [...]
>> +/* --------------- CUSTOM CTRLS --------------- */
>> +
>> +static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
>> + .id = TC358743_CID_AUDIO_SAMPLING_RATE,
>> + .name = "Audio sampling rate",
>> + .type = V4L2_CTRL_TYPE_INTEGER,
>> + .min = 0,
>> + .max = 768000,
>> + .step = 1,
>> + .def = 0,
>> + .flags = V4L2_CTRL_FLAG_READ_ONLY,
>> +};
>> +
>> +static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
>> + .id = TC358743_CID_AUDIO_PRESENT,
>> + .name = "Audio present",
>> + .type = V4L2_CTRL_TYPE_BOOLEAN,
> If I don't add
> + .max = 1,
> + .step = 1,
> here, I get -ERANGE from v4l2_ctrl_new_custom for this control.
The product I use for testing of this driver has a really old kernel
where this validation of the boolean controls is missing. I'll fix this
in the next revision of this driver.
Thanks,
Mats Randgaard
>
> regards
> Philipp
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RFC v01] Driver for Toshiba TC358743 CSI-2 to HDMI bridge
2014-12-15 18:21 [RFC v01] Driver for Toshiba TC358743 CSI-2 to HDMI bridge matrandg
2014-12-17 10:32 ` Hans Verkuil
2015-01-08 17:12 ` Philipp Zabel
@ 2015-02-17 8:50 ` Philipp Zabel
2015-02-17 15:53 ` Mats Randgaard (matrandg)
2 siblings, 1 reply; 7+ messages in thread
From: Philipp Zabel @ 2015-02-17 8:50 UTC (permalink / raw)
To: matrandg; +Cc: linux-media, hansverk
Hi Mats,
Am Montag, den 15.12.2014, 19:21 +0100 schrieb matrandg@cisco.com:
[...]
> +static void tc358743_set_pll(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct tc358743_platform_data *pdata = &state->pdata;
> + u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
> + u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
> + SET_PLL_FBD(pdata->pll_fbd);
> +
> + v4l2_dbg(2, debug, sd, "%s:\n", __func__);
> +
> + /* Only rewrite when needed, since rewriting triggers another format
> + * change event. */
> + if (pllctl0 != pllctl0_new) {
> + u32 hsck = (pdata->refclk_hz * pdata->pll_prd) / pdata->pll_fbd;
This is the wrong way around. refclk_hz is divided by pll_prd to get the
PLL input clock. The PLL then multiplies by pll_fbd. Example:
refclk_hz = 27000000, pll_prd = 4, pll_fbd = 88
--> hsck = refclk_hz / pll_prd * pll_fbd = 594 MHz, pll_frs should be 0.
[...]
> +static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct v4l2_bt_timings *bt = &state->timings.bt;
> + u32 bits_pr_pixel =
> + (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
> + u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
I think this calculation should include the blanking intervals.
> +static void tc358743_set_csi(struct v4l2_subdev *sd)
> +{
> + struct tc358743_state *state = to_state(sd);
> + struct tc358743_platform_data *pdata = &state->pdata;
> + unsigned lanes = tc358743_num_csi_lanes_needed(sd);
> +
> + v4l2_dbg(3, debug, sd, "%s:\n", __func__);
> +
> + tc358743_reset(sd, MASK_CTXRST);
> +
> + if (lanes < 1)
> + i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
> + if (lanes < 1)
> + i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
> + if (lanes < 2)
> + i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
> + if (lanes < 3)
> + i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
> + if (lanes < 4)
> + i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
> +
> + i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
> + i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
> + i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
> + i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
> + i2c_wr32(sd, TWAKEUP, pdata->twakeup);
> + i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
> + i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
> +
> + i2c_wr32(sd, HSTXVREGEN,
> + ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
> + ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
> + ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
> + ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
> + ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
> +
> + i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
Since anything below can't be undone without pulling CTXRST, I propose
to split tc358743_set_csi into tc358743_set_csi (above) and
tc358743_start_csi (below).
To make this driver work with the Synopsys DesignWare MIPI CSI-2 Host
Controller, there needs to be a time when the lanes are in stop state
first, so the host can synchronize. I'd then like to call start_csi in
s_stream only.
> + i2c_wr32(sd, STARTCNTRL, MASK_START);
> + i2c_wr32(sd, CSI_START, MASK_STRT);
> +
> + i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
> + MASK_ADDRESS_CSI_CONTROL |
> + MASK_CSI_MODE |
> + MASK_TXHSMD |
> + ((lanes == 4) ? MASK_NOL_4 :
> + (lanes == 3) ? MASK_NOL_3 :
> + (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
> +
> + i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
> + MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
> + MASK_WCER | MASK_INER);
> +
> + i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
> + MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
> +
> + i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
> + MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
> +}
[...]
regards
Philipp
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RFC v01] Driver for Toshiba TC358743 CSI-2 to HDMI bridge
2015-02-17 8:50 ` Philipp Zabel
@ 2015-02-17 15:53 ` Mats Randgaard (matrandg)
2015-02-18 17:00 ` Philipp Zabel
0 siblings, 1 reply; 7+ messages in thread
From: Mats Randgaard (matrandg) @ 2015-02-17 15:53 UTC (permalink / raw)
To: Philipp Zabel; +Cc: linux-media, hansverk
Thank you again for testing this driver!
I am sorry I haven't had time to prepare a second RFC for this driver,
but I will try to do that as soon as possible.
On 02/17/2015 09:50 AM, Philipp Zabel wrote:
> Hi Mats,
>
> Am Montag, den 15.12.2014, 19:21 +0100 schrieb matrandg@cisco.com:
> [...]
>> +static void tc358743_set_pll(struct v4l2_subdev *sd)
>> +{
>> + struct tc358743_state *state = to_state(sd);
>> + struct tc358743_platform_data *pdata = &state->pdata;
>> + u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
>> + u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
>> + SET_PLL_FBD(pdata->pll_fbd);
>> +
>> + v4l2_dbg(2, debug, sd, "%s:\n", __func__);
>> +
>> + /* Only rewrite when needed, since rewriting triggers another format
>> + * change event. */
>> + if (pllctl0 != pllctl0_new) {
>> + u32 hsck = (pdata->refclk_hz * pdata->pll_prd) / pdata->pll_fbd;
> This is the wrong way around. refclk_hz is divided by pll_prd to get the
> PLL input clock. The PLL then multiplies by pll_fbd. Example:
>
> refclk_hz = 27000000, pll_prd = 4, pll_fbd = 88
> --> hsck = refclk_hz / pll_prd * pll_fbd = 594 MHz, pll_frs should be 0.
Yes, you are right, and there was a bug in SET_PLL_FRS() as well, so the
bits where always set to zero. I will fix that!
> [...]
>> +static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
>> +{
>> + struct tc358743_state *state = to_state(sd);
>> + struct v4l2_bt_timings *bt = &state->timings.bt;
>> + u32 bits_pr_pixel =
>> + (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
>> + u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
> I think this calculation should include the blanking intervals.
As far as I understand is only the active video from the HDMI interface
transferred on the CSI interface, so I think this calculation is
correct. We transfer 1080p60 video on four lanes with 823.5 Mbps/lane,
which would not have been possible if the blanking should have been
transferred as well ((2200 * 1125 * 60 * 24) bps / 823.5 Mbps/lane =
4.33 lanes.
>> +static void tc358743_set_csi(struct v4l2_subdev *sd)
>> +{
>> + struct tc358743_state *state = to_state(sd);
>> + struct tc358743_platform_data *pdata = &state->pdata;
>> + unsigned lanes = tc358743_num_csi_lanes_needed(sd);
>> +
>> + v4l2_dbg(3, debug, sd, "%s:\n", __func__);
>> +
>> + tc358743_reset(sd, MASK_CTXRST);
>> +
>> + if (lanes < 1)
>> + i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
>> + if (lanes < 1)
>> + i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
>> + if (lanes < 2)
>> + i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
>> + if (lanes < 3)
>> + i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
>> + if (lanes < 4)
>> + i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
>> +
>> + i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
>> + i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
>> + i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
>> + i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
>> + i2c_wr32(sd, TWAKEUP, pdata->twakeup);
>> + i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
>> + i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
>> +
>> + i2c_wr32(sd, HSTXVREGEN,
>> + ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
>> + ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
>> + ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
>> + ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
>> + ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
>> +
>> + i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
> Since anything below can't be undone without pulling CTXRST, I propose
> to split tc358743_set_csi into tc358743_set_csi (above) and
> tc358743_start_csi (below).
>
> To make this driver work with the Synopsys DesignWare MIPI CSI-2 Host
> Controller, there needs to be a time when the lanes are in stop state
> first, so the host can synchronize. I'd then like to call start_csi in
> s_stream only.
With help from Toshiba we have now implemented start and stop of the CSI
interface without pulling CTXRST. You can see our solution in the next
RFC, and I would appreciate if you could test if that works fine for you
as well!
Regards,
Mats Randgaard
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RFC v01] Driver for Toshiba TC358743 CSI-2 to HDMI bridge
2015-02-17 15:53 ` Mats Randgaard (matrandg)
@ 2015-02-18 17:00 ` Philipp Zabel
0 siblings, 0 replies; 7+ messages in thread
From: Philipp Zabel @ 2015-02-18 17:00 UTC (permalink / raw)
To: Mats Randgaard (matrandg); +Cc: linux-media, hansverk
Hi Mats,
Am Dienstag, den 17.02.2015, 16:53 +0100 schrieb Mats Randgaard
(matrandg):
> > I think this calculation should include the blanking intervals.
>
> As far as I understand is only the active video from the HDMI interface
> transferred on the CSI interface, so I think this calculation is
> correct. We transfer 1080p60 video on four lanes with 823.5 Mbps/lane,
> which would not have been possible if the blanking should have been
> transferred as well ((2200 * 1125 * 60 * 24) bps / 823.5 Mbps/lane =
> 4.33 lanes.
You are right, I confused the "reference" and "minimum" suitable CSI
lane speed fields in REF_02. There ought to be _some_ overhead though?
(1920 * 1080 * 60 * 24) bps = 746.496 Mbps, but REF_02 suggests a
minimum of 820.92 Mbps per lane (reference is 891 Mbps as expected).
[...]
> >> + i2c_wr32(sd, HSTXVREGEN,
> >> + ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
> >> + ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
> >> + ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
> >> + ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
> >> + ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
> >> +
> >> + i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
> > Since anything below can't be undone without pulling CTXRST, I propose
> > to split tc358743_set_csi into tc358743_set_csi (above) and
> > tc358743_start_csi (below).
> >
> > To make this driver work with the Synopsys DesignWare MIPI CSI-2 Host
> > Controller, there needs to be a time when the lanes are in stop state
> > first, so the host can synchronize. I'd then like to call start_csi in
> > s_stream only.
>
> With help from Toshiba we have now implemented start and stop of the CSI
> interface without pulling CTXRST. You can see our solution in the next
> RFC, and I would appreciate if you could test if that works fine for you
> as well!
I'm looking forward to it.
regards
Philipp
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2015-02-18 17:00 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-12-15 18:21 [RFC v01] Driver for Toshiba TC358743 CSI-2 to HDMI bridge matrandg
2014-12-17 10:32 ` Hans Verkuil
2015-01-08 17:12 ` Philipp Zabel
2015-01-09 7:50 ` Mats Randgaard (matrandg)
2015-02-17 8:50 ` Philipp Zabel
2015-02-17 15:53 ` Mats Randgaard (matrandg)
2015-02-18 17:00 ` Philipp Zabel
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