[U-Boot] ot1200: add basic SPL support

[U-Boot] ot1200: add basic SPL support

[Christian Gmeiner]

This patch series add basic SPL support for the ot1200. In future patches
this support will gets extended to support different memory configurations.

[U-Boot] [PATCH 1/7] ot1200: select SUPPORT_SPL

[Christian Gmeiner]

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5eb1d03..5734405 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -663,6 +663,7 @@ config TARGET_TQMA6
 config TARGET_OT1200
 	bool "Bachmann OT1200"
 	select CPU_V7
+	select SUPPORT_SPL
 
 config OMAP34XX
 	bool "OMAP34XX SoC"
-- 
2.1.0

[U-Boot] [PATCH 2/7] ot1200: make use of imx_ddr_size(..)

[Christian Gmeiner]

To support different ddr3 memory sizes we should start using
imx_ddr_size(..) instead of the define PHYS_SDRAM_SIZE.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
---
 board/bachmann/ot1200/ot1200.c | 3 ++-
 include/configs/ot1200.h       | 1 -
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index 93f3d65..039e858 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -16,6 +16,7 @@
 #include <asm/imx-common/mxc_i2c.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <netdev.h>
@@ -46,7 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+	gd->ram_size = imx_ddr_size();
 
 	return 0;
 }
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 255c933..97ee664 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -159,7 +159,6 @@
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
-#define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-- 
2.1.0

[U-Boot] [PATCH 3/7] ot1200: move ccgr and gpr init to c functions

[Christian Gmeiner]

We need this way for SPL boot.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
---
 board/bachmann/ot1200/mx6q_4x_mt41j128.cfg | 14 --------------
 board/bachmann/ot1200/ot1200.c             | 28 ++++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 14 deletions(-)

diff --git a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
index bb6c60b..c25f99d 100644
--- a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
+++ b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
@@ -142,20 +142,6 @@ DATA 4 0x021b48b8 0x00000800
 DATA 4 0x021b001c 0x00000000
 DATA 4 0x021b0404 0x00011006
 
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
 
 /*
  * Setup CCM_CCOSR register as follows:
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index 039e858..6b6c1a3 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
@@ -119,8 +120,35 @@ static void setup_iomux_features(void)
 		ARRAY_SIZE(feature_pads));
 }
 
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	writel(0x007F007F, &iomux->gpr[6]);
+	writel(0x007F007F, &iomux->gpr[7]);
+}
+
 int board_early_init_f(void)
 {
+	ccgr_init();
+	gpr_init();
+
 	setup_iomux_uart();
 	setup_iomux_spi();
 	setup_iomux_features();
-- 
2.1.0

[U-Boot] [PATCH 4/7] ot1200: enable spi clock directly in ccgr_init(..)

[Christian Gmeiner]

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
---
 board/bachmann/ot1200/ot1200.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index 6b6c1a3..e434ed9 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -125,7 +125,7 @@ static void ccgr_init(void)
 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
 	writel(0x00C03F3F, &ccm->CCGR0);
-	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0030FC33, &ccm->CCGR1);
 	writel(0x0FFFC000, &ccm->CCGR2);
 	writel(0x3FF00000, &ccm->CCGR3);
 	writel(0x00FFF300, &ccm->CCGR4);
@@ -319,9 +319,6 @@ int board_init(void)
 
 	leds_on();
 
-	/* enable ecspi3 clocks */
-	enable_cspi_clock(1, 2);
-
 #ifdef CONFIG_CMD_SATA
 	setup_sata();
 #endif
-- 
2.1.0

[U-Boot] [PATCH 5/7] ot1200: add SPL configuration

[Christian Gmeiner]

We will only support loading u-boot.img from SPI flash stored
at the offset of 64k.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
---
 include/configs/ot1200.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 97ee664..c061e93 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -108,6 +108,16 @@
 #endif
 
 
+/* SPL */
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     (64 * 1024)
+#define CONFIG_SPL_SPI_LOAD
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
-- 
2.1.0

[U-Boot] [PATCH 6/7] ot1200: add basic SPL support

[Christian Gmeiner]

Currently we only support the Micron MT41K128M16JT-125 ddr3 chip.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
---
 board/bachmann/ot1200/Makefile     |   4 +
 board/bachmann/ot1200/ot1200_spl.c | 162 +++++++++++++++++++++++++++++++++++++
 2 files changed, 166 insertions(+)
 create mode 100644 board/bachmann/ot1200/ot1200_spl.c

diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile
index 1bd42e8..9e50bfe 100644
--- a/board/bachmann/ot1200/Makefile
+++ b/board/bachmann/ot1200/Makefile
@@ -6,4 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+ifdef CONFIG_SPL_BUILD
+obj-y  := ot1200.o ot1200_spl.o
+else
 obj-y  := ot1200.o
+endif
diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c
new file mode 100644
index 0000000..9c77fd3
--- /dev/null
+++ b/board/bachmann/ot1200/ot1200_spl.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2015, Bachmann electronic GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
+	.dram_sdclk_0   = 0x00000028,
+	.dram_sdclk_1   = 0x00000028,
+	.dram_cas       = 0x00000028,
+	.dram_ras       = 0x00000028,
+	.dram_reset     = 0x00000028,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0    = 0x00003000,
+	.dram_sdcke1    = 0x00003000,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2	    = 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 48 ohm */
+	.dram_sdodt0    = 0x00000028,
+	.dram_sdodt1    = 0x00000028,
+	/* SDQS[0:7]: Differential input, 48 ohm */
+	.dram_sdqs0     = 0x00000028,
+	.dram_sdqs1     = 0x00000028,
+	.dram_sdqs2     = 0x00000028,
+	.dram_sdqs3     = 0x00000028,
+	.dram_sdqs4     = 0x00000028,
+	.dram_sdqs5     = 0x00000028,
+	.dram_sdqs6     = 0x00000028,
+	.dram_sdqs7     = 0x00000028,
+	/* DQM[0:7]: Differential input, 48 ohm */
+	.dram_dqm0      = 0x00000028,
+	.dram_dqm1      = 0x00000028,
+	.dram_dqm2      = 0x00000028,
+	.dram_dqm3      = 0x00000028,
+	.dram_dqm4      = 0x00000028,
+	.dram_dqm5      = 0x00000028,
+	.dram_dqm6      = 0x00000028,
+	.dram_dqm7      = 0x00000028,
+};
+
+/* Configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
+	/* DDR3 */
+	.grp_ddr_type    = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	/* Disable DDR pullups */
+	.grp_ddrpke      = 0x00000000,
+	/* ADDR[00:16], SDBA[0:1]: 48 ohm */
+	.grp_addds       = 0x00000028,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */
+	.grp_ctlds       = 0x00000028,
+	/* DATA[00:63]: Differential input, 48 ohm */
+	.grp_ddrmode     = 0x00020000,
+	.grp_b0ds        = 0x00000028,
+	.grp_b1ds        = 0x00000028,
+	.grp_b2ds        = 0x00000028,
+	.grp_b3ds        = 0x00000028,
+	.grp_b4ds        = 0x00000028,
+	.grp_b5ds        = 0x00000028,
+	.grp_b6ds        = 0x00000028,
+	.grp_b7ds        = 0x00000028,
+};
+
+static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
+	/* Width of data bus: 0=16, 1=32, 2=64 */
+	.dsize      = 2,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density = 32, /* 32Gb per CS */
+	/* Single chip select */
+	.ncs        = 1,
+	.cs1_mirror = 0,	/* war 0 */
+	.rtt_wr     = 1,	/* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
+	.rtt_nom    = 1,	/* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
+	.walat      = 1,	/* Write additional latency */
+	.ralat      = 5,	/* Read additional latency */
+	.mif3_mode  = 3,	/* Command prediction working mode */
+	.bi_on      = 1,	/* Bank interleaving enabled */	/* war 1 */
+	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+};
+
+/* MT41K128M16JT-125 */
+static struct mx6_ddr3_cfg micron_2gib_1600 = {
+	.mem_speed = 1600,
+	.density   = 2,
+	.width     = 16,
+	.banks     = 8,
+	.rowaddr   = 14,
+	.coladdr   = 10,
+	.pagesz    = 2,
+	.trcd      = 1375,
+	.trcmin    = 4875,
+	.trasmin   = 3500,
+	.SRT       = 1,
+};
+
+static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x00260025,
+	.p0_mpwldectrl1 = 0x00270021,
+	.p1_mpwldectrl0 = 0x00180034,
+	.p1_mpwldectrl1 = 0x00180024,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0   = 0x04380344,
+	.p0_mpdgctrl1   = 0x0330032C,
+	.p1_mpdgctrl0   = 0x0338033C,
+	.p1_mpdgctrl1   = 0x032C0300,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl   = 0x3C2E3238,
+	.p1_mprddlctl   = 0x3A2E303C,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl   = 0x36384036,
+	.p1_mpwrdlctl   = 0x442E4438,
+};
+
+static void ot1200_spl_dram_init(void)
+{
+	mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs);
+	mx6_dram_cfg(&ot1200_ddr_sysinfo, &micron_2gib_1600_mmdc_calib,
+		     &micron_2gib_1600);
+}
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* configure MMDC for SDRAM width/size and per-model calibration */
+	ot1200_spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
-- 
2.1.0

[U-Boot] [PATCH 7/7] ot1200: add ot1200_spl_defconfig file

[Christian Gmeiner]

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
---
 configs/ot1200_spl_defconfig | 4 ++++
 1 file changed, 4 insertions(+)
 create mode 100644 configs/ot1200_spl_defconfig

diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
new file mode 100644
index 0000000..74ebf85
--- /dev/null
+++ b/configs/ot1200_spl_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_OT1200=y
\ No newline at end of file
-- 
2.1.0

[U-Boot] [PATCH 7/7] ot1200: add ot1200_spl_defconfig file

[Stefano Babic]

Hi Christian,

On 19/01/2015 17:26, Christian Gmeiner wrote:
> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> ---
>  configs/ot1200_spl_defconfig | 4 ++++
>  1 file changed, 4 insertions(+)
>  create mode 100644 configs/ot1200_spl_defconfig
> 
> diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
> new file mode 100644
> index 0000000..74ebf85
> --- /dev/null
> +++ b/configs/ot1200_spl_defconfig
> @@ -0,0 +1,4 @@
> +CONFIG_SPL=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
> ++S:CONFIG_ARM=y
> ++S:CONFIG_TARGET_OT1200=y
> \ No newline at end of file
> 

The series looks ok to me - ready to be merged.

Acked-by: Stefano Babic <sbabic@denx.de>#

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 1/7] ot1200: select SUPPORT_SPL

[Stefano Babic]

On 19/01/2015 17:26, Christian Gmeiner wrote:
> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> ---
>  arch/arm/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5eb1d03..5734405 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -663,6 +663,7 @@ config TARGET_TQMA6
>  config TARGET_OT1200
>  	bool "Bachmann OT1200"
>  	select CPU_V7
> +	select SUPPORT_SPL
>  
>  config OMAP34XX
>  	bool "OMAP34XX SoC"
> 

Whole series merged into u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================