From: Wenyou Yang <wenyou.yang@atmel.com> To: <nicolas.ferre@atmel.com>, <linux@arm.linux.org.uk> Cc: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <alexandre.belloni@free-electrons.com>, <sylvain.rochet@finsecur.com>, <peda@axentia.se>, <wenyou.yang@atmel.com> Subject: [PATCH v2 08/12] pm: at91: rename file name: pm_slowclock.S -->pm_suspend.S Date: Mon, 26 Jan 2015 17:42:54 +0800 [thread overview] Message-ID: <1422265374-23273-1-git-send-email-wenyou.yang@atmel.com> (raw) In-Reply-To: <1422265005-22937-1-git-send-email-wenyou.yang@atmel.com> Because the sram function is used for the suspend to standby mode as well, more than suspend to memory, so renaming is more elegant. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- arch/arm/mach-at91/Makefile | 2 +- arch/arm/mach-at91/pm_slowclock.S | 281 ------------------------------------- arch/arm/mach-at91/pm_suspend.S | 281 +++++++++++++++++++++++++++++++++++++ 3 files changed, 282 insertions(+), 282 deletions(-) delete mode 100644 arch/arm/mach-at91/pm_slowclock.S create mode 100644 arch/arm/mach-at91/pm_suspend.S diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 13dd3e6..aba208f 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -27,7 +27,7 @@ obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o # Power Management obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM) += pm_slowclock.o +obj-$(CONFIG_PM) += pm_suspend.o ifeq ($(CONFIG_PM_DEBUG),y) CFLAGS_pm.o += -DDEBUG diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S deleted file mode 100644 index f56d114..0000000 --- a/arch/arm/mach-at91/pm_slowclock.S +++ /dev/null @@ -1,281 +0,0 @@ -/* - * arch/arm/mach-at91/pm_slow_clock.S - * - * Copyright (C) 2006 Savin Zlobec - * - * AT91SAM9 support: - * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include <linux/linkage.h> -#include <linux/clk/at91_pmc.h> -#include <mach/hardware.h> -#include <mach/at91_ramc.h> - -#include "pm.h" - -pmc .req r0 -sdramc .req r1 -ramc1 .req r2 -memctrl .req r3 -tmp1 .req r4 -tmp2 .req r5 -mode .req r6 - -/* - * Wait until master clock is ready (after switching master clock source) - */ - .macro wait_mckrdy -1: ldr tmp1, [pmc, #AT91_PMC_SR] - tst tmp1, #AT91_PMC_MCKRDY - beq 1b - .endm - -/* - * Wait until master oscillator has stabilized. - */ - .macro wait_moscrdy -1: ldr tmp1, [pmc, #AT91_PMC_SR] - tst tmp1, #AT91_PMC_MOSCS - beq 1b - .endm - -/* - * Wait until PLLA has locked. - */ - .macro wait_pllalock -1: ldr tmp1, [pmc, #AT91_PMC_SR] - tst tmp1, #AT91_PMC_LOCKA - beq 1b - .endm - - .text - -/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc, - * void __iomem *ramc1, int memctrl) - */ -ENTRY(at91_slow_clock) - /* Save registers on stack */ - stmfd sp!, {r4 - r12, lr} - - /* - * Register usage: - * R0 = Base address of AT91_PMC - * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS) - * R2 = Base address of second RAM Controller or 0 if not present - * R3 = Memory controller - * R4 = temporary register - * R5 = temporary register - */ - - /* Drain write buffer */ - mov tmp1, #0 - mcr p15, 0, tmp1, c7, c10, 4 - - mov tmp1, memctrl - mov tmp2, tmp1, lsr#AT91_PM_MODE_OFFSET - and mode, tmp2, #AT91_PM_MODE_MASK - - mov tmp1, memctrl - and memctrl, tmp1, #AT91_PM_MEMCTRL_MASK - - cmp memctrl, #AT91_MEMCTRL_MC - bne ddr_sr_enable - - /* - * at91rm9200 Memory controller - */ - /* Put SDRAM in self-refresh mode */ - mov tmp1, #1 - str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR] - b sdr_sr_done - - /* - * DDRSDR Memory controller - */ -ddr_sr_enable: - cmp memctrl, #AT91_MEMCTRL_DDRSDR - bne sdr_sr_enable - - /* LPDDR1 --> force DDR2 mode during self-refresh */ - ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR] - str tmp1, .saved_sam9_mdr - bic tmp1, tmp1, #~AT91_DDRSDRC_MD - cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR - ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR] - biceq tmp1, tmp1, #AT91_DDRSDRC_MD - orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2 - streq tmp1, [sdramc, #AT91_DDRSDRC_MDR] - - /* prepare for DDRAM self-refresh mode */ - ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR] - str tmp1, .saved_sam9_lpr - bic tmp1, #AT91_DDRSDRC_LPCB - orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH - - /* figure out if we use the second ram controller */ - cmp ramc1, #0 - beq ddr_no_2nd_ctrl - - ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR] - str tmp2, .saved_sam9_mdr1 - bic tmp2, tmp2, #~AT91_DDRSDRC_MD - cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR - ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR] - biceq tmp2, tmp2, #AT91_DDRSDRC_MD - orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2 - streq tmp2, [ramc1, #AT91_DDRSDRC_MDR] - - ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR] - str tmp2, .saved_sam9_lpr1 - bic tmp2, #AT91_DDRSDRC_LPCB - orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH - - /* Enable DDRAM self-refresh mode */ - str tmp2, [ramc1, #AT91_DDRSDRC_LPR] -ddr_no_2nd_ctrl: - str tmp1, [sdramc, #AT91_DDRSDRC_LPR] - - b sdr_sr_done - - /* - * SDRAMC Memory controller - */ -sdr_sr_enable: - /* Enable SDRAM self-refresh mode */ - ldr tmp1, [sdramc, #AT91_SDRAMC_LPR] - str tmp1, .saved_sam9_lpr - - bic tmp1, #AT91_SDRAMC_LPCB - orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH - str tmp1, [sdramc, #AT91_SDRAMC_LPR] - -sdr_sr_done: - tst mode, #AT91_PM_SLOW_CLOCK - beq skip_disable_main_clock - - /* Save Master clock setting */ - ldr tmp1, [pmc, #AT91_PMC_MCKR] - str tmp1, .saved_mckr - - /* - * Set the Master clock source to slow clock - */ - bic tmp1, tmp1, #AT91_PMC_CSS - str tmp1, [pmc, #AT91_PMC_MCKR] - - wait_mckrdy - - /* Save PLLA setting and disable it */ - ldr tmp1, [pmc, #AT91_CKGR_PLLAR] - str tmp1, .saved_pllar - - mov tmp1, #AT91_PMC_PLLCOUNT - orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ - str tmp1, [pmc, #AT91_CKGR_PLLAR] - - /* Turn off the main oscillator */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] - bic tmp1, tmp1, #AT91_PMC_MOSCEN - str tmp1, [pmc, #AT91_CKGR_MOR] - -skip_disable_main_clock: - /* Wait for interrupt */ - mcr p15, 0, tmp1, c7, c0, 4 - - tst mode, #AT91_PM_SLOW_CLOCK - beq skip_enable_main_clock - - /* Turn on the main oscillator */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] - orr tmp1, tmp1, #AT91_PMC_MOSCEN - str tmp1, [pmc, #AT91_CKGR_MOR] - - wait_moscrdy - - /* Restore PLLA setting */ - ldr tmp1, .saved_pllar - str tmp1, [pmc, #AT91_CKGR_PLLAR] - - tst tmp1, #(AT91_PMC_MUL & 0xff0000) - bne 3f - tst tmp1, #(AT91_PMC_MUL & ~0xff0000) - beq 4f -3: - wait_pllalock -4: - - /* - * Restore master clock setting - */ -2: ldr tmp1, .saved_mckr - str tmp1, [pmc, #AT91_PMC_MCKR] - - wait_mckrdy - -skip_enable_main_clock: - /* - * at91rm9200 Memory controller - * Do nothing - self-refresh is automatically disabled. - */ - cmp memctrl, #AT91_MEMCTRL_MC - beq ram_restored - - /* - * DDRSDR Memory controller - */ - cmp memctrl, #AT91_MEMCTRL_DDRSDR - bne sdr_en_restore - /* Restore MDR in case of LPDDR1 */ - ldr tmp1, .saved_sam9_mdr - str tmp1, [sdramc, #AT91_DDRSDRC_MDR] - /* Restore LPR on AT91 with DDRAM */ - ldr tmp1, .saved_sam9_lpr - str tmp1, [sdramc, #AT91_DDRSDRC_LPR] - - /* if we use the second ram controller */ - cmp ramc1, #0 - ldrne tmp2, .saved_sam9_mdr1 - strne tmp2, [ramc1, #AT91_DDRSDRC_MDR] - ldrne tmp2, .saved_sam9_lpr1 - strne tmp2, [ramc1, #AT91_DDRSDRC_LPR] - - b ram_restored - - /* - * SDRAMC Memory controller - */ -sdr_en_restore: - /* Restore LPR on AT91 with SDRAM */ - ldr tmp1, .saved_sam9_lpr - str tmp1, [sdramc, #AT91_SDRAMC_LPR] - -ram_restored: - /* Restore registers, and return */ - ldmfd sp!, {r4 - r12, pc} - - -.saved_mckr: - .word 0 - -.saved_pllar: - .word 0 - -.saved_sam9_lpr: - .word 0 - -.saved_sam9_lpr1: - .word 0 - -.saved_sam9_mdr: - .word 0 - -.saved_sam9_mdr1: - .word 0 - -ENTRY(at91_slow_clock_sz) - .word .-at91_slow_clock diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S new file mode 100644 index 0000000..8edbad0 --- /dev/null +++ b/arch/arm/mach-at91/pm_suspend.S @@ -0,0 +1,281 @@ +/* + * arch/arm/mach-at91/pm_suspend.S + * + * Copyright (C) 2006 Savin Zlobec + * + * AT91SAM9 support: + * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include <linux/linkage.h> +#include <linux/clk/at91_pmc.h> +#include <mach/hardware.h> +#include <mach/at91_ramc.h> + +#include "pm.h" + +pmc .req r0 +sdramc .req r1 +ramc1 .req r2 +memctrl .req r3 +tmp1 .req r4 +tmp2 .req r5 +mode .req r6 + +/* + * Wait until master clock is ready (after switching master clock source) + */ + .macro wait_mckrdy +1: ldr tmp1, [pmc, #AT91_PMC_SR] + tst tmp1, #AT91_PMC_MCKRDY + beq 1b + .endm + +/* + * Wait until master oscillator has stabilized. + */ + .macro wait_moscrdy +1: ldr tmp1, [pmc, #AT91_PMC_SR] + tst tmp1, #AT91_PMC_MOSCS + beq 1b + .endm + +/* + * Wait until PLLA has locked. + */ + .macro wait_pllalock +1: ldr tmp1, [pmc, #AT91_PMC_SR] + tst tmp1, #AT91_PMC_LOCKA + beq 1b + .endm + + .text + +/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc, + * void __iomem *ramc1, int memctrl) + */ +ENTRY(at91_slow_clock) + /* Save registers on stack */ + stmfd sp!, {r4 - r12, lr} + + /* + * Register usage: + * R0 = Base address of AT91_PMC + * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS) + * R2 = Base address of second RAM Controller or 0 if not present + * R3 = Memory controller + * R4 = temporary register + * R5 = temporary register + */ + + /* Drain write buffer */ + mov tmp1, #0 + mcr p15, 0, tmp1, c7, c10, 4 + + mov tmp1, memctrl + mov tmp2, tmp1, lsr#AT91_PM_MODE_OFFSET + and mode, tmp2, #AT91_PM_MODE_MASK + + mov tmp1, memctrl + and memctrl, tmp1, #AT91_PM_MEMCTRL_MASK + + cmp memctrl, #AT91_MEMCTRL_MC + bne ddr_sr_enable + + /* + * at91rm9200 Memory controller + */ + /* Put SDRAM in self-refresh mode */ + mov tmp1, #1 + str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR] + b sdr_sr_done + + /* + * DDRSDR Memory controller + */ +ddr_sr_enable: + cmp memctrl, #AT91_MEMCTRL_DDRSDR + bne sdr_sr_enable + + /* LPDDR1 --> force DDR2 mode during self-refresh */ + ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR] + str tmp1, .saved_sam9_mdr + bic tmp1, tmp1, #~AT91_DDRSDRC_MD + cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR + ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR] + biceq tmp1, tmp1, #AT91_DDRSDRC_MD + orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2 + streq tmp1, [sdramc, #AT91_DDRSDRC_MDR] + + /* prepare for DDRAM self-refresh mode */ + ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR] + str tmp1, .saved_sam9_lpr + bic tmp1, #AT91_DDRSDRC_LPCB + orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH + + /* figure out if we use the second ram controller */ + cmp ramc1, #0 + beq ddr_no_2nd_ctrl + + ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR] + str tmp2, .saved_sam9_mdr1 + bic tmp2, tmp2, #~AT91_DDRSDRC_MD + cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR + ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR] + biceq tmp2, tmp2, #AT91_DDRSDRC_MD + orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2 + streq tmp2, [ramc1, #AT91_DDRSDRC_MDR] + + ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR] + str tmp2, .saved_sam9_lpr1 + bic tmp2, #AT91_DDRSDRC_LPCB + orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH + + /* Enable DDRAM self-refresh mode */ + str tmp2, [ramc1, #AT91_DDRSDRC_LPR] +ddr_no_2nd_ctrl: + str tmp1, [sdramc, #AT91_DDRSDRC_LPR] + + b sdr_sr_done + + /* + * SDRAMC Memory controller + */ +sdr_sr_enable: + /* Enable SDRAM self-refresh mode */ + ldr tmp1, [sdramc, #AT91_SDRAMC_LPR] + str tmp1, .saved_sam9_lpr + + bic tmp1, #AT91_SDRAMC_LPCB + orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH + str tmp1, [sdramc, #AT91_SDRAMC_LPR] + +sdr_sr_done: + tst mode, #AT91_PM_SLOW_CLOCK + beq skip_disable_main_clock + + /* Save Master clock setting */ + ldr tmp1, [pmc, #AT91_PMC_MCKR] + str tmp1, .saved_mckr + + /* + * Set the Master clock source to slow clock + */ + bic tmp1, tmp1, #AT91_PMC_CSS + str tmp1, [pmc, #AT91_PMC_MCKR] + + wait_mckrdy + + /* Save PLLA setting and disable it */ + ldr tmp1, [pmc, #AT91_CKGR_PLLAR] + str tmp1, .saved_pllar + + mov tmp1, #AT91_PMC_PLLCOUNT + orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ + str tmp1, [pmc, #AT91_CKGR_PLLAR] + + /* Turn off the main oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + bic tmp1, tmp1, #AT91_PMC_MOSCEN + str tmp1, [pmc, #AT91_CKGR_MOR] + +skip_disable_main_clock: + /* Wait for interrupt */ + mcr p15, 0, tmp1, c7, c0, 4 + + tst mode, #AT91_PM_SLOW_CLOCK + beq skip_enable_main_clock + + /* Turn on the main oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + orr tmp1, tmp1, #AT91_PMC_MOSCEN + str tmp1, [pmc, #AT91_CKGR_MOR] + + wait_moscrdy + + /* Restore PLLA setting */ + ldr tmp1, .saved_pllar + str tmp1, [pmc, #AT91_CKGR_PLLAR] + + tst tmp1, #(AT91_PMC_MUL & 0xff0000) + bne 3f + tst tmp1, #(AT91_PMC_MUL & ~0xff0000) + beq 4f +3: + wait_pllalock +4: + + /* + * Restore master clock setting + */ +2: ldr tmp1, .saved_mckr + str tmp1, [pmc, #AT91_PMC_MCKR] + + wait_mckrdy + +skip_enable_main_clock: + /* + * at91rm9200 Memory controller + * Do nothing - self-refresh is automatically disabled. + */ + cmp memctrl, #AT91_MEMCTRL_MC + beq ram_restored + + /* + * DDRSDR Memory controller + */ + cmp memctrl, #AT91_MEMCTRL_DDRSDR + bne sdr_en_restore + /* Restore MDR in case of LPDDR1 */ + ldr tmp1, .saved_sam9_mdr + str tmp1, [sdramc, #AT91_DDRSDRC_MDR] + /* Restore LPR on AT91 with DDRAM */ + ldr tmp1, .saved_sam9_lpr + str tmp1, [sdramc, #AT91_DDRSDRC_LPR] + + /* if we use the second ram controller */ + cmp ramc1, #0 + ldrne tmp2, .saved_sam9_mdr1 + strne tmp2, [ramc1, #AT91_DDRSDRC_MDR] + ldrne tmp2, .saved_sam9_lpr1 + strne tmp2, [ramc1, #AT91_DDRSDRC_LPR] + + b ram_restored + + /* + * SDRAMC Memory controller + */ +sdr_en_restore: + /* Restore LPR on AT91 with SDRAM */ + ldr tmp1, .saved_sam9_lpr + str tmp1, [sdramc, #AT91_SDRAMC_LPR] + +ram_restored: + /* Restore registers, and return */ + ldmfd sp!, {r4 - r12, pc} + + +.saved_mckr: + .word 0 + +.saved_pllar: + .word 0 + +.saved_sam9_lpr: + .word 0 + +.saved_sam9_lpr1: + .word 0 + +.saved_sam9_mdr: + .word 0 + +.saved_sam9_mdr1: + .word 0 + +ENTRY(at91_slow_clock_sz) + .word .-at91_slow_clock -- 1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: wenyou.yang@atmel.com (Wenyou Yang) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 08/12] pm: at91: rename file name: pm_slowclock.S -->pm_suspend.S Date: Mon, 26 Jan 2015 17:42:54 +0800 [thread overview] Message-ID: <1422265374-23273-1-git-send-email-wenyou.yang@atmel.com> (raw) In-Reply-To: <1422265005-22937-1-git-send-email-wenyou.yang@atmel.com> Because the sram function is used for the suspend to standby mode as well, more than suspend to memory, so renaming is more elegant. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- arch/arm/mach-at91/Makefile | 2 +- arch/arm/mach-at91/pm_slowclock.S | 281 ------------------------------------- arch/arm/mach-at91/pm_suspend.S | 281 +++++++++++++++++++++++++++++++++++++ 3 files changed, 282 insertions(+), 282 deletions(-) delete mode 100644 arch/arm/mach-at91/pm_slowclock.S create mode 100644 arch/arm/mach-at91/pm_suspend.S diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 13dd3e6..aba208f 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -27,7 +27,7 @@ obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o # Power Management obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM) += pm_slowclock.o +obj-$(CONFIG_PM) += pm_suspend.o ifeq ($(CONFIG_PM_DEBUG),y) CFLAGS_pm.o += -DDEBUG diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S deleted file mode 100644 index f56d114..0000000 --- a/arch/arm/mach-at91/pm_slowclock.S +++ /dev/null @@ -1,281 +0,0 @@ -/* - * arch/arm/mach-at91/pm_slow_clock.S - * - * Copyright (C) 2006 Savin Zlobec - * - * AT91SAM9 support: - * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include <linux/linkage.h> -#include <linux/clk/at91_pmc.h> -#include <mach/hardware.h> -#include <mach/at91_ramc.h> - -#include "pm.h" - -pmc .req r0 -sdramc .req r1 -ramc1 .req r2 -memctrl .req r3 -tmp1 .req r4 -tmp2 .req r5 -mode .req r6 - -/* - * Wait until master clock is ready (after switching master clock source) - */ - .macro wait_mckrdy -1: ldr tmp1, [pmc, #AT91_PMC_SR] - tst tmp1, #AT91_PMC_MCKRDY - beq 1b - .endm - -/* - * Wait until master oscillator has stabilized. - */ - .macro wait_moscrdy -1: ldr tmp1, [pmc, #AT91_PMC_SR] - tst tmp1, #AT91_PMC_MOSCS - beq 1b - .endm - -/* - * Wait until PLLA has locked. - */ - .macro wait_pllalock -1: ldr tmp1, [pmc, #AT91_PMC_SR] - tst tmp1, #AT91_PMC_LOCKA - beq 1b - .endm - - .text - -/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc, - * void __iomem *ramc1, int memctrl) - */ -ENTRY(at91_slow_clock) - /* Save registers on stack */ - stmfd sp!, {r4 - r12, lr} - - /* - * Register usage: - * R0 = Base address of AT91_PMC - * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS) - * R2 = Base address of second RAM Controller or 0 if not present - * R3 = Memory controller - * R4 = temporary register - * R5 = temporary register - */ - - /* Drain write buffer */ - mov tmp1, #0 - mcr p15, 0, tmp1, c7, c10, 4 - - mov tmp1, memctrl - mov tmp2, tmp1, lsr#AT91_PM_MODE_OFFSET - and mode, tmp2, #AT91_PM_MODE_MASK - - mov tmp1, memctrl - and memctrl, tmp1, #AT91_PM_MEMCTRL_MASK - - cmp memctrl, #AT91_MEMCTRL_MC - bne ddr_sr_enable - - /* - * at91rm9200 Memory controller - */ - /* Put SDRAM in self-refresh mode */ - mov tmp1, #1 - str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR] - b sdr_sr_done - - /* - * DDRSDR Memory controller - */ -ddr_sr_enable: - cmp memctrl, #AT91_MEMCTRL_DDRSDR - bne sdr_sr_enable - - /* LPDDR1 --> force DDR2 mode during self-refresh */ - ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR] - str tmp1, .saved_sam9_mdr - bic tmp1, tmp1, #~AT91_DDRSDRC_MD - cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR - ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR] - biceq tmp1, tmp1, #AT91_DDRSDRC_MD - orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2 - streq tmp1, [sdramc, #AT91_DDRSDRC_MDR] - - /* prepare for DDRAM self-refresh mode */ - ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR] - str tmp1, .saved_sam9_lpr - bic tmp1, #AT91_DDRSDRC_LPCB - orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH - - /* figure out if we use the second ram controller */ - cmp ramc1, #0 - beq ddr_no_2nd_ctrl - - ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR] - str tmp2, .saved_sam9_mdr1 - bic tmp2, tmp2, #~AT91_DDRSDRC_MD - cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR - ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR] - biceq tmp2, tmp2, #AT91_DDRSDRC_MD - orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2 - streq tmp2, [ramc1, #AT91_DDRSDRC_MDR] - - ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR] - str tmp2, .saved_sam9_lpr1 - bic tmp2, #AT91_DDRSDRC_LPCB - orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH - - /* Enable DDRAM self-refresh mode */ - str tmp2, [ramc1, #AT91_DDRSDRC_LPR] -ddr_no_2nd_ctrl: - str tmp1, [sdramc, #AT91_DDRSDRC_LPR] - - b sdr_sr_done - - /* - * SDRAMC Memory controller - */ -sdr_sr_enable: - /* Enable SDRAM self-refresh mode */ - ldr tmp1, [sdramc, #AT91_SDRAMC_LPR] - str tmp1, .saved_sam9_lpr - - bic tmp1, #AT91_SDRAMC_LPCB - orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH - str tmp1, [sdramc, #AT91_SDRAMC_LPR] - -sdr_sr_done: - tst mode, #AT91_PM_SLOW_CLOCK - beq skip_disable_main_clock - - /* Save Master clock setting */ - ldr tmp1, [pmc, #AT91_PMC_MCKR] - str tmp1, .saved_mckr - - /* - * Set the Master clock source to slow clock - */ - bic tmp1, tmp1, #AT91_PMC_CSS - str tmp1, [pmc, #AT91_PMC_MCKR] - - wait_mckrdy - - /* Save PLLA setting and disable it */ - ldr tmp1, [pmc, #AT91_CKGR_PLLAR] - str tmp1, .saved_pllar - - mov tmp1, #AT91_PMC_PLLCOUNT - orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ - str tmp1, [pmc, #AT91_CKGR_PLLAR] - - /* Turn off the main oscillator */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] - bic tmp1, tmp1, #AT91_PMC_MOSCEN - str tmp1, [pmc, #AT91_CKGR_MOR] - -skip_disable_main_clock: - /* Wait for interrupt */ - mcr p15, 0, tmp1, c7, c0, 4 - - tst mode, #AT91_PM_SLOW_CLOCK - beq skip_enable_main_clock - - /* Turn on the main oscillator */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] - orr tmp1, tmp1, #AT91_PMC_MOSCEN - str tmp1, [pmc, #AT91_CKGR_MOR] - - wait_moscrdy - - /* Restore PLLA setting */ - ldr tmp1, .saved_pllar - str tmp1, [pmc, #AT91_CKGR_PLLAR] - - tst tmp1, #(AT91_PMC_MUL & 0xff0000) - bne 3f - tst tmp1, #(AT91_PMC_MUL & ~0xff0000) - beq 4f -3: - wait_pllalock -4: - - /* - * Restore master clock setting - */ -2: ldr tmp1, .saved_mckr - str tmp1, [pmc, #AT91_PMC_MCKR] - - wait_mckrdy - -skip_enable_main_clock: - /* - * at91rm9200 Memory controller - * Do nothing - self-refresh is automatically disabled. - */ - cmp memctrl, #AT91_MEMCTRL_MC - beq ram_restored - - /* - * DDRSDR Memory controller - */ - cmp memctrl, #AT91_MEMCTRL_DDRSDR - bne sdr_en_restore - /* Restore MDR in case of LPDDR1 */ - ldr tmp1, .saved_sam9_mdr - str tmp1, [sdramc, #AT91_DDRSDRC_MDR] - /* Restore LPR on AT91 with DDRAM */ - ldr tmp1, .saved_sam9_lpr - str tmp1, [sdramc, #AT91_DDRSDRC_LPR] - - /* if we use the second ram controller */ - cmp ramc1, #0 - ldrne tmp2, .saved_sam9_mdr1 - strne tmp2, [ramc1, #AT91_DDRSDRC_MDR] - ldrne tmp2, .saved_sam9_lpr1 - strne tmp2, [ramc1, #AT91_DDRSDRC_LPR] - - b ram_restored - - /* - * SDRAMC Memory controller - */ -sdr_en_restore: - /* Restore LPR on AT91 with SDRAM */ - ldr tmp1, .saved_sam9_lpr - str tmp1, [sdramc, #AT91_SDRAMC_LPR] - -ram_restored: - /* Restore registers, and return */ - ldmfd sp!, {r4 - r12, pc} - - -.saved_mckr: - .word 0 - -.saved_pllar: - .word 0 - -.saved_sam9_lpr: - .word 0 - -.saved_sam9_lpr1: - .word 0 - -.saved_sam9_mdr: - .word 0 - -.saved_sam9_mdr1: - .word 0 - -ENTRY(at91_slow_clock_sz) - .word .-at91_slow_clock diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S new file mode 100644 index 0000000..8edbad0 --- /dev/null +++ b/arch/arm/mach-at91/pm_suspend.S @@ -0,0 +1,281 @@ +/* + * arch/arm/mach-at91/pm_suspend.S + * + * Copyright (C) 2006 Savin Zlobec + * + * AT91SAM9 support: + * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include <linux/linkage.h> +#include <linux/clk/at91_pmc.h> +#include <mach/hardware.h> +#include <mach/at91_ramc.h> + +#include "pm.h" + +pmc .req r0 +sdramc .req r1 +ramc1 .req r2 +memctrl .req r3 +tmp1 .req r4 +tmp2 .req r5 +mode .req r6 + +/* + * Wait until master clock is ready (after switching master clock source) + */ + .macro wait_mckrdy +1: ldr tmp1, [pmc, #AT91_PMC_SR] + tst tmp1, #AT91_PMC_MCKRDY + beq 1b + .endm + +/* + * Wait until master oscillator has stabilized. + */ + .macro wait_moscrdy +1: ldr tmp1, [pmc, #AT91_PMC_SR] + tst tmp1, #AT91_PMC_MOSCS + beq 1b + .endm + +/* + * Wait until PLLA has locked. + */ + .macro wait_pllalock +1: ldr tmp1, [pmc, #AT91_PMC_SR] + tst tmp1, #AT91_PMC_LOCKA + beq 1b + .endm + + .text + +/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc, + * void __iomem *ramc1, int memctrl) + */ +ENTRY(at91_slow_clock) + /* Save registers on stack */ + stmfd sp!, {r4 - r12, lr} + + /* + * Register usage: + * R0 = Base address of AT91_PMC + * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS) + * R2 = Base address of second RAM Controller or 0 if not present + * R3 = Memory controller + * R4 = temporary register + * R5 = temporary register + */ + + /* Drain write buffer */ + mov tmp1, #0 + mcr p15, 0, tmp1, c7, c10, 4 + + mov tmp1, memctrl + mov tmp2, tmp1, lsr#AT91_PM_MODE_OFFSET + and mode, tmp2, #AT91_PM_MODE_MASK + + mov tmp1, memctrl + and memctrl, tmp1, #AT91_PM_MEMCTRL_MASK + + cmp memctrl, #AT91_MEMCTRL_MC + bne ddr_sr_enable + + /* + * at91rm9200 Memory controller + */ + /* Put SDRAM in self-refresh mode */ + mov tmp1, #1 + str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR] + b sdr_sr_done + + /* + * DDRSDR Memory controller + */ +ddr_sr_enable: + cmp memctrl, #AT91_MEMCTRL_DDRSDR + bne sdr_sr_enable + + /* LPDDR1 --> force DDR2 mode during self-refresh */ + ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR] + str tmp1, .saved_sam9_mdr + bic tmp1, tmp1, #~AT91_DDRSDRC_MD + cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR + ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR] + biceq tmp1, tmp1, #AT91_DDRSDRC_MD + orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2 + streq tmp1, [sdramc, #AT91_DDRSDRC_MDR] + + /* prepare for DDRAM self-refresh mode */ + ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR] + str tmp1, .saved_sam9_lpr + bic tmp1, #AT91_DDRSDRC_LPCB + orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH + + /* figure out if we use the second ram controller */ + cmp ramc1, #0 + beq ddr_no_2nd_ctrl + + ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR] + str tmp2, .saved_sam9_mdr1 + bic tmp2, tmp2, #~AT91_DDRSDRC_MD + cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR + ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR] + biceq tmp2, tmp2, #AT91_DDRSDRC_MD + orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2 + streq tmp2, [ramc1, #AT91_DDRSDRC_MDR] + + ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR] + str tmp2, .saved_sam9_lpr1 + bic tmp2, #AT91_DDRSDRC_LPCB + orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH + + /* Enable DDRAM self-refresh mode */ + str tmp2, [ramc1, #AT91_DDRSDRC_LPR] +ddr_no_2nd_ctrl: + str tmp1, [sdramc, #AT91_DDRSDRC_LPR] + + b sdr_sr_done + + /* + * SDRAMC Memory controller + */ +sdr_sr_enable: + /* Enable SDRAM self-refresh mode */ + ldr tmp1, [sdramc, #AT91_SDRAMC_LPR] + str tmp1, .saved_sam9_lpr + + bic tmp1, #AT91_SDRAMC_LPCB + orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH + str tmp1, [sdramc, #AT91_SDRAMC_LPR] + +sdr_sr_done: + tst mode, #AT91_PM_SLOW_CLOCK + beq skip_disable_main_clock + + /* Save Master clock setting */ + ldr tmp1, [pmc, #AT91_PMC_MCKR] + str tmp1, .saved_mckr + + /* + * Set the Master clock source to slow clock + */ + bic tmp1, tmp1, #AT91_PMC_CSS + str tmp1, [pmc, #AT91_PMC_MCKR] + + wait_mckrdy + + /* Save PLLA setting and disable it */ + ldr tmp1, [pmc, #AT91_CKGR_PLLAR] + str tmp1, .saved_pllar + + mov tmp1, #AT91_PMC_PLLCOUNT + orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ + str tmp1, [pmc, #AT91_CKGR_PLLAR] + + /* Turn off the main oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + bic tmp1, tmp1, #AT91_PMC_MOSCEN + str tmp1, [pmc, #AT91_CKGR_MOR] + +skip_disable_main_clock: + /* Wait for interrupt */ + mcr p15, 0, tmp1, c7, c0, 4 + + tst mode, #AT91_PM_SLOW_CLOCK + beq skip_enable_main_clock + + /* Turn on the main oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + orr tmp1, tmp1, #AT91_PMC_MOSCEN + str tmp1, [pmc, #AT91_CKGR_MOR] + + wait_moscrdy + + /* Restore PLLA setting */ + ldr tmp1, .saved_pllar + str tmp1, [pmc, #AT91_CKGR_PLLAR] + + tst tmp1, #(AT91_PMC_MUL & 0xff0000) + bne 3f + tst tmp1, #(AT91_PMC_MUL & ~0xff0000) + beq 4f +3: + wait_pllalock +4: + + /* + * Restore master clock setting + */ +2: ldr tmp1, .saved_mckr + str tmp1, [pmc, #AT91_PMC_MCKR] + + wait_mckrdy + +skip_enable_main_clock: + /* + * at91rm9200 Memory controller + * Do nothing - self-refresh is automatically disabled. + */ + cmp memctrl, #AT91_MEMCTRL_MC + beq ram_restored + + /* + * DDRSDR Memory controller + */ + cmp memctrl, #AT91_MEMCTRL_DDRSDR + bne sdr_en_restore + /* Restore MDR in case of LPDDR1 */ + ldr tmp1, .saved_sam9_mdr + str tmp1, [sdramc, #AT91_DDRSDRC_MDR] + /* Restore LPR on AT91 with DDRAM */ + ldr tmp1, .saved_sam9_lpr + str tmp1, [sdramc, #AT91_DDRSDRC_LPR] + + /* if we use the second ram controller */ + cmp ramc1, #0 + ldrne tmp2, .saved_sam9_mdr1 + strne tmp2, [ramc1, #AT91_DDRSDRC_MDR] + ldrne tmp2, .saved_sam9_lpr1 + strne tmp2, [ramc1, #AT91_DDRSDRC_LPR] + + b ram_restored + + /* + * SDRAMC Memory controller + */ +sdr_en_restore: + /* Restore LPR on AT91 with SDRAM */ + ldr tmp1, .saved_sam9_lpr + str tmp1, [sdramc, #AT91_SDRAMC_LPR] + +ram_restored: + /* Restore registers, and return */ + ldmfd sp!, {r4 - r12, pc} + + +.saved_mckr: + .word 0 + +.saved_pllar: + .word 0 + +.saved_sam9_lpr: + .word 0 + +.saved_sam9_lpr1: + .word 0 + +.saved_sam9_mdr: + .word 0 + +.saved_sam9_mdr1: + .word 0 + +ENTRY(at91_slow_clock_sz) + .word .-at91_slow_clock -- 1.7.9.5
next prev parent reply other threads:[~2015-01-26 9:43 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-01-26 9:36 [PATCH v2 00/12] AT91 pm cleanup for 3.20 Wenyou Yang 2015-01-26 9:36 ` Wenyou Yang 2015-01-26 9:37 ` [PATCH v2 01/12] pm: at91: pm_slowclock: improve reliability of suspend/resume Wenyou Yang 2015-01-26 9:37 ` Wenyou Yang 2015-01-26 14:54 ` [PATCH v2 0/2] " Sylvain Rochet 2015-01-26 14:54 ` Sylvain Rochet 2015-01-26 14:54 ` [PATCH v2 1/2] pm: at91: pm_slowclock: fix suspend/resume hang up in timeouts Sylvain Rochet 2015-01-26 14:54 ` Sylvain Rochet 2015-01-26 14:54 ` [PATCH v2 2/2] pm: at91: pm_slowclock: remove clocks which are already stopped when entering slow clock mode Sylvain Rochet 2015-01-26 14:54 ` Sylvain Rochet 2015-01-26 9:38 ` [PATCH v2 02/12] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories Wenyou Yang 2015-01-26 9:38 ` Wenyou Yang 2015-01-26 10:36 ` Sylvain Rochet 2015-01-26 10:36 ` Sylvain Rochet 2015-01-26 13:34 ` Nicolas Ferre 2015-01-26 13:34 ` Nicolas Ferre 2015-01-26 13:44 ` Sylvain Rochet 2015-01-26 13:44 ` Sylvain Rochet 2015-01-26 15:58 ` Peter Rosin 2015-01-26 15:58 ` Peter Rosin 2015-01-26 16:04 ` Nicolas Ferre 2015-01-26 16:04 ` Nicolas Ferre 2015-01-26 16:11 ` Sylvain Rochet 2015-01-26 16:11 ` Sylvain Rochet 2015-01-26 9:39 ` [PATCH v2 03/12] pm: at91: pm_slowclock: remove the unused code related with SLOWDOWN_MASTER_CLOCK Wenyou Yang 2015-01-26 9:39 ` Wenyou Yang 2015-01-26 9:40 ` [PATCH v2 04/12] pm: at91: move the copying the sram function to the sram initializationi phase Wenyou Yang 2015-01-26 9:40 ` Wenyou Yang 2015-01-26 12:57 ` Sergei Shtylyov 2015-01-26 12:57 ` Sergei Shtylyov 2015-01-27 3:27 ` Yang, Wenyou 2015-01-27 3:27 ` Yang, Wenyou 2015-01-26 9:40 ` [PATCH v2 05/12] ARM: at91: move select SRAM to ARCH_AT91 Wenyou Yang 2015-01-26 9:40 ` Wenyou Yang 2015-01-26 9:41 ` [PATCH v2 06/12] pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK Wenyou Yang 2015-01-26 9:41 ` Wenyou Yang 2015-01-26 9:42 ` [PATCH v2 07/12] pm: at91: the standby mode uses the same sram function as the suspend to memory mode Wenyou Yang 2015-01-26 9:42 ` Wenyou Yang 2015-01-26 10:09 ` Sylvain Rochet 2015-01-26 10:09 ` Sylvain Rochet 2015-01-27 4:44 ` Yang, Wenyou 2015-01-27 4:44 ` Yang, Wenyou 2015-01-26 9:42 ` Wenyou Yang [this message] 2015-01-26 9:42 ` [PATCH v2 08/12] pm: at91: rename file name: pm_slowclock.S -->pm_suspend.S Wenyou Yang 2015-01-26 9:43 ` [PATCH v2 09/12] pm: at91: rename function name: at91_slow_clock()-->at91_pm_suspend_sram_fn Wenyou Yang 2015-01-26 9:43 ` Wenyou Yang 2015-01-26 9:44 ` [PATCH v2 10/12] pm: at91: remove the at91_xxx_standby() function definitions in the pm.h Wenyou Yang 2015-01-26 9:44 ` Wenyou Yang 2015-01-26 9:45 ` [PATCH v2 11/12] pm: at91: setup: remove the struct ramc_ids .data at91_xxx_standby members Wenyou Yang 2015-01-26 9:45 ` Wenyou Yang 2015-01-26 9:45 ` [PATCH v2 12/12] pm: at91: amend the pm_suspend entry for at91_cpuidle_device Wenyou Yang 2015-01-26 9:45 ` Wenyou Yang 2015-01-26 9:55 ` [PATCH v2 00/12] AT91 pm cleanup for 3.20 Sylvain Rochet 2015-01-26 9:55 ` Sylvain Rochet 2015-01-27 2:58 ` Yang, Wenyou 2015-01-27 2:58 ` Yang, Wenyou
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