From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 4/9] target-tricore: Fix bugs found by coverity
Date: Mon, 26 Jan 2015 20:03:15 +0000 [thread overview]
Message-ID: <1422302600-21514-5-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1422302600-21514-1-git-send-email-kbastian@mail.uni-paderborn.de>
This fixes one bug and one false positive found by coverity. The bug is,
that gen_mtcr was missing a mask to check the flag, which resulted in dead code.
The false positive is a intentional missing break for a jump and link address
insn followed by a jump and link insn. This adds a fall through comment to avoid
the false positive in the future.
Reported-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/cpu.h | 1 +
target-tricore/translate.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h
index 7555b70..e5409e4 100644
--- a/target-tricore/cpu.h
+++ b/target-tricore/cpu.h
@@ -238,6 +238,7 @@ struct CPUTriCoreState {
#define MASK_LCX_LCXS 0x000f0000
#define MASK_LCX_LCX0 0x0000ffff
+#define TRICORE_HFLAG_KUU 0x3
#define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */
#define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */
#define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 61518f3..57949fa 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -343,7 +343,7 @@ static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset)
static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1,
int32_t offset)
{
- if (ctx->hflags & TRICORE_HFLAG_SM) {
+ if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
/* since we're caching PSW make this a special case */
if (offset == 0xfe04) {
gen_helper_psw_write(cpu_env, r1);
@@ -1647,6 +1647,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
break;
case OPC1_32_B_JLA:
tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
+ /* fall through */
case OPC1_32_B_JA:
gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
break;
--
2.2.2
next prev parent reply other threads:[~2015-01-26 19:02 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-26 20:03 [Qemu-devel] [PULL 0/9] tricore patches Bastian Koppelmann
2015-01-26 20:03 ` [Qemu-devel] [PULL 1/9] target-tricore: Add missing ULL suffix on 64 bit constant Bastian Koppelmann
2015-01-26 20:03 ` [Qemu-devel] [PULL 2/9] target-tricore: Several translator and cpu model fixes Bastian Koppelmann
2015-01-26 20:03 ` [Qemu-devel] [PULL 3/9] target-tricore: calculate av bits before saturation Bastian Koppelmann
2015-01-26 20:03 ` Bastian Koppelmann [this message]
2015-01-26 20:03 ` [Qemu-devel] [PULL 5/9] target-tricore: split up suov32 into suov32_pos and suov32_neg Bastian Koppelmann
2015-01-26 20:03 ` [Qemu-devel] [PULL 6/9] target-tricore: target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode Bastian Koppelmann
2015-01-26 20:03 ` [Qemu-devel] [PULL 7/9] target-tricore: Add instructions of RR2 opcode format Bastian Koppelmann
2015-01-26 20:03 ` [Qemu-devel] [PULL 8/9] target-tricore: Add instructions of RRPW " Bastian Koppelmann
2015-01-26 20:03 ` [Qemu-devel] [PULL 9/9] target-tricore: Add instructions of RRR " Bastian Koppelmann
2015-01-27 10:40 ` [Qemu-devel] [PULL 0/9] tricore patches Peter Maydell
2015-01-27 11:45 ` Bastian Koppelmann
2015-01-27 11:23 ` Peter Maydell
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