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* [PATCH] tools/intel_reg_read: Adding the reg offset for VLV and CHT
@ 2015-01-28  8:49 meghanelogal
  2015-01-28  9:46 ` Daniel Vetter
  0 siblings, 1 reply; 2+ messages in thread
From: meghanelogal @ 2015-01-28  8:49 UTC (permalink / raw)
  To: intel-gfx; +Cc: manikandan.k.pillai, meghanelogal, pratyush.dutta

From: meghanelogal <megha.i.nelogal@intel.com>

For VLV and CHT for each register access we need to add base offset of
0x180000.

Signed-off-by: meghanelogal <megha.i.nelogal@intel.com>
---
 tools/intel_reg_read.c |   20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/tools/intel_reg_read.c b/tools/intel_reg_read.c
index 3b91291..c550b02 100644
--- a/tools/intel_reg_read.c
+++ b/tools/intel_reg_read.c
@@ -48,11 +48,13 @@ static void bit_decode(uint32_t reg)
 
 static void dump_range(uint32_t start, uint32_t end)
 {
-	int i;
-
+	int i, reg = 0;
+	struct pci_device *dev = intel_get_pci_device();
+	if (IS_CHERRYVIEW(dev->device_id) || IS_VALLEYVIEW(dev->device_id))
+		reg = 0x180000;
 	for (i = start; i < end; i += 4)
 		printf("0x%X : 0x%X\n", i,
-		       *(volatile uint32_t *)((volatile char*)mmio + i));
+		       *(volatile uint32_t *)((volatile char*)mmio + i + reg));
 }
 
 static void usage(char *cmdname)
@@ -129,11 +131,17 @@ int main(int argc, char** argv)
 			sscanf(argv[i], "0x%x", &reg);
 			dump_range(reg, reg + (dwords * 4));
 
-			if (decode_bits)
-				bit_decode(*(volatile uint32_t *)((volatile char*)mmio + reg));
+			if (decode_bits) {
+				struct pci_device *dev = intel_get_pci_device();
+				if (IS_CHERRYVIEW(dev->device_id) ||
+						IS_VALLEYVIEW(dev->device_id)) {
+					reg += 0x180000;
+					bit_decode(*(volatile uint32_t *)
+						((volatile char*)mmio + reg));
+				}
+			}
 		}
 	}
-
 	intel_register_access_fini();
 
 out:
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] tools/intel_reg_read: Adding the reg offset for VLV and CHT
  2015-01-28  8:49 [PATCH] tools/intel_reg_read: Adding the reg offset for VLV and CHT meghanelogal
@ 2015-01-28  9:46 ` Daniel Vetter
  0 siblings, 0 replies; 2+ messages in thread
From: Daniel Vetter @ 2015-01-28  9:46 UTC (permalink / raw)
  To: meghanelogal; +Cc: intel-gfx, manikandan.k.pillai, pratyush.dutta

On Wed, Jan 28, 2015 at 02:19:50PM +0530, meghanelogal wrote:
> From: meghanelogal <megha.i.nelogal@intel.com>
> 
> For VLV and CHT for each register access we need to add base offset of
> 0x180000.
> 
> Signed-off-by: meghanelogal <megha.i.nelogal@intel.com>

Nah, vlv/cht have new decoder tools, and skl will have yet another one.
Unfortunately no one unified them yet really. See tools/quick_dump.
-Daniel

> ---
>  tools/intel_reg_read.c |   20 ++++++++++++++------
>  1 file changed, 14 insertions(+), 6 deletions(-)
> 
> diff --git a/tools/intel_reg_read.c b/tools/intel_reg_read.c
> index 3b91291..c550b02 100644
> --- a/tools/intel_reg_read.c
> +++ b/tools/intel_reg_read.c
> @@ -48,11 +48,13 @@ static void bit_decode(uint32_t reg)
>  
>  static void dump_range(uint32_t start, uint32_t end)
>  {
> -	int i;
> -
> +	int i, reg = 0;
> +	struct pci_device *dev = intel_get_pci_device();
> +	if (IS_CHERRYVIEW(dev->device_id) || IS_VALLEYVIEW(dev->device_id))
> +		reg = 0x180000;
>  	for (i = start; i < end; i += 4)
>  		printf("0x%X : 0x%X\n", i,
> -		       *(volatile uint32_t *)((volatile char*)mmio + i));
> +		       *(volatile uint32_t *)((volatile char*)mmio + i + reg));
>  }
>  
>  static void usage(char *cmdname)
> @@ -129,11 +131,17 @@ int main(int argc, char** argv)
>  			sscanf(argv[i], "0x%x", &reg);
>  			dump_range(reg, reg + (dwords * 4));
>  
> -			if (decode_bits)
> -				bit_decode(*(volatile uint32_t *)((volatile char*)mmio + reg));
> +			if (decode_bits) {
> +				struct pci_device *dev = intel_get_pci_device();
> +				if (IS_CHERRYVIEW(dev->device_id) ||
> +						IS_VALLEYVIEW(dev->device_id)) {
> +					reg += 0x180000;
> +					bit_decode(*(volatile uint32_t *)
> +						((volatile char*)mmio + reg));
> +				}
> +			}
>  		}
>  	}
> -
>  	intel_register_access_fini();
>  
>  out:
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2015-01-28  8:49 [PATCH] tools/intel_reg_read: Adding the reg offset for VLV and CHT meghanelogal
2015-01-28  9:46 ` Daniel Vetter

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