[U-Boot] [RFC PATCH 3/6] x86: quark: Add Cache-As-RAM initialization

[Bin Meng <bmeng.cn@gmail.com>]

Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
initialized by hardware. eSRAM is the ideal place to be used
for Cache-As-RAM (CAR) before system memory is available.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/quark/car.S | 105 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644 arch/x86/cpu/quark/car.S

diff --git a/arch/x86/cpu/quark/car.S b/arch/x86/cpu/quark/car.S
new file mode 100644
index 0000000..6b7b249
--- /dev/null
+++ b/arch/x86/cpu/quark/car.S
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/post.h>
+#include <asm/arch/quark.h>
+
+.globl car_init
+car_init:
+	post_code(POST_CAR_START)
+
+	/*
+	 * Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
+	 * initialized by hardware. eSRAM is the ideal place to be used
+	 * for Cache-As-RAM (CAR) before system memory is available.
+	 *
+	 * Relocate this eSRAM to a suitable location in the physical
+	 * memory map and enable it.
+	 */
+
+	/* Host Memory Bound Register P03h:R08h */
+	mov	$0x00030800, %eax
+	mov	$(DRAM_BASE + DRAM_MAX_SIZE + ESRAM_SIZE), %edx
+	lea	1f, %esp
+	jmp	msg_port_write
+1:
+
+	/* eSRAM Block Page Control Register P05h:R82h = 10000080h */
+	mov	$0x00058200, %eax
+	mov	$0x10000080, %edx
+	lea	2f, %esp
+	jmp	msg_port_write
+2:
+
+	post_code(POST_CAR_CPU_CACHE)
+	jmp	car_init_ret
+
+msg_port_read:
+	/*
+	 * Parameter:
+	 *   EAX[23:16] - Message Port ID
+	 *   EAX[15:08] - Register Address
+	 *
+	 * Return Value:
+	 *   EAX - Message Port Register value
+	 *
+	 * Return Address: ESP
+	 */
+
+	/* opcode 0x10, all bytes enable 0xf0 */
+	or	$0x100000f0, %eax
+	mov	%eax, %ebx
+
+	/* Write MCR B0:D0:F0:RD0 */
+	mov	$0x800000d0, %eax
+	mov	$0xcf8, %dx
+	out	%eax, %dx
+	mov	$0xcfc, %dx
+	mov	%ebx, %eax
+	out	%eax, %dx
+
+	/* Read MDR B0:D0:F0:RD4 */
+	mov	$0x800000d4, %eax
+	mov	$0xcf8, %dx
+	out	%eax, %dx
+	mov	$0xcfc, %dx
+	in	%dx, %eax
+
+	jmp	*%esp
+
+msg_port_write:
+	/*
+	 * Parameter:
+	 *   EAX[23:16] - Message Port ID
+	 *   EAX[15:08] - Register Address
+	 *   EDX        - Message Port Register value to write
+	 *
+	 * Return Address: ESP
+	 */
+
+	/* opcode 0x11, all bytes enable 0xf0 */
+	or	$0x110000f0, %eax
+	mov	%eax, %esi
+	mov	%edx, %edi
+
+	/* Write MDR B0:D0:F0:RD4 */
+	mov	$0x800000d4, %eax
+	mov	$0xcf8, %dx
+	out	%eax, %dx
+	mov	$0xcfc, %dx
+	mov	%edi, %eax
+	out	%eax, %dx
+
+	/* Write MCR B0:D0:F0:RD0 */
+	mov	$0x800000d0, %eax
+	mov	$0xcf8, %dx
+	out	%eax, %dx
+	mov	$0xcfc, %dx
+	mov	%esi, %eax
+	out	%eax, %dx
+
+	jmp	*%esp
-- 
1.8.2.1