From: James Hogan <james.hogan@imgtec.com> To: Ralf Baechle <ralf@linux-mips.org>, <linux-mips@linux-mips.org> Cc: <linux-kernel@vger.kernel.org>, James Hogan <james.hogan@imgtec.com> Subject: [PATCH 5/9] MIPS: Malta: Implement get_c0_fdc_int() Date: Thu, 29 Jan 2015 11:14:10 +0000 [thread overview] Message-ID: <1422530054-7976-6-git-send-email-james.hogan@imgtec.com> (raw) In-Reply-To: <1422530054-7976-1-git-send-email-james.hogan@imgtec.com> Implement the weak get_c0_fdc_int() function for Malta. The Fast Debug Channel (FDC) interrupt is obtained mainly depending on whether a GIC is present. Vectored external interrupt mode isn't yet supported. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org --- EIC mode not supported because I don't have anything to try it on (and it isn't clear which interrupt priority level would get used). It may make sense to have a common default implementation of get_c0_fdc_int(), but this isn't done for the other local IRQs yet so I've kept it like this for consistency. --- arch/mips/mti-malta/malta-time.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index ce02dbdedc62..7d4b86571564 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -115,6 +115,22 @@ void read_persistent_clock(struct timespec *ts) ts->tv_nsec = 0; } +int get_c0_fdc_int(void) +{ + int mips_cpu_fdc_irq; + + if (cpu_has_veic) + mips_cpu_fdc_irq = -1; + else if (gic_present) + mips_cpu_fdc_irq = gic_get_c0_fdc_int(); + else if (cp0_fdc_irq >= 0) + mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq; + else + mips_cpu_fdc_irq = -1; + + return mips_cpu_fdc_irq; +} + int get_c0_perfcount_int(void) { if (cpu_has_veic) { -- 2.0.5
WARNING: multiple messages have this Message-ID (diff)
From: James Hogan <james.hogan@imgtec.com> To: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org, James Hogan <james.hogan@imgtec.com> Subject: [PATCH 5/9] MIPS: Malta: Implement get_c0_fdc_int() Date: Thu, 29 Jan 2015 11:14:10 +0000 [thread overview] Message-ID: <1422530054-7976-6-git-send-email-james.hogan@imgtec.com> (raw) Message-ID: <20150129111410.KC_NEiTQQ2uhPqkyF7tsmGrWcTjMWNuhXs0x7gdd6oU@z> (raw) In-Reply-To: <1422530054-7976-1-git-send-email-james.hogan@imgtec.com> Implement the weak get_c0_fdc_int() function for Malta. The Fast Debug Channel (FDC) interrupt is obtained mainly depending on whether a GIC is present. Vectored external interrupt mode isn't yet supported. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org --- EIC mode not supported because I don't have anything to try it on (and it isn't clear which interrupt priority level would get used). It may make sense to have a common default implementation of get_c0_fdc_int(), but this isn't done for the other local IRQs yet so I've kept it like this for consistency. --- arch/mips/mti-malta/malta-time.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index ce02dbdedc62..7d4b86571564 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -115,6 +115,22 @@ void read_persistent_clock(struct timespec *ts) ts->tv_nsec = 0; } +int get_c0_fdc_int(void) +{ + int mips_cpu_fdc_irq; + + if (cpu_has_veic) + mips_cpu_fdc_irq = -1; + else if (gic_present) + mips_cpu_fdc_irq = gic_get_c0_fdc_int(); + else if (cp0_fdc_irq >= 0) + mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq; + else + mips_cpu_fdc_irq = -1; + + return mips_cpu_fdc_irq; +} + int get_c0_perfcount_int(void) { if (cpu_has_veic) { -- 2.0.5
next prev parent reply other threads:[~2015-01-29 11:17 UTC|newest] Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-01-29 11:14 [PATCH 0/9] Add MIPS EJTAG Fast Debug Channel TTY driver James Hogan 2015-01-29 11:14 ` James Hogan 2015-01-29 11:14 ` [PATCH 1/9] MIPS: Add architectural FDC IRQ fields James Hogan 2015-01-29 11:14 ` James Hogan 2015-01-29 11:14 ` [PATCH 2/9] MIPS: Read CPU IRQ line that FDC to routed to James Hogan 2015-01-29 11:14 ` James Hogan 2015-01-29 11:14 ` [PATCH 3/9] irqchip: mips-gic: Don't treat FDC IRQ as percpu devid James Hogan 2015-01-29 11:14 ` James Hogan 2015-01-29 11:14 ` [PATCH 4/9] irqchip: mips-gic: Add function for retrieving FDC IRQ James Hogan 2015-01-29 11:14 ` James Hogan 2015-01-29 11:14 ` James Hogan [this message] 2015-01-29 11:14 ` [PATCH 5/9] MIPS: Malta: Implement get_c0_fdc_int() James Hogan 2015-01-29 11:14 ` [PATCH 6/9] MIPS: idle: Workaround wait + FDC problems James Hogan 2015-01-29 11:14 ` James Hogan 2015-01-29 11:14 ` [PATCH 7/9] tty: Add MIPS EJTAG Fast Debug Channel TTY driver James Hogan 2015-01-29 11:14 ` James Hogan 2015-03-26 15:09 ` Greg Kroah-Hartman 2015-01-29 11:14 ` [PATCH 8/9] MIPS, ttyFDC: Add early FDC console support James Hogan 2015-01-29 11:14 ` James Hogan 2015-03-26 15:09 ` Greg Kroah-Hartman 2015-01-29 11:14 ` [PATCH 9/9] ttyFDC: Implement KGDB IO operations James Hogan 2015-01-29 11:14 ` James Hogan 2015-03-26 15:09 ` Greg Kroah-Hartman 2015-02-25 11:06 ` [PATCH 0/9] Add MIPS EJTAG Fast Debug Channel TTY driver James Hogan 2015-02-25 11:06 ` James Hogan
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