* [U-Boot] [PATCH 0/11] ARM: remove non-generic boards
@ 2015-02-10 4:44 Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 01/11] ARM: remove mx31ads board support Masahiro Yamada
` (10 more replies)
0 siblings, 11 replies; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 4:44 UTC (permalink / raw)
To: u-boot
Based on Tom's announce mail
(http://lists.denx.de/pipermail/u-boot/2015-February/203606.html),
let's start removing non-generic ARM boards.
No conversion patches have been posted for these boards.
Masahiro Yamada (11):
ARM: remove mx31ads board support
ARM: mx31: remove imx31_phycore board
ARM: remove jadecpu board support
ARM: remove zmx25 board support
ARM: remove devkit3250 board support
ARM: remove dkb board support
ARM: remove cm4008 and cm41xx board support
ARM: remove a320evb board support
ARM: armada100: remove aspenite and gplugd board support
ARM: remove tnetv107x board support
ARM: davinci: remove hawkboard support
arch/arm/Kconfig | 60 --
arch/arm/cpu/arm1176/Makefile | 1 -
arch/arm/cpu/arm1176/start.S | 22 -
arch/arm/cpu/arm1176/tnetv107x/Makefile | 6 -
arch/arm/cpu/arm1176/tnetv107x/aemif.c | 78 ---
arch/arm/cpu/arm1176/tnetv107x/clock.c | 432 ------------
arch/arm/cpu/arm1176/tnetv107x/init.c | 22 -
arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S | 10 -
arch/arm/cpu/arm1176/tnetv107x/mux.c | 319 ---------
arch/arm/cpu/arm1176/tnetv107x/timer.c | 93 ---
arch/arm/cpu/arm920t/Makefile | 2 -
arch/arm/cpu/arm920t/a320/Makefile | 9 -
arch/arm/cpu/arm920t/a320/reset.S | 10 -
arch/arm/cpu/arm920t/a320/timer.c | 118 ----
arch/arm/cpu/arm920t/ks8695/Makefile | 9 -
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 189 ------
arch/arm/cpu/arm920t/ks8695/timer.c | 77 ---
arch/arm/cpu/arm926ejs/Makefile | 4 -
arch/arm/cpu/arm926ejs/armada100/Makefile | 9 -
arch/arm/cpu/arm926ejs/armada100/cpu.c | 92 ---
arch/arm/cpu/arm926ejs/armada100/dram.c | 116 ----
arch/arm/cpu/arm926ejs/armada100/timer.c | 194 ------
arch/arm/cpu/arm926ejs/davinci/Kconfig | 4 -
arch/arm/cpu/arm926ejs/lpc32xx/Makefile | 8 -
arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 104 ---
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 57 --
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 39 --
arch/arm/cpu/arm926ejs/lpc32xx/timer.c | 82 ---
arch/arm/cpu/arm926ejs/mb86r0x/Makefile | 8 -
arch/arm/cpu/arm926ejs/mb86r0x/clock.c | 27 -
arch/arm/cpu/arm926ejs/mb86r0x/reset.c | 24 -
arch/arm/cpu/arm926ejs/mb86r0x/timer.c | 115 ----
arch/arm/cpu/arm926ejs/pantheon/Makefile | 9 -
arch/arm/cpu/arm926ejs/pantheon/cpu.c | 85 ---
arch/arm/cpu/arm926ejs/pantheon/dram.c | 117 ----
arch/arm/cpu/arm926ejs/pantheon/timer.c | 201 ------
arch/arm/include/asm/arch-a320/a320.h | 22 -
arch/arm/include/asm/arch-armada100/armada100.h | 60 --
arch/arm/include/asm/arch-armada100/config.h | 42 --
arch/arm/include/asm/arch-armada100/cpu.h | 162 -----
arch/arm/include/asm/arch-armada100/gpio.h | 32 -
arch/arm/include/asm/arch-armada100/mfp.h | 80 ---
arch/arm/include/asm/arch-armada100/spi.h | 79 ---
.../include/asm/arch-armada100/utmi-armada100.h | 63 --
arch/arm/include/asm/arch-ks8695/platform.h | 294 ---------
arch/arm/include/asm/arch-lpc32xx/clk.h | 157 -----
arch/arm/include/asm/arch-lpc32xx/config.h | 59 --
arch/arm/include/asm/arch-lpc32xx/cpu.h | 51 --
arch/arm/include/asm/arch-lpc32xx/emc.h | 79 ---
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 12 -
arch/arm/include/asm/arch-lpc32xx/timer.h | 61 --
arch/arm/include/asm/arch-lpc32xx/uart.h | 101 ---
arch/arm/include/asm/arch-lpc32xx/wdt.h | 38 --
arch/arm/include/asm/arch-mb86r0x/hardware.h | 15 -
arch/arm/include/asm/arch-mb86r0x/mb86r0x.h | 599 -----------------
arch/arm/include/asm/arch-pantheon/config.h | 53 --
arch/arm/include/asm/arch-pantheon/cpu.h | 77 ---
arch/arm/include/asm/arch-pantheon/gpio.h | 0
arch/arm/include/asm/arch-pantheon/mfp.h | 39 --
arch/arm/include/asm/arch-pantheon/pantheon.h | 38 --
arch/arm/include/asm/arch-tnetv107x/clock.h | 53 --
arch/arm/include/asm/arch-tnetv107x/hardware.h | 160 -----
arch/arm/include/asm/arch-tnetv107x/mux.h | 291 ---------
arch/arm/lib/asm-offsets.c | 46 --
board/Marvell/aspenite/Kconfig | 15 -
board/Marvell/aspenite/MAINTAINERS | 6 -
board/Marvell/aspenite/Makefile | 10 -
board/Marvell/aspenite/aspenite.c | 43 --
board/Marvell/dkb/Kconfig | 15 -
board/Marvell/dkb/MAINTAINERS | 6 -
board/Marvell/dkb/Makefile | 9 -
board/Marvell/dkb/dkb.c | 85 ---
board/Marvell/gplugd/Kconfig | 15 -
board/Marvell/gplugd/MAINTAINERS | 6 -
board/Marvell/gplugd/Makefile | 15 -
board/Marvell/gplugd/gplugd.c | 130 ----
board/cm4008/Kconfig | 12 -
board/cm4008/MAINTAINERS | 6 -
board/cm4008/Makefile | 8 -
board/cm4008/cm4008.c | 88 ---
board/cm4008/config.mk | 1 -
board/cm4008/flash.c | 395 -----------
board/cm41xx/Kconfig | 12 -
board/cm41xx/MAINTAINERS | 6 -
board/cm41xx/Makefile | 8 -
board/cm41xx/cm41xx.c | 88 ---
board/cm41xx/config.mk | 1 -
board/cm41xx/flash.c | 395 -----------
board/davinci/da8xxevm/Kconfig | 13 -
board/davinci/da8xxevm/MAINTAINERS | 8 -
board/davinci/da8xxevm/Makefile | 1 -
board/davinci/da8xxevm/README.hawkboard | 92 ---
board/davinci/da8xxevm/hawkboard-ais-nand.cfg | 4 -
board/davinci/da8xxevm/hawkboard.c | 120 ----
board/davinci/da8xxevm/u-boot-spl-hawk.lds | 69 --
board/faraday/a320evb/Kconfig | 15 -
board/faraday/a320evb/MAINTAINERS | 6 -
board/faraday/a320evb/Makefile | 9 -
board/faraday/a320evb/a320evb.c | 59 --
board/faraday/a320evb/lowlevel_init.S | 106 ---
board/freescale/mx31ads/Kconfig | 15 -
board/freescale/mx31ads/MAINTAINERS | 6 -
board/freescale/mx31ads/Makefile | 8 -
board/freescale/mx31ads/lowlevel_init.S | 268 --------
board/freescale/mx31ads/mx31ads.c | 114 ----
board/freescale/mx31ads/u-boot.lds | 110 ----
board/imx31_phycore/Kconfig | 12 -
board/imx31_phycore/MAINTAINERS | 11 -
board/imx31_phycore/Makefile | 9 -
board/imx31_phycore/imx31_phycore.c | 153 -----
board/imx31_phycore/lowlevel_init.S | 88 ---
board/syteco/jadecpu/Kconfig | 15 -
board/syteco/jadecpu/MAINTAINERS | 6 -
board/syteco/jadecpu/Makefile | 13 -
board/syteco/jadecpu/jadecpu.c | 160 -----
board/syteco/jadecpu/lowlevel_init.S | 249 -------
board/syteco/zmx25/Kconfig | 15 -
board/syteco/zmx25/MAINTAINERS | 6 -
board/syteco/zmx25/Makefile | 9 -
board/syteco/zmx25/lowlevel_init.S | 97 ---
board/syteco/zmx25/zmx25.c | 174 -----
board/ti/tnetv107xevm/Kconfig | 15 -
board/ti/tnetv107xevm/MAINTAINERS | 6 -
board/ti/tnetv107xevm/Makefile | 5 -
board/ti/tnetv107xevm/config.mk | 5 -
board/ti/tnetv107xevm/sdb_board.c | 134 ----
board/timll/devkit3250/Kconfig | 15 -
board/timll/devkit3250/MAINTAINERS | 6 -
board/timll/devkit3250/Makefile | 8 -
board/timll/devkit3250/devkit3250.c | 52 --
configs/a320evb_defconfig | 2 -
configs/aspenite_defconfig | 2 -
configs/cm4008_defconfig | 2 -
configs/cm41xx_defconfig | 2 -
configs/devkit3250_defconfig | 2 -
configs/dkb_defconfig | 2 -
configs/gplugd_defconfig | 2 -
configs/hawkboard_defconfig | 4 -
configs/hawkboard_uart_defconfig | 5 -
configs/imx31_phycore_defconfig | 2 -
configs/imx31_phycore_eet_defconfig | 3 -
configs/jadecpu_defconfig | 2 -
configs/mx31ads_defconfig | 2 -
configs/tnetv107x_evm_defconfig | 2 -
configs/zmx25_defconfig | 2 -
doc/README.scrapyard | 47 +-
drivers/net/Makefile | 2 -
drivers/net/armada100_fec.c | 726 ---------------------
drivers/net/armada100_fec.h | 209 ------
drivers/net/ks8695eth.c | 229 -------
drivers/serial/Makefile | 2 -
drivers/serial/lpc32xx_hsuart.c | 89 ---
drivers/serial/serial.c | 4 -
drivers/serial/serial_ks8695.c | 121 ----
drivers/spi/Makefile | 1 -
drivers/spi/armada100_spi.c | 203 ------
drivers/usb/host/Makefile | 1 -
drivers/usb/host/ehci-armada100.c | 48 --
drivers/usb/host/utmi-armada100.c | 80 ---
drivers/video/Makefile | 1 -
drivers/video/mb86r0xgdc.c | 168 -----
drivers/watchdog/Makefile | 1 -
drivers/watchdog/tnetv107x_wdt.c | 165 -----
include/configs/a320evb.h | 211 ------
include/configs/aspenite.h | 55 --
include/configs/cm4008.h | 104 ---
include/configs/cm41xx.h | 104 ---
include/configs/devkit3250.h | 101 ---
include/configs/dkb.h | 51 --
include/configs/gplugd.h | 134 ----
include/configs/hawkboard.h | 220 -------
include/configs/imx31_phycore.h | 202 ------
include/configs/jadecpu.h | 273 --------
include/configs/mx31ads.h | 188 ------
include/configs/tnetv107x_evm.h | 139 ----
include/configs/zmx25.h | 162 -----
include/netdev.h | 2 -
include/serial.h | 4 +-
178 files changed, 31 insertions(+), 13228 deletions(-)
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/Makefile
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/aemif.c
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/clock.c
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/init.c
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/mux.c
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/timer.c
delete mode 100644 arch/arm/cpu/arm920t/a320/Makefile
delete mode 100644 arch/arm/cpu/arm920t/a320/reset.S
delete mode 100644 arch/arm/cpu/arm920t/a320/timer.c
delete mode 100644 arch/arm/cpu/arm920t/ks8695/Makefile
delete mode 100644 arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
delete mode 100644 arch/arm/cpu/arm920t/ks8695/timer.c
delete mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile
delete mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c
delete mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c
delete mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c
delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/Makefile
delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/clk.c
delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/devices.c
delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/timer.c
delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/Makefile
delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/clock.c
delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/reset.c
delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/timer.c
delete mode 100644 arch/arm/cpu/arm926ejs/pantheon/Makefile
delete mode 100644 arch/arm/cpu/arm926ejs/pantheon/cpu.c
delete mode 100644 arch/arm/cpu/arm926ejs/pantheon/dram.c
delete mode 100644 arch/arm/cpu/arm926ejs/pantheon/timer.c
delete mode 100644 arch/arm/include/asm/arch-a320/a320.h
delete mode 100644 arch/arm/include/asm/arch-armada100/armada100.h
delete mode 100644 arch/arm/include/asm/arch-armada100/config.h
delete mode 100644 arch/arm/include/asm/arch-armada100/cpu.h
delete mode 100644 arch/arm/include/asm/arch-armada100/gpio.h
delete mode 100644 arch/arm/include/asm/arch-armada100/mfp.h
delete mode 100644 arch/arm/include/asm/arch-armada100/spi.h
delete mode 100644 arch/arm/include/asm/arch-armada100/utmi-armada100.h
delete mode 100644 arch/arm/include/asm/arch-ks8695/platform.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/clk.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/config.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/cpu.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/emc.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/sys_proto.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/timer.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/uart.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/wdt.h
delete mode 100644 arch/arm/include/asm/arch-mb86r0x/hardware.h
delete mode 100644 arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
delete mode 100644 arch/arm/include/asm/arch-pantheon/config.h
delete mode 100644 arch/arm/include/asm/arch-pantheon/cpu.h
delete mode 100644 arch/arm/include/asm/arch-pantheon/gpio.h
delete mode 100644 arch/arm/include/asm/arch-pantheon/mfp.h
delete mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h
delete mode 100644 arch/arm/include/asm/arch-tnetv107x/clock.h
delete mode 100644 arch/arm/include/asm/arch-tnetv107x/hardware.h
delete mode 100644 arch/arm/include/asm/arch-tnetv107x/mux.h
delete mode 100644 board/Marvell/aspenite/Kconfig
delete mode 100644 board/Marvell/aspenite/MAINTAINERS
delete mode 100644 board/Marvell/aspenite/Makefile
delete mode 100644 board/Marvell/aspenite/aspenite.c
delete mode 100644 board/Marvell/dkb/Kconfig
delete mode 100644 board/Marvell/dkb/MAINTAINERS
delete mode 100644 board/Marvell/dkb/Makefile
delete mode 100644 board/Marvell/dkb/dkb.c
delete mode 100644 board/Marvell/gplugd/Kconfig
delete mode 100644 board/Marvell/gplugd/MAINTAINERS
delete mode 100644 board/Marvell/gplugd/Makefile
delete mode 100644 board/Marvell/gplugd/gplugd.c
delete mode 100644 board/cm4008/Kconfig
delete mode 100644 board/cm4008/MAINTAINERS
delete mode 100644 board/cm4008/Makefile
delete mode 100644 board/cm4008/cm4008.c
delete mode 100644 board/cm4008/config.mk
delete mode 100644 board/cm4008/flash.c
delete mode 100644 board/cm41xx/Kconfig
delete mode 100644 board/cm41xx/MAINTAINERS
delete mode 100644 board/cm41xx/Makefile
delete mode 100644 board/cm41xx/cm41xx.c
delete mode 100644 board/cm41xx/config.mk
delete mode 100644 board/cm41xx/flash.c
delete mode 100644 board/davinci/da8xxevm/README.hawkboard
delete mode 100644 board/davinci/da8xxevm/hawkboard-ais-nand.cfg
delete mode 100644 board/davinci/da8xxevm/hawkboard.c
delete mode 100644 board/davinci/da8xxevm/u-boot-spl-hawk.lds
delete mode 100644 board/faraday/a320evb/Kconfig
delete mode 100644 board/faraday/a320evb/MAINTAINERS
delete mode 100644 board/faraday/a320evb/Makefile
delete mode 100644 board/faraday/a320evb/a320evb.c
delete mode 100644 board/faraday/a320evb/lowlevel_init.S
delete mode 100644 board/freescale/mx31ads/Kconfig
delete mode 100644 board/freescale/mx31ads/MAINTAINERS
delete mode 100644 board/freescale/mx31ads/Makefile
delete mode 100644 board/freescale/mx31ads/lowlevel_init.S
delete mode 100644 board/freescale/mx31ads/mx31ads.c
delete mode 100644 board/freescale/mx31ads/u-boot.lds
delete mode 100644 board/imx31_phycore/Kconfig
delete mode 100644 board/imx31_phycore/MAINTAINERS
delete mode 100644 board/imx31_phycore/Makefile
delete mode 100644 board/imx31_phycore/imx31_phycore.c
delete mode 100644 board/imx31_phycore/lowlevel_init.S
delete mode 100644 board/syteco/jadecpu/Kconfig
delete mode 100644 board/syteco/jadecpu/MAINTAINERS
delete mode 100644 board/syteco/jadecpu/Makefile
delete mode 100644 board/syteco/jadecpu/jadecpu.c
delete mode 100644 board/syteco/jadecpu/lowlevel_init.S
delete mode 100644 board/syteco/zmx25/Kconfig
delete mode 100644 board/syteco/zmx25/MAINTAINERS
delete mode 100644 board/syteco/zmx25/Makefile
delete mode 100644 board/syteco/zmx25/lowlevel_init.S
delete mode 100644 board/syteco/zmx25/zmx25.c
delete mode 100644 board/ti/tnetv107xevm/Kconfig
delete mode 100644 board/ti/tnetv107xevm/MAINTAINERS
delete mode 100644 board/ti/tnetv107xevm/Makefile
delete mode 100644 board/ti/tnetv107xevm/config.mk
delete mode 100644 board/ti/tnetv107xevm/sdb_board.c
delete mode 100644 board/timll/devkit3250/Kconfig
delete mode 100644 board/timll/devkit3250/MAINTAINERS
delete mode 100644 board/timll/devkit3250/Makefile
delete mode 100644 board/timll/devkit3250/devkit3250.c
delete mode 100644 configs/a320evb_defconfig
delete mode 100644 configs/aspenite_defconfig
delete mode 100644 configs/cm4008_defconfig
delete mode 100644 configs/cm41xx_defconfig
delete mode 100644 configs/devkit3250_defconfig
delete mode 100644 configs/dkb_defconfig
delete mode 100644 configs/gplugd_defconfig
delete mode 100644 configs/hawkboard_defconfig
delete mode 100644 configs/hawkboard_uart_defconfig
delete mode 100644 configs/imx31_phycore_defconfig
delete mode 100644 configs/imx31_phycore_eet_defconfig
delete mode 100644 configs/jadecpu_defconfig
delete mode 100644 configs/mx31ads_defconfig
delete mode 100644 configs/tnetv107x_evm_defconfig
delete mode 100644 configs/zmx25_defconfig
delete mode 100644 drivers/net/armada100_fec.c
delete mode 100644 drivers/net/armada100_fec.h
delete mode 100644 drivers/net/ks8695eth.c
delete mode 100644 drivers/serial/lpc32xx_hsuart.c
delete mode 100644 drivers/serial/serial_ks8695.c
delete mode 100644 drivers/spi/armada100_spi.c
delete mode 100644 drivers/usb/host/ehci-armada100.c
delete mode 100644 drivers/usb/host/utmi-armada100.c
delete mode 100644 drivers/video/mb86r0xgdc.c
delete mode 100644 drivers/watchdog/tnetv107x_wdt.c
delete mode 100644 include/configs/a320evb.h
delete mode 100644 include/configs/aspenite.h
delete mode 100644 include/configs/cm4008.h
delete mode 100644 include/configs/cm41xx.h
delete mode 100644 include/configs/devkit3250.h
delete mode 100644 include/configs/dkb.h
delete mode 100644 include/configs/gplugd.h
delete mode 100644 include/configs/hawkboard.h
delete mode 100644 include/configs/imx31_phycore.h
delete mode 100644 include/configs/jadecpu.h
delete mode 100644 include/configs/mx31ads.h
delete mode 100644 include/configs/tnetv107x_evm.h
delete mode 100644 include/configs/zmx25.h
--
1.9.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 01/11] ARM: remove mx31ads board support
2015-02-10 4:44 [U-Boot] [PATCH 0/11] ARM: remove non-generic boards Masahiro Yamada
@ 2015-02-10 4:44 ` Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 02/11] ARM: mx31: remove imx31_phycore board Masahiro Yamada
` (9 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 4:44 UTC (permalink / raw)
To: u-boot
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
arch/arm/Kconfig | 5 -
board/freescale/mx31ads/Kconfig | 15 --
board/freescale/mx31ads/MAINTAINERS | 6 -
board/freescale/mx31ads/Makefile | 8 -
board/freescale/mx31ads/lowlevel_init.S | 268 --------------------------------
board/freescale/mx31ads/mx31ads.c | 114 --------------
board/freescale/mx31ads/u-boot.lds | 110 -------------
configs/mx31ads_defconfig | 2 -
doc/README.scrapyard | 35 +++--
include/configs/mx31ads.h | 188 ----------------------
10 files changed, 18 insertions(+), 733 deletions(-)
delete mode 100644 board/freescale/mx31ads/Kconfig
delete mode 100644 board/freescale/mx31ads/MAINTAINERS
delete mode 100644 board/freescale/mx31ads/Makefile
delete mode 100644 board/freescale/mx31ads/lowlevel_init.S
delete mode 100644 board/freescale/mx31ads/mx31ads.c
delete mode 100644 board/freescale/mx31ads/u-boot.lds
delete mode 100644 configs/mx31ads_defconfig
delete mode 100644 include/configs/mx31ads.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 986b4c5..f12dac9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -373,10 +373,6 @@ config TARGET_QONG
bool "Support qong"
select CPU_ARM1136
-config TARGET_MX31ADS
- bool "Support mx31ads"
- select CPU_ARM1136
-
config TARGET_MX31PDK
bool "Support mx31pdk"
select CPU_ARM1136
@@ -919,7 +915,6 @@ source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx25pdk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
-source "board/freescale/mx31ads/Kconfig"
source "board/freescale/mx31pdk/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/mx51evk/Kconfig"
diff --git a/board/freescale/mx31ads/Kconfig b/board/freescale/mx31ads/Kconfig
deleted file mode 100644
index eeeb6f4..0000000
--- a/board/freescale/mx31ads/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_MX31ADS
-
-config SYS_BOARD
- default "mx31ads"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "mx31"
-
-config SYS_CONFIG_NAME
- default "mx31ads"
-
-endif
diff --git a/board/freescale/mx31ads/MAINTAINERS b/board/freescale/mx31ads/MAINTAINERS
deleted file mode 100644
index 5f6ec26..0000000
--- a/board/freescale/mx31ads/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MX31ADS BOARD
-#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
-S: Orphan (since 2013-09)
-F: board/freescale/mx31ads/
-F: include/configs/mx31ads.h
-F: configs/mx31ads_defconfig
diff --git a/board/freescale/mx31ads/Makefile b/board/freescale/mx31ads/Makefile
deleted file mode 100644
index 5e1440d..0000000
--- a/board/freescale/mx31ads/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mx31ads.o
-obj-y += lowlevel_init.o
diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S
deleted file mode 100644
index fcb5549..0000000
--- a/board/freescale/mx31ads/lowlevel_init.S
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/imx-regs.h>
-
-.macro REG reg, val
- ldr r2, =\reg
- ldr r3, =\val
- str r3, [r2]
-.endm
-
-.macro REG8 reg, val
- ldr r2, =\reg
- ldr r3, =\val
- strb r3, [r2]
-.endm
-
-.macro DELAY loops
- ldr r2, =\loops
-1:
- subs r2, r2, #1
- nop
- bcs 1b
-.endm
-
-/* RedBoot: AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- ldr r0, =0x43F00000
- ldr r1, =0x77777777
- str r1, [r0, #0x00]
- str r1, [r0, #0x04]
- ldr r0, =0x53F00000
- str r1, [r0, #0x00]
- str r1, [r0, #0x04]
-
- /*
- * Clear the on and off peripheral modules Supervisor Protect bit
- * for SDMA to access them. Did not change the AIPS control registers
- * (offset 0x20) access type
- */
- ldr r0, =0x43F00000
- ldr r1, =0x0
- str r1, [r0, #0x40]
- str r1, [r0, #0x44]
- str r1, [r0, #0x48]
- str r1, [r0, #0x4C]
- ldr r1, [r0, #0x50]
- and r1, r1, #0x00FFFFFF
- str r1, [r0, #0x50]
-
- ldr r0, =0x53F00000
- ldr r1, =0x0
- str r1, [r0, #0x40]
- str r1, [r0, #0x44]
- str r1, [r0, #0x48]
- str r1, [r0, #0x4C]
- ldr r1, [r0, #0x50]
- and r1, r1, #0x00FFFFFF
- str r1, [r0, #0x50]
-.endm /* init_aips */
-
-/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
-.macro init_max
- ldr r0, =0x43F04000
- /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
- ldr r1, =0x00302154
- str r1, [r0, #0x000] /* for S0 */
- str r1, [r0, #0x100] /* for S1 */
- str r1, [r0, #0x200] /* for S2 */
- str r1, [r0, #0x300] /* for S3 */
- str r1, [r0, #0x400] /* for S4 */
- /* SGPCR - always park on last master */
- ldr r1, =0x10
- str r1, [r0, #0x010] /* for S0 */
- str r1, [r0, #0x110] /* for S1 */
- str r1, [r0, #0x210] /* for S2 */
- str r1, [r0, #0x310] /* for S3 */
- str r1, [r0, #0x410] /* for S4 */
- /* MGPCR - restore default values */
- ldr r1, =0x0
- str r1, [r0, #0x800] /* for M0 */
- str r1, [r0, #0x900] /* for M1 */
- str r1, [r0, #0xA00] /* for M2 */
- str r1, [r0, #0xB00] /* for M3 */
- str r1, [r0, #0xC00] /* for M4 */
- str r1, [r0, #0xD00] /* for M5 */
-.endm /* init_max */
-
-/* RedBoot: M3IF setup */
-.macro init_m3if
- /* Configure M3IF registers */
- ldr r1, =0xB8003000
- /*
- * M3IF Control Register (M3IFCTL)
- * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
- * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
- * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
- * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
- * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
- * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
- * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
- * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
- * ------------
- * 0x00000040
- */
- ldr r0, =0x00000040
- str r0, [r1] /* M3IF control reg */
-.endm /* init_m3if */
-
-/* RedBoot: To support 133MHz DDR */
-.macro init_drive_strength
- /*
- * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
- * in SW_PAD_CTL registers
- */
-
- /* SDCLK */
- ldr r1, =0x43FAC200
- ldr r0, [r1, #0x6C]
- bic r0, r0, #(1 << 12)
- str r0, [r1, #0x6C]
-
- /* CAS */
- ldr r0, [r1, #0x70]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x70]
-
- /* RAS */
- ldr r0, [r1, #0x74]
- bic r0, r0, #(1 << 2)
- str r0, [r1, #0x74]
-
- /* CS2 (CSD0) */
- ldr r0, [r1, #0x7C]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x7C]
-
- /* DQM3 */
- ldr r0, [r1, #0x84]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x84]
-
- /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
- ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
-pad_loop:
- ldr r0, [r1, #0x88]
- bic r0, r0, #(1 << 22)
- bic r0, r0, #(1 << 12)
- bic r0, r0, #(1 << 2)
- str r0, [r1, #0x88]
- add r1, r1, #4
- subs r2, r2, #0x1
- bne pad_loop
-.endm /* init_drive_strength */
-
-/* CPLD on CS4 setup */
-.macro init_cs4
- ldr r0, =WEIM_BASE
- ldr r1, =0x0000D843
- str r1, [r0, #0x40]
- ldr r1, =0x22252521
- str r1, [r0, #0x44]
- ldr r1, =0x22220A00
- str r1, [r0, #0x48]
-.endm /* init_cs4 */
-
-.globl lowlevel_init
-lowlevel_init:
-
- /* Redboot initializes very early AIPS, what for?
- * Then it also initializes Multi-Layer AHB Crossbar Switch,
- * M3IF */
- /* Also setup the Peripheral Port Remap register inside the core */
- ldr r0, =0x40000015 /* start from AIPS 2GB region */
- mcr p15, 0, r0, c15, c2, 4
-
- init_aips
-
- init_max
-
- init_m3if
-
- init_drive_strength
-
- init_cs4
-
- /* Image Processing Unit: */
- /* Too early to switch display on? */
- REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */
- /* Clock Control Module: */
- REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
-
- DELAY 0x40000
-
- REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
- REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */
-
- /* PBC CPLD on CS4 */
- mov r1, #CS4_BASE
- ldrh r1, [r1, #0x2]
- /* Is 27MHz switch set? */
- ands r1, r1, #0x10
-
- /* 532-133-66.5 */
- ldr r0, =CCM_BASE
- ldr r1, =0xFF871D58
- /* PDR0 */
- str r1, [r0, #0x4]
- ldreq r1, MPCTL_PARAM_532
- ldrne r1, MPCTL_PARAM_532_27
- /* MPCTL */
- str r1, [r0, #0x10]
-
- /* Set UPLL=240MHz, USB=60MHz */
- ldr r1, =0x49FCFE7F
- /* PDR1 */
- str r1, [r0, #0x8]
- ldreq r1, UPCTL_PARAM_240
- ldrne r1, UPCTL_PARAM_240_27
- /* UPCTL */
- str r1, [r0, #0x14]
- /* default CLKO to 1/8 of the ARM core */
- mov r1, #0x000002C0
- add r1, r1, #0x00000006
- /* COSR */
- str r1, [r0, #0x1c]
-
- /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
-/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
-
- /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
-/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
- /* Default: 1, 4, 12, 1 */
- REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
-
- /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
- REG 0xB8001010, 0x00000004
- REG 0xB8001004, 0x006ac73a
- REG 0xB8001000, 0x92100000
- REG 0x80000f00, 0x12344321
- REG 0xB8001000, 0xa2100000
- REG 0x80000000, 0x12344321
- REG 0x80000000, 0x12344321
- REG 0xB8001000, 0xb2100000
- REG8 0x80000033, 0xda
- REG8 0x81000000, 0xff
- REG 0xB8001000, 0x82226080
- REG 0x80000000, 0xDEADBEEF
- REG 0xB8001010, 0x0000000c
-
- mov pc, lr
-
-MPCTL_PARAM_532:
- .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
-MPCTL_PARAM_532_27:
- .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
-UPCTL_PARAM_240:
- .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
-UPCTL_PARAM_240_27:
- .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c
deleted file mode 100644
index ad89cb0..0000000
--- a/board/freescale/mx31ads/mx31ads.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-int board_early_init_f(void)
-{
- int i;
-
- /* CS0: Nor Flash */
- /*
- * CS0L and CS0A values are from the RedBoot sources by Freescale
- * and are also equal to those used by Sascha Hauer for the Phytec
- * i.MX31 board. CS0U is just a slightly optimized hardware default:
- * the only non-zero field "Wait State Control" is set to half the
- * default value.
- */
- static const struct mxc_weimcs cs0 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
- };
-
- mxc_setup_weimcs(0, &cs0);
-
- /* setup pins for UART1 */
- mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
- mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
- mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
- mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
- /* SPI2 */
- mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
- mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
- mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
- mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
- mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
- mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
- mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
-
- /* start SPI2 clock */
- __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
-
- /* PBC setup */
- /* Enable UART transceivers also reset the Ethernet/external UART */
- readw(CS4_BASE + 4);
-
- writew(0x8023, CS4_BASE + 4);
-
- /* RedBoot also has an empty loop with 100000 iterations here -
- * clock doesn't run yet */
- for (i = 0; i < 100000; i++)
- ;
-
- /* Clear the reset, toggle the LEDs */
- writew(0xDF, CS4_BASE + 6);
-
- /* clock still doesn't run */
- for (i = 0; i < 100000; i++)
- ;
-
- /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
- readb(CS4_BASE + 8);
- readb(CS4_BASE + 7);
- readb(CS4_BASE + 8);
- readb(CS4_BASE + 7);
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
-
- return 0;
-}
-
-int checkboard(void)
-{
- printf("Board: MX31ADS\n");
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_CS8900
- rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
deleted file mode 100644
index 8a4a8a2..0000000
--- a/board/freescale/mx31ads/u-boot.lds
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- * (.vectors)
- arch/arm/cpu/arm1136/start.o (.text*)
- board/freescale/mx31ads/built-in.o (.text*)
- arch/arm/lib/built-in.o (.text*)
- net/built-in.o (.text*)
- drivers/mtd/built-in.o (.text*)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o(.text*)
-
- *(.text*)
- }
- . = ALIGN(4);
- .rodata : { *(.rodata*) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .hash : { *(.hash*) }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .gnu.hash : { *(.gnu.hash) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/configs/mx31ads_defconfig b/configs/mx31ads_defconfig
deleted file mode 100644
index 5105a9a..0000000
--- a/configs/mx31ads_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_MX31ADS=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 952ab87..c6f3d14 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,23 +12,24 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-icecube_5200 powerpc mpc5xxx - - Wolfgang Denk <wd@denx.de>
-Lite5200 powerpc mpc5xxx - -
-cpci5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-mecp5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-pf5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-PM520 powerpc mpc5xxx - - Josef Wagner <Wagner@Microsys.de>
-Total5200 powerpc mpc5xxx - -
-CATcenter powerpc ppc4xx - -
-PPChameleonEVB powerpc ppc4xx - - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-P2020DS powerpc mpc85xx - -
-P2020COME powerpc mpc85xx - - Ira W. Snyder <iws@ovro.caltech.edu>
-P2020RDB powerpc mpc85xx - - Poonam Aggrwal <poonam.aggrwal@freescale.com>
-P2010RDB powerpc mpc85xx - -
-P1020RDB powerpc mpc85xx - -
-P1011RDB powerpc mpc85xx - -
-MPC8360EMDS powerpc mpc83xx - - Dave Liu <daveliu@freescale.com>
-MPC8360ERDK powerpc mpc83xx - - Anton Vorontsov <avorontsov@ru.mvista.com>
+mx31ads arm arm1136 - - Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de>
+Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23
+cpci5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+mecp5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+pf5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+PM520 powerpc mpc5xxx a258e732 2015-01-23 Josef Wagner <Wagner@Microsys.de>
+Total5200 powerpc mpc5xxx ad734f7d 2015-01-23
+CATcenter powerpc ppc4xx 5344cc1a 2015-01-23
+PPChameleonEVB powerpc ppc4xx 5344cc1a 2015-01-23 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+P2020DS powerpc mpc85xx 168dcc6c 2015-01-23
+P2020COME powerpc mpc85xx 89123536 2015-01-23 Ira W. Snyder <iws@ovro.caltech.edu>
+P2020RDB powerpc mpc85xx 743d4815 2015-01-23 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+P2010RDB powerpc mpc85xx 743d4815 2015-01-23
+P1020RDB powerpc mpc85xx 743d4815 2015-01-23
+P1011RDB powerpc mpc85xx 743d4815 2015-01-23
+MPC8360EMDS powerpc mpc83xx 8d1e3cb1 2015-01-23 Dave Liu <daveliu@freescale.com>
+MPC8360ERDK powerpc mpc83xx 8d1e3cb1 2015-01-23 Anton Vorontsov <avorontsov@ru.mvista.com>
P3G4 powerpc 74xx_7xx d928664f 2015-01-16 Wolfgang Denk <wd@denx.de>
ZUMA powerpc 74xx_7xx d928664f 2015-01-16 Nye Liu <nyet@zumanetworks.com>
ppmc7xx powerpc 74xx_7xx d928664f 2015-01-16
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
deleted file mode 100644
index 0f4bd91..0000000
--- a/include/configs/mx31ads.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
- *
- * Configuration settings for the MX31ADS Freescale board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
- /* High Level Configuration Options */
-#define CONFIG_MX31 1 /* This is a mx31 */
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_TEXT_BASE 0xA0000000
-
-#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS
-
-/*
- * Disabled for now due to build problems under Debian and a significant increase
- * in the final file size: 144260 vs. 109536 Bytes.
- */
-#if 0
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_FIT 1
-#define CONFIG_FIT_VERBOSE 1
-#endif
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-#define CONFIG_HARD_SPI 1
-#define CONFIG_MXC_SPI 1
-#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_MXC_GPIO
-
-/* PMIC Controller */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-#define CONFIG_FSL_PMIC_BUS 1
-#define CONFIG_FSL_PMIC_CS 0
-#define CONFIG_FSL_PMIC_CLK 1000000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13XXX
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_DATE
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot_addr=0xa0000000\0" \
- "uboot=mx31ads/u-boot.bin\0" \
- "kernel=mx31ads/uImage\0" \
- "nfsroot=/opt/eldk/arm\0" \
- "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
- "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "bootcmd=run bootcmd_net\0" \
- "bootcmd_net=run bootargs_base bootargs_nfs; " \
- "tftpboot ${loadaddr} ${kernel}; bootm\0" \
- "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
- "protect off ${uboot_addr} 0xa003ffff; " \
- "erase ${uboot_addr} 0xa003ffff; " \
- "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
- "setenv filesize; saveenv\0"
-
-#define CONFIG_CS8900
-#define CONFIG_CS8900_BASE 0xb4020300
-#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */
-
-/*
- * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
- * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
- * controller inverted. The controller is capable of detecting and correcting
- * this, but it needs 4 network packets for that. Which means, at startup, you
- * will not receive answers to the first 4 packest, unless there have been some
- * broadcasts on the network, or your board is on a hub. Reducing the ARP
- * timeout from default 5 seconds to 200ms we speed up the initial TFTP
- * transfer, should the user wish one, significantly.
- */
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x10000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING 1
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CSD0_BASE
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
-#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
-
-/*
- * JFFS2 partitions
- */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 02/11] ARM: mx31: remove imx31_phycore board
2015-02-10 4:44 [U-Boot] [PATCH 0/11] ARM: remove non-generic boards Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 01/11] ARM: remove mx31ads board support Masahiro Yamada
@ 2015-02-10 4:44 ` Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 03/11] ARM: remove jadecpu board support Masahiro Yamada
` (8 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 4:44 UTC (permalink / raw)
To: u-boot
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
arch/arm/Kconfig | 5 -
board/imx31_phycore/Kconfig | 12 ---
board/imx31_phycore/MAINTAINERS | 11 --
board/imx31_phycore/Makefile | 9 --
board/imx31_phycore/imx31_phycore.c | 153 ---------------------------
board/imx31_phycore/lowlevel_init.S | 88 ----------------
configs/imx31_phycore_defconfig | 2 -
configs/imx31_phycore_eet_defconfig | 3 -
doc/README.scrapyard | 1 +
include/configs/imx31_phycore.h | 202 ------------------------------------
10 files changed, 1 insertion(+), 485 deletions(-)
delete mode 100644 board/imx31_phycore/Kconfig
delete mode 100644 board/imx31_phycore/MAINTAINERS
delete mode 100644 board/imx31_phycore/Makefile
delete mode 100644 board/imx31_phycore/imx31_phycore.c
delete mode 100644 board/imx31_phycore/lowlevel_init.S
delete mode 100644 configs/imx31_phycore_defconfig
delete mode 100644 configs/imx31_phycore_eet_defconfig
delete mode 100644 include/configs/imx31_phycore.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f12dac9..d49142e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -365,10 +365,6 @@ config TARGET_INTEGRATORCP_CM1136
bool "Support integratorcp_cm1136"
select CPU_ARM1136
-config TARGET_IMX31_PHYCORE
- bool "Support imx31_phycore"
- select CPU_ARM1136
-
config TARGET_QONG
bool "Support qong"
select CPU_ARM1136
@@ -934,7 +930,6 @@ source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hale/tt01/Kconfig"
source "board/icpdas/lp8x4x/Kconfig"
-source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/jornada/Kconfig"
source "board/karo/tx25/Kconfig"
diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig
deleted file mode 100644
index d3d2025..0000000
--- a/board/imx31_phycore/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_IMX31_PHYCORE
-
-config SYS_BOARD
- default "imx31_phycore"
-
-config SYS_SOC
- default "mx31"
-
-config SYS_CONFIG_NAME
- default "imx31_phycore"
-
-endif
diff --git a/board/imx31_phycore/MAINTAINERS b/board/imx31_phycore/MAINTAINERS
deleted file mode 100644
index 41f6cae..0000000
--- a/board/imx31_phycore/MAINTAINERS
+++ /dev/null
@@ -1,11 +0,0 @@
-IMX31_PHYCORE BOARD
-#M: -
-S: Maintained
-F: board/imx31_phycore/
-F: include/configs/imx31_phycore.h
-F: configs/imx31_phycore_defconfig
-
-IMX31_PHYCORE_EET BOARD
-#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
-S: Orphan (since 2013-09)
-F: configs/imx31_phycore_eet_defconfig
diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile
deleted file mode 100644
index e781c13..0000000
--- a/board/imx31_phycore/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := imx31_phycore.o
-obj-y += lowlevel_init.o
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
deleted file mode 100644
index 3f45e4e..0000000
--- a/board/imx31_phycore/imx31_phycore.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <s6e63d6.h>
-#include <netdev.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-int board_init(void)
-{
-
- gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */
- gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /* CS0: Nor Flash */
- static const struct mxc_weimcs cs0 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
- };
-
- /* CS1: Network Controller */
- static const struct mxc_weimcs cs1 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
- };
-
- /* CS4: SRAM */
- static const struct mxc_weimcs cs4 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
- };
-
- mxc_setup_weimcs(0, &cs0);
- mxc_setup_weimcs(1, &cs1);
- mxc_setup_weimcs(4, &cs4);
-
- /* setup pins for UART1 */
- mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
- mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
- mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
- mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
- /* setup pins for I2C2 (for EEPROM, RTC) */
- mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
- mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_S6E63D6
- struct s6e63d6 data = {
- /*
- * See comment in mxc_spi.c::decode_cs() for .cs field format.
- * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
- * 2 of the SPI controller #1, since it is unused.
- */
- .cs = 2 | (57 << 8),
- .bus = 0,
- .id = 0,
- };
- int ret;
-
- /* SPI1 */
- mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
- mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
- mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
- mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
- mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
- mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
- mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
-
- /* start SPI1 clock */
- __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
-
- /* GPIO 57 */
- /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
- mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
-
- /* SPI1 CS2 is free */
- ret = s6e63d6_init(&data);
- if (ret)
- return ret;
-
- /*
- * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
- * OLED display connected to a S6E63D6 SPI display controller in the
- * 18 bit RGB mode
- */
- s6e63d6_index(&data, 2);
- s6e63d6_param(&data, 0x0182);
- s6e63d6_index(&data, 3);
- s6e63d6_param(&data, 0x8130);
- s6e63d6_index(&data, 0x10);
- s6e63d6_param(&data, 0x0000);
- s6e63d6_index(&data, 5);
- s6e63d6_param(&data, 0x0001);
- s6e63d6_index(&data, 0x22);
-#endif
- return 0;
-}
-#endif
-
-int checkboard (void)
-{
- printf("Board: Phytec phyCore i.MX31\n");
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S
deleted file mode 100644
index 6ea3878..0000000
--- a/board/imx31_phycore/lowlevel_init.S
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/imx-regs.h>
-
-.macro REG reg, val
- ldr r2, =\reg
- ldr r3, =\val
- str r3, [r2]
-.endm
-
-.macro REG8 reg, val
- ldr r2, =\reg
- ldr r3, =\val
- strb r3, [r2]
-.endm
-
-.macro DELAY loops
- ldr r2, =\loops
-1:
- subs r2, r2, #1
- nop
- bcs 1b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-
- REG IPU_CONF, IPU_CONF_DI_EN
- REG CCM_CCMR, 0x074B0BF5
-
- DELAY 0x40000
-
- REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
- REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
-
- REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
-
- REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
-
- REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
-
- REG 0x43FAC26C, 0 /* SDCLK */
- REG 0x43FAC270, 0 /* CAS */
- REG 0x43FAC274, 0 /* RAS */
- REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */
- REG 0x43FAC284, 0 /* DQM3 */
- REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
- REG 0x43FAC28C, 0
- REG 0x43FAC290, 0
- REG 0x43FAC294, 0
- REG 0x43FAC298, 0
- REG 0x43FAC29C, 0
- REG 0x43FAC2A0, 0
- REG 0x43FAC2A4, 0
- REG 0x43FAC2A8, 0
- REG 0x43FAC2AC, 0
- REG 0x43FAC2B0, 0
- REG 0x43FAC2B4, 0
- REG 0x43FAC2B8, 0
- REG 0x43FAC2BC, 0
- REG 0x43FAC2C0, 0
- REG 0x43FAC2C4, 0
- REG 0x43FAC2C8, 0
- REG 0x43FAC2CC, 0
- REG 0x43FAC2D0, 0
- REG 0x43FAC2D4, 0
- REG 0x43FAC2D8, 0
- REG 0x43FAC2DC, 0
- REG 0xB8001010, 0x00000004
- REG 0xB8001004, 0x006ac73a
- REG 0xB8001000, 0x92100000
- REG 0x80000f00, 0x12344321
- REG 0xB8001000, 0xa2100000
- REG 0x80000000, 0x12344321
- REG 0x80000000, 0x12344321
- REG 0xB8001000, 0xb2100000
- REG8 0x80000033, 0xda
- REG8 0x81000000, 0xff
- REG 0xB8001000, 0x82226080
- REG 0x80000000, 0xDEADBEEF
- REG 0xB8001010, 0x0000000c
-
- mov pc, lr
diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig
deleted file mode 100644
index 563de57..0000000
--- a/configs/imx31_phycore_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_IMX31_PHYCORE=y
diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig
deleted file mode 100644
index 9531952..0000000
--- a/configs/imx31_phycore_eet_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET"
-CONFIG_ARM=y
-CONFIG_TARGET_IMX31_PHYCORE=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index c6f3d14..cd51249 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+imx31_phycore arm arm1136 - - Guennadi Liakhovetski <g.liakhovetski@gmx.de>
mx31ads arm arm1136 - - Guennadi Liakhovetski <g.liakhovetski@gmx.de>
icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de>
Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
deleted file mode 100644
index 4195fa3..0000000
--- a/include/configs/imx31_phycore.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Kshitij Gupta <kshitij@ti.com>
- *
- * Configuration settings for the phyCORE-i.MX31 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-/* High Level Configuration Options */
-#define CONFIG_MX31 /* This is a mx31 */
-#define CONFIG_MX31_CLK32 32000
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-
-#define CONFIG_BOOTDELAY 3
-
-#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \
- "1536k(kernel),-(root)"
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.23.168
-#define CONFIG_SERVERIP 192.168.23.2
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
- "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
- "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
- "bootargs_flash=setenv bootargs $(bootargs) " \
- "root=/dev/mtdblock2 rootfstype=jffs2\0" \
- "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
- "bootcmd=run bootcmd_net\0" \
- "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \
- "tftpboot 0x80000000 $(uimage);bootm\0" \
- "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \
- "bootm 0x80000000\0" \
- "unlock=yes\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "prg_uboot=tftpboot 0x80000000 $(uboot);" \
- "protect off 0xa0000000 +0x20000;" \
- "erase 0xa0000000 +0x20000;" \
- "cp.b 0x80000000 0xa0000000 $(filesize)\0" \
- "prg_kernel=tftpboot 0x80000000 $(uimage);" \
- "erase 0xa0040000 +0x180000;" \
- "cp.b 0x80000000 0xa0040000 $(filesize)\0" \
- "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \
- "erase 0xa01c0000 0xa1ffffff;" \
- "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
- "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \
- "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
- "sync:1241513985,vmode:0\0"
-
-
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_BASE 0xa8000000
-#define CONFIG_SMC911X_32_BIT
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "uboot> "
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x10000
-
-#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
-
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SYS_TEXT_BASE 0xA0000000
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE 0xa0000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */
-/* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */
-#define CONFIG_ENV_SIZE 4096
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */
-
-/*
- * CFI FLASH driver setup
- */
-#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
-
-/*
- * Timeout for Flash Erase and Flash Write
- * timeout values are in ticks
- */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ)
-
-/*
- * JFFS2 partitions
- */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-
-/* EET platform additions */
-#ifdef CONFIG_IMX31_PHYCORE_EET
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_MXC_GPIO
-
-#define CONFIG_HARD_SPI
-#define CONFIG_MXC_SPI
-#define CONFIG_CMD_SPI
-
-#define CONFIG_S6E63D6
-
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_MX3
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_CMD_BMP
-#define CONFIG_BMP_16BPP
-#endif
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 03/11] ARM: remove jadecpu board support
2015-02-10 4:44 [U-Boot] [PATCH 0/11] ARM: remove non-generic boards Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 01/11] ARM: remove mx31ads board support Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 02/11] ARM: mx31: remove imx31_phycore board Masahiro Yamada
@ 2015-02-10 4:44 ` Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 04/11] ARM: remove zmx25 " Masahiro Yamada
` (7 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 4:44 UTC (permalink / raw)
To: u-boot
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Matthias Weisser <weisserm@arcor.de>
---
arch/arm/Kconfig | 5 -
arch/arm/cpu/arm926ejs/Makefile | 1 -
arch/arm/cpu/arm926ejs/mb86r0x/Makefile | 8 -
arch/arm/cpu/arm926ejs/mb86r0x/clock.c | 27 --
arch/arm/cpu/arm926ejs/mb86r0x/reset.c | 24 --
arch/arm/cpu/arm926ejs/mb86r0x/timer.c | 115 -----
arch/arm/include/asm/arch-mb86r0x/hardware.h | 15 -
arch/arm/include/asm/arch-mb86r0x/mb86r0x.h | 599 ---------------------------
arch/arm/lib/asm-offsets.c | 46 --
board/syteco/jadecpu/Kconfig | 15 -
board/syteco/jadecpu/MAINTAINERS | 6 -
board/syteco/jadecpu/Makefile | 13 -
board/syteco/jadecpu/jadecpu.c | 160 -------
board/syteco/jadecpu/lowlevel_init.S | 249 -----------
configs/jadecpu_defconfig | 2 -
doc/README.scrapyard | 1 +
drivers/video/Makefile | 1 -
drivers/video/mb86r0xgdc.c | 168 --------
include/configs/jadecpu.h | 273 ------------
include/serial.h | 2 +-
20 files changed, 2 insertions(+), 1728 deletions(-)
delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/Makefile
delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/clock.c
delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/reset.c
delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/timer.c
delete mode 100644 arch/arm/include/asm/arch-mb86r0x/hardware.h
delete mode 100644 arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
delete mode 100644 board/syteco/jadecpu/Kconfig
delete mode 100644 board/syteco/jadecpu/MAINTAINERS
delete mode 100644 board/syteco/jadecpu/Makefile
delete mode 100644 board/syteco/jadecpu/jadecpu.c
delete mode 100644 board/syteco/jadecpu/lowlevel_init.S
delete mode 100644 configs/jadecpu_defconfig
delete mode 100644 drivers/video/mb86r0xgdc.c
delete mode 100644 include/configs/jadecpu.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d49142e..3ade156 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -245,10 +245,6 @@ config TARGET_DEVKIT3250
bool "Support devkit3250"
select CPU_ARM926EJS
-config TARGET_JADECPU
- bool "Support jadecpu"
- select CPU_ARM926EJS
-
config TARGET_MX25PDK
bool "Support mx25pdk"
select CPU_ARM926EJS
@@ -969,7 +965,6 @@ source "board/st-ericsson/snowball/Kconfig"
source "board/st-ericsson/u8500/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
-source "board/syteco/jadecpu/Kconfig"
source "board/syteco/zmx25/Kconfig"
source "board/taskit/stamp9g20/Kconfig"
source "board/tbs/tbs2910/Kconfig"
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index adcea9f..607d29f 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_AT91FAMILY) += at91/
obj-$(CONFIG_ARCH_DAVINCI) += davinci/
obj-$(CONFIG_KIRKWOOD) += kirkwood/
obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
-obj-$(CONFIG_MB86R0x) += mb86r0x/
obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
deleted file mode 100644
index 365892c..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = clock.o reset.o timer.o
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
deleted file mode 100644
index 1f6f66e..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Get the peripheral bus frequency depending on pll pin settings
- */
-ulong get_bus_freq(ulong dummy)
-{
- struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
- MB86R0x_CRG_BASE;
- uint32_t pllmode;
-
- pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE;
-
- if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20)
- return 40000000;
-
- return 41164767;
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
deleted file mode 100644
index 7bd77ff..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Reset the cpu by setting software reset request bit
- */
-void reset_cpu(ulong ignored)
-{
- struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
- MB86R0x_CRG_BASE;
-
- writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr);
- while (1)
- /* NOP */;
- /* Never reached */
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
deleted file mode 100644
index bb07819..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2010
- * Matthias Weisser, Graf-Syteco <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <div64.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, TIMER_FREQ);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= TIMER_FREQ;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int timer_init(void)
-{
- struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
- MB86R0x_TIMER_BASE;
- ulong ctrl = readl(&timer->control);
-
- writel(TIMER_LOAD_VAL, &timer->load);
-
- ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S |
- MB86R0x_TIMER_SIZE_32;
-
- writel(ctrl, &timer->control);
-
- /* capture current value time */
- lastdec = readl(&timer->value);
- timestamp = 0; /* start "advancing" time stamp from 0 */
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-unsigned long long get_ticks(void)
-{
- struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
- MB86R0x_TIMER_BASE;
- ulong now = readl(&timer->value);
-
- if (now <= lastdec) {
- /* normal mode (non roll) */
- /* move stamp forward with absolut diff ticks */
- timestamp += lastdec - now;
- } else {
- /* we have rollover of incrementer */
- timestamp += lastdec + TIMER_LOAD_VAL - now;
- }
- lastdec = now;
- return timestamp;
-}
-
-ulong get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long tmp;
- ulong tmo;
-
- tmo = usec_to_tick(usec);
- tmp = get_ticks(); /* get current timestamp */
-
- while ((get_ticks() - tmp) < tmo) /* loop till event */
- /*NOP*/;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- ulong tbclk;
-
- tbclk = TIMER_FREQ;
- return tbclk;
-}
diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h
deleted file mode 100644
index 42a52bc..0000000
--- a/arch/arm/include/asm/arch-mb86r0x/hardware.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2007
- *
- * Author : Carsten Schneider, mycable GmbH
- * <cs@mycable.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <linux/sizes.h>
-#include <asm/arch/mb86r0x.h>
-
-#endif
diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
deleted file mode 100644
index 7fec971..0000000
--- a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- * (C) Copyright 2007
- *
- * mb86r0x definitions
- *
- * Author : Carsten Schneider, mycable GmbH
- * <cs@mycable.de>
- *
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef MB86R0X_H
-#define MB86R0X_H
-
-#ifndef __ASSEMBLY__
-
-/* GPIO registers */
-struct mb86r0x_gpio {
- uint32_t gpdr0;
- uint32_t gpdr1;
- uint32_t gpdr2;
- uint32_t res;
- uint32_t gpddr0;
- uint32_t gpddr1;
- uint32_t gpddr2;
-};
-
-/* PWM registers */
-struct mb86r0x_pwm {
- uint32_t bcr;
- uint32_t tpr;
- uint32_t pr;
- uint32_t dr;
- uint32_t cr;
- uint32_t sr;
- uint32_t ccr;
- uint32_t ir;
-};
-
-/* The mb86r0x chip control (CCNT) register set. */
-struct mb86r0x_ccnt {
- uint32_t ccid;
- uint32_t csrst;
- uint32_t pad0[2];
- uint32_t cist;
- uint32_t cistm;
- uint32_t cgpio_ist;
- uint32_t cgpio_istm;
- uint32_t cgpio_ip;
- uint32_t cgpio_im;
- uint32_t caxi_bw;
- uint32_t caxi_ps;
- uint32_t cmux_md;
- uint32_t cex_pin_st;
- uint32_t cmlb;
- uint32_t pad1[1];
- uint32_t cusb;
- uint32_t pad2[41];
- uint32_t cbsc;
- uint32_t cdcrc;
- uint32_t cmsr0;
- uint32_t cmsr1;
- uint32_t pad3[2];
-};
-
-/* The mb86r0x clock reset generator */
-struct mb86r0x_crg {
- uint32_t crpr;
- uint32_t pad0;
- uint32_t crwr;
- uint32_t crsr;
- uint32_t crda;
- uint32_t crdb;
- uint32_t crha;
- uint32_t crpa;
- uint32_t crpb;
- uint32_t crhb;
- uint32_t cram;
-};
-
-/* The mb86r0x timer */
-struct mb86r0x_timer {
- uint32_t load;
- uint32_t value;
- uint32_t control;
- uint32_t intclr;
- uint32_t ris;
- uint32_t mis;
- uint32_t bgload;
-};
-
-/* mb86r0x gdc display controller */
-struct mb86r0x_gdc_dsp {
- /* Display settings */
- uint32_t dcm0;
- uint16_t pad00;
- uint16_t htp;
- uint16_t hdp;
- uint16_t hdb;
- uint16_t hsp;
- uint8_t hsw;
- uint8_t vsw;
- uint16_t pad01;
- uint16_t vtr;
- uint16_t vsp;
- uint16_t vdp;
- uint16_t wx;
- uint16_t wy;
- uint16_t ww;
- uint16_t wh;
-
- /* Layer 0 */
- uint32_t l0m;
- uint32_t l0oa;
- uint32_t l0da;
- uint16_t l0dx;
- uint16_t l0dy;
-
- /* Layer 1 */
- uint32_t l1m;
- uint32_t cbda0;
- uint32_t cbda1;
- uint32_t pad02;
-
- /* Layer 2 */
- uint32_t l2m;
- uint32_t l2oa0;
- uint32_t l2da0;
- uint32_t l2oa1;
- uint32_t l2da1;
- uint16_t l2dx;
- uint16_t l2dy;
-
- /* Layer 3 */
- uint32_t l3m;
- uint32_t l3oa0;
- uint32_t l3da0;
- uint32_t l3oa1;
- uint32_t l3da1;
- uint16_t l3dx;
- uint16_t l3dy;
-
- /* Layer 4 */
- uint32_t l4m;
- uint32_t l4oa0;
- uint32_t l4da0;
- uint32_t l4oa1;
- uint32_t l4da1;
- uint16_t l4dx;
- uint16_t l4dy;
-
- /* Layer 5 */
- uint32_t l5m;
- uint32_t l5oa0;
- uint32_t l5da0;
- uint32_t l5oa1;
- uint32_t l5da1;
- uint16_t l5dx;
- uint16_t l5dy;
-
- /* Cursor */
- uint16_t cutc;
- uint8_t cpm;
- uint8_t csize;
- uint32_t cuoa0;
- uint16_t cux0;
- uint16_t cuy0;
- uint32_t cuoa1;
- uint16_t cux1;
- uint16_t cuy1;
-
- /* Layer blending */
- uint32_t l0bld;
- uint32_t pad03;
- uint32_t l0tc;
- uint16_t l3tc;
- uint16_t l2tc;
- uint32_t pad04[15];
-
- /* Display settings */
- uint32_t dcm1;
- uint32_t dcm2;
- uint32_t dcm3;
- uint32_t pad05;
-
- /* Layer 0 extended */
- uint32_t l0em;
- uint16_t l0wx;
- uint16_t l0wy;
- uint16_t l0ww;
- uint16_t l0wh;
- uint32_t pad06;
-
- /* Layer 1 extended */
- uint32_t l1em;
- uint16_t l1wx;
- uint16_t l1wy;
- uint16_t l1ww;
- uint16_t l1wh;
- uint32_t pad07;
-
- /* Layer 2 extended */
- uint32_t l2em;
- uint16_t l2wx;
- uint16_t l2wy;
- uint16_t l2ww;
- uint16_t l2wh;
- uint32_t pad08;
-
- /* Layer 3 extended */
- uint32_t l3em;
- uint16_t l3wx;
- uint16_t l3wy;
- uint16_t l3ww;
- uint16_t l3wh;
- uint32_t pad09;
-
- /* Layer 4 extended */
- uint32_t l4em;
- uint16_t l4wx;
- uint16_t l4wy;
- uint16_t l4ww;
- uint16_t l4wh;
- uint32_t pad10;
-
- /* Layer 5 extended */
- uint32_t l5em;
- uint16_t l5wx;
- uint16_t l5wy;
- uint16_t l5ww;
- uint16_t l5wh;
- uint32_t pad11;
-
- /* Multi screen control */
- uint32_t msc;
- uint32_t pad12[3];
- uint32_t dls;
- uint32_t dbgc;
-
- /* Layer blending */
- uint32_t l1bld;
- uint32_t l2bld;
- uint32_t l3bld;
- uint32_t l4bld;
- uint32_t l5bld;
- uint32_t pad13;
-
- /* Extended transparency control */
- uint32_t l0etc;
- uint32_t l1etc;
- uint32_t l2etc;
- uint32_t l3etc;
- uint32_t l4etc;
- uint32_t l5etc;
- uint32_t pad14[10];
-
- /* YUV coefficients */
- uint32_t l1ycr0;
- uint32_t l1ycr1;
- uint32_t l1ycg0;
- uint32_t l1ycg1;
- uint32_t l1ycb0;
- uint32_t l1ycb1;
- uint32_t pad15[130];
-
- /* Layer palletes */
- uint32_t l0pal[256];
- uint32_t l1pal[256];
- uint32_t pad16[256];
- uint32_t l2pal[256];
- uint32_t l3pal[256];
- uint32_t pad17[256];
-
- /* PWM settings */
- uint32_t vpwmm;
- uint16_t vpwms;
- uint16_t vpwme;
- uint32_t vpwmc;
- uint32_t pad18[253];
-};
-
-/* mb86r0x gdc capture controller */
-struct mb86r0x_gdc_cap {
- uint32_t vcm;
- uint32_t csc;
- uint32_t vcs;
- uint32_t pad01;
-
- uint32_t cbm;
- uint32_t cboa;
- uint32_t cbla;
- uint16_t cihstr;
- uint16_t civstr;
- uint16_t cihend;
- uint16_t civend;
- uint32_t pad02;
-
- uint32_t chp;
- uint32_t cvp;
- uint32_t pad03[4];
-
- uint32_t clpf;
- uint32_t pad04;
- uint32_t cmss;
- uint32_t cmds;
- uint32_t pad05[12];
-
- uint32_t rgbhc;
- uint32_t rgbhen;
- uint32_t rgbven;
- uint32_t pad06;
- uint32_t rgbs;
- uint32_t pad07[11];
-
- uint32_t rgbcmy;
- uint32_t rgbcmcb;
- uint32_t rgbcmcr;
- uint32_t rgbcmb;
- uint32_t pad08[12 + 1984];
-};
-
-/* mb86r0x gdc draw */
-struct mb86r0x_gdc_draw {
- uint32_t ys;
- uint32_t xs;
- uint32_t dxdy;
- uint32_t xus;
- uint32_t dxudy;
- uint32_t xls;
- uint32_t dxldy;
- uint32_t usn;
- uint32_t lsn;
- uint32_t pad01[7];
- uint32_t rs;
- uint32_t drdx;
- uint32_t drdy;
- uint32_t gs;
- uint32_t dgdx;
- uint32_t dgdy;
- uint32_t bs;
- uint32_t dbdx;
- uint32_t dbdy;
- uint32_t pad02[7];
- uint32_t zs;
- uint32_t dzdx;
- uint32_t dzdy;
- uint32_t pad03[13];
- uint32_t ss;
- uint32_t dsdx;
- uint32_t dsdy;
- uint32_t ts;
- uint32_t dtdx;
- uint32_t dtdy;
- uint32_t qs;
- uint32_t dqdx;
- uint32_t dqdy;
- uint32_t pad04[23];
- uint32_t lpn;
- uint32_t lxs;
- uint32_t lxde;
- uint32_t lys;
- uint32_t lyde;
- uint32_t lzs;
- uint32_t lzde;
- uint32_t pad05[13];
- uint32_t pxdc;
- uint32_t pydc;
- uint32_t pzdc;
- uint32_t pad06[25];
- uint32_t rxs;
- uint32_t rys;
- uint32_t rsizex;
- uint32_t rsizey;
- uint32_t pad07[12];
- uint32_t saddr;
- uint32_t sstride;
- uint32_t srx;
- uint32_t sry;
- uint32_t daddr;
- uint32_t dstride;
- uint32_t drx;
- uint32_t dry;
- uint32_t brsizex;
- uint32_t brsizey;
- uint32_t tcolor;
- uint32_t pad08[93];
- uint32_t blpo;
- uint32_t pad09[7];
- uint32_t ctr;
- uint32_t ifsr;
- uint32_t ifcnt;
- uint32_t sst;
- uint32_t ds;
- uint32_t pst;
- uint32_t est;
- uint32_t pad10;
- uint32_t mdr0;
- uint32_t mdr1;
- uint32_t mdr2;
- uint32_t mdr3;
- uint32_t mdr4;
- uint32_t pad14[2];
- uint32_t mdr7;
- uint32_t fbr;
- uint32_t xres;
- uint32_t zbr;
- uint32_t tbr;
- uint32_t pfbr;
- uint32_t cxmin;
- uint32_t cxmax;
- uint32_t cymin;
- uint32_t cymax;
- uint32_t txs;
- uint32_t tis;
- uint32_t toa;
- uint32_t sho;
- uint32_t abr;
- uint32_t pad15[2];
- uint32_t fc;
- uint32_t bc;
- uint32_t alf;
- uint32_t blp;
- uint32_t pad16;
- uint32_t tbc;
- uint32_t pad11[42];
- uint32_t lx0dc;
- uint32_t ly0dc;
- uint32_t lx1dc;
- uint32_t ly1dc;
- uint32_t pad12[12];
- uint32_t x0dc;
- uint32_t y0dc;
- uint32_t x1dc;
- uint32_t y1dc;
- uint32_t x2dc;
- uint32_t y2dc;
- uint32_t pad13[666];
-};
-
-/* mb86r0x gdc geometry engine */
-struct mb86r0x_gdc_geom {
- uint32_t gctr;
- uint32_t pad00[15];
- uint32_t gmdr0;
- uint32_t gmdr1;
- uint32_t gmdr2;
- uint32_t pad01[237];
- uint32_t dfifog;
- uint32_t pad02[767];
-};
-
-/* mb86r0x gdc */
-struct mb86r0x_gdc {
- uint32_t pad00[2];
- uint32_t lts;
- uint32_t pad01;
- uint32_t lsta;
- uint32_t pad02[3];
- uint32_t ist;
- uint32_t imask;
- uint32_t pad03[6];
- uint32_t lsa;
- uint32_t lco;
- uint32_t lreq;
-
- uint32_t pad04[16*1024 - 19];
- struct mb86r0x_gdc_dsp dsp0;
- struct mb86r0x_gdc_dsp dsp1;
- uint32_t pad05[4*1024 - 2];
- uint32_t vccc;
- uint32_t vcsr;
- struct mb86r0x_gdc_cap cap0;
- struct mb86r0x_gdc_cap cap1;
- uint32_t pad06[4*1024];
- uint32_t texture_base[16*1024];
- struct mb86r0x_gdc_draw draw;
- uint32_t pad07[7*1024];
- struct mb86r0x_gdc_geom geom;
- uint32_t pad08[7*1024];
-};
-
-/* mb86r0x ddr2c */
-struct mb86r0x_ddr2c {
- uint16_t dric;
- uint16_t dric1;
- uint16_t dric2;
- uint16_t drca;
- uint16_t drcm;
- uint16_t drcst1;
- uint16_t drcst2;
- uint16_t drcr;
- uint16_t pad00[8];
- uint16_t drcf;
- uint16_t pad01[7];
- uint16_t drasr;
- uint16_t pad02[15];
- uint16_t drims;
- uint16_t pad03[7];
- uint16_t dros;
- uint16_t pad04;
- uint16_t dribsodt1;
- uint16_t dribsocd;
- uint16_t dribsocd2;
- uint16_t pad05[3];
- uint16_t droaba;
- uint16_t pad06[9];
- uint16_t drobs;
- uint16_t pad07[5];
- uint16_t drimr1;
- uint16_t drimr2;
- uint16_t drimr3;
- uint16_t drimr4;
- uint16_t droisr1;
- uint16_t droisr2;
-};
-
-/* mb86r0x memc */
-struct mb86r0x_memc {
- uint32_t mcfmode[8];
- uint32_t mcftim[8];
- uint32_t mcfarea[8];
-};
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Physical Address Defines
- */
-#define MB86R0x_DDR2_BASE 0xf3000000
-#define MB86R0x_GDC_BASE 0xf1fc0000
-#define MB86R0x_CCNT_BASE 0xfff42000
-#define MB86R0x_CAN0_BASE 0xfff54000
-#define MB86R0x_CAN1_BASE 0xfff55000
-#define MB86R0x_I2C0_BASE 0xfff56000
-#define MB86R0x_I2C1_BASE 0xfff57000
-#define MB86R0x_EHCI_BASE 0xfff80000
-#define MB86R0x_OHCI_BASE 0xfff81000
-#define MB86R0x_IRC1_BASE 0xfffb0000
-#define MB86R0x_MEMC_BASE 0xfffc0000
-#define MB86R0x_TIMER_BASE 0xfffe0000
-#define MB86R0x_UART0_BASE 0xfffe1000
-#define MB86R0x_UART1_BASE 0xfffe2000
-#define MB86R0x_IRCE_BASE 0xfffe4000
-#define MB86R0x_CRG_BASE 0xfffe7000
-#define MB86R0x_IRC0_BASE 0xfffe8000
-#define MB86R0x_GPIO_BASE 0xfffe9000
-#define MB86R0x_PWM0_BASE 0xfff41000
-#define MB86R0x_PWM1_BASE 0xfff41100
-
-#define MB86R0x_CRSR_SWRSTREQ (1 << 1)
-
-/*
- * Timer register bits
- */
-#define MB86R0x_TIMER_ENABLE (1 << 7)
-#define MB86R0x_TIMER_MODE_MSK (1 << 6)
-#define MB86R0x_TIMER_MODE_FR (0 << 6)
-#define MB86R0x_TIMER_MODE_PD (1 << 6)
-
-#define MB86R0x_TIMER_INT_EN (1 << 5)
-#define MB86R0x_TIMER_PRS_MSK (3 << 2)
-#define MB86R0x_TIMER_PRS_4S (1 << 2)
-#define MB86R0x_TIMER_PRS_8S (1 << 3)
-#define MB86R0x_TIMER_SIZE_32 (1 << 1)
-#define MB86R0x_TIMER_ONE_SHT (1 << 0)
-
-/*
- * Clock reset generator bits
- */
-#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8)
-#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0)
-/*
- * DDR2 controller bits
- */
-#define MB86R0x_DDR2_DRCI_DRINI (1 << 15)
-#define MB86R0x_DDR2_DRCI_CKEN (1 << 14)
-#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0)
-#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \
- MB86R0x_DDR2_DRCI_CKEN | \
- MB86R0x_DDR2_DRCI_DRCMD)
-#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \
- MB86R0x_DDR2_DRCI_CKEN)
-#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN
-#endif /* MB86R0X_H */
diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
index b0c26e5..e5bcaea 100644
--- a/arch/arm/lib/asm-offsets.c
+++ b/arch/arm/lib/asm-offsets.c
@@ -15,9 +15,6 @@
#include <common.h>
#include <linux/kbuild.h>
-#if defined(CONFIG_MB86R0x)
-#include <asm/arch/mb86r0x.h>
-#endif
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
@@ -27,8 +24,6 @@ int main(void)
{
/*
* TODO : Check if each entry in this file is really necessary.
- * - struct mb86r0x_ddr2
- * - struct mb86r0x_memc
* - struct esdramc_regs
* - struct max_regs
* - struct aips_regs
@@ -40,47 +35,6 @@ int main(void)
* code. Is it better to define the macros directly in headers?
*/
-#if defined(CONFIG_MB86R0x)
- /* ddr2 controller */
- DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
- DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
- DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
- DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
- DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
- DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
- DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
- DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
- DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
- DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
- DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
- DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
- DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
- DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
- DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
-
- /* clock reset generator */
- DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
- DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
- DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
- DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
- DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
- DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
-
- /* chip control module */
- DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
-
- /* external bus interface */
- DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
- DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
- DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
- DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
- DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
- DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
- DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
- DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
- DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
-#endif
-
#if defined(CONFIG_MX25)
/* Clock Control Module */
DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
diff --git a/board/syteco/jadecpu/Kconfig b/board/syteco/jadecpu/Kconfig
deleted file mode 100644
index 6e9392e..0000000
--- a/board/syteco/jadecpu/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_JADECPU
-
-config SYS_BOARD
- default "jadecpu"
-
-config SYS_VENDOR
- default "syteco"
-
-config SYS_SOC
- default "mb86r0x"
-
-config SYS_CONFIG_NAME
- default "jadecpu"
-
-endif
diff --git a/board/syteco/jadecpu/MAINTAINERS b/board/syteco/jadecpu/MAINTAINERS
deleted file mode 100644
index b53e7ca..0000000
--- a/board/syteco/jadecpu/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-JADECPU BOARD
-M: Matthias Weisser <weisserm@arcor.de>
-S: Maintained
-F: board/syteco/jadecpu/
-F: include/configs/jadecpu.h
-F: configs/jadecpu_defconfig
diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile
deleted file mode 100644
index 7426436..0000000
--- a/board/syteco/jadecpu/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2008
-# Stelian Pop <stelian@popies.net>
-# Lead Tech Design <www.leadtechdesign.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += jadecpu.o
-obj-y += lowlevel_init.o
diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c
deleted file mode 100644
index 6c60a41..0000000
--- a/board/syteco/jadecpu/jadecpu.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * (c) 2010 Graf-Syteco, Matthias Weisser
- * <weisserm@arcor.de>
- *
- * (C) Copyright 2007, mycable GmbH
- * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/mb86r0x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
- MB86R0x_CCNT_BASE;
-
- /* We select mode 0 for group 2 and mode 1 for group 4 */
- writel(0x00000010, &ccnt->cmux_md);
-
- gd->flags = 0;
- gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
-
- icache_enable();
- dcache_enable();
-
- return 0;
-}
-
-static void setup_display_power(uint32_t pwr_bit, char *pwm_opts,
- unsigned long pwm_base)
-{
- struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
- MB86R0x_GPIO_BASE;
- struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base;
- const char *e;
-
- writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2);
-
- e = getenv(pwm_opts);
- if (e != NULL) {
- const char *s;
- uint32_t freq, init;
-
- freq = 0;
- init = 0;
-
- s = strchr(e, 'f');
- if (s != NULL)
- freq = simple_strtol(s + 2, NULL, 0);
-
- s = strchr(e, 'i');
- if (s != NULL)
- init = simple_strtol(s + 2, NULL, 0);
-
- if (freq > 0) {
- writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
- &pwm->bcr);
- writel(1002, &pwm->tpr);
- writel(1, &pwm->pr);
- writel(init * 10 + 1, &pwm->dr);
- writel(1, &pwm->cr);
- writel(1, &pwm->sr);
- }
- }
-}
-
-int board_late_init(void)
-{
- struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
- MB86R0x_GPIO_BASE;
- uint32_t in_word;
-
-#ifdef CONFIG_VIDEO_MB86R0xGDC
- /* Check if we have valid display settings and turn on power if so */
- /* Display 0 */
- if (getenv("gs_dsp_0_param") || getenv("videomode"))
- setup_display_power((1 << 3), "gs_dsp_0_pwm",
- MB86R0x_PWM0_BASE);
-
- /* The corresponding GPIO is always an output */
- writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
-
- /* Display 1 */
- if (getenv("gs_dsp_1_param") || getenv("videomode1"))
- setup_display_power((1 << 4), "gs_dsp_1_pwm",
- MB86R0x_PWM1_BASE);
-
- /* The corresponding GPIO is always an output */
- writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
-#endif /* CONFIG_VIDEO_MB86R0xGDC */
-
- /* 5V enable */
- writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
- writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
-
- /* We have special boot options if told by GPIOs */
- in_word = readl(&gpio->gpdr1);
-
- if ((in_word & 0xC0) == 0xC0) {
- setenv("stdin", "serial");
- setenv("stdout", "serial");
- setenv("stderr", "serial");
- setenv("preboot", "run gs_slow_boot");
- } else if ((in_word & 0xC0) != 0) {
- setenv("stdout", "vga");
- setenv("preboot", "run gs_slow_boot");
- } else {
- setenv("stdin", "serial");
- setenv("stdout", "serial");
- setenv("stderr", "serial");
- if (getenv("gs_devel")) {
- setenv("preboot", "run gs_slow_boot");
- } else {
- setenv("preboot", "run gs_fast_boot");
- }
- }
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-/*
- * DRAM configuration
- */
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
- PHYS_SDRAM_SIZE);
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size = gd->ram_size;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S
deleted file mode 100644
index 9568cec..0000000
--- a/board/syteco/jadecpu/lowlevel_init.S
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2007, mycable GmbH
- * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
- *
- * (C) Copyright 2003, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/macro.h>
-#include <asm/arch/mb86r0x.h>
-#include <generated/asm-offsets.h>
-
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
-/*
- * Initialize Clock Reset Generator (CRG)
- */
-
- ldr r0, =MB86R0x_CRG_BASE
-
- /* Not change the initial value that is set by external pin.*/
-WAIT_PLL:
- ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */
- tst r2, #MB86R0x_CRG_CRPR_PLLRDY
- beq WAIT_PLL
-
- /* Set clock gate control */
- ldr r1, =CONFIG_SYS_CRG_CRHA_INIT
- str r1, [r0, #CRG_CRHA]
- ldr r1, =CONFIG_SYS_CRG_CRPA_INIT
- str r1, [r0, #CRG_CRPA]
- ldr r1, =CONFIG_SYS_CRG_CRPB_INIT
- str r1, [r0, #CRG_CRPB]
- ldr r1, =CONFIG_SYS_CRG_CRHB_INIT
- str r1, [r0, #CRG_CRHB]
- ldr r1, =CONFIG_SYS_CRG_CRAM_INIT
- str r1, [r0, #CRG_CRAM]
-
-/*
- * Initialize External Bus Interface
- */
- ldr r0, =MB86R0x_MEMC_BASE
-
- ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
- str r1, [r0, #MEMC_MCFMODE0]
- ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
- str r1, [r0, #MEMC_MCFMODE2]
- ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
- str r1, [r0, #MEMC_MCFMODE4]
-
- ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
- str r1, [r0, #MEMC_MCFTIM0]
- ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
- str r1, [r0, #MEMC_MCFTIM2]
- ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
- str r1, [r0, #MEMC_MCFTIM4]
-
- ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
- str r1, [r0, #MEMC_MCFAREA0]
- ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
- str r1, [r0, #MEMC_MCFAREA2]
- ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
- str r1, [r0, #MEMC_MCFAREA4]
-
-/*
- * Initialize DDR2 Controller
- */
-
- /* Wait for PLL LOCK up time or more */
- wait_timer 20
-
- /*
- * (2) Initialize DDRIF
- */
- ldr r0, =MB86R0x_DDR2_BASE
- ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT
- strh r1, [r0, #DDR2_DRIMS]
-
- /*
- * (3) Wait for 20MCKPs(120nsec) or more
- */
- wait_timer 20
-
- /*
- * (4) IRESET/IUSRRST release
- */
- ldr r0, =MB86R0x_CCNT_BASE
- ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
- str r1, [r0, #CCNT_CDCRC]
-
- /*
- * (5) Wait for 20MCKPs(120nsec) or more
- */
- wait_timer 20
-
- /*
- * (6) IDLLRST release
- */
- ldr r0, =MB86R0x_CCNT_BASE
- ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
- str r1, [r0, #CCNT_CDCRC]
-
- /*
- * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
- */
- wait_timer 33536
-
- /*
- * (9) MCKE ON
- */
- ldr r0, =MB86R0x_DDR2_BASE
- ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT
- strh r1, [r0, #DDR2_DRCA]
- ldr r1, =MB86R0x_DDR2_DRCI_INIT
- strh r1, [r0, #DDR2_DRIC]
-
- /*
- * (10) Initialize SDRAM
- */
-
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- wait_timer 67 /* 400ns wait */
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- wait_timer 200
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- wait_timer 18 /* 105ns wait */
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- wait_timer 200 /* MRS to OCD: 200clock */
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT
- strh r1, [r0, #DDR2_DRCM]
-
- ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT
- strh r1, [r0, #DDR2_DRCST1]
-
- ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT
- strh r1, [r0, #DDR2_DRCST2]
-
- ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT
- strh r1, [r0, #DDR2_DRCR]
-
- ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT
- strh r1, [r0, #DDR2_DRCF]
-
- ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT
- strh r1, [r0, #DDR2_DRASR]
-
- /*
- * (11) ODT setting
- */
- ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT
- strh r1, [r0, #DDR2_DROBS]
- ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT
- strh r1, [r0, #DDR2_DROABA]
- ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
- strh r1, [r0, #DDR2_DRIBSODT1]
-
- /*
- * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
- */
- ldr r1, =CONFIG_SYS_DDR2_DROS_INIT
- strh r1, [r0, #DDR2_DROS]
- ldr r1, =MB86R0x_DDR2_DRCI_NORMAL
- strh r1, [r0, #DDR2_DRIC]
-
- mov pc, lr
diff --git a/configs/jadecpu_defconfig b/configs/jadecpu_defconfig
deleted file mode 100644
index 4348e0e..0000000
--- a/configs/jadecpu_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_JADECPU=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index cd51249..fbeb2cd 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
imx31_phycore arm arm1136 - - Guennadi Liakhovetski <g.liakhovetski@gmx.de>
mx31ads arm arm1136 - - Guennadi Liakhovetski <g.liakhovetski@gmx.de>
icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de>
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index af2d47b..22a316b 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o
obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
-obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
diff --git a/drivers/video/mb86r0xgdc.c b/drivers/video/mb86r0xgdc.c
deleted file mode 100644
index bb7a749..0000000
--- a/drivers/video/mb86r0xgdc.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic
- * controller.
- */
-
-#include <common.h>
-
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <video_fb.h>
-#include "videomodes.h"
-
-/*
- * 4MB (at the end of system RAM)
- */
-#define VIDEO_MEM_SIZE 0x400000
-
-#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */
-
-/*
- * Graphic Device
- */
-static GraphicDevice mb86r0x;
-
-static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr,
- u32 *videomem)
-{
- struct ctfb_res_modes var_mode;
- u32 dcm1, dcm2, dcm3;
- u16 htp, hdp, hdb, hsp, vtr, vsp, vdp;
- u8 hsw, vsw;
- u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1;
- u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh;
- unsigned long div;
- int bpp;
-
- bpp = video_get_params(&var_mode, modestr);
-
- if (bpp == 0) {
- var_mode.xres = 640;
- var_mode.yres = 480;
- var_mode.pixclock = 39721; /* 25MHz */
- var_mode.left_margin = 48;
- var_mode.right_margin = 16;
- var_mode.upper_margin = 33;
- var_mode.lower_margin = 10;
- var_mode.hsync_len = 96;
- var_mode.vsync_len = 2;
- var_mode.sync = 0;
- var_mode.vmode = 0;
- bpp = 15;
- }
-
- /* Fill memory with white */
- memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2);
-
- mb86r0x.winSizeX = var_mode.xres;
- mb86r0x.winSizeY = var_mode.yres;
-
- /* LCD base clock is ~ 660MHZ. We do calculations in kHz */
- div = 660000 / (1000000000L / var_mode.pixclock);
- if (div > 64)
- div = 64;
- if (0 == div)
- div = 1;
-
- dcm1 = (div - 1) << 8;
- dcm2 = 0x00000000;
- if (var_mode.sync & FB_SYNC_CLK_INV)
- dcm3 = 0x00000100;
- else
- dcm3 = 0x00000000;
-
- htp = var_mode.left_margin + var_mode.xres +
- var_mode.hsync_len + var_mode.right_margin;
- hdp = var_mode.xres;
- hdb = var_mode.xres;
- hsp = var_mode.xres + var_mode.right_margin;
- hsw = var_mode.hsync_len;
-
- vsw = var_mode.vsync_len;
- vtr = var_mode.upper_margin + var_mode.yres +
- var_mode.vsync_len + var_mode.lower_margin;
- vsp = var_mode.yres + var_mode.lower_margin;
- vdp = var_mode.yres;
-
- l2m = ((var_mode.yres - 1) << (0)) |
- (((var_mode.xres * 2) / 64) << (16)) |
- ((1) << (31));
-
- l2em = (1 << 0) | (1 << 1);
-
- l2oa0 = mb86r0x.frameAdrs;
- l2da0 = mb86r0x.frameAdrs;
- l2oa1 = mb86r0x.frameAdrs;
- l2da1 = mb86r0x.frameAdrs;
- l2dx = 0;
- l2dy = 0;
- l2wx = 0;
- l2wy = 0;
- l2ww = var_mode.xres;
- l2wh = var_mode.yres - 1;
-
- writel(dcm1, &dsp->dcm1);
- writel(dcm2, &dsp->dcm2);
- writel(dcm3, &dsp->dcm3);
-
- writew(htp, &dsp->htp);
- writew(hdp, &dsp->hdp);
- writew(hdb, &dsp->hdb);
- writew(hsp, &dsp->hsp);
- writeb(hsw, &dsp->hsw);
-
- writeb(vsw, &dsp->vsw);
- writew(vtr, &dsp->vtr);
- writew(vsp, &dsp->vsp);
- writew(vdp, &dsp->vdp);
-
- writel(l2m, &dsp->l2m);
- writel(l2em, &dsp->l2em);
- writel(l2oa0, &dsp->l2oa0);
- writel(l2da0, &dsp->l2da0);
- writel(l2oa1, &dsp->l2oa1);
- writel(l2da1, &dsp->l2da1);
- writew(l2dx, &dsp->l2dx);
- writew(l2dy, &dsp->l2dy);
- writew(l2wx, &dsp->l2wx);
- writew(l2wy, &dsp->l2wy);
- writew(l2ww, &dsp->l2ww);
- writew(l2wh, &dsp->l2wh);
-
- writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1);
-}
-
-void *video_hw_init(void)
-{
- struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE;
- GraphicDevice *pGD = &mb86r0x;
- char *s;
- u32 *vid;
-
- memset(pGD, 0, sizeof(GraphicDevice));
-
- pGD->gdfIndex = GDF_15BIT_555RGB;
- pGD->gdfBytesPP = 2;
- pGD->memSize = VIDEO_MEM_SIZE;
- pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
-
- vid = (u32 *)pGD->frameAdrs;
-
- s = getenv("videomode");
- if (s != NULL)
- dsp_init(&gdc->dsp0, s, vid);
-
- s = getenv("videomode1");
- if (s != NULL)
- dsp_init(&gdc->dsp1, s, vid);
-
- return pGD;
-}
diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h
deleted file mode 100644
index 8175621..0000000
--- a/include/configs/jadecpu.h
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * Configuation settings for the jadecpu board
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MB86R0x
-#define CONFIG_MB86R0x_IOCLK get_bus_freq(0)
-#define CONFIG_SYS_TEXT_BASE 0x10000000
-
-
-#define CONFIG_USE_ARCH_MEMCPY
-#define CONFIG_USE_ARCH_MEMSET
-
-#define MACH_TYPE_JADECPU 2636
-
-#define CONFIG_MACH_TYPE MACH_TYPE_JADECPU
-
-/*
- * Environment settings
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "gs_fast_boot=setenv bootdelay 5\0" \
- "gs_slow_boot=setenv bootdelay 10\0" \
- "bootcmd=dcache off; mw.l 0x40000000 0 1024; usb start;" \
- "fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \
- "bootelf 0x40000000\0" \
- ""
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_BOARD_LATE_INIT
-
-/*
- * Compressions
- */
-#define CONFIG_LZO
-
-/*
- * Hardware drivers
- */
-
-/*
- * Serial
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */
-#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */
-#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */
-#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */
-
-#define CONFIG_CONS_INDEX 4
-
-/*
- * Ethernet
- */
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_BASE 0x02000000
-#define CONFIG_SMC911X_16_BIT
-
-/*
- * Video
- */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_MB86R0xGDC
-#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024)
-#define VIDEO_FB_16BPP_WORD_SWAP
-#define VIDEO_KBD_INIT_FCT 0
-#define VIDEO_TSTC_FCT serial_stub_tstc
-#define VIDEO_GETC_FCT serial_stub_getc
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE 1
-#define CONFIG_BOOTP_BOOTPATH 1
-#define CONFIG_BOOTP_GATEWAY 1
-#define CONFIG_BOOTP_HOSTNAME 1
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
-
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_CACHE
-
-#define CONFIG_SYS_HUSH_PARSER
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-
-/* SDRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */
-#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_SP_ADDR 0x01008000
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE 0x10000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE (128 * 1024)
-
-/*
- * CFI FLASH driver setup
- */
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
-
-#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */
-
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_PROMPT "jade> "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-
-#define CONFIG_PREBOOT ""
-
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR "delaygs"
-#define CONFIG_AUTOBOOT_STOP_STR "stopgs"
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (10 << 20)
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 20)
-
-/*
- * Clock reset generator init
- */
-#define CONFIG_SYS_CRG_CRHA_INIT 0xffff
-#define CONFIG_SYS_CRG_CRPA_INIT 0xffff
-#define CONFIG_SYS_CRG_CRPB_INIT 0xfffe
-#define CONFIG_SYS_CRG_CRHB_INIT 0xffff
-#define CONFIG_SYS_CRG_CRAM_INIT 0xffef
-
-/*
- * Memory controller settings
- */
-#define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */
-#define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */
-#define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/
-#define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008
-#define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008
-#define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804
-#define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */
-#define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */
-#define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */
-
-/*
- * DDR2 controller init settings
- */
-#define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555
-#define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002
-#define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003
-#define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f
-#define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000
-#define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */
-#define CONFIG_SYS_DDR2_DRCM_INIT 0x0032
-#define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418
-#define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32
-#define CONFIG_SYS_DDR2_DRCR_INIT 0x0141
-#define CONFIG_SYS_DDR2_DRCF_INIT 0x0002
-#define CONFIG_SYS_DDR2_DRASR_INIT 0x0001
-#define CONFIG_SYS_DDR2_DROBS_INIT 0x0001
-#define CONFIG_SYS_DDR2_DROABA_INIT 0x0103
-#define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F
-#define CONFIG_SYS_DDR2_DROS_INIT 0x0001
-
-/*
- * DRAM init sequence
- */
-
-/* PALL Command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017
-#define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400
-
-/* EMR(2) command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006
-#define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000
-
-/* EMR(3) command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007
-#define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000
-
-/* EMR(1) command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005
-#define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000
-
-/* MRS command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004
-#define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532
-
-/* PALL command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017
-#define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400
-
-/* REF command 1 */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f
-#define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000
-
-/* MRS command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004
-#define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432
-
-/* EMR(1) command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005
-#define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380
-
-/* EMR(1) command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005
-#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002
-
-#endif /* __CONFIG_H */
diff --git a/include/serial.h b/include/serial.h
index 66ed12c..3d2e569 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -29,7 +29,7 @@ extern struct serial_device *default_serial_console(void);
#if defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_440) || \
- defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
+ defined(CONFIG_MPC5xxx) || \
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 04/11] ARM: remove zmx25 board support
2015-02-10 4:44 [U-Boot] [PATCH 0/11] ARM: remove non-generic boards Masahiro Yamada
` (2 preceding siblings ...)
2015-02-10 4:44 ` [U-Boot] [PATCH 03/11] ARM: remove jadecpu board support Masahiro Yamada
@ 2015-02-10 4:44 ` Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 05/11] ARM: remove devkit3250 " Masahiro Yamada
` (6 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 4:44 UTC (permalink / raw)
To: u-boot
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Matthias Weisser <weisserm@arcor.de>
---
arch/arm/Kconfig | 5 --
board/syteco/zmx25/Kconfig | 15 ----
board/syteco/zmx25/MAINTAINERS | 6 --
board/syteco/zmx25/Makefile | 9 --
board/syteco/zmx25/lowlevel_init.S | 97 ---------------------
board/syteco/zmx25/zmx25.c | 174 -------------------------------------
configs/zmx25_defconfig | 2 -
doc/README.scrapyard | 1 +
include/configs/zmx25.h | 162 ----------------------------------
9 files changed, 1 insertion(+), 470 deletions(-)
delete mode 100644 board/syteco/zmx25/Kconfig
delete mode 100644 board/syteco/zmx25/MAINTAINERS
delete mode 100644 board/syteco/zmx25/Makefile
delete mode 100644 board/syteco/zmx25/lowlevel_init.S
delete mode 100644 board/syteco/zmx25/zmx25.c
delete mode 100644 configs/zmx25_defconfig
delete mode 100644 include/configs/zmx25.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3ade156..cbed2f4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -254,10 +254,6 @@ config TARGET_TX25
select CPU_ARM926EJS
select SUPPORT_SPL
-config TARGET_ZMX25
- bool "Support zmx25"
- select CPU_ARM926EJS
-
config TARGET_APF27
bool "Support apf27"
select CPU_ARM926EJS
@@ -965,7 +961,6 @@ source "board/st-ericsson/snowball/Kconfig"
source "board/st-ericsson/u8500/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
-source "board/syteco/zmx25/Kconfig"
source "board/taskit/stamp9g20/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
diff --git a/board/syteco/zmx25/Kconfig b/board/syteco/zmx25/Kconfig
deleted file mode 100644
index 59a415d..0000000
--- a/board/syteco/zmx25/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_ZMX25
-
-config SYS_BOARD
- default "zmx25"
-
-config SYS_VENDOR
- default "syteco"
-
-config SYS_SOC
- default "mx25"
-
-config SYS_CONFIG_NAME
- default "zmx25"
-
-endif
diff --git a/board/syteco/zmx25/MAINTAINERS b/board/syteco/zmx25/MAINTAINERS
deleted file mode 100644
index 90f9fab..0000000
--- a/board/syteco/zmx25/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ZMX25 BOARD
-M: Matthias Weisser <weisserm@arcor.de>
-S: Maintained
-F: board/syteco/zmx25/
-F: include/configs/zmx25.h
-F: configs/zmx25_defconfig
diff --git a/board/syteco/zmx25/Makefile b/board/syteco/zmx25/Makefile
deleted file mode 100644
index d5edb48..0000000
--- a/board/syteco/zmx25/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (c) 2010 Graf-Syteco, Matthias Weisser
-# <weisserm@arcor.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += zmx25.o
-obj-y += lowlevel_init.o
diff --git a/board/syteco/zmx25/lowlevel_init.S b/board/syteco/zmx25/lowlevel_init.S
deleted file mode 100644
index 5eccf09..0000000
--- a/board/syteco/zmx25/lowlevel_init.S
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * (C) Copyright 2011
- * Matthias Weisser <weisserm@arcor.de>
- *
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on U-Boot and RedBoot sources for several different i.mx
- * platforms.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/macro.h>
-#include <asm/arch/macro.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-
-/*
- * clocks
- */
-.macro init_clocks
-
- /* disable clock output */
- write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
- write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
-
- /*
- * enable all implemented clocks in all three
- * clock control registers
- */
- write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
- write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
- write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
-
- /* Devide NAND clock by 32 */
- write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
-.endm
-
-/*
- * sdram controller init
- */
-.macro init_lpddr
- ldr r0, =IMX_ESDRAMC_BASE
- ldr r2, =IMX_SDRAM_BANK0_BASE
-
- /*
- * reset SDRAM controller
- * then wait for initialization to complete
- */
- ldr r1, =(1 << 1) | (1 << 2)
- str r1, [r0, #ESDRAMC_ESDMISC]
-1: ldr r3, [r0, #ESDRAMC_ESDMISC]
- tst r3, #(1 << 31)
- beq 1b
- ldr r1, =(1 << 2)
- str r1, [r0, #ESDRAMC_ESDMISC]
-
- ldr r1, =0x002a7420
- str r1, [r0, #ESDRAMC_ESDCFG0]
-
- /* control | precharge */
- ldr r1, =0x92216008
- str r1, [r0, #ESDRAMC_ESDCTL0]
- /* dram command encoded in address */
- str r1, [r2, #0x400]
-
- /* auto refresh */
- ldr r1, =0xa2216008
- str r1, [r0, #ESDRAMC_ESDCTL0]
- /* read dram twice to auto refresh */
- ldr r3, [r2]
- ldr r3, [r2]
-
- /* control | load mode */
- ldr r1, =0xb2216008
- str r1, [r0, #ESDRAMC_ESDCTL0]
-
- /* mode register of lpddram */
- strb r1, [r2, #0x33]
-
- /* extended mode register of lpddrram */
- ldr r2, =0x81000000
- strb r1, [r2]
-
- /* control | normal */
- ldr r1, =0x82216008
- str r1, [r0, #ESDRAMC_ESDCTL0]
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
- init_aips
- init_max
- init_clocks
- init_lpddr
- mov pc, lr
diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c
deleted file mode 100644
index bdbf02a..0000000
--- a/board/syteco/zmx25/zmx25.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * (c) 2011 Graf-Syteco, Matthias Weisser
- * <weisserm@arcor.de>
- *
- * Based on tx25.c:
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on imx27lite.c:
- * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- * And:
- * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx25.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init()
-{
- static const iomux_v3_cfg_t sdhc1_pads[] = {
- NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
- };
-
- static const iomux_v3_cfg_t dig_out_pads[] = {
- MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */
- MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */
- NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */
- NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */
- };
-
- static const iomux_v3_cfg_t led_pads[] = {
- MX25_PAD_CSI_D9__GPIO_4_21,
- MX25_PAD_CSI_D4__GPIO_1_29,
- };
-
- static const iomux_v3_cfg_t can_pads[] = {
- NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL),
- };
-
- static const iomux_v3_cfg_t i2c3_pads[] = {
- MX25_PAD_CSPI1_SS1__I2C3_DAT,
- MX25_PAD_GPIO_E__I2C3_CLK,
- };
-
- icache_enable();
-
- /* Setup of core voltage selection pin to run at 1.4V */
- imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */
- gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
-
- /* Setup of SD card pins*/
- imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
-
- /* Setup of digital output for USB power and OC */
- imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */
- gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
-
- imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */
- gpio_direction_input(IMX_GPIO_NR(1, 18));
-
- /* Setup of digital output control pins */
- imx_iomux_v3_setup_multiple_pads(dig_out_pads,
- ARRAY_SIZE(dig_out_pads));
-
- /* Switch both output drivers off */
- gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
- gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
-
- /* Setup of key input pin */
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0));
- gpio_direction_input(IMX_GPIO_NR(2, 29));
-
- /* Setup of status LED outputs */
- imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
-
- /* Switch both LEDs off */
- gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
- gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
-
- /* Setup of CAN1 and CAN2 signals */
- imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads));
-
- /* Setup of I2C3 signals */
- imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
-
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- return 0;
-}
-
-int board_late_init(void)
-{
- const char *e;
-
-#ifdef CONFIG_FEC_MXC
-/*
- * FIXME: need to revisit this
- * The original code enabled PUE and 100-k pull-down without PKE, so the right
- * value here is likely:
- * 0 for no pull
- * or:
- * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
- */
-#define FEC_OUT_PAD_CTRL 0
-
- static const iomux_v3_cfg_t fec_pads[] = {
- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX25_PAD_FEC_RX_DV__FEC_RX_DV,
- MX25_PAD_FEC_RDATA0__FEC_RDATA0,
- NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
- MX25_PAD_FEC_MDIO__FEC_MDIO,
- MX25_PAD_FEC_RDATA1__FEC_RDATA1,
- NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
-
- MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */
- MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */
- };
-
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-
- /* assert PHY reset (low) */
- gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
-
- udelay(5000);
-
- /* deassert PHY reset */
- gpio_set_value(IMX_GPIO_NR(3, 16), 1);
-
- udelay(5000);
-#endif
-
- e = getenv("gs_base_board");
- if (e != NULL) {
- if (strcmp(e, "G283") == 0) {
- int key = gpio_get_value(IMX_GPIO_NR(2, 29));
-
- if (key) {
- /* Switch on both LEDs to inidcate boot mode */
- gpio_set_value(IMX_GPIO_NR(1, 29), 0);
- gpio_set_value(IMX_GPIO_NR(4, 21), 0);
-
- setenv("preboot", "run gs_slow_boot");
- } else
- setenv("preboot", "run gs_fast_boot");
- }
- }
-
- return 0;
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
- PHYS_SDRAM_SIZE);
- return 0;
-}
diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig
deleted file mode 100644
index 80a66d0..0000000
--- a/configs/zmx25_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_ZMX25=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index fbeb2cd..b24bfea 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+zmx25 arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
imx31_phycore arm arm1136 - - Guennadi Liakhovetski <g.liakhovetski@gmx.de>
mx31ads arm arm1136 - - Guennadi Liakhovetski <g.liakhovetski@gmx.de>
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
deleted file mode 100644
index 356ac88..0000000
--- a/include/configs/zmx25.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * (c) 2011 Graf-Syteco, Matthias Weisser
- * <weisserm@arcor.de>
- *
- * Configuation settings for the zmx25 board
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_MX25
-#define CONFIG_SYS_TEXT_BASE 0xA0000000
-
-#define CONFIG_SYS_TIMER_RATE 32768
-#define CONFIG_SYS_TIMER_COUNTER \
- (&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
-
-#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25
-/*
- * Environment settings
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "gs_fast_boot=setenv bootdelay 5\0" \
- "gs_slow_boot=setenv bootdelay 10\0" \
- "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
- "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
- "bootm 0x81000000; bootelf 0x81000000\0"
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_BOARD_LATE_INIT
-
-/*
- * Compressions
- */
-#define CONFIG_LZO
-
-/*
- * Hardware drivers
- */
-
-/*
- * GPIO
- */
-#define CONFIG_MXC_GPIO
-
-/*
- * Serial
- */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_CONS_INDEX 1 /* use UART2 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-
-/*
- * Ethernet
- */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_PHYADDR 0x00
-#define CONFIG_MII
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_CACHE
-
-/*
- * Additional command
- */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_USB
-
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * USB
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_MXC
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORT 1
-#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL
-#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SUPPORT_VFAT
-#endif /* CONFIG_CMD_USB */
-
-/* SDRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */
-#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE 0xA0000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE (128 * 1024)
-
-/*
- * CFI FLASH driver setup
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
-
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
-
-#define CONFIG_SYS_PROMPT "zmx25> "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-
-#define CONFIG_PREBOOT ""
-
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR "delaygs"
-#define CONFIG_AUTOBOOT_STOP_STR "stopgs"
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 05/11] ARM: remove devkit3250 board support
2015-02-10 4:44 [U-Boot] [PATCH 0/11] ARM: remove non-generic boards Masahiro Yamada
` (3 preceding siblings ...)
2015-02-10 4:44 ` [U-Boot] [PATCH 04/11] ARM: remove zmx25 " Masahiro Yamada
@ 2015-02-10 4:44 ` Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 06/11] ARM: remove dkb " Masahiro Yamada
` (5 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 4:44 UTC (permalink / raw)
To: u-boot
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
---
arch/arm/Kconfig | 5 -
arch/arm/cpu/arm926ejs/Makefile | 1 -
arch/arm/cpu/arm926ejs/lpc32xx/Makefile | 8 --
arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 104 -----------------
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 57 ----------
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 39 -------
arch/arm/cpu/arm926ejs/lpc32xx/timer.c | 82 --------------
arch/arm/include/asm/arch-lpc32xx/clk.h | 157 --------------------------
arch/arm/include/asm/arch-lpc32xx/config.h | 59 ----------
arch/arm/include/asm/arch-lpc32xx/cpu.h | 51 ---------
arch/arm/include/asm/arch-lpc32xx/emc.h | 79 -------------
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 12 --
arch/arm/include/asm/arch-lpc32xx/timer.h | 61 ----------
arch/arm/include/asm/arch-lpc32xx/uart.h | 101 -----------------
arch/arm/include/asm/arch-lpc32xx/wdt.h | 38 -------
board/timll/devkit3250/Kconfig | 15 ---
board/timll/devkit3250/MAINTAINERS | 6 -
board/timll/devkit3250/Makefile | 8 --
board/timll/devkit3250/devkit3250.c | 52 ---------
configs/devkit3250_defconfig | 2 -
doc/README.scrapyard | 1 +
drivers/serial/Makefile | 1 -
drivers/serial/lpc32xx_hsuart.c | 89 ---------------
drivers/serial/serial.c | 2 -
include/configs/devkit3250.h | 101 -----------------
include/serial.h | 1 -
26 files changed, 1 insertion(+), 1131 deletions(-)
delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/Makefile
delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/clk.c
delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/devices.c
delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/timer.c
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/clk.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/config.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/cpu.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/emc.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/sys_proto.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/timer.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/uart.h
delete mode 100644 arch/arm/include/asm/arch-lpc32xx/wdt.h
delete mode 100644 board/timll/devkit3250/Kconfig
delete mode 100644 board/timll/devkit3250/MAINTAINERS
delete mode 100644 board/timll/devkit3250/Makefile
delete mode 100644 board/timll/devkit3250/devkit3250.c
delete mode 100644 configs/devkit3250_defconfig
delete mode 100644 drivers/serial/lpc32xx_hsuart.c
delete mode 100644 include/configs/devkit3250.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cbed2f4..b0b7eaf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -241,10 +241,6 @@ config TARGET_MAXBCM
bool "Support maxbcm"
select CPU_V7
-config TARGET_DEVKIT3250
- bool "Support devkit3250"
- select CPU_ARM926EJS
-
config TARGET_MX25PDK
bool "Support mx25pdk"
select CPU_ARM926EJS
@@ -968,7 +964,6 @@ source "board/ti/am43xx/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/ti/tnetv107xevm/Kconfig"
-source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/trizepsiv/Kconfig"
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 607d29f..bfa365e 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -18,7 +18,6 @@ obj-$(CONFIG_ARMADA100) += armada100/
obj-$(CONFIG_AT91FAMILY) += at91/
obj-$(CONFIG_ARCH_DAVINCI) += davinci/
obj-$(CONFIG_KIRKWOOD) += kirkwood/
-obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
deleted file mode 100644
index 314f004..0000000
--- a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o clk.o devices.o timer.o
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
deleted file mode 100644
index b7a44d5..0000000
--- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/io.h>
-
-static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
-
-unsigned int get_sys_clk_rate(void)
-{
- if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)
- return RTC_CLK_FREQUENCY * 397;
- else
- return OSC_CLK_FREQUENCY;
-}
-
-unsigned int get_hclk_pll_rate(void)
-{
- unsigned long long fin, fref, fcco, fout;
- u32 val, m_div, n_div, p_div;
-
- /*
- * Valid frequency ranges:
- * 1 * 10^6 <= Fin <= 20 * 10^6
- * 1 * 10^6 <= Fref <= 27 * 10^6
- * 156 * 10^6 <= Fcco <= 320 * 10^6
- */
-
- fref = fin = get_sys_clk_rate();
- if (fin > 20000000ULL || fin < 1000000ULL)
- return 0;
-
- val = readl(&clk->hclkpll_ctrl);
- m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
- n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
- if (val & CLK_HCLK_PLL_DIRECT)
- p_div = 0;
- else
- p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
- p_div = 1 << p_div;
-
- if (val & CLK_HCLK_PLL_BYPASS) {
- do_div(fin, p_div);
- return fin;
- }
-
- do_div(fref, n_div);
- if (fref > 27000000ULL || fref < 1000000ULL)
- return 0;
-
- fout = fref * m_div;
- if (val & CLK_HCLK_PLL_FEEDBACK) {
- fcco = fout;
- do_div(fout, p_div);
- } else
- fcco = fout * p_div;
-
- if (fcco > 320000000ULL || fcco < 156000000ULL)
- return 0;
-
- return fout;
-}
-
-unsigned int get_hclk_clk_div(void)
-{
- u32 val;
-
- val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
-
- return 1 << val;
-}
-
-unsigned int get_hclk_clk_rate(void)
-{
- return get_hclk_pll_rate() / get_hclk_clk_div();
-}
-
-unsigned int get_periph_clk_div(void)
-{
- u32 val;
-
- val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
-
- return (val >> 2) + 1;
-}
-
-unsigned int get_periph_clk_rate(void)
-{
- if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
- return get_sys_clk_rate();
-
- return get_hclk_pll_rate() / get_periph_clk_div();
-}
-
-int get_serial_clock(void)
-{
- return get_periph_clk_rate();
-}
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
deleted file mode 100644
index 35095a9..0000000
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/wdt.h>
-#include <asm/io.h>
-
-static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
-static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
-
-void reset_cpu(ulong addr)
-{
- /* Enable watchdog clock */
- setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
-
- /* Reset pulse length is 13005 peripheral clock frames */
- writel(13000, &wdt->pulse);
-
- /* Force WDOG_RESET2 and RESOUT_N signal active */
- writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
- &wdt->mctrl);
-
- while (1)
- /* NOP */;
-}
-
-#if defined(CONFIG_ARCH_CPU_INIT)
-int arch_cpu_init(void)
-{
- /*
- * It might be necessary to flush data cache, if U-boot is loaded
- * from kickstart bootloader, e.g. from S1L loader
- */
- flush_dcache_all();
-
- return 0;
-}
-#else
-#error "You have to select CONFIG_ARCH_CPU_INIT"
-#endif
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- printf("CPU: NXP LPC32XX\n");
- printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
- printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
- printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
-
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
deleted file mode 100644
index b567657..0000000
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/uart.h>
-#include <asm/io.h>
-
-static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
-static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
-
-void lpc32xx_uart_init(unsigned int uart_id)
-{
- if (uart_id < 1 || uart_id > 7)
- return;
-
- /* Disable loopback mode, if it is set by S1L bootloader */
- clrbits_le32(&ctrl->loop,
- UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
-
- if (uart_id < 3 || uart_id > 6)
- return;
-
- /* Enable UART system clock */
- setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
-
- /* Set UART into autoclock mode */
- clrsetbits_le32(&ctrl->clkmode,
- UART_CLKMODE_MASK(uart_id),
- UART_CLKMODE_AUTO(uart_id));
-
- /* Bypass pre-divider of UART clock */
- writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
- &clk->u3clk + (uart_id - 3));
-}
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
deleted file mode 100644
index dc1217e..0000000
--- a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/timer.h>
-#include <asm/io.h>
-
-static struct timer_regs *timer0 = (struct timer_regs *)TIMER0_BASE;
-static struct timer_regs *timer1 = (struct timer_regs *)TIMER1_BASE;
-static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
-
-static void lpc32xx_timer_clock(u32 bit, int enable)
-{
- if (enable)
- setbits_le32(&clk->timclk_ctrl1, bit);
- else
- clrbits_le32(&clk->timclk_ctrl1, bit);
-}
-
-static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq)
-{
- writel(TIMER_TCR_COUNTER_RESET, &timer->tcr);
- writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
- writel(0, &timer->tc);
- writel(0, &timer->pr);
-
- /* Count mode is every rising PCLK edge */
- writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr);
-
- /* Set prescale counter value */
- writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
-}
-
-static void lpc32xx_timer_count(struct timer_regs *timer, int enable)
-{
- if (enable)
- writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr);
- else
- writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
-}
-
-int timer_init(void)
-{
- lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1);
- lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ);
- lpc32xx_timer_count(timer0, 1);
-
- return 0;
-}
-
-ulong get_timer(ulong base)
-{
- return readl(&timer0->tc) - base;
-}
-
-void __udelay(unsigned long usec)
-{
- lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1);
- lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000);
- lpc32xx_timer_count(timer1, 1);
-
- while (readl(&timer1->tc) < usec)
- /* NOP */;
-
- lpc32xx_timer_count(timer1, 0);
- lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0);
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
deleted file mode 100644
index 92f6c15..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _LPC32XX_CLK_H
-#define _LPC32XX_CLK_H
-
-#include <asm/types.h>
-
-#define OSC_CLK_FREQUENCY 13000000
-#define RTC_CLK_FREQUENCY 32768
-
-/* Clocking and Power Control Registers */
-struct clk_pm_regs {
- u32 reserved0[5];
- u32 boot_map; /* Boot Map Control Register */
- u32 p0_intr_er; /* Port 0/1 Start and Interrupt Enable */
- u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */
- /* Internal Start Signal Sources Registers */
- u32 start_er_int; /* Start Enable Register */
- u32 start_rsr_int; /* Start Raw Status Register */
- u32 start_sr_int; /* Start Status Register */
- u32 start_apr_int; /* Start Activation Polarity Register */
- /* Device Pin Start Signal Sources Registers */
- u32 start_er_pin; /* Start Enable Register */
- u32 start_rsr_pin; /* Start Raw Status Register */
- u32 start_sr_pin; /* Start Status Register */
- u32 start_apr_pin; /* Start Activation Polarity Register */
- /* Clock Control Registers */
- u32 hclkdiv_ctrl; /* HCLK Divider Control Register */
- u32 pwr_ctrl; /* Power Control Register */
- u32 pll397_ctrl; /* PLL397 Control Register */
- u32 osc_ctrl; /* Main Oscillator Control Register */
- u32 sysclk_ctrl; /* SYSCLK Control Register */
- u32 lcdclk_ctrl; /* LCD Clock Control Register */
- u32 hclkpll_ctrl; /* HCLK PLL Control Register */
- u32 reserved1;
- u32 adclk_ctrl1; /* ADC Clock Control1 Register */
- u32 usb_ctrl; /* USB Control Register */
- u32 sdramclk_ctrl; /* SDRAM Clock Control Register */
- u32 ddr_lap_nom; /* DDR Calibration Nominal Value */
- u32 ddr_lap_count; /* DDR Calibration Measured Value */
- u32 ddr_cal_delay; /* DDR Calibration Delay Value */
- u32 ssp_ctrl; /* SSP Control Register */
- u32 i2s_ctrl; /* I2S Clock Control Register */
- u32 ms_ctrl; /* Memory Card Control Register */
- u32 reserved2[3];
- u32 macclk_ctrl; /* Ethernet MAC Clock Control Register */
- u32 reserved3[4];
- u32 test_clk; /* Test Clock Selection Register */
- u32 sw_int; /* Software Interrupt Register */
- u32 i2cclk_ctrl; /* I2C Clock Control Register */
- u32 keyclk_ctrl; /* Keyboard Scan Clock Control Register */
- u32 adclk_ctrl; /* ADC Clock Control Register */
- u32 pwmclk_ctrl; /* PWM Clock Control Register */
- u32 timclk_ctrl; /* Watchdog and Highspeed Timer Control */
- u32 timclk_ctrl1; /* Motor and Timer Clock Control */
- u32 spi_ctrl; /* SPI Control Register */
- u32 flashclk_ctrl; /* NAND Flash Clock Control Register */
- u32 reserved4;
- u32 u3clk; /* UART 3 Clock Control Register */
- u32 u4clk; /* UART 4 Clock Control Register */
- u32 u5clk; /* UART 5 Clock Control Register */
- u32 u6clk; /* UART 6 Clock Control Register */
- u32 irdaclk; /* IrDA Clock Control Register */
- u32 uartclk_ctrl; /* UART Clock Control Register */
- u32 dmaclk_ctrl; /* DMA Clock Control Register */
- u32 autoclk_ctrl; /* Autoclock Control Register */
-};
-
-/* HCLK Divider Control Register bits */
-#define CLK_HCLK_DDRAM_HALF (0x2 << 7)
-#define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7)
-#define CLK_HCLK_DDRAM_STOPPED (0x0 << 7)
-#define CLK_HCLK_PERIPH_DIV_MASK (0x1F << 2)
-#define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2)
-#define CLK_HCLK_ARM_PLL_DIV_MASK (0x3 << 0)
-#define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0)
-#define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0)
-#define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0)
-
-/* Power Control Register bits */
-#define CLK_PWR_HCLK_RUN_PERIPH (1 << 10)
-#define CLK_PWR_EMC_SREFREQ (1 << 9)
-#define CLK_PWR_EMC_SREFREQ_UPDATE (1 << 8)
-#define CLK_PWR_SDRAM_SREFREQ (1 << 7)
-#define CLK_PWR_HIGHCORE_LEVEL (1 << 5)
-#define CLK_PWR_SYSCLKEN_LEVEL (1 << 4)
-#define CLK_PWR_SYSCLKEN_CTRL (1 << 3)
-#define CLK_PWR_NORMAL_RUN (1 << 2)
-#define CLK_PWR_HIGHCORE_CTRL (1 << 1)
-#define CLK_PWR_STOP_MODE (1 << 0)
-
-/* SYSCLK Control Register bits */
-#define CLK_SYSCLK_PLL397 (1 << 1)
-#define CLK_SYSCLK_MUX (1 << 0)
-
-/* HCLK PLL Control Register bits */
-#define CLK_HCLK_PLL_OPERATING (1 << 16)
-#define CLK_HCLK_PLL_BYPASS (1 << 15)
-#define CLK_HCLK_PLL_DIRECT (1 << 14)
-#define CLK_HCLK_PLL_FEEDBACK (1 << 13)
-#define CLK_HCLK_PLL_POSTDIV_MASK (0x3 << 11)
-#define CLK_HCLK_PLL_POSTDIV_16 (0x3 << 11)
-#define CLK_HCLK_PLL_POSTDIV_8 (0x2 << 11)
-#define CLK_HCLK_PLL_POSTDIV_4 (0x1 << 11)
-#define CLK_HCLK_PLL_POSTDIV_2 (0x0 << 11)
-#define CLK_HCLK_PLL_PREDIV_MASK (0x3 << 9)
-#define CLK_HCLK_PLL_PREDIV_4 (0x3 << 9)
-#define CLK_HCLK_PLL_PREDIV_3 (0x2 << 9)
-#define CLK_HCLK_PLL_PREDIV_2 (0x1 << 9)
-#define CLK_HCLK_PLL_PREDIV_1 (0x0 << 9)
-#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK (0xFF << 1)
-#define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1)
-#define CLK_HCLK_PLL_LOCKED (1 << 0)
-
-/* Ethernet MAC Clock Control Register bits */
-#define CLK_MAC_RMII (0x3 << 3)
-#define CLK_MAC_MII (0x1 << 3)
-#define CLK_MAC_MASTER (1 << 2)
-#define CLK_MAC_SLAVE (1 << 1)
-#define CLK_MAC_REG (1 << 0)
-
-/* Timer Clock Control1 Register bits */
-#define CLK_TIMCLK_MOTOR (1 << 6)
-#define CLK_TIMCLK_TIMER3 (1 << 5)
-#define CLK_TIMCLK_TIMER2 (1 << 4)
-#define CLK_TIMCLK_TIMER1 (1 << 3)
-#define CLK_TIMCLK_TIMER0 (1 << 2)
-#define CLK_TIMCLK_TIMER5 (1 << 1)
-#define CLK_TIMCLK_TIMER4 (1 << 0)
-
-/* Timer Clock Control Register bits */
-#define CLK_TIMCLK_HSTIMER (1 << 1)
-#define CLK_TIMCLK_WATCHDOG (1 << 0)
-
-/* UART Clock Control Register bits */
-#define CLK_UART(n) (1 << ((n) - 3))
-
-/* UARTn Clock Select Registers bits */
-#define CLK_UART_HCLK (1 << 16)
-#define CLK_UART_X_DIV(n) (((n) & 0xFF) << 8)
-#define CLK_UART_Y_DIV(n) (((n) & 0xFF) << 0)
-
-/* DMA Clock Control Register bits */
-#define CLK_DMA_ENABLE (1 << 0)
-
-unsigned int get_sys_clk_rate(void);
-unsigned int get_hclk_pll_rate(void);
-unsigned int get_hclk_clk_div(void);
-unsigned int get_hclk_clk_rate(void);
-unsigned int get_periph_clk_div(void);
-unsigned int get_periph_clk_rate(void);
-
-#endif /* _LPC32XX_CLK_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
deleted file mode 100644
index 8f6426b..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Common definitions for LPC32XX board configurations
- *
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _LPC32XX_CONFIG_H
-#define _LPC32XX_CONFIG_H
-
-/* Basic CPU architecture */
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_NR_DRAM_BANKS_MAX 2
-
-/* UART configuration */
-#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2)
-#elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
- (CONFIG_SYS_LPC32XX_UART == 7)
-#define CONFIG_LPC32XX_HSUART
-#else
-#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7"
-#endif
-
-#if defined(CONFIG_SYS_NS16550_SERIAL)
-#define CONFIG_SYS_NS16550
-
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#define CONFIG_SYS_NS16550_COM1 UART3_BASE
-#define CONFIG_SYS_NS16550_COM2 UART4_BASE
-#define CONFIG_SYS_NS16550_COM3 UART5_BASE
-#define CONFIG_SYS_NS16550_COM4 UART6_BASE
-#endif
-
-#if defined(CONFIG_LPC32XX_HSUART)
-#if CONFIG_SYS_LPC32XX_UART == 1
-#define HS_UART_BASE HS_UART1_BASE
-#elif CONFIG_SYS_LPC32XX_UART == 2
-#define HS_UART_BASE HS_UART2_BASE
-#else /* CONFIG_SYS_LPC32XX_UART == 7 */
-#define HS_UART_BASE HS_UART7_BASE
-#endif
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
-
-/* NOR Flash */
-#if defined(CONFIG_SYS_FLASH_CFI)
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_PROTECTION
-#endif
-
-#endif /* _LPC32XX_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h
deleted file mode 100644
index 199b4a0..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _LPC32XX_CPU_H
-#define _LPC32XX_CPU_H
-
-/* LPC32XX Memory map */
-
-/* AHB physical base addresses */
-#define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
-#define SSP0_BASE 0x20084000 /* SSP0 registers base */
-#define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
-#define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
-#define DMA_BASE 0x31000000 /* DMA controller registers base */
-#define USB_BASE 0x31020000 /* USB registers base */
-#define LCD_BASE 0x31040000 /* LCD registers base */
-#define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
-#define EMC_BASE 0x31080000 /* EMC configuration registers base */
-
-/* FAB peripherals base addresses */
-#define CLK_PM_BASE 0x40004000 /* System control registers base */
-#define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */
-#define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */
-#define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */
-#define RTC_BASE 0x40024000 /* RTC registers base */
-#define GPIO_BASE 0x40028000 /* GPIO registers base */
-#define WDT_BASE 0x4003C000 /* Watchdog timer registers base */
-#define TIMER0_BASE 0x40044000 /* Timer0 registers base */
-#define TIMER1_BASE 0x4004C000 /* Timer1 registers base */
-#define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */
-
-/* APB peripherals base addresses */
-#define UART3_BASE 0x40080000 /* UART 3 registers base */
-#define UART4_BASE 0x40088000 /* UART 4 registers base */
-#define UART5_BASE 0x40090000 /* UART 5 registers base */
-#define UART6_BASE 0x40098000 /* UART 6 registers base */
-
-/* External SDRAM Memory Bank base addresses */
-#define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */
-#define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */
-
-/* External Static Memory Bank base addresses */
-#define EMC_CS0_BASE 0xE0000000
-#define EMC_CS1_BASE 0xE1000000
-#define EMC_CS2_BASE 0xE2000000
-#define EMC_CS3_BASE 0xE3000000
-
-#endif /* _LPC32XX_CPU_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h
deleted file mode 100644
index 82d9bcc..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/emc.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _LPC32XX_EMC_H
-#define _LPC32XX_EMC_H
-
-#include <asm/types.h>
-
-/* EMC Registers */
-struct emc_regs {
- u32 ctrl; /* Controls operation of the EMC */
- u32 status; /* Provides EMC status information */
- u32 config; /* Configures operation of the EMC */
- u32 reserved0[5];
- u32 control; /* Controls dyn memory operation */
- u32 refresh; /* Configures dyn memory refresh operation */
- u32 read_config; /* Configures the dyn memory read strategy */
- u32 reserved1;
- u32 t_rp; /* Precharge command period */
- u32 t_ras; /* Active to precharge command period */
- u32 t_srex; /* Self-refresh exit time */
- u32 reserved2[2];
- u32 t_wr; /* Write recovery time */
- u32 t_rc; /* Active to active command period */
- u32 t_rfc; /* Auto-refresh period */
- u32 t_xsr; /* Exit self-refresh to active command time */
- u32 t_rrd; /* Active bank A to active bank B latency */
- u32 t_mrd; /* Load mode register to active command time */
- u32 t_cdlr; /* Last data in to read command time */
- u32 reserved3[8];
- u32 extended_wait; /* time for static memory rd/wr transfers */
- u32 reserved4[31];
- u32 config0; /* Configuration information for the SDRAM */
- u32 rascas0; /* RAS and CAS latencies for the SDRAM */
- u32 reserved5[6];
- u32 config1; /* Configuration information for the SDRAM */
- u32 rascas1; /* RAS and CAS latencies for the SDRAM */
- u32 reserved6[54];
- struct emc_stat_t {
- u32 config; /* Static memory configuration */
- u32 waitwen; /* Delay from chip select to write enable */
- u32 waitoen; /* Delay to output enable */
- u32 waitrd; /* Delay to a read access */
- u32 waitpage; /* Delay for async page mode read */
- u32 waitwr; /* Delay to a write access */
- u32 waitturn; /* Number of bus turnaround cycles */
- u32 reserved;
- } stat[4];
- u32 reserved7[96];
- struct emc_ahb_t {
- u32 control; /* Control register for AHB */
- u32 status; /* Status register for AHB */
- u32 timeout; /* Timeout register for AHB */
- u32 reserved[5];
- } ahb[5];
-};
-
-/* Static Memory Configuration Register bits */
-#define EMC_STAT_CONFIG_WP (1 << 20)
-#define EMC_STAT_CONFIG_EW (1 << 8)
-#define EMC_STAT_CONFIG_PB (1 << 7)
-#define EMC_STAT_CONFIG_PC (1 << 6)
-#define EMC_STAT_CONFIG_PM (1 << 3)
-#define EMC_STAT_CONFIG_32BIT (2 << 0)
-#define EMC_STAT_CONFIG_16BIT (1 << 0)
-#define EMC_STAT_CONFIG_8BIT (0 << 0)
-
-/* Static Memory Delay Registers */
-#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F)
-#define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F)
-#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F)
-#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F)
-#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F)
-#define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F)
-
-#endif /* _LPC32XX_EMC_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
deleted file mode 100644
index 28812be..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _LPC32XX_SYS_PROTO_H
-#define _LPC32XX_SYS_PROTO_H
-
-void lpc32xx_uart_init(unsigned int uart_id);
-
-#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/timer.h b/arch/arm/include/asm/arch-lpc32xx/timer.h
deleted file mode 100644
index bd90144..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/timer.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _LPC32XX_TIMER_H
-#define _LPC32XX_TIMER_H
-
-#include <asm/types.h>
-
-/* Timer/Counter Registers */
-struct timer_regs {
- u32 ir; /* Interrupt Register */
- u32 tcr; /* Timer Control Register */
- u32 tc; /* Timer Counter */
- u32 pr; /* Prescale Register */
- u32 pc; /* Prescale Counter */
- u32 mcr; /* Match Control Register */
- u32 mr[4]; /* Match Registers */
- u32 ccr; /* Capture Control Register */
- u32 cr[4]; /* Capture Registers */
- u32 emr; /* External Match Register */
- u32 reserved[12];
- u32 ctcr; /* Count Control Register */
-};
-
-/* Timer/Counter Interrupt Register bits */
-#define TIMER_IR_CR(n) (1 << ((n) + 4))
-#define TIMER_IR_MR(n) (1 << (n))
-
-/* Timer/Counter Timer Control Register bits */
-#define TIMER_TCR_COUNTER_RESET (1 << 1)
-#define TIMER_TCR_COUNTER_ENABLE (1 << 0)
-#define TIMER_TCR_COUNTER_DISABLE (0 << 0)
-
-/* Timer/Counter Match Control Register bits */
-#define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2))
-#define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1))
-#define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n)))
-
-/* Timer/Counter Capture Control Register bits */
-#define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2))
-#define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1))
-#define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n)))
-
-/* Timer/Counter External Match Register bits */
-#define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4))
-#define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4))
-#define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4))
-#define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4))
-#define TIMER_EMR_EM(n) (1 << (n))
-
-/* Timer/Counter Count Control Register bits */
-#define TIMER_CTCR_INPUT(n) ((n) << 2)
-#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0)
-#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0)
-#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0)
-#define TIMER_CTCR_MODE_TIMER (0x0 << 0)
-
-#endif /* _LPC32XX_TIMER_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/uart.h b/arch/arm/include/asm/arch-lpc32xx/uart.h
deleted file mode 100644
index 01dacd6..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/uart.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _LPC32XX_UART_H
-#define _LPC32XX_UART_H
-
-#include <asm/types.h>
-
-/* 14-clock UART Registers */
-struct hsuart_regs {
- union {
- u32 rx; /* Receiver FIFO */
- u32 tx; /* Transmitter FIFO */
- };
- u32 level; /* FIFO Level Register */
- u32 iir; /* Interrupt ID Register */
- u32 ctrl; /* Control Register */
- u32 rate; /* Rate Control Register */
-};
-
-/* 14-clock UART Receiver FIFO Register bits */
-#define HSUART_RX_BREAK (1 << 10)
-#define HSUART_RX_ERROR (1 << 9)
-#define HSUART_RX_EMPTY (1 << 8)
-#define HSUART_RX_DATA (0xff << 0)
-
-/* 14-clock UART Level Register bits */
-#define HSUART_LEVEL_TX (0xff << 8)
-#define HSUART_LEVEL_RX (0xff << 0)
-
-/* 14-clock UART Interrupt Identification Register bits */
-#define HSUART_IIR_TX_INT_SET (1 << 6)
-#define HSUART_IIR_RX_OE (1 << 5)
-#define HSUART_IIR_BRK (1 << 4)
-#define HSUART_IIR_FE (1 << 3)
-#define HSUART_IIR_RX_TIMEOUT (1 << 2)
-#define HSUART_IIR_RX_TRIG (1 << 1)
-#define HSUART_IIR_TX (1 << 0)
-
-/* 14-clock UART Control Register bits */
-#define HSUART_CTRL_HRTS_INV (1 << 21)
-#define HSUART_CTRL_HRTS_TRIG_48 (0x3 << 19)
-#define HSUART_CTRL_HRTS_TRIG_32 (0x2 << 19)
-#define HSUART_CTRL_HRTS_TRIG_16 (0x1 << 19)
-#define HSUART_CTRL_HRTS_TRIG_8 (0x0 << 19)
-#define HSUART_CTRL_HRTS_EN (1 << 18)
-#define HSUART_CTRL_TMO_16 (0x3 << 16)
-#define HSUART_CTRL_TMO_8 (0x2 << 16)
-#define HSUART_CTRL_TMO_4 (0x1 << 16)
-#define HSUART_CTRL_TMO_DISABLED (0x0 << 16)
-#define HSUART_CTRL_HCTS_INV (1 << 15)
-#define HSUART_CTRL_HCTS_EN (1 << 14)
-#define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9)
-#define HSUART_CTRL_HSU_BREAK (1 << 8)
-#define HSUART_CTRL_HSU_ERR_INT_EN (1 << 7)
-#define HSUART_CTRL_HSU_RX_INT_EN (1 << 6)
-#define HSUART_CTRL_HSU_TX_INT_EN (1 << 5)
-#define HSUART_CTRL_HSU_RX_TRIG_48 (0x5 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_32 (0x4 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_16 (0x3 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_8 (0x2 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_4 (0x1 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_1 (0x0 << 2)
-#define HSUART_CTRL_HSU_TX_TRIG_16 (0x3 << 0)
-#define HSUART_CTRL_HSU_TX_TRIG_8 (0x2 << 0)
-#define HSUART_CTRL_HSU_TX_TRIG_4 (0x1 << 0)
-#define HSUART_CTRL_HSU_TX_TRIG_0 (0x0 << 0)
-
-/* UART Control Registers */
-struct uart_ctrl_regs {
- u32 ctrl; /* Control Register */
- u32 clkmode; /* Clock Mode Register */
- u32 loop; /* Loopback Control Register */
-};
-
-/* UART Control Register bits */
-#define UART_CTRL_UART3_MD_CTRL (1 << 11)
-#define UART_CTRL_HDPX_INV (1 << 10)
-#define UART_CTRL_HDPX_EN (1 << 9)
-#define UART_CTRL_UART6_IRDA (1 << 5)
-#define UART_CTRL_IR_TX6_INV (1 << 4)
-#define UART_CTRL_IR_RX6_INV (1 << 3)
-#define UART_CTRL_IR_RX_LENGTH (1 << 2)
-#define UART_CTRL_IR_TX_LENGTH (1 << 1)
-#define UART_CTRL_UART5_USB_MODE (1 << 0)
-
-/* UART Clock Mode Register bits */
-#define UART_CLKMODE_STATX(n) (1 << ((n) + 16))
-#define UART_CLKMODE_STAT (1 << 14)
-#define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2))
-#define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2))
-#define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2))
-#define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2))
-
-/* UART Loopback Control Register bits */
-#define UART_LOOPBACK(n) (1 << ((n) - 1))
-
-#endif /* _LPC32XX_UART_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/wdt.h b/arch/arm/include/asm/arch-lpc32xx/wdt.h
deleted file mode 100644
index d7903c2..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/wdt.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _LPC32XX_WDT_H
-#define _LPC32XX_WDT_H
-
-#include <asm/types.h>
-
-/* Watchdog Timer Registers */
-struct wdt_regs {
- u32 isr; /* Interrupt Status Register */
- u32 ctrl; /* Control Register */
- u32 counter; /* Counter Value Register */
- u32 mctrl; /* Match Control Register */
- u32 match0; /* Match 0 Register */
- u32 emr; /* External Match Control Register */
- u32 pulse; /* Reset Pulse Length Register */
- u32 res; /* Reset Source Register */
-};
-
-/* Watchdog Timer Control Register bits */
-#define WDTIM_CTRL_PAUSE_EN (1 << 2)
-#define WDTIM_CTRL_RESET_COUNT (1 << 1)
-#define WDTIM_CTRL_COUNT_ENAB (1 << 0)
-
-/* Watchdog Timer Match Control Register bits */
-#define WDTIM_MCTRL_RESFRC2 (1 << 6)
-#define WDTIM_MCTRL_RESFRC1 (1 << 5)
-#define WDTIM_MCTRL_M_RES2 (1 << 4)
-#define WDTIM_MCTRL_M_RES1 (1 << 3)
-#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2)
-#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1)
-#define WDTIM_MCTRL_MR0_INT (1 << 0)
-
-#endif /* _LPC32XX_WDT_H */
diff --git a/board/timll/devkit3250/Kconfig b/board/timll/devkit3250/Kconfig
deleted file mode 100644
index e3bd456..0000000
--- a/board/timll/devkit3250/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_DEVKIT3250
-
-config SYS_BOARD
- default "devkit3250"
-
-config SYS_VENDOR
- default "timll"
-
-config SYS_SOC
- default "lpc32xx"
-
-config SYS_CONFIG_NAME
- default "devkit3250"
-
-endif
diff --git a/board/timll/devkit3250/MAINTAINERS b/board/timll/devkit3250/MAINTAINERS
deleted file mode 100644
index cb93563..0000000
--- a/board/timll/devkit3250/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DEVKIT3250 BOARD
-M: Vladimir Zapolskiy <vz@mleia.com>
-S: Maintained
-F: board/timll/devkit3250/
-F: include/configs/devkit3250.h
-F: configs/devkit3250_defconfig
diff --git a/board/timll/devkit3250/Makefile b/board/timll/devkit3250/Makefile
deleted file mode 100644
index 4722986..0000000
--- a/board/timll/devkit3250/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
-# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := devkit3250.o
diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c
deleted file mode 100644
index 6acc416..0000000
--- a/board/timll/devkit3250/devkit3250.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Embest/Timll DevKit3250 board support
- *
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/emc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
-
-int board_early_init_f(void)
-{
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_SYS_FLASH_CFI
- /* Use 16-bit memory interface for NOR Flash */
- emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
-
- /* Change the NOR timings to optimum value to get maximum bandwidth */
- emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
- emc->stat[0].waitoen = EMC_STAT_WAITOEN(1);
- emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
- emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
- emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
- emc->stat[0].waitturn = EMC_STAT_WAITTURN(2);
-#endif
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
-
- return 0;
-}
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
deleted file mode 100644
index ba990bc..0000000
--- a/configs/devkit3250_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_DEVKIT3250=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index b24bfea..649d4d0 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+devkit3250 arm arm926ejs - - Vladimir Zapolskiy <vz@mleia.com>
zmx25 arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
imx31_phycore arm arm1136 - - Guennadi Liakhovetski <g.liakhovetski@gmx.de>
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 4cc00cd..cedf246 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -20,7 +20,6 @@ obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
obj-$(CONFIG_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
obj-$(CONFIG_DW_SERIAL) += serial_dw.o
-obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += mcfuart.o
obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
obj-$(CONFIG_SYS_NS16550) += ns16550.o
diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c
deleted file mode 100644
index c8926a8..0000000
--- a/drivers/serial/lpc32xx_hsuart.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/uart.h>
-#include <asm/io.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct hsuart_regs *hsuart = (struct hsuart_regs *)HS_UART_BASE;
-
-static void lpc32xx_serial_setbrg(void)
-{
- u32 div;
-
- /* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
- div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1;
- if (div > 255)
- div = 255;
-
- writel(div, &hsuart->rate);
-}
-
-static int lpc32xx_serial_getc(void)
-{
- while (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
- /* NOP */;
-
- return readl(&hsuart->rx) & HSUART_RX_DATA;
-}
-
-static void lpc32xx_serial_putc(const char c)
-{
- if (c == '\n')
- serial_putc('\r');
-
- writel(c, &hsuart->tx);
-
- /* Wait for character to be sent */
- while (readl(&hsuart->level) & HSUART_LEVEL_TX)
- /* NOP */;
-}
-
-static int lpc32xx_serial_tstc(void)
-{
- if (readl(&hsuart->level) & HSUART_LEVEL_RX)
- return 1;
-
- return 0;
-}
-
-static int lpc32xx_serial_init(void)
-{
- lpc32xx_serial_setbrg();
-
- /* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
- writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
- HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
- &hsuart->ctrl);
- return 0;
-}
-
-static struct serial_device lpc32xx_serial_drv = {
- .name = "lpc32xx_serial",
- .start = lpc32xx_serial_init,
- .stop = NULL,
- .setbrg = lpc32xx_serial_setbrg,
- .putc = lpc32xx_serial_putc,
- .puts = default_serial_puts,
- .getc = lpc32xx_serial_getc,
- .tstc = lpc32xx_serial_tstc,
-};
-
-void lpc32xx_serial_initialize(void)
-{
- serial_register(&lpc32xx_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &lpc32xx_serial_drv;
-}
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 95c992a..3210a26 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -131,7 +131,6 @@ serial_initfunc(ks8695_serial_initialize);
serial_initfunc(leon2_serial_initialize);
serial_initfunc(leon3_serial_initialize);
serial_initfunc(lh7a40x_serial_initialize);
-serial_initfunc(lpc32xx_serial_initialize);
serial_initfunc(marvell_serial_initialize);
serial_initfunc(max3100_serial_initialize);
serial_initfunc(mcf_serial_initialize);
@@ -224,7 +223,6 @@ void serial_initialize(void)
leon2_serial_initialize();
leon3_serial_initialize();
lh7a40x_serial_initialize();
- lpc32xx_serial_initialize();
marvell_serial_initialize();
max3100_serial_initialize();
mcf_serial_initialize();
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
deleted file mode 100644
index bd96a7d..0000000
--- a/include/configs/devkit3250.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Embest/Timll DevKit3250 board configuration file
- *
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_DEVKIT3250_H__
-#define __CONFIG_DEVKIT3250_H__
-
-/* SoC and board defines */
-#include <linux/sizes.h>
-#include <asm/arch/cpu.h>
-
-/*
- * Define DevKit3250 machine type by hand until it lands in mach-types
- */
-#define MACH_TYPE_DEVKIT3250 3697
-#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
-
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/*
- * Memory configurations
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_MALLOC_LEN SZ_1M
-#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_64M
-#define CONFIG_SYS_TEXT_BASE 0x83FA0000
-#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
- - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART 2 /* UART2 */
-#define CONFIG_BAUDRATE 115200
-
-/*
- * NOR Flash
- */
-#define CONFIG_CMD_FLASH
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 71
-#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
-#define CONFIG_SYS_FLASH_SIZE SZ_4M
-#define CONFIG_SYS_FLASH_CFI
-
-/*
- * U-Boot General Configurations
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE SZ_128K
-
-/*
- * U-Boot Commands
- */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_CACHE
-
-/*
- * Boot Linux
- */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_BOOTARGS "console=ttyS2,115200n8"
-#define CONFIG_LOADADDR 0x80008000
-
-/*
- * Include SoC specific configuration
- */
-#include <asm/arch/config.h>
-
-#endif /* __CONFIG_DEVKIT3250_H__*/
diff --git a/include/serial.h b/include/serial.h
index 3d2e569..42e2cc1 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -186,7 +186,6 @@ void ks8695_serial_initialize(void);
void leon2_serial_initialize(void);
void leon3_serial_initialize(void);
void lh7a40x_serial_initialize(void);
-void lpc32xx_serial_initialize(void);
void marvell_serial_initialize(void);
void max3100_serial_initialize(void);
void mcf_serial_initialize(void);
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 06/11] ARM: remove dkb board support
2015-02-10 4:44 [U-Boot] [PATCH 0/11] ARM: remove non-generic boards Masahiro Yamada
` (4 preceding siblings ...)
2015-02-10 4:44 ` [U-Boot] [PATCH 05/11] ARM: remove devkit3250 " Masahiro Yamada
@ 2015-02-10 4:44 ` Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 07/11] ARM: remove cm4008 and cm41xx " Masahiro Yamada
` (4 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 4:44 UTC (permalink / raw)
To: u-boot
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Lei Wen <leiwen@marvell.com>
---
arch/arm/Kconfig | 5 -
arch/arm/cpu/arm926ejs/Makefile | 1 -
arch/arm/cpu/arm926ejs/pantheon/Makefile | 9 --
arch/arm/cpu/arm926ejs/pantheon/cpu.c | 85 -----------
arch/arm/cpu/arm926ejs/pantheon/dram.c | 117 ---------------
arch/arm/cpu/arm926ejs/pantheon/timer.c | 201 --------------------------
arch/arm/include/asm/arch-pantheon/config.h | 53 -------
arch/arm/include/asm/arch-pantheon/cpu.h | 77 ----------
arch/arm/include/asm/arch-pantheon/gpio.h | 0
arch/arm/include/asm/arch-pantheon/mfp.h | 39 -----
arch/arm/include/asm/arch-pantheon/pantheon.h | 38 -----
board/Marvell/dkb/Kconfig | 15 --
board/Marvell/dkb/MAINTAINERS | 6 -
board/Marvell/dkb/Makefile | 9 --
board/Marvell/dkb/dkb.c | 85 -----------
configs/dkb_defconfig | 2 -
doc/README.scrapyard | 1 +
include/configs/dkb.h | 51 -------
18 files changed, 1 insertion(+), 793 deletions(-)
delete mode 100644 arch/arm/cpu/arm926ejs/pantheon/Makefile
delete mode 100644 arch/arm/cpu/arm926ejs/pantheon/cpu.c
delete mode 100644 arch/arm/cpu/arm926ejs/pantheon/dram.c
delete mode 100644 arch/arm/cpu/arm926ejs/pantheon/timer.c
delete mode 100644 arch/arm/include/asm/arch-pantheon/config.h
delete mode 100644 arch/arm/include/asm/arch-pantheon/cpu.h
delete mode 100644 arch/arm/include/asm/arch-pantheon/gpio.h
delete mode 100644 arch/arm/include/asm/arch-pantheon/mfp.h
delete mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h
delete mode 100644 board/Marvell/dkb/Kconfig
delete mode 100644 board/Marvell/dkb/MAINTAINERS
delete mode 100644 board/Marvell/dkb/Makefile
delete mode 100644 board/Marvell/dkb/dkb.c
delete mode 100644 configs/dkb_defconfig
delete mode 100644 include/configs/dkb.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b0b7eaf..74dd164 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -316,10 +316,6 @@ config ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
-config TARGET_DKB
- bool "Support dkb"
- select CPU_ARM926EJS
-
config TARGET_SPEAR300
bool "Support spear300"
select CPU_ARM926EJS
@@ -843,7 +839,6 @@ source "board/BuS/vl_ma2sc/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/db-mv784mp-gp/Kconfig"
-source "board/Marvell/dkb/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/afeb9260/Kconfig"
source "board/altera/socfpga/Kconfig"
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index bfa365e..38ab0d4 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -23,6 +23,5 @@ obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(CONFIG_ARCH_NOMADIK) += nomadik/
obj-$(CONFIG_ORION5X) += orion5x/
-obj-$(CONFIG_PANTHEON) += pantheon/
obj-$(if $(filter spear,$(SOC)),y) += spear/
obj-$(CONFIG_ARCH_VERSATILE) += versatile/
diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile
deleted file mode 100644
index 988341f..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2011
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Lei Wen <leiwen@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o timer.o dram.o
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
deleted file mode 100644
index 4e2a177..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID (1<<8)
-#define L2C_RAM_SEL (1<<4)
-
-int arch_cpu_init(void)
-{
- u32 val;
- struct panthcpu_registers *cpuregs =
- (struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
- struct panthapb_registers *apbclkres =
- (struct panthapb_registers*) PANTHEON_APBC_BASE;
-
- struct panthmpmu_registers *mpmu =
- (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
-
- struct panthapmu_registers *apmu =
- (struct panthapmu_registers *) PANTHEON_APMU_BASE;
-
- /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
- val = readl(&cpuregs->cpu_conf);
- val = val | SET_MRVL_ID;
- writel(val, &cpuregs->cpu_conf);
-
- /* Turn on clock gating (PMUM_CCGR) */
- writel(0xFFFFFFFF, &mpmu->ccgr);
-
- /* Turn on clock gating (PMUM_ACGR) */
- writel(0xFFFFFFFF, &mpmu->acgr);
-
- /* Turn on uart2 clock */
- writel(UARTCLK14745KHZ, &apbclkres->uart0);
-
- /* Enable GPIO clock */
- writel(APBC_APBCLK, &apbclkres->gpio);
-
-#ifdef CONFIG_I2C_MV
- /* Enable I2C clock */
- writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
- writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
-#endif
-
-#ifdef CONFIG_MV_SDHCI
- /* Enable mmc clock */
- writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
- &apmu->sd1);
- writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
- &apmu->sd3);
-#endif
-
- icache_enable();
-
- return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- u32 id;
- struct panthcpu_registers *cpuregs =
- (struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
- id = readl(&cpuregs->chip_id);
- printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
- return 0;
-}
-#endif
-
-#ifdef CONFIG_I2C_MV
-void i2c_clk_enable(void)
-{
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c
deleted file mode 100644
index f77e3d0..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/dram.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>,
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pantheon.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Pantheon DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet 4.4
- */
-struct panthddr_map_registers {
- u32 cs; /* Memory Address Map Register -CS */
- u32 pad[3];
-};
-
-struct panthddr_registers {
- u8 pad[0x100 - 0x000];
- struct panthddr_map_registers mmap[2];
-};
-
-/*
- * panth_sdram_base - reads SDRAM Base Address Register
- */
-u32 panth_sdram_base(int chip_sel)
-{
- struct panthddr_registers *ddr_regs =
- (struct panthddr_registers *)PANTHEON_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
- return result;
-}
-
-/*
- * panth_sdram_size - reads SDRAM size
- */
-u32 panth_sdram_size(int chip_sel)
-{
- struct panthddr_registers *ddr_regs =
- (struct panthddr_registers *)PANTHEON_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs);
- result = (result >> 16) & 0xF;
- if (result < 0x7) {
- printf("Unknown DRAM Size\n");
- return -1;
- } else {
- return ((0x8 << (result - 0x7)) * 1024 * 1024);
- }
-}
-
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
-int dram_init(void)
-{
- int i;
-
- gd->ram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = panth_sdram_base(i);
- gd->bd->bi_dram[i].size = panth_sdram_size(i);
- /*
- * It is assumed that all memory banks are consecutive
- * and without gaps.
- * If the gap is found, ram_size will be reported for
- * consecutive memory only
- */
- if (gd->bd->bi_dram[i].start != gd->ram_size)
- break;
-
- gd->ram_size += gd->bd->bi_dram[i].size;
-
- }
-
- for (; i < CONFIG_NR_DRAM_BANKS; i++) {
- /*
- * If above loop terminated prematurely, we need to set
- * remaining banks' start address & size as 0. Otherwise other
- * u-boot functions and Linux kernel gets wrong values which
- * could result in crash
- */
- gd->bd->bi_dram[i].start = 0;
- gd->bd->bi_dram[i].size = 0;
- }
- return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-void dram_init_banksize(void)
-{
- dram_init();
-}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
deleted file mode 100644
index 6382d3b..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/timer.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-/*
- * Timer registers
- * Refer 6.2.9 in Datasheet
- */
-struct panthtmr_registers {
- u32 clk_ctrl; /* Timer clk control reg */
- u32 match[9]; /* Timer match registers */
- u32 count[3]; /* Timer count registers */
- u32 status[3];
- u32 ie[3];
- u32 preload[3]; /* Timer preload value */
- u32 preload_ctrl[3];
- u32 wdt_match_en;
- u32 wdt_match_r;
- u32 wdt_val;
- u32 wdt_sts;
- u32 icr[3];
- u32 wdt_icr;
- u32 cer; /* Timer count enable reg */
- u32 cmr;
- u32 ilr[3];
- u32 wcr;
- u32 wfar;
- u32 wsar;
- u32 cvwr[3];
-};
-
-#define TIMER 0 /* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x) ((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 0xffffffff
-#define COUNT_RD_REQ 0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
-
-/*
- * For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
- volatile int loop=100;
- ulong val;
-
- writel(COUNT_RD_REQ, &panthtimers->cvwr);
- while (loop--)
- val = readl(&panthtimers->cvwr);
-
- /*
- * This stop gcc complain and prevent loop mistake init to 0
- */
- val = readl(&panthtimers->cvwr);
-
- return val;
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (now >= gd->arch.tbl) {
- /* normal mode */
- gd->arch.tbu += now - gd->arch.tbl;
- } else {
- /* we have an overflow ... */
- gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
- }
- gd->arch.tbl = now;
-
- return gd->arch.tbu;
-}
-
-ulong get_timer(ulong base)
-{
- return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
- base);
-}
-
-void __udelay(unsigned long usec)
-{
- ulong delayticks;
- ulong endtime;
-
- delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
- endtime = get_timer_masked() + delayticks;
-
- while (get_timer_masked() < endtime)
- ;
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
- struct panthapb_registers *apb1clkres =
- (struct panthapb_registers *) PANTHEON_APBC_BASE;
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
-
- /* Enable Timer clock@3.25 MHZ */
- writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
- /* load value into timer */
- writel(0x0, &panthtimers->clk_ctrl);
- /* Use Timer 0 Match Resiger 0 */
- writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
- /* Preload value is 0 */
- writel(0x0, &panthtimers->preload[TIMER]);
- /* Enable match comparator 0 for Timer 0 */
- writel(0x1, &panthtimers->preload_ctrl[TIMER]);
-
- /* Enable timer 0 */
- writel(0x1, &panthtimers->cer);
- /* init the gd->arch.tbu and gd->arch.tbl value */
- gd->arch.tbl = read_timer();
- gd->arch.tbu = 0;
-
- return 0;
-}
-
-#define MPMU_APRR_WDTR (1<<4)
-#define TMR_WFAR 0xbaba /* WDT Register First key */
-#define TMP_WSAR 0xeb10 /* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu (unsigned long ignored)
-{
- struct panthmpmu_registers *mpmu =
- (struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
- u32 val;
-
- /* negate hardware reset to the WDT after system reset */
- val = readl(&mpmu->aprr);
- val = val | MPMU_APRR_WDTR;
- writel(val, &mpmu->aprr);
-
- /* reset/enable WDT clock */
- writel(APBC_APBCLK, &mpmu->wdtpcr);
-
- /* clear previous WDT status */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0, &panthtimers->wdt_sts);
-
- /* set match counter */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0xf, &panthtimers->wdt_match_r);
-
- /* enable WDT reset */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0x3, &panthtimers->wdt_match_en);
-
- /*enable functional WDT clock */
- writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
deleted file mode 100644
index 1eed7b1..0000000
--- a/arch/arm/include/asm/arch-pantheon/config.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PANTHEON_CONFIG_H
-#define _PANTHEON_CONFIG_H
-
-#include <asm/arch/pantheon.h>
-
-/* default Dcache Line length for pantheon */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
-#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
-#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
-#define MV_MFPR_BASE PANTHEON_MFPR_BASE
-#define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE
-#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
- represents UART Unit Enable */
-/*
- * I2C definition
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MV 1
-#define CONFIG_MV_I2C_REG 0xd4011000
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 0
-#define CONFIG_SYS_I2C_SLAVE 0xfe
-#endif
-
-/*
- * MMC definition
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT 1
-#define CONFIG_MMC 1
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_SDHCI 1
-#define CONFIG_MMC_SDHCI_IO_ACCESSORS 1
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
-#define CONFIG_MMC_SDMA 1
-#define CONFIG_MV_SDHCI 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-#define CONFIG_SYS_MMC_NUM 2
-#define CONFIG_SYS_MMC_BASE {0xD4280000, 0xd4281000}
-#endif
-
-#endif /* _PANTHEON_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h
deleted file mode 100644
index 3ccdf8a..0000000
--- a/arch/arm/include/asm/arch-pantheon/cpu.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PANTHEON_CPU_H
-#define _PANTHEON_CPU_H
-
-#include <asm/io.h>
-#include <asm/system.h>
-
-/*
- * Main Power Management (MPMU) Registers
- * Refer Register Datasheet 9.1
- */
-struct panthmpmu_registers {
- u8 pad0[0x0024];
- u32 ccgr; /*0x0024*/
- u8 pad1[0x0200 - 0x024 - 4];
- u32 wdtpcr; /*0x0200*/
- u8 pad2[0x1020 - 0x200 - 4];
- u32 aprr; /*0x1020*/
- u32 acgr; /*0x1024*/
-};
-
-/*
- * Application Power Management (APMU) Registers
- * Refer Register Datasheet 9.2
- */
-struct panthapmu_registers {
- u8 pad0[0x0054];
- u32 sd1; /*0x0054*/
- u8 pad1[0x00e0 - 0x054 - 4];
- u32 sd3; /*0x00e0*/
-};
-
-/*
- * APB Clock Reset/Control Registers
- * Refer Register Datasheet 6.14
- */
-struct panthapb_registers {
- u32 uart0; /*0x000*/
- u32 uart1; /*0x004*/
- u32 gpio; /*0x008*/
- u8 pad0[0x02c - 0x08 - 4];
- u32 twsi; /*0x02c*/
- u8 pad1[0x034 - 0x2c - 4];
- u32 timers; /*0x034*/
-};
-
-/*
- * CPU Interface Registers
- * Refer Register Datasheet 4.3
- */
-struct panthcpu_registers {
- u32 chip_id; /* Chip Id Reg */
- u32 pad;
- u32 cpu_conf; /* CPU Conf Reg */
- u32 pad1;
- u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
- u32 pad2;
- u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
- u32 mcb_conf; /* MCB Conf Reg */
- u32 sys_boot_ctl; /* Sytem Boot Control */
-};
-
-/*
- * Functions
- */
-u32 panth_sdram_base(int);
-u32 panth_sdram_size(int);
-int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
-
-#endif /* _PANTHEON_CPU_H */
diff --git a/arch/arm/include/asm/arch-pantheon/gpio.h b/arch/arm/include/asm/arch-pantheon/gpio.h
deleted file mode 100644
index e69de29..0000000
diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h
deleted file mode 100644
index 7909d53..0000000
--- a/arch/arm/include/asm/arch-pantheon/mfp.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Based on arch/arm/include/asm/arch-armada100/mfp.h
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PANTHEON_MFP_H
-#define __PANTHEON_MFP_H
-
-/*
- * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
- *
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-/* UART2 */
-#define MFP47_UART2_RXD (MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP48_UART2_TXD (MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP53_CI2C_SCL (MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* More macros can be defined here... */
-#define MFP_MMC1_DAT7 (MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT6 (MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT5 (MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT4 (MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT3 (MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT2 (MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT1 (MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT0 (MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CMD (MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CLK (MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CD (MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_WP (MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-
-#define MFP_PIN_MAX 117
-#endif
diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h
deleted file mode 100644
index c3a71bf..0000000
--- a/arch/arm/include/asm/arch-pantheon/pantheon.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PANTHEON_H
-#define _PANTHEON_H
-
-/* Common APB clock register bit definitions */
-#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
-#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
-#define APBC_RST (1<<2) /* Reset Generation */
-/* Functional Clock Selection Mask */
-#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
-
-/* Common APMU register bit definitions */
-#define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */
-#define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/
-#define APMU_PERI_RST (1<<1) /* Peripheral Reset */
-#define APMU_AXI_RST (1<<0) /* AXI Reset */
-
-/* Register Base Addresses */
-#define PANTHEON_DRAM_BASE 0xB0000000
-#define PANTHEON_TIMER_BASE 0xD4014000
-#define PANTHEON_WD_TIMER_BASE 0xD4080000
-#define PANTHEON_APBC_BASE 0xD4015000
-#define PANTHEON_UART1_BASE 0xD4017000
-#define PANTHEON_UART2_BASE 0xD4018000
-#define PANTHEON_GPIO_BASE 0xD4019000
-#define PANTHEON_MFPR_BASE 0xD401E000
-#define PANTHEON_MPMU_BASE 0xD4050000
-#define PANTHEON_APMU_BASE 0xD4282800
-#define PANTHEON_CPU_BASE 0xD4282C00
-
-#endif /* _PANTHEON_H */
diff --git a/board/Marvell/dkb/Kconfig b/board/Marvell/dkb/Kconfig
deleted file mode 100644
index f674894..0000000
--- a/board/Marvell/dkb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_DKB
-
-config SYS_BOARD
- default "dkb"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_SOC
- default "pantheon"
-
-config SYS_CONFIG_NAME
- default "dkb"
-
-endif
diff --git a/board/Marvell/dkb/MAINTAINERS b/board/Marvell/dkb/MAINTAINERS
deleted file mode 100644
index c272b7a..0000000
--- a/board/Marvell/dkb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DKB BOARD
-M: Lei Wen <leiwen@marvell.com>
-S: Maintained
-F: board/Marvell/dkb/
-F: include/configs/dkb.h
-F: configs/dkb_defconfig
diff --git a/board/Marvell/dkb/Makefile b/board/Marvell/dkb/Makefile
deleted file mode 100644
index 9d88579..0000000
--- a/board/Marvell/dkb/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2011
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Lei Wen <leiwen@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dkb.o
diff --git a/board/Marvell/dkb/dkb.c b/board/Marvell/dkb/dkb.c
deleted file mode 100644
index c0c3125..0000000
--- a/board/Marvell/dkb/dkb.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mvmfp.h>
-#include <i2c.h>
-#include <asm/arch/mfp.h>
-#include <asm/arch/cpu.h>
-#ifdef CONFIG_GENERIC_MMC
-#include <sdhci.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- u32 mfp_cfg[] = {
- /* Enable Console on UART2 */
- MFP47_UART2_RXD,
- MFP48_UART2_TXD,
-
- /* I2C */
- MFP53_CI2C_SCL,
- MFP54_CI2C_SDA,
-
- /* MMC1 */
- MFP_MMC1_DAT7,
- MFP_MMC1_DAT6,
- MFP_MMC1_DAT5,
- MFP_MMC1_DAT4,
- MFP_MMC1_DAT3,
- MFP_MMC1_DAT2,
- MFP_MMC1_DAT1,
- MFP_MMC1_DAT0,
- MFP_MMC1_CMD,
- MFP_MMC1_CLK,
- MFP_MMC1_CD,
- MFP_MMC1_WP,
-
- MFP_EOC /*End of configureation*/
- };
- /* configure MFP's */
- mfp_config(mfp_cfg);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* arch number of Board */
- gd->bd->bi_arch_number = MACH_TYPE_TTC_DKB;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = panth_sdram_base(0) + 0x100;
- return 0;
-}
-
-#ifdef CONFIG_GENERIC_MMC
-#define I2C_SLAVE_ADDR 0x34
-#define LDO13_REG 0x28
-#define LDO_V30 0x6
-#define LDO_VOLTAGE(x) ((x & 0x7) << 1)
-#define LDO_EN 0x1
-int board_mmc_init(bd_t *bd)
-{
- ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
- u8 i, data;
-
- /* set LDO 13 to 3.0v */
- data = LDO_VOLTAGE(LDO_V30) | LDO_EN;
- i2c_write(I2C_SLAVE_ADDR, LDO13_REG, 1, &data, 1);
-
- for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
- if (mv_sdh_init(mmc_base_address[i], 0, 0,
- SDHCI_QUIRK_32BIT_DMA_ADDR))
- return 1;
- }
-
- return 0;
-}
-#endif
diff --git a/configs/dkb_defconfig b/configs/dkb_defconfig
deleted file mode 100644
index 0be9578..0000000
--- a/configs/dkb_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_DKB=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 649d4d0..809556e 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>
devkit3250 arm arm926ejs - - Vladimir Zapolskiy <vz@mleia.com>
zmx25 arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
diff --git a/include/configs/dkb.h b/include/configs/dkb.h
deleted file mode 100644
index 7ffbb14..0000000
--- a/include/configs/dkb.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_DKB_H
-#define __CONFIG_DKB_H
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-TTC DKB"
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
-#define CONFIG_PANTHEON 1 /* SOC Family Name */
-#define CONFIG_MACH_TTC_DKB 1 /* Machine type */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
-#define CONFIG_NR_DRAM_BANKS_MAX 2
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MMC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-#undef CONFIG_ARCH_MISC_INIT
-
-/*
- * Environment variables configurations
- */
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
-#define CONFIG_ENV_SIZE 0x20000 /* 64k */
-
-#endif /* __CONFIG_DKB_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 07/11] ARM: remove cm4008 and cm41xx board support
2015-02-10 4:44 [U-Boot] [PATCH 0/11] ARM: remove non-generic boards Masahiro Yamada
` (5 preceding siblings ...)
2015-02-10 4:44 ` [U-Boot] [PATCH 06/11] ARM: remove dkb " Masahiro Yamada
@ 2015-02-10 4:44 ` Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 08/11] ARM: remove a320evb " Masahiro Yamada
` (3 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 4:44 UTC (permalink / raw)
To: u-boot
These are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Greg Ungerer <greg.ungerer@opengear.com>
---
arch/arm/Kconfig | 10 -
arch/arm/cpu/arm920t/Makefile | 1 -
arch/arm/cpu/arm920t/ks8695/Makefile | 9 -
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 189 -------------
arch/arm/cpu/arm920t/ks8695/timer.c | 77 ------
arch/arm/include/asm/arch-ks8695/platform.h | 294 ---------------------
board/cm4008/Kconfig | 12 -
board/cm4008/MAINTAINERS | 6 -
board/cm4008/Makefile | 8 -
board/cm4008/cm4008.c | 88 -------
board/cm4008/config.mk | 1 -
board/cm4008/flash.c | 395 ----------------------------
board/cm41xx/Kconfig | 12 -
board/cm41xx/MAINTAINERS | 6 -
board/cm41xx/Makefile | 8 -
board/cm41xx/cm41xx.c | 88 -------
board/cm41xx/config.mk | 1 -
board/cm41xx/flash.c | 395 ----------------------------
configs/cm4008_defconfig | 2 -
configs/cm41xx_defconfig | 2 -
doc/README.scrapyard | 2 +
drivers/net/Makefile | 1 -
drivers/net/ks8695eth.c | 229 ----------------
drivers/serial/Makefile | 1 -
drivers/serial/serial.c | 2 -
drivers/serial/serial_ks8695.c | 121 ---------
include/configs/cm4008.h | 104 --------
include/configs/cm41xx.h | 104 --------
include/netdev.h | 1 -
include/serial.h | 1 -
30 files changed, 2 insertions(+), 2168 deletions(-)
delete mode 100644 arch/arm/cpu/arm920t/ks8695/Makefile
delete mode 100644 arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
delete mode 100644 arch/arm/cpu/arm920t/ks8695/timer.c
delete mode 100644 arch/arm/include/asm/arch-ks8695/platform.h
delete mode 100644 board/cm4008/Kconfig
delete mode 100644 board/cm4008/MAINTAINERS
delete mode 100644 board/cm4008/Makefile
delete mode 100644 board/cm4008/cm4008.c
delete mode 100644 board/cm4008/config.mk
delete mode 100644 board/cm4008/flash.c
delete mode 100644 board/cm41xx/Kconfig
delete mode 100644 board/cm41xx/MAINTAINERS
delete mode 100644 board/cm41xx/Makefile
delete mode 100644 board/cm41xx/cm41xx.c
delete mode 100644 board/cm41xx/config.mk
delete mode 100644 board/cm41xx/flash.c
delete mode 100644 configs/cm4008_defconfig
delete mode 100644 configs/cm41xx_defconfig
delete mode 100644 drivers/net/ks8695eth.c
delete mode 100644 drivers/serial/serial_ks8695.c
delete mode 100644 include/configs/cm4008.h
delete mode 100644 include/configs/cm41xx.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 74dd164..d6bb5c3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -97,14 +97,6 @@ config TARGET_SCB9328
bool "Support scb9328"
select CPU_ARM920T
-config TARGET_CM4008
- bool "Support cm4008"
- select CPU_ARM920T
-
-config TARGET_CM41XX
- bool "Support cm41xx"
- select CPU_ARM920T
-
config TARGET_VCMA9
bool "Support VCMA9"
select CPU_ARM920T
@@ -871,8 +863,6 @@ source "board/calao/sbc35_a9g20/Kconfig"
source "board/calao/tny_a9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
-source "board/cm4008/Kconfig"
-source "board/cm41xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
index a72e5de..a30a572 100644
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -14,5 +14,4 @@ obj-$(if $(filter a320,$(SOC)),y) += a320/
obj-$(CONFIG_AT91FAMILY) += at91/
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
-obj-$(CONFIG_KS8695) += ks8695/
obj-$(CONFIG_S3C24X0) += s3c24x0/
diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile
deleted file mode 100644
index 400aa89..0000000
--- a/arch/arm/cpu/arm920t/ks8695/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = lowlevel_init.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
deleted file mode 100644
index a2a07f2..0000000
--- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * lowlevel_init.S - basic hardware initialization for the KS8695 CPU
- *
- * Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/platform.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-/*
- *************************************************************************
- *
- * Handy dandy macros
- *
- *************************************************************************
- */
-
-/* Delay a bit */
-.macro DELAY_FOR cycles, reg0
- ldr \reg0, =\cycles
- subs \reg0, \reg0, #1
- subne pc, pc, #0xc
-.endm
-
-/*
- *************************************************************************
- *
- * Some local storage.
- *
- *************************************************************************
- */
-
-/* Should we boot with an interactive console or not */
-.globl serial_console
-
-/*
- *************************************************************************
- *
- * Raw hardware initialization code. The important thing is to get
- * SDRAM setup and running. We do some other basic things here too,
- * like getting the PLL set for high speed, and init the LEDs.
- *
- *************************************************************************
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-#if DEBUG
- /*
- * enable UART for early debug trace
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
- mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
- str r2, [r1]
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
- mov r2, #KS8695_UART_LINEC_WLEN8
- str r2, [r1] /* 8 data bits, no parity, 1 stop */
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
- mov r2, #0x41
- str r2, [r1] /* write 'A' */
-#endif
-#if DEBUG
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
- mov r2, #0x42
- str r2, [r1]
-#endif
-
- /*
- * remap the memory and flash regions. we want to end up with
- * ram from address 0, and flash at 32MB.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
- ldr r2, =0xbfc00040
- str r2, [r1] /* large flash map */
- ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
-highflash:
- ldr r2, =0x8fe00040
- str r2, [r1] /* remap flash range */
-
- /*
- * remap the second select region to the 4MB immediately after
- * the first region. This way if you have a larger flash (say 8Mb)
- * then you can have it all mapped nicely. Has no effect if you
- * only have a 4Mb or smaller flash.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
- ldr r2, =0x9fe40040
- str r2, [r1] /* remap flash2 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
- ldr r2, =0x30000005
- str r2, [r1] /* enable both flash selects */
-
-#ifdef CONFIG_CM41xx
- /*
- * map the second flash chip, using the external IO lines.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
- ldr r2, =0xafe80b6d
- str r2, [r1] /* remap io0 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
- ldr r2, =0xbfec0b6d
- str r2, [r1] /* remap io1 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
- ldr r2, =0x30050005
- str r2, [r1] /* enable second flash */
-#endif
-
- /*
- * before relocating, we have to setup RAM timing
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
-#if (PHYS_SDRAM_1_SIZE == 0x02000000)
- ldr r2, =0x7fc0000e /* 32MB */
-#else
- ldr r2, =0x3fc0000e /* 16MB */
-#endif
- str r2, [r1] /* configure sdram bank0 setup */
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
- mov r2, #0
- str r2, [r1] /* configure sdram bank1 setup */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
- ldr r2, =0x0000000a
- str r2, [r1] /* set RAS/CAS timing */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
- ldr r2, =0x00030000
- str r2, [r1] /* send NOP command */
- DELAY_FOR 0x100, r0
- ldr r2, =0x00010000
- str r2, [r1] /* send PRECHARGE-ALL */
- DELAY_FOR 0x100, r0
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
- ldr r2, =0x00000020
- str r2, [r1] /* set for fast refresh */
- DELAY_FOR 0x100, r0
- ldr r2, =0x00000190
- str r2, [r1] /* set normal refresh timing */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
- ldr r2, =0x00020033
- str r2, [r1] /* send mode command */
- DELAY_FOR 0x100, r0
- ldr r2, =0x01f00000
- str r2, [r1] /* enable sdram fifos */
-
- /*
- * set pll to top speed
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
- mov r2, #0
- str r2, [r1] /* set pll clock to 166MHz */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
- ldr r2, [r1] /* Get switch ctrl0 register */
- and r2, r2, #0x0fc00000 /* Mask out LED control bits */
- orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
- str r2, [r1]
-
-#ifdef CONFIG_CM4008
- ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
- ldr r2, =0x0000fe30
- str r2, [r1] /* enable LED's as outputs */
- ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
- ldr r2, =0x0000fe20
- str r2, [r1] /* turn on power LED */
-#endif
-#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
- ldr r2, [r1] /* get current GPIO input data */
- tst r2, #0x8 /* check if "erase" depressed */
- beq nobutton
- mov r2, #0 /* be quiet on boot, no console */
- ldr r1, =serial_console
- str r2, [r1]
-nobutton:
-#endif
-
- add lr, lr, #0x02000000 /* flash is now mapped high */
- add ip, ip, #0x02000000 /* this is a hack */
- mov pc, lr /* all done, return */
-
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/ks8695/timer.c b/arch/arm/cpu/arm920t/ks8695/timer.c
deleted file mode 100644
index 23db557..0000000
--- a/arch/arm/cpu/arm920t/ks8695/timer.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-
-/*
- * Initial timer set constants. Nothing complicated, just set for a 1ms
- * tick.
- */
-#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1)
-#define TIMER_COUNT (TIMER_INTERVAL / 2)
-#define TIMER_PULSE TIMER_COUNT
-
-/*
- * Handy KS8695 register access functions.
- */
-#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a)))
-#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
-
-ulong timer_ticks;
-
-int timer_init (void)
-{
- /* Set the hadware timer for 1ms */
- ks8695_write(KS8695_TIMER1, TIMER_COUNT);
- ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
- ks8695_write(KS8695_TIMER_CTRL, 0x2);
- timer_ticks = 0;
-
- return 0;
-}
-
-ulong get_timer_masked(void)
-{
- /* Check for timer wrap */
- if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
- /* Clear interrupt condition */
- ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
- timer_ticks++;
- }
- return timer_ticks;
-}
-
-ulong get_timer(ulong base)
-{
- return (get_timer_masked() - base);
-}
-
-void __udelay(ulong usec)
-{
- ulong start = get_timer_masked();
- ulong end;
-
- /* Only 1ms resolution :-( */
- end = usec / 1000;
- while (get_timer(start) < end)
- ;
-}
-
-void reset_cpu (ulong ignored)
-{
- ulong tc;
-
- /* Set timer0 to watchdog, and let it timeout */
- tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
- ks8695_write(KS8695_TIMER_CTRL, tc);
- ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
- ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
-
- /* Should only wait here till watchdog resets */
- for (;;)
- ;
-}
diff --git a/arch/arm/include/asm/arch-ks8695/platform.h b/arch/arm/include/asm/arch-ks8695/platform.h
deleted file mode 100644
index 02f6049..0000000
--- a/arch/arm/include/asm/arch-ks8695/platform.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __address_h
-#define __address_h 1
-
-#define KS8695_SDRAM_START 0x00000000
-#define KS8695_SDRAM_SIZE 0x01000000
-#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE
-#define KS8695_MEM_START KS8695_SDRAM_START
-
-#define KS8695_PCMCIA_IO_BASE 0x03800000
-#define KS8695_PCMCIA_IO_SIZE 0x00040000
-
-#define KS8695_IO_BASE 0x03FF0000
-#define KS8695_IO_SIZE 0x00010000
-
-#define KS8695_SYSTEN_CONFIG 0x00
-#define KS8695_SYSTEN_BUS_CLOCK 0x04
-
-#define KS8695_FLASH_START 0x02800000
-#define KS8695_FLASH_SIZE 0x00400000
-
-/*i/o control registers offset difinitions*/
-#define KS8695_IO_CTRL0 0x4000
-#define KS8695_IO_CTRL1 0x4004
-#define KS8695_IO_CTRL2 0x4008
-#define KS8695_IO_CTRL3 0x400C
-
-/*memory control registers offset difinitions*/
-#define KS8695_MEM_CTRL0 0x4010
-#define KS8695_MEM_CTRL1 0x4014
-#define KS8695_MEM_CTRL2 0x4018
-#define KS8695_MEM_CTRL3 0x401C
-#define KS8695_MEM_GENERAL 0x4020
-#define KS8695_SDRAM_CTRL0 0x4030
-#define KS8695_SDRAM_CTRL1 0x4034
-#define KS8695_SDRAM_GENERAL 0x4038
-#define KS8695_SDRAM_BUFFER 0x403C
-#define KS8695_SDRAM_REFRESH 0x4040
-
-/*WAN control registers offset difinitions*/
-#define KS8695_WAN_DMA_TX 0x6000
-#define KS8695_WAN_DMA_RX 0x6004
-#define KS8695_WAN_DMA_TX_START 0x6008
-#define KS8695_WAN_DMA_RX_START 0x600C
-#define KS8695_WAN_TX_LIST 0x6010
-#define KS8695_WAN_RX_LIST 0x6014
-#define KS8695_WAN_MAC_LOW 0x6018
-#define KS8695_WAN_MAC_HIGH 0x601C
-#define KS8695_WAN_MAC_ELOW 0x6080
-#define KS8695_WAN_MAC_EHIGH 0x6084
-
-/*LAN control registers offset difinitions*/
-#define KS8695_LAN_DMA_TX 0x8000
-#define KS8695_LAN_DMA_RX 0x8004
-#define KS8695_LAN_DMA_TX_START 0x8008
-#define KS8695_LAN_DMA_RX_START 0x800C
-#define KS8695_LAN_TX_LIST 0x8010
-#define KS8695_LAN_RX_LIST 0x8014
-#define KS8695_LAN_MAC_LOW 0x8018
-#define KS8695_LAN_MAC_HIGH 0x801C
-#define KS8695_LAN_MAC_ELOW 0X8080
-#define KS8695_LAN_MAC_EHIGH 0X8084
-
-/*HPNA control registers offset difinitions*/
-#define KS8695_HPNA_DMA_TX 0xA000
-#define KS8695_HPNA_DMA_RX 0xA004
-#define KS8695_HPNA_DMA_TX_START 0xA008
-#define KS8695_HPNA_DMA_RX_START 0xA00C
-#define KS8695_HPNA_TX_LIST 0xA010
-#define KS8695_HPNA_RX_LIST 0xA014
-#define KS8695_HPNA_MAC_LOW 0xA018
-#define KS8695_HPNA_MAC_HIGH 0xA01C
-#define KS8695_HPNA_MAC_ELOW 0xA080
-#define KS8695_HPNA_MAC_EHIGH 0xA084
-
-/*UART control registers offset difinitions*/
-#define KS8695_UART_RX_BUFFER 0xE000
-#define KS8695_UART_TX_HOLDING 0xE004
-
-#define KS8695_UART_FIFO_CTRL 0xE008
-#define KS8695_UART_FIFO_TRIG01 0x00
-#define KS8695_UART_FIFO_TRIG04 0x80
-#define KS8695_UART_FIFO_TXRST 0x03
-#define KS8695_UART_FIFO_RXRST 0x02
-#define KS8695_UART_FIFO_FEN 0x01
-
-#define KS8695_UART_LINE_CTRL 0xE00C
-#define KS8695_UART_LINEC_BRK 0x40
-#define KS8695_UART_LINEC_EPS 0x10
-#define KS8695_UART_LINEC_PEN 0x08
-#define KS8695_UART_LINEC_STP2 0x04
-#define KS8695_UART_LINEC_WLEN8 0x03
-#define KS8695_UART_LINEC_WLEN7 0x02
-#define KS8695_UART_LINEC_WLEN6 0x01
-#define KS8695_UART_LINEC_WLEN5 0x00
-
-#define KS8695_UART_MODEM_CTRL 0xE010
-#define KS8695_UART_MODEMC_RTS 0x02
-#define KS8695_UART_MODEMC_DTR 0x01
-
-#define KS8695_UART_LINE_STATUS 0xE014
-#define KS8695_UART_LINES_TXFE 0x20
-#define KS8695_UART_LINES_BE 0x10
-#define KS8695_UART_LINES_FE 0x08
-#define KS8695_UART_LINES_PE 0x04
-#define KS8695_UART_LINES_OE 0x02
-#define KS8695_UART_LINES_RXFE 0x01
-#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
-
-#define KS8695_UART_MODEM_STATUS 0xE018
-#define KS8695_UART_MODEM_DCD 0x80
-#define KS8695_UART_MODEM_DSR 0x20
-#define KS8695_UART_MODEM_CTS 0x10
-#define KS8695_UART_MODEM_DDCD 0x08
-#define KS8695_UART_MODEM_DDSR 0x02
-#define KS8695_UART_MODEM_DCTS 0x01
-#define UART8695_MODEM_ANY 0xFF
-
-#define KS8695_UART_DIVISOR 0xE01C
-#define KS8695_UART_STATUS 0xE020
-
-/*Interrupt controlller registers offset difinitions*/
-#define KS8695_INT_CONTL 0xE200
-#define KS8695_INT_ENABLE 0xE204
-#define KS8695_INT_ENABLE_MODEM 0x0800
-#define KS8695_INT_ENABLE_ERR 0x0400
-#define KS8695_INT_ENABLE_RX 0x0200
-#define KS8695_INT_ENABLE_TX 0x0100
-
-#define KS8695_INT_STATUS 0xE208
-#define KS8695_INT_WAN_PRIORITY 0xE20C
-#define KS8695_INT_HPNA_PRIORITY 0xE210
-#define KS8695_INT_LAN_PRIORITY 0xE214
-#define KS8695_INT_TIMER_PRIORITY 0xE218
-#define KS8695_INT_UART_PRIORITY 0xE21C
-#define KS8695_INT_EXT_PRIORITY 0xE220
-#define KS8695_INT_CHAN_PRIORITY 0xE224
-#define KS8695_INT_BUSERROR_PRO 0xE228
-#define KS8695_INT_MASK_STATUS 0xE22C
-#define KS8695_FIQ_PEND_PRIORITY 0xE230
-#define KS8695_IRQ_PEND_PRIORITY 0xE234
-
-/*timer registers offset difinitions*/
-#define KS8695_TIMER_CTRL 0xE400
-#define KS8695_TIMER1 0xE404
-#define KS8695_TIMER0 0xE408
-#define KS8695_TIMER1_PCOUNT 0xE40C
-#define KS8695_TIMER0_PCOUNT 0xE410
-
-/*GPIO registers offset difinitions*/
-#define KS8695_GPIO_MODE 0xE600
-#define KS8695_GPIO_CTRL 0xE604
-#define KS8695_GPIO_DATA 0xE608
-
-/*SWITCH registers offset difinitions*/
-#define KS8695_SWITCH_CTRL0 0xE800
-#define KS8695_SWITCH_CTRL1 0xE804
-#define KS8695_SWITCH_PORT1 0xE808
-#define KS8695_SWITCH_PORT2 0xE80C
-#define KS8695_SWITCH_PORT3 0xE810
-#define KS8695_SWITCH_PORT4 0xE814
-#define KS8695_SWITCH_PORT5 0xE818
-#define KS8695_SWITCH_AUTO0 0xE81C
-#define KS8695_SWITCH_AUTO1 0xE820
-#define KS8695_SWITCH_LUE_CTRL 0xE824
-#define KS8695_SWITCH_LUE_HIGH 0xE828
-#define KS8695_SWITCH_LUE_LOW 0xE82C
-#define KS8695_SWITCH_ADVANCED 0xE830
-
-#define KS8695_SWITCH_LPPM12 0xE874
-#define KS8695_SWITCH_LPPM34 0xE878
-
-/*host communication registers difinitions*/
-#define KS8695_DSCP_HIGH 0xE834
-#define KS8695_DSCP_LOW 0xE838
-#define KS8695_SWITCH_MAC_HIGH 0xE83C
-#define KS8695_SWITCH_MAC_LOW 0xE840
-
-/*miscellaneours registers difinitions*/
-#define KS8695_MANAGE_COUNTER 0xE844
-#define KS8695_MANAGE_DATA 0xE848
-#define KS8695_LAN12_POWERMAGR 0xE84C
-#define KS8695_LAN34_POWERMAGR 0xE850
-
-#define KS8695_DEVICE_ID 0xEA00
-#define KS8695_REVISION_ID 0xEA04
-
-#define KS8695_MISC_CONTROL 0xEA08
-#define KS8695_WAN_CONTROL 0xEA0C
-#define KS8695_WAN_POWERMAGR 0xEA10
-#define KS8695_WAN_PHY_CONTROL 0xEA14
-#define KS8695_WAN_PHY_STATUS 0xEA18
-
-/* bus clock definitions*/
-#define KS8695_BUS_CLOCK_125MHZ 0x0
-#define KS8695_BUS_CLOCK_100MHZ 0x1
-#define KS8695_BUS_CLOCK_62MHZ 0x2
-#define KS8695_BUS_CLOCK_50MHZ 0x3
-#define KS8695_BUS_CLOCK_41MHZ 0x4
-#define KS8695_BUS_CLOCK_33MHZ 0x5
-#define KS8695_BUS_CLOCK_31MHZ 0x6
-#define KS8695_BUS_CLOCK_25MHZ 0x7
-
-/* -------------------------------------------------------------------------------
- * definations for IRQ
- * -------------------------------------------------------------------------------*/
-
-#define KS8695_INT_EXT_INT0 2
-#define KS8695_INT_EXT_INT1 3
-#define KS8695_INT_EXT_INT2 4
-#define KS8695_INT_EXT_INT3 5
-#define KS8695_INT_TIMERINT0 6
-#define KS8695_INT_TIMERINT1 7
-#define KS8695_INT_UART_TX 8
-#define KS8695_INT_UART_RX 9
-#define KS8695_INT_UART_LINE_ERR 10
-#define KS8695_INT_UART_MODEMS 11
-#define KS8695_INT_LAN_STOP_RX 12
-#define KS8695_INT_LAN_STOP_TX 13
-#define KS8695_INT_LAN_BUF_RX_STATUS 14
-#define KS8695_INT_LAN_BUF_TX_STATUS 15
-#define KS8695_INT_LAN_RX_STATUS 16
-#define KS8695_INT_LAN_TX_STATUS 17
-#define KS8695_INT_HPAN_STOP_RX 18
-#define KS8695_INT_HPNA_STOP_TX 19
-#define KS8695_INT_HPNA_BUF_RX_STATUS 20
-#define KS8695_INT_HPNA_BUF_TX_STATUS 21
-#define KS8695_INT_HPNA_RX_STATUS 22
-#define KS8695_INT_HPNA_TX_STATUS 23
-#define KS8695_INT_BUS_ERROR 24
-#define KS8695_INT_WAN_STOP_RX 25
-#define KS8695_INT_WAN_STOP_TX 26
-#define KS8695_INT_WAN_BUF_RX_STATUS 27
-#define KS8695_INT_WAN_BUF_TX_STATUS 28
-#define KS8695_INT_WAN_RX_STATUS 29
-#define KS8695_INT_WAN_TX_STATUS 30
-
-#define KS8695_INT_UART KS8695_INT_UART_TX
-
-/* -------------------------------------------------------------------------------
- * Interrupt bit positions
- *
- * -------------------------------------------------------------------------------
- */
-
-#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 )
-#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 )
-#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 )
-#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 )
-#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 )
-#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 )
-#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX )
-#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX )
-#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR )
-#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS )
-#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX )
-#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX )
-#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
-#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
-#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
-#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
-#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX )
-#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX )
-#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
-#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
-#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS )
-#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS )
-#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR )
-#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX )
-#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX )
-#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
-#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
-#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS )
-#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS )
-
-#define KS8695_SC_VALID_INT 0xFFFFFFFF
-#define MAXIRQNUM 31
-
-/*
- * Timer definitions
- *
- * Use timer 1 & 2
- * (both run at 25MHz).
- *
- */
-#define TICKS_PER_uSEC 25
-#define mSEC_1 1000
-#define mSEC_10 (mSEC_1 * 10)
-
-#endif
-
-/* END */
diff --git a/board/cm4008/Kconfig b/board/cm4008/Kconfig
deleted file mode 100644
index de87d5b..0000000
--- a/board/cm4008/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CM4008
-
-config SYS_BOARD
- default "cm4008"
-
-config SYS_SOC
- default "ks8695"
-
-config SYS_CONFIG_NAME
- default "cm4008"
-
-endif
diff --git a/board/cm4008/MAINTAINERS b/board/cm4008/MAINTAINERS
deleted file mode 100644
index 5f08bc3..0000000
--- a/board/cm4008/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM4008 BOARD
-M: Greg Ungerer <greg.ungerer@opengear.com>
-S: Maintained
-F: board/cm4008/
-F: include/configs/cm4008.h
-F: configs/cm4008_defconfig
diff --git a/board/cm4008/Makefile b/board/cm4008/Makefile
deleted file mode 100644
index 04b1529..0000000
--- a/board/cm4008/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cm4008.o flash.o
diff --git a/board/cm4008/cm4008.c b/board/cm4008/cm4008.c
deleted file mode 100644
index 740e164..0000000
--- a/board/cm4008/cm4008.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * (C) Copyright 2005
- * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
-#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-int env_flash_cmdline (void)
-{
- char *sp = (char *) 0x0201c020;
- char *ep;
- int len;
-
- /* Check if "erase" push button is depressed */
- if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
- printf("### Entering network recovery mode...\n");
- setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0");
- setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
- setenv("bootdelay", "2");
- return 0;
- }
-
- /* Check for flash based kernel boot args to use as default */
- for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
- ;
-
- if ((len > 0) && (len <1024))
- setenv("bootargs", sp);
-
- return 0;
-}
-
-int board_late_init (void)
-{
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return ks8695_eth_initialize();
-}
-
-int board_init (void)
-{
- /* arch number of CM4008 */
- gd->bd->bi_arch_number = 624;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- /* power down all but port 0 on the switch */
- ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
- ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
-
- return 0;
-}
-
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return (0);
-}
diff --git a/board/cm4008/config.mk b/board/cm4008/config.mk
deleted file mode 100644
index 0d5923b..0000000
--- a/board/cm4008/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00f00000
diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c
deleted file mode 100644
index 8315a57..0000000
--- a/board/cm4008/flash.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * (C) Copyright 2005
- * Greg Ungerer, OpenGear Inc, greg.ungerer at opengear.com
- *
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-#include <asm/sections.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, unsigned char data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
- break;
- case 1:
- /* ignore for now */
- flash_info[i].flash_id = FLASH_UNKNOWN;
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
- &flash_info[0]);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return;
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
-{
- volatile unsigned char value;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = 0xAA;
- addr[0x2AAA] = 0x55;
- addr[0x5555] = 0x90;
-
- mb ();
- value = addr[0];
-
- switch (value) {
-
- case (unsigned char)INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = 0xFF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[2]; /* device ID */
-
- switch (value) {
-
- case (unsigned char)INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (unsigned char)INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = 0xFF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int prot, sect;
- ulong type;
- int rcode = 0;
- ulong start;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot)
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- else
- printf ("\n");
-
- /* Disable interrupts which might cause a timeout here */
- disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- volatile unsigned char *addr;
- unsigned char status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- addr = (volatile unsigned char *) (info->start[sect]);
- *addr = 0x50; /* clear status register */
- *addr = 0x20; /* erase setup */
- *addr = 0xD0; /* erase confirm */
-
- while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer(start) >
- CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0xB0; /* suspend erase */
- *addr = 0xFF; /* reset to read mode */
- rcode = 1;
- break;
- }
- }
-
- *addr = 0x50; /* clear status register cmd */
- *addr = 0xFF; /* resest to read mode */
-
- printf (" done\n");
- }
- }
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- unsigned char data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return 4;
-
- wp = addr;
- port_width = 1;
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, unsigned char data)
-{
- volatile unsigned char *addr = (volatile unsigned char *) dest;
- ulong status;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased@%08lx (%lx)\n", (ulong) addr,
- (ulong) * addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- disable_interrupts();
-
- *addr = 0x40; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait while polling the status register */
- while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = 0xFF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = 0xFF; /* restore read mode */
-
- return (0);
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
diff --git a/board/cm41xx/Kconfig b/board/cm41xx/Kconfig
deleted file mode 100644
index 99e675b..0000000
--- a/board/cm41xx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CM41XX
-
-config SYS_BOARD
- default "cm41xx"
-
-config SYS_SOC
- default "ks8695"
-
-config SYS_CONFIG_NAME
- default "cm41xx"
-
-endif
diff --git a/board/cm41xx/MAINTAINERS b/board/cm41xx/MAINTAINERS
deleted file mode 100644
index f10eeb5..0000000
--- a/board/cm41xx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM41XX BOARD
-#M: -
-S: Maintained
-F: board/cm41xx/
-F: include/configs/cm41xx.h
-F: configs/cm41xx_defconfig
diff --git a/board/cm41xx/Makefile b/board/cm41xx/Makefile
deleted file mode 100644
index b71ea05..0000000
--- a/board/cm41xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cm41xx.o flash.o
diff --git a/board/cm41xx/cm41xx.c b/board/cm41xx/cm41xx.c
deleted file mode 100644
index eabad48..0000000
--- a/board/cm41xx/cm41xx.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * (C) Copyright 2005
- * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
-#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-int env_flash_cmdline (void)
-{
- char *sp = (char *) 0x0201c020;
- char *ep;
- int len;
-
- /* Check if "erase" push button is depressed */
- if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
- printf("### Entering network recovery mode...\n");
- setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0");
- setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
- setenv("bootdelay", "2");
- return 0;
- }
-
- /* Check for flash based kernel boot args to use as default */
- for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
- ;
-
- if ((len > 0) && (len <1024))
- setenv("bootargs", sp);
-
- return 0;
-}
-
-int board_late_init (void)
-{
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return ks8695_eth_initialize();
-}
-
-int board_init (void)
-{
- /* arch number of CM41xx */
- gd->bd->bi_arch_number = 672;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- /* power down all but port 0 on the switch */
- ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
- ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
-
- return 0;
-}
-
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return (0);
-}
diff --git a/board/cm41xx/config.mk b/board/cm41xx/config.mk
deleted file mode 100644
index 0d5923b..0000000
--- a/board/cm41xx/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00f00000
diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c
deleted file mode 100644
index 8315a57..0000000
--- a/board/cm41xx/flash.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * (C) Copyright 2005
- * Greg Ungerer, OpenGear Inc, greg.ungerer at opengear.com
- *
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-#include <asm/sections.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, unsigned char data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
- break;
- case 1:
- /* ignore for now */
- flash_info[i].flash_id = FLASH_UNKNOWN;
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
- &flash_info[0]);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return;
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
-{
- volatile unsigned char value;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = 0xAA;
- addr[0x2AAA] = 0x55;
- addr[0x5555] = 0x90;
-
- mb ();
- value = addr[0];
-
- switch (value) {
-
- case (unsigned char)INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = 0xFF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[2]; /* device ID */
-
- switch (value) {
-
- case (unsigned char)INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (unsigned char)INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = 0xFF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int prot, sect;
- ulong type;
- int rcode = 0;
- ulong start;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot)
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- else
- printf ("\n");
-
- /* Disable interrupts which might cause a timeout here */
- disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- volatile unsigned char *addr;
- unsigned char status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- addr = (volatile unsigned char *) (info->start[sect]);
- *addr = 0x50; /* clear status register */
- *addr = 0x20; /* erase setup */
- *addr = 0xD0; /* erase confirm */
-
- while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer(start) >
- CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0xB0; /* suspend erase */
- *addr = 0xFF; /* reset to read mode */
- rcode = 1;
- break;
- }
- }
-
- *addr = 0x50; /* clear status register cmd */
- *addr = 0xFF; /* resest to read mode */
-
- printf (" done\n");
- }
- }
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- unsigned char data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return 4;
-
- wp = addr;
- port_width = 1;
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, unsigned char data)
-{
- volatile unsigned char *addr = (volatile unsigned char *) dest;
- ulong status;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased@%08lx (%lx)\n", (ulong) addr,
- (ulong) * addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- disable_interrupts();
-
- *addr = 0x40; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait while polling the status register */
- while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = 0xFF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = 0xFF; /* restore read mode */
-
- return (0);
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
diff --git a/configs/cm4008_defconfig b/configs/cm4008_defconfig
deleted file mode 100644
index 487589d..0000000
--- a/configs/cm4008_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_CM4008=y
diff --git a/configs/cm41xx_defconfig b/configs/cm41xx_defconfig
deleted file mode 100644
index 15e9362..0000000
--- a/configs/cm41xx_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_CM41XX=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 809556e..a42b0e1 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
+cm41xx arm arm920t - -
dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>
devkit3250 arm arm926ejs - - Vladimir Zapolskiy <vz@mleia.com>
zmx25 arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 46c4ac6..da5e2bc 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -33,7 +33,6 @@ obj-$(CONFIG_FTMAC110) += ftmac110.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
obj-$(CONFIG_GRETH) += greth.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
-obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
obj-$(CONFIG_MACB) += macb.o
diff --git a/drivers/net/ks8695eth.c b/drivers/net/ks8695eth.c
deleted file mode 100644
index b4822e9..0000000
--- a/drivers/net/ks8695eth.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * ks8695eth.c -- KS8695 ethernet driver
- *
- * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/****************************************************************************/
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <asm/arch/platform.h>
-
-/****************************************************************************/
-
-/*
- * Hardware register access to the KS8695 LAN ethernet port
- * (well, it is the 4 port switch really).
- */
-#define ks8695_read(a) *((volatile unsigned long *) (KS8695_IO_BASE + (a)))
-#define ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v)
-
-/****************************************************************************/
-
-/*
- * Define the descriptor in-memory data structures.
- */
-struct ks8695_txdesc {
- uint32_t owner;
- uint32_t ctrl;
- uint32_t addr;
- uint32_t next;
-};
-
-struct ks8695_rxdesc {
- uint32_t status;
- uint32_t ctrl;
- uint32_t addr;
- uint32_t next;
-};
-
-/****************************************************************************/
-
-/*
- * Allocate local data structures to use for receiving and sending
- * packets. Just to keep it all nice and simple.
- */
-
-#define TXDESCS 4
-#define RXDESCS 4
-#define BUFSIZE 2048
-
-volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256)));
-volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256)));
-volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));;
-
-/****************************************************************************/
-
-/*
- * Ideally we want to use the MAC address stored in flash.
- * But we do some sanity checks in case they are not present
- * first.
- */
-unsigned char eth_mac[] = {
- 0x00, 0x13, 0xc6, 0x00, 0x00, 0x00
-};
-
-void ks8695_getmac(void)
-{
- unsigned char *fp;
- int i;
-
- /* Check if flash MAC is valid */
- fp = (unsigned char *) 0x0201c000;
- for (i = 0; (i < 6); i++) {
- if ((fp[i] != 0) && (fp[i] != 0xff))
- break;
- }
-
- /* If we found a valid looking MAC address then use it */
- if (i < 6)
- memcpy(ð_mac[0], fp, 6);
-}
-
-/****************************************************************************/
-
-static int ks8695_eth_init(struct eth_device *dev, bd_t *bd)
-{
- int i;
-
- debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__);
-
- /* Reset the ethernet engines first */
- ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
- ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
-
- ks8695_getmac();
-
- /* Set MAC address */
- ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) |
- (eth_mac[3] << 16) | (eth_mac[2] << 24)));
- ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8)));
-
- /* Turn the 4 port switch on */
- i = ks8695_read(KS8695_SWITCH_CTRL0);
- ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1));
- /* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */
-
- /* Initialize descriptor rings */
- for (i = 0; (i < TXDESCS); i++) {
- ks8695_tx[i].owner = 0;
- ks8695_tx[i].ctrl = 0;
- ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE];
- ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1];
- }
- ks8695_tx[TXDESCS-1].ctrl = 0x02000000;
- ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0];
-
- for (i = 0; (i < RXDESCS); i++) {
- ks8695_rx[i].status = 0x80000000;
- ks8695_rx[i].ctrl = BUFSIZE - 4;
- ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE];
- ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1];
- }
- ks8695_rx[RXDESCS-1].ctrl |= 0x00080000;
- ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0];
-
- /* The KS8695 is pretty slow reseting the ethernets... */
- udelay(2000000);
-
- /* Enable the ethernet engine */
- ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]);
- ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]);
- ks8695_write(KS8695_LAN_DMA_TX, 0x3);
- ks8695_write(KS8695_LAN_DMA_RX, 0x71);
- ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
-
- printf("KS8695 ETHERNET: %pM\n", eth_mac);
- return 0;
-}
-
-/****************************************************************************/
-
-static void ks8695_eth_halt(struct eth_device *dev)
-{
- debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__);
-
- /* Reset the ethernet engines */
- ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
- ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
-}
-
-/****************************************************************************/
-
-static int ks8695_eth_recv(struct eth_device *dev)
-{
- volatile struct ks8695_rxdesc *dp;
- int i, len = 0;
-
- debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__);
-
- for (i = 0; (i < RXDESCS); i++) {
- dp= &ks8695_rx[i];
- if ((dp->status & 0x80000000) == 0) {
- len = (dp->status & 0x7ff) - 4;
- NetReceive((void *) dp->addr, len);
- dp->status = 0x80000000;
- ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
- break;
- }
- }
-
- return len;
-}
-
-/****************************************************************************/
-
-static int ks8695_eth_send(struct eth_device *dev, void *packet, int len)
-{
- volatile struct ks8695_txdesc *dp;
- static int next = 0;
-
- debug ("%s(%d): eth_send(packet=%p,len=%d)\n", __FILE__, __LINE__,
- packet, len);
-
- dp = &ks8695_tx[next];
- memcpy((void *) dp->addr, (void *) packet, len);
-
- if (len < 64) {
- memset((void *) (dp->addr + len), 0, 64-len);
- len = 64;
- }
-
- dp->ctrl = len | 0xe0000000;
- dp->owner = 0x80000000;
-
- ks8695_write(KS8695_LAN_DMA_TX, 0x3);
- ks8695_write(KS8695_LAN_DMA_TX_START, 0x1);
-
- if (++next >= TXDESCS)
- next = 0;
-
- return 0;
-}
-
-/****************************************************************************/
-
-int ks8695_eth_initialize(void)
-{
- struct eth_device *dev;
-
- dev = malloc(sizeof(*dev));
- if (dev == NULL)
- return -1;
- memset(dev, 0, sizeof(*dev));
-
- dev->iobase = KS8695_IO_BASE + KS8695_LAN_DMA_TX;
- dev->init = ks8695_eth_init;
- dev->halt = ks8695_eth_halt;
- dev->send = ks8695_eth_send;
- dev->recv = ks8695_eth_recv;
- strcpy(dev->name, "ks8695eth");
-
- eth_register(dev);
- return 0;
-}
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index cedf246..78d4f51 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
obj-$(CONFIG_SYS_NS16550) += ns16550.o
obj-$(CONFIG_S5P) += serial_s5p.o
obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
-obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 3210a26..d2f34ad 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -127,7 +127,6 @@ serial_initfunc(evb64260_serial_initialize);
serial_initfunc(imx_serial_initialize);
serial_initfunc(iop480_serial_initialize);
serial_initfunc(jz_serial_initialize);
-serial_initfunc(ks8695_serial_initialize);
serial_initfunc(leon2_serial_initialize);
serial_initfunc(leon3_serial_initialize);
serial_initfunc(lh7a40x_serial_initialize);
@@ -219,7 +218,6 @@ void serial_initialize(void)
imx_serial_initialize();
iop480_serial_initialize();
jz_serial_initialize();
- ks8695_serial_initialize();
leon2_serial_initialize();
leon3_serial_initialize();
lh7a40x_serial_initialize();
diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c
deleted file mode 100644
index 13adabd..0000000
--- a/drivers/serial/serial_ks8695.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * serial.c -- KS8695 serial driver
- *
- * (C) Copyright 2004, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#ifndef CONFIG_SERIAL1
-#error "Bad: you didn't configure serial ..."
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Define the UART hardware register access structure.
- */
-struct ks8695uart {
- unsigned int RX; /* 0x00 - Receive data (r) */
- unsigned int TX; /* 0x04 - Transmit data (w) */
- unsigned int FCR; /* 0x08 - Fifo Control (r/w) */
- unsigned int LCR; /* 0x0c - Line Control (r/w) */
- unsigned int MCR; /* 0x10 - Modem Control (r/w) */
- unsigned int LSR; /* 0x14 - Line Status (r/w) */
- unsigned int MSR; /* 0x18 - Modem Status (r/w) */
- unsigned int BD; /* 0x1c - Baud Rate (r/w) */
- unsigned int SR; /* 0x20 - Status (r/w) */
-};
-
-#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER))
-#define KS8695_UART_CLK 25000000
-
-
-/*
- * Under some circumstances we want to be "quiet" and not issue any
- * serial output - though we want u-boot to otherwise work and behave
- * the same. By default be noisy.
- */
-int serial_console = 1;
-
-
-static void ks8695_serial_setbrg(void)
-{
- volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
-
- /* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/
- uartp->BD = KS8695_UART_CLK / gd->baudrate;
- uartp->LCR = KS8695_UART_LINEC_WLEN8;
-}
-
-static int ks8695_serial_init(void)
-{
- serial_console = 1;
- serial_setbrg();
- return 0;
-}
-
-static void ks8695_serial_raw_putc(const char c)
-{
- volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
- int i;
-
- for (i = 0; (i < 0x100000); i++) {
- if (uartp->LSR & KS8695_UART_LINES_TXFE)
- break;
- }
-
- uartp->TX = c;
-}
-
-static void ks8695_serial_putc(const char c)
-{
- if (serial_console) {
- ks8695_serial_raw_putc(c);
- if (c == '\n')
- ks8695_serial_raw_putc('\r');
- }
-}
-
-static int ks8695_serial_tstc(void)
-{
- volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
- if (serial_console)
- return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0);
- return 0;
-}
-
-static int ks8695_serial_getc(void)
-{
- volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
-
- while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0)
- ;
- return (uartp->RX);
-}
-
-static struct serial_device ks8695_serial_drv = {
- .name = "ks8695_serial",
- .start = ks8695_serial_init,
- .stop = NULL,
- .setbrg = ks8695_serial_setbrg,
- .putc = ks8695_serial_putc,
- .puts = default_serial_puts,
- .getc = ks8695_serial_getc,
- .tstc = ks8695_serial_tstc,
-};
-
-void ks8695_serial_initialize(void)
-{
- serial_register(&ks8695_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &ks8695_serial_drv;
-}
diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h
deleted file mode 100644
index 1cb54b3..0000000
--- a/include/configs/cm4008.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * (C) Copyright 2004
- * Greg Ungerer <greg.ungerer@opengear.com>.
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
-#define CONFIG_CM4008 1 /* it is an OpenGear CM4008 boad */
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_KS8695_SERIAL
-#define CONFIG_SERIAL1
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_SAVEENV
-
-
-#define CONFIG_BOOTDELAY 0
-#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200"
-#define CONFIG_BOOTCOMMAND "gofsk 0x02200000"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
-
-#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h
deleted file mode 100644
index adebd4b..0000000
--- a/include/configs/cm41xx.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * (C) Copyright 2005
- * Greg Ungerer <greg.ungerer@opengear.com>.
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
-#define CONFIG_CM41xx 1 /* it is an OpenGear CM41xx boad */
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_KS8695_SERIAL
-#define CONFIG_SERIAL1
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_SAVEENV
-
-
-#define CONFIG_BOOTDELAY 0
-#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200"
-#define CONFIG_BOOTCOMMAND "gofsk 0x02200000"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
-
-#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
-
-#endif /* __CONFIG_H */
diff --git a/include/netdev.h b/include/netdev.h
index daffc12..90140bd 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -55,7 +55,6 @@ int ftmac100_initialize(bd_t *bits);
int ftmac110_initialize(bd_t *bits);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
-int ks8695_eth_initialize(void);
int ks8851_mll_initialize(u8 dev_num, int base_addr);
int lan91c96_initialize(u8 dev_num, int base_addr);
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
diff --git a/include/serial.h b/include/serial.h
index 42e2cc1..cd48e6f 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -182,7 +182,6 @@ void evb64260_serial_initialize(void);
void imx_serial_initialize(void);
void iop480_serial_initialize(void);
void jz_serial_initialize(void);
-void ks8695_serial_initialize(void);
void leon2_serial_initialize(void);
void leon3_serial_initialize(void);
void lh7a40x_serial_initialize(void);
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 08/11] ARM: remove a320evb board support
2015-02-10 4:44 [U-Boot] [PATCH 0/11] ARM: remove non-generic boards Masahiro Yamada
` (6 preceding siblings ...)
2015-02-10 4:44 ` [U-Boot] [PATCH 07/11] ARM: remove cm4008 and cm41xx " Masahiro Yamada
@ 2015-02-10 4:44 ` Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 09/11] ARM: armada100: remove aspenite and gplugd " Masahiro Yamada
` (2 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 4:44 UTC (permalink / raw)
To: u-boot
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Po-Yu Chuang <ratbert@faraday-tech.com>
---
arch/arm/Kconfig | 5 -
arch/arm/cpu/arm920t/Makefile | 1 -
arch/arm/cpu/arm920t/a320/Makefile | 9 --
arch/arm/cpu/arm920t/a320/reset.S | 10 --
arch/arm/cpu/arm920t/a320/timer.c | 118 -------------------
arch/arm/include/asm/arch-a320/a320.h | 22 ----
board/faraday/a320evb/Kconfig | 15 ---
board/faraday/a320evb/MAINTAINERS | 6 -
board/faraday/a320evb/Makefile | 9 --
board/faraday/a320evb/a320evb.c | 59 ----------
board/faraday/a320evb/lowlevel_init.S | 106 -----------------
configs/a320evb_defconfig | 2 -
doc/README.scrapyard | 1 +
include/configs/a320evb.h | 211 ----------------------------------
14 files changed, 1 insertion(+), 573 deletions(-)
delete mode 100644 arch/arm/cpu/arm920t/a320/Makefile
delete mode 100644 arch/arm/cpu/arm920t/a320/reset.S
delete mode 100644 arch/arm/cpu/arm920t/a320/timer.c
delete mode 100644 arch/arm/include/asm/arch-a320/a320.h
delete mode 100644 board/faraday/a320evb/Kconfig
delete mode 100644 board/faraday/a320evb/MAINTAINERS
delete mode 100644 board/faraday/a320evb/Makefile
delete mode 100644 board/faraday/a320evb/a320evb.c
delete mode 100644 board/faraday/a320evb/lowlevel_init.S
delete mode 100644 configs/a320evb_defconfig
delete mode 100644 include/configs/a320evb.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d6bb5c3..3ec570b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -73,10 +73,6 @@ config TARGET_INTEGRATORCP_CM920T
bool "Support integratorcp_cm920t"
select CPU_ARM920T
-config TARGET_A320EVB
- bool "Support a320evb"
- select CPU_ARM920T
-
config TARGET_AT91RM9200EK
bool "Support at91rm9200ek"
select CPU_ARM920T
@@ -877,7 +873,6 @@ source "board/esd/otc570/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
source "board/eukrea/cpu9260/Kconfig"
source "board/eukrea/cpuat91/Kconfig"
-source "board/faraday/a320evb/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
index a30a572..b07e13a 100644
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -10,7 +10,6 @@ extra-y = start.o
obj-y += cpu.o
obj-$(CONFIG_USE_IRQ) += interrupts.o
-obj-$(if $(filter a320,$(SOC)),y) += a320/
obj-$(CONFIG_AT91FAMILY) += at91/
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile
deleted file mode 100644
index bbdab58..0000000
--- a/arch/arm/cpu/arm920t/a320/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += reset.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/arm920t/a320/reset.S b/arch/arm/cpu/arm920t/a320/reset.S
deleted file mode 100644
index 81f9dc9..0000000
--- a/arch/arm/cpu/arm920t/a320/reset.S
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.global reset_cpu
-reset_cpu:
- b reset_cpu
diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c
deleted file mode 100644
index 1ac5b60..0000000
--- a/arch/arm/cpu/arm920t/a320/timer.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <faraday/ftpmu010.h>
-#include <faraday/fttmr010.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TIMER_CLOCK 32768
-#define TIMER_LOAD_VAL 0xffffffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, gd->arch.timer_rate_hz);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= gd->arch.timer_rate_hz;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-int timer_init(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
- unsigned int cr;
-
- debug("%s()\n", __func__);
-
- /* disable timers */
- writel(0, &tmr->cr);
-
- /* use 32768Hz oscillator for RTC, WDT, TIMER */
- ftpmu010_32768osc_enable();
-
- /* setup timer */
- writel(TIMER_LOAD_VAL, &tmr->timer3_load);
- writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
- writel(0, &tmr->timer3_match1);
- writel(0, &tmr->timer3_match2);
-
- /* we don't want timer to issue interrupts */
- writel(FTTMR010_TM3_MATCH1 |
- FTTMR010_TM3_MATCH2 |
- FTTMR010_TM3_OVERFLOW,
- &tmr->interrupt_mask);
-
- cr = readl(&tmr->cr);
- cr |= FTTMR010_TM3_CLOCK; /* use external clock */
- cr |= FTTMR010_TM3_ENABLE;
- writel(cr, &tmr->cr);
-
- gd->arch.timer_rate_hz = TIMER_CLOCK;
- gd->arch.tbu = gd->arch.tbl = 0;
-
- return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
- ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
-
- /* increment tbu if tbl has rolled over */
- if (now < gd->arch.tbl)
- gd->arch.tbu++;
- gd->arch.tbl = now;
- return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long start;
- ulong tmo;
-
- start = get_ticks(); /* get current timestamp */
- tmo = usec_to_tick(usec); /* convert usecs to ticks */
- while ((get_ticks() - start) < tmo)
- ; /* loop till time has passed */
-}
-
-/*
- * get_timer(base) can be used to check for timeouts or
- * to measure elasped time relative to an event:
- *
- * ulong start_time = get_timer(0) sets start_time to the current
- * time value.
- * get_timer(start_time) returns the time elapsed since then.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-ulong get_timer(ulong base)
-{
- return tick_to_time(get_ticks()) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return gd->arch.timer_rate_hz;
-}
diff --git a/arch/arm/include/asm/arch-a320/a320.h b/arch/arm/include/asm/arch-a320/a320.h
deleted file mode 100644
index f2db8e1..0000000
--- a/arch/arm/include/asm/arch-a320/a320.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __A320_H
-#define __A320_H
-
-/*
- * Hardware register bases
- */
-#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */
-#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */
-#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */
-#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
-#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
-#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */
-#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/
-
-#endif /* __A320_H */
diff --git a/board/faraday/a320evb/Kconfig b/board/faraday/a320evb/Kconfig
deleted file mode 100644
index 02c42cb..0000000
--- a/board/faraday/a320evb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_A320EVB
-
-config SYS_BOARD
- default "a320evb"
-
-config SYS_VENDOR
- default "faraday"
-
-config SYS_SOC
- default "a320"
-
-config SYS_CONFIG_NAME
- default "a320evb"
-
-endif
diff --git a/board/faraday/a320evb/MAINTAINERS b/board/faraday/a320evb/MAINTAINERS
deleted file mode 100644
index f13b015..0000000
--- a/board/faraday/a320evb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-A320EVB BOARD
-M: Po-Yu Chuang <ratbert@faraday-tech.com>
-S: Maintained
-F: board/faraday/a320evb/
-F: include/configs/a320evb.h
-F: configs/a320evb_defconfig
diff --git a/board/faraday/a320evb/Makefile b/board/faraday/a320evb/Makefile
deleted file mode 100644
index 518ce3f..0000000
--- a/board/faraday/a320evb/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := a320evb.o
-obj-y += lowlevel_init.o
diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c
deleted file mode 100644
index c42635b..0000000
--- a/board/faraday/a320evb/a320evb.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-
-#include <faraday/ftsmc020.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- ftsmc020_init(); /* initialize Flash */
- return 0;
-}
-
-int dram_init(void)
-{
- unsigned long sdram_base = PHYS_SDRAM_1;
- unsigned long expected_size = PHYS_SDRAM_1_SIZE;
- unsigned long actual_size;
-
- actual_size = get_ram_size((void *)sdram_base, expected_size);
-
- gd->ram_size = actual_size;
-
- if (expected_size != actual_size)
- printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
- actual_size >> 20, expected_size >> 20);
-
- return 0;
-}
-
-int board_eth_init(bd_t *bd)
-{
- return ftmac100_initialize(bd);
-}
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = FLASH_CFI_8BIT;
- info->chipwidth = FLASH_CFI_BY8;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else
- return 0;
-}
diff --git a/board/faraday/a320evb/lowlevel_init.S b/board/faraday/a320evb/lowlevel_init.S
deleted file mode 100644
index d366260..0000000
--- a/board/faraday/a320evb/lowlevel_init.S
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-
-#include <asm/macro.h>
-#include <faraday/ftsdmc020.h>
-
-/*
- * parameters for the SDRAM controller
- */
-#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
-#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
-#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
-#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
-#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
-
-#define TP0_D CONFIG_SYS_FTSDMC020_TP0
-#define TP1_D CONFIG_SYS_FTSDMC020_TP1
-#define CR_D1 FTSDMC020_CR_IPREC
-#define CR_D2 FTSDMC020_CR_ISMR
-#define CR_D3 FTSDMC020_CR_IREF
-
-#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
- FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
-#define ACR_D FTSDMC020_ACR_TOC(0x18)
-
-/*
- * numeric 7 segment display
- */
-.macro led, num
- write32 CONFIG_DEBUG_LED, \num
-.endm
-
-/*
- * Waiting for SDRAM to set up
- */
-.macro wait_sdram
- ldr r0, =CONFIG_FTSDMC020_BASE
-1:
- ldr r1, [r0, #FTSDMC020_OFFSET_CR]
- cmp r1, #0
- bne 1b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
- mov r11, lr
-
- led 0x0
-
- bl init_sdmc
-
- led 0x1
-
- /* everything is fine now */
- mov lr, r11
- mov pc, lr
-
-/*
- * memory initialization
- */
-init_sdmc:
- led 0x10
-
- /* set SDRAM register */
-
- write32 TP0_A, TP0_D
- led 0x11
-
- write32 TP1_A, TP1_D
- led 0x12
-
- /* set to precharge */
- write32 CR_A, CR_D1
- led 0x13
-
- wait_sdram
- led 0x14
-
- /* set mode register */
- write32 CR_A, CR_D2
- led 0x15
-
- wait_sdram
- led 0x16
-
- /* set to refresh */
- write32 CR_A, CR_D3
- led 0x17
-
- wait_sdram
- led 0x18
-
- write32 B0_BSR_A, B0_BSR_D
- led 0x19
-
- write32 ACR_A, ACR_D
- led 0x1a
-
- mov pc, lr
diff --git a/configs/a320evb_defconfig b/configs/a320evb_defconfig
deleted file mode 100644
index 5ebf5e6..0000000
--- a/configs/a320evb_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_A320EVB=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index a42b0e1..d78dc93 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+a320evb arm arm920t - - Po-Yu Chuang <ratbert@faraday-tech.com>
cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
cm41xx arm arm920t - -
dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>
diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h
deleted file mode 100644
index 0d3cf36..0000000
--- a/include/configs/a320evb.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * Configuation settings for the Faraday A320 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/a320.h>
-
-/*
- * mach-type definition
- */
-#define MACH_TYPE_FARADAY 758
-#define CONFIG_MACH_TYPE MACH_TYPE_FARADAY
-
-/*
- * Linux kernel tagged list
- */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-/*
- * CPU and Board Configuration Options
- */
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-
-/*
- * Power Management Unit
- */
-#define CONFIG_FTPMU010_POWER
-
-/*
- * Timer
- */
-
-/*
- * Real Time Clock
- */
-#define CONFIG_RTC_FTRTC010
-
-/*
- * Serial console configuration
- */
-
-/* FTUART is a high speed NS 16C550A compatible UART */
-#define CONFIG_BAUDRATE 38400
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_COM1 0x98200000
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_CLK 18432000
-
-/*
- * Ethernet
- */
-#define CONFIG_FTMAC100
-
-#define CONFIG_BOOTDELAY 3
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_PING
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-
-/*
- * SDRAM controller configuration
- */
-#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
- FTSDMC020_TP0_TRP(1) | \
- FTSDMC020_TP0_TRCD(1) | \
- FTSDMC020_TP0_TRF(3) | \
- FTSDMC020_TP0_TWR(1) | \
- FTSDMC020_TP0_TCL(2))
-
-#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
- FTSDMC020_TP1_INI_REFT(8) | \
- FTSDMC020_TP1_REF_INTV(0x180))
-
-#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
- FTSDMC020_BANK_DDW_X16 | \
- FTSDMC020_BANK_DSZ_256M | \
- FTSDMC020_BANK_MBW_32 | \
- FTSDMC020_BANK_SIZE_64M)
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
- GENERATED_GBL_DATA_SIZE)
-
-/*
- * Load address and memory test area should agree with
- * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
- */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000)
-
-/* memtest works on 63 MB in DRAM */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000)
-
-#define CONFIG_SYS_TEXT_BASE 0
-
-/*
- * Static memory controller configuration
- */
-
-#define CONFIG_FTSMC020
-#include <faraday/ftsmc020.h>
-
-#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
- FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
- FTSMC020_BANK_SIZE_1M | \
- FTSMC020_BANK_MBW_8)
-
-#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
- FTSMC020_TPR_AST(3) | \
- FTSMC020_TPR_CTW(3) | \
- FTSMC020_TPR_ATI(0xf) | \
- FTSMC020_TPR_AT2(3) | \
- FTSMC020_TPR_WTC(3) | \
- FTSMC020_TPR_AHT(3) | \
- FTSMC020_TPR_TRNA(0xf))
-
-#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
- FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
- FTSMC020_BANK_SIZE_32M | \
- FTSMC020_BANK_MBW_32)
-
-#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
- FTSMC020_TPR_CTW(3) | \
- FTSMC020_TPR_ATI(0xf) | \
- FTSMC020_TPR_AT2(3) | \
- FTSMC020_TPR_WTC(3) | \
- FTSMC020_TPR_AHT(3) | \
- FTSMC020_TPR_TRNA(0xf))
-
-#define CONFIG_SYS_FTSMC020_CONFIGS { \
- { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
- { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
-}
-
-/*
- * FLASH and environment organization
- */
-
-/* use CFI framework */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-/* support JEDEC */
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_LEGACY_512Kx8
-
-#define PHYS_FLASH_1 0x00000000
-#define PHYS_FLASH_2 0x00400000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
-
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-
-/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#undef CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* environments */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
-#define CONFIG_ENV_SIZE 0x20000
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 09/11] ARM: armada100: remove aspenite and gplugd board support
2015-02-10 4:44 [U-Boot] [PATCH 0/11] ARM: remove non-generic boards Masahiro Yamada
` (7 preceding siblings ...)
2015-02-10 4:44 ` [U-Boot] [PATCH 08/11] ARM: remove a320evb " Masahiro Yamada
@ 2015-02-10 4:44 ` Masahiro Yamada
2015-02-10 5:06 ` Ajay Bhargav
2015-02-10 4:44 ` [U-Boot] [PATCH 10/11] ARM: remove tnetv107x " Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 11/11] ARM: davinci: remove hawkboard support Masahiro Yamada
10 siblings, 1 reply; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 4:44 UTC (permalink / raw)
To: u-boot
These are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Ajay Bhargav <ajay.bhargav@einfochips.com>
---
arch/arm/Kconfig | 10 -
arch/arm/cpu/arm926ejs/Makefile | 1 -
arch/arm/cpu/arm926ejs/armada100/Makefile | 9 -
arch/arm/cpu/arm926ejs/armada100/cpu.c | 92 ---
arch/arm/cpu/arm926ejs/armada100/dram.c | 116 ----
arch/arm/cpu/arm926ejs/armada100/timer.c | 194 ------
arch/arm/include/asm/arch-armada100/armada100.h | 60 --
arch/arm/include/asm/arch-armada100/config.h | 42 --
arch/arm/include/asm/arch-armada100/cpu.h | 162 -----
arch/arm/include/asm/arch-armada100/gpio.h | 32 -
arch/arm/include/asm/arch-armada100/mfp.h | 80 ---
arch/arm/include/asm/arch-armada100/spi.h | 79 ---
.../include/asm/arch-armada100/utmi-armada100.h | 63 --
board/Marvell/aspenite/Kconfig | 15 -
board/Marvell/aspenite/MAINTAINERS | 6 -
board/Marvell/aspenite/Makefile | 10 -
board/Marvell/aspenite/aspenite.c | 43 --
board/Marvell/gplugd/Kconfig | 15 -
board/Marvell/gplugd/MAINTAINERS | 6 -
board/Marvell/gplugd/Makefile | 15 -
board/Marvell/gplugd/gplugd.c | 130 ----
configs/aspenite_defconfig | 2 -
configs/gplugd_defconfig | 2 -
doc/README.scrapyard | 2 +
drivers/net/Makefile | 1 -
drivers/net/armada100_fec.c | 726 ---------------------
drivers/net/armada100_fec.h | 209 ------
drivers/spi/Makefile | 1 -
drivers/spi/armada100_spi.c | 203 ------
drivers/usb/host/Makefile | 1 -
drivers/usb/host/ehci-armada100.c | 48 --
drivers/usb/host/utmi-armada100.c | 80 ---
include/configs/aspenite.h | 55 --
include/configs/gplugd.h | 134 ----
include/netdev.h | 1 -
35 files changed, 2 insertions(+), 2643 deletions(-)
delete mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile
delete mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c
delete mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c
delete mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c
delete mode 100644 arch/arm/include/asm/arch-armada100/armada100.h
delete mode 100644 arch/arm/include/asm/arch-armada100/config.h
delete mode 100644 arch/arm/include/asm/arch-armada100/cpu.h
delete mode 100644 arch/arm/include/asm/arch-armada100/gpio.h
delete mode 100644 arch/arm/include/asm/arch-armada100/mfp.h
delete mode 100644 arch/arm/include/asm/arch-armada100/spi.h
delete mode 100644 arch/arm/include/asm/arch-armada100/utmi-armada100.h
delete mode 100644 board/Marvell/aspenite/Kconfig
delete mode 100644 board/Marvell/aspenite/MAINTAINERS
delete mode 100644 board/Marvell/aspenite/Makefile
delete mode 100644 board/Marvell/aspenite/aspenite.c
delete mode 100644 board/Marvell/gplugd/Kconfig
delete mode 100644 board/Marvell/gplugd/MAINTAINERS
delete mode 100644 board/Marvell/gplugd/Makefile
delete mode 100644 board/Marvell/gplugd/gplugd.c
delete mode 100644 configs/aspenite_defconfig
delete mode 100644 configs/gplugd_defconfig
delete mode 100644 drivers/net/armada100_fec.c
delete mode 100644 drivers/net/armada100_fec.h
delete mode 100644 drivers/spi/armada100_spi.c
delete mode 100644 drivers/usb/host/ehci-armada100.c
delete mode 100644 drivers/usb/host/utmi-armada100.c
delete mode 100644 include/configs/aspenite.h
delete mode 100644 include/configs/gplugd.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3ec570b..702302f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -109,14 +109,6 @@ config TARGET_INTEGRATORCP_CM926EJS
bool "Support integratorcp_cm926ejs"
select CPU_ARM926EJS
-config TARGET_ASPENITE
- bool "Support aspenite"
- select CPU_ARM926EJS
-
-config TARGET_GPLUGD
- bool "Support gplugd"
- select CPU_ARM926EJS
-
config TARGET_AFEB9260
bool "Support afeb9260"
select CPU_ARM926EJS
@@ -825,9 +817,7 @@ source "board/BuR/tseries/Kconfig"
source "board/BuS/eb_cpux9k2/Kconfig"
source "board/BuS/vl_ma2sc/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
-source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/db-mv784mp-gp/Kconfig"
-source "board/Marvell/gplugd/Kconfig"
source "board/afeb9260/Kconfig"
source "board/altera/socfpga/Kconfig"
source "board/armadeus/apf27/Kconfig"
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 38ab0d4..f6000af 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -14,7 +14,6 @@ extra-y :=
endif
endif
-obj-$(CONFIG_ARMADA100) += armada100/
obj-$(CONFIG_AT91FAMILY) += at91/
obj-$(CONFIG_ARCH_DAVINCI) += davinci/
obj-$(CONFIG_KIRKWOOD) += kirkwood/
diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile
deleted file mode 100644
index fca98ef..0000000
--- a/arch/arm/cpu/arm926ejs/armada100/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2010
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o timer.o dram.o
diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c
deleted file mode 100644
index 8b02d0b..0000000
--- a/arch/arm/cpu/arm926ejs/armada100/cpu.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/armada100.h>
-
-#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID (1<<8)
-#define L2C_RAM_SEL (1<<4)
-
-int arch_cpu_init(void)
-{
- u32 val;
- struct armd1cpu_registers *cpuregs =
- (struct armd1cpu_registers *) ARMD1_CPU_BASE;
-
- struct armd1apb1_registers *apb1clkres =
- (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
-
- struct armd1mpmu_registers *mpmu =
- (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
-
- /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
- val = readl(&cpuregs->cpu_conf);
- val = val | SET_MRVL_ID;
- writel(val, &cpuregs->cpu_conf);
-
- /* Enable Clocks for all hardware units */
- writel(0xFFFFFFFF, &mpmu->acgr);
-
- /* Turn on AIB and AIB-APB Functional clock */
- writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
-
- /* ensure L2 cache is not mapped as SRAM */
- val = readl(&cpuregs->cpu_conf);
- val = val & ~(L2C_RAM_SEL);
- writel(val, &cpuregs->cpu_conf);
-
- /* Enable GPIO clock */
- writel(APBC_APBCLK, &apb1clkres->gpio);
-
-#ifdef CONFIG_I2C_MV
- /* Enable general I2C clock */
- writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
- writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
-
- /* Enable power I2C clock */
- writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
- writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
-#endif
-
- /*
- * Enable Functional and APB clock at 14.7456MHz
- * for configured UART console
- */
-#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
- writel(UARTCLK14745KHZ, &apb1clkres->uart3);
-#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
- writel(UARTCLK14745KHZ, &apb1clkres->uart2);
-#else
- writel(UARTCLK14745KHZ, &apb1clkres->uart1);
-#endif
- icache_enable();
-
- return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- u32 id;
- struct armd1cpu_registers *cpuregs =
- (struct armd1cpu_registers *) ARMD1_CPU_BASE;
-
- id = readl(&cpuregs->chip_id);
- printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
- return 0;
-}
-#endif
-
-#ifdef CONFIG_I2C_MV
-void i2c_clk_enable(void)
-{
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c
deleted file mode 100644
index 8d7c71f..0000000
--- a/arch/arm/cpu/arm926ejs/armada100/dram.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/armada100.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * ARMADA100 DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet Appendix A.17
- */
-struct armd1ddr_map_registers {
- u32 cs; /* Memory Address Map Register -CS */
- u32 pad[3];
-};
-
-struct armd1ddr_registers {
- u8 pad[0x100 - 0x000];
- struct armd1ddr_map_registers mmap[2];
-};
-
-/*
- * armd1_sdram_base - reads SDRAM Base Address Register
- */
-u32 armd1_sdram_base(int chip_sel)
-{
- struct armd1ddr_registers *ddr_regs =
- (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
- return result;
-}
-
-/*
- * armd1_sdram_size - reads SDRAM size
- */
-u32 armd1_sdram_size(int chip_sel)
-{
- struct armd1ddr_registers *ddr_regs =
- (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs);
- result = (result >> 16) & 0xF;
- if (result < 0x7) {
- printf("Unknown DRAM Size\n");
- return -1;
- } else {
- return ((0x8 << (result - 0x7)) * 1024 * 1024);
- }
-}
-
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
-int dram_init(void)
-{
- int i;
-
- gd->ram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = armd1_sdram_base(i);
- gd->bd->bi_dram[i].size = armd1_sdram_size(i);
- /*
- * It is assumed that all memory banks are consecutive
- * and without gaps.
- * If the gap is found, ram_size will be reported for
- * consecutive memory only
- */
- if (gd->bd->bi_dram[i].start != gd->ram_size)
- break;
-
- gd->ram_size += gd->bd->bi_dram[i].size;
-
- }
-
- for (; i < CONFIG_NR_DRAM_BANKS; i++) {
- /* If above loop terminated prematurely, we need to set
- * remaining banks' start address & size as 0. Otherwise other
- * u-boot functions and Linux kernel gets wrong values which
- * could result in crash */
- gd->bd->bi_dram[i].start = 0;
- gd->bd->bi_dram[i].size = 0;
- }
- return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-void dram_init_banksize(void)
-{
- dram_init();
-}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
deleted file mode 100644
index bbd0505..0000000
--- a/arch/arm/cpu/arm926ejs/armada100/timer.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/armada100.h>
-
-/*
- * Timer registers
- * Refer Section A.6 in Datasheet
- */
-struct armd1tmr_registers {
- u32 clk_ctrl; /* Timer clk control reg */
- u32 match[9]; /* Timer match registers */
- u32 count[3]; /* Timer count registers */
- u32 status[3];
- u32 ie[3];
- u32 preload[3]; /* Timer preload value */
- u32 preload_ctrl[3];
- u32 wdt_match_en;
- u32 wdt_match_r;
- u32 wdt_val;
- u32 wdt_sts;
- u32 icr[3];
- u32 wdt_icr;
- u32 cer; /* Timer count enable reg */
- u32 cmr;
- u32 ilr[3];
- u32 wcr;
- u32 wfar;
- u32 wsar;
- u32 cvwr;
-};
-
-#define TIMER 0 /* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x) ((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 0xffffffff
-#define COUNT_RD_REQ 0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
-
-/* For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
- struct armd1tmr_registers *armd1timers =
- (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
- volatile int loop=100;
-
- writel(COUNT_RD_REQ, &armd1timers->cvwr);
- while (loop--);
- return(readl(&armd1timers->cvwr));
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (now >= gd->arch.tbl) {
- /* normal mode */
- gd->arch.tbu += now - gd->arch.tbl;
- } else {
- /* we have an overflow ... */
- gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
- }
- gd->arch.tbl = now;
-
- return gd->arch.tbu;
-}
-
-ulong get_timer(ulong base)
-{
- return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
- base);
-}
-
-void __udelay(unsigned long usec)
-{
- ulong delayticks;
- ulong endtime;
-
- delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
- endtime = get_timer_masked() + delayticks;
-
- while (get_timer_masked() < endtime);
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
- struct armd1apb1_registers *apb1clkres =
- (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
- struct armd1tmr_registers *armd1timers =
- (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
-
- /* Enable Timer clock@3.25 MHZ */
- writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
- /* load value into timer */
- writel(0x0, &armd1timers->clk_ctrl);
- /* Use Timer 0 Match Resiger 0 */
- writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
- /* Preload value is 0 */
- writel(0x0, &armd1timers->preload[TIMER]);
- /* Enable match comparator 0 for Timer 0 */
- writel(0x1, &armd1timers->preload_ctrl[TIMER]);
-
- /* Enable timer 0 */
- writel(0x1, &armd1timers->cer);
- /* init the gd->arch.tbu and gd->arch.tbl value */
- gd->arch.tbl = read_timer();
- gd->arch.tbu = 0;
-
- return 0;
-}
-
-#define MPMU_APRR_WDTR (1<<4)
-#define TMR_WFAR 0xbaba /* WDT Register First key */
-#define TMP_WSAR 0xeb10 /* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu (unsigned long ignored)
-{
- struct armd1mpmu_registers *mpmu =
- (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
- struct armd1tmr_registers *armd1timers =
- (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
- u32 val;
-
- /* negate hardware reset to the WDT after system reset */
- val = readl(&mpmu->aprr);
- val = val | MPMU_APRR_WDTR;
- writel(val, &mpmu->aprr);
-
- /* reset/enable WDT clock */
- writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
- readl(&mpmu->wdtpcr);
- writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
- readl(&mpmu->wdtpcr);
-
- /* clear previous WDT status */
- writel(TMR_WFAR, &armd1timers->wfar);
- writel(TMP_WSAR, &armd1timers->wsar);
- writel(0, &armd1timers->wdt_sts);
-
- /* set match counter */
- writel(TMR_WFAR, &armd1timers->wfar);
- writel(TMP_WSAR, &armd1timers->wsar);
- writel(0xf, &armd1timers->wdt_match_r);
-
- /* enable WDT reset */
- writel(TMR_WFAR, &armd1timers->wfar);
- writel(TMP_WSAR, &armd1timers->wsar);
- writel(0x3, &armd1timers->wdt_match_en);
-
- while(1);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
deleted file mode 100644
index d9feb16..0000000
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_ARMADA100_H
-#define _ASM_ARCH_ARMADA100_H
-
-#if defined (CONFIG_ARMADA100)
-
-/* Common APB clock register bit definitions */
-#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
-#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
-#define APBC_RST (1<<2) /* Reset Generation */
-/* Functional Clock Selection Mask */
-#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
-
-/* Fast Ethernet Controller Clock register definition */
-#define FE_CLK_RST 0x1
-#define FE_CLK_ENA 0x8
-
-/* SSP2 Clock Control */
-#define SSP2_APBCLK 0x01
-#define SSP2_FNCLK 0x02
-
-/* USB Clock/reset control bits */
-#define USB_SPH_AXICLK_EN 0x10
-#define USB_SPH_AXI_RST 0x02
-
-/* MPMU Clocks */
-#define APB2_26M_EN (1 << 20)
-#define AP_26M (1 << 4)
-
-/* Register Base Addresses */
-#define ARMD1_DRAM_BASE 0xB0000000
-#define ARMD1_FEC_BASE 0xC0800000
-#define ARMD1_TIMER_BASE 0xD4014000
-#define ARMD1_APBC1_BASE 0xD4015000
-#define ARMD1_APBC2_BASE 0xD4015800
-#define ARMD1_UART1_BASE 0xD4017000
-#define ARMD1_UART2_BASE 0xD4018000
-#define ARMD1_GPIO_BASE 0xD4019000
-#define ARMD1_SSP1_BASE 0xD401B000
-#define ARMD1_SSP2_BASE 0xD401C000
-#define ARMD1_MFPR_BASE 0xD401E000
-#define ARMD1_SSP3_BASE 0xD401F000
-#define ARMD1_SSP4_BASE 0xD4020000
-#define ARMD1_SSP5_BASE 0xD4021000
-#define ARMD1_UART3_BASE 0xD4026000
-#define ARMD1_MPMU_BASE 0xD4050000
-#define ARMD1_USB_HOST_BASE 0xD4209000
-#define ARMD1_APMU_BASE 0xD4282800
-#define ARMD1_CPU_BASE 0xD4282C00
-
-#endif /* CONFIG_ARMADA100 */
-#endif /* _ASM_ARCH_ARMADA100_H */
diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
deleted file mode 100644
index e062da1..0000000
--- a/arch/arm/include/asm/arch-armada100/config.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * This file should be included in board config header file.
- *
- * It supports common definitions for Armada100 platform
- */
-
-#ifndef _ARMD1_CONFIG_H
-#define _ARMD1_CONFIG_H
-
-#include <asm/arch/armada100.h>
-/* default Dcache Line length for armada100 */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
-#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
-#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
-#define MV_MFPR_BASE ARMD1_MFPR_BASE
-#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE
-#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
- represents UART Unit Enable */
-/*
- * I2C definition
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MV 1
-#define CONFIG_MV_I2C_NUM 2
-#define CONFIG_I2C_MULTI_BUS 1
-#define CONFIG_MV_I2C_REG {0xd4011000, 0xd4025000}
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 0
-#define CONFIG_SYS_I2C_SLAVE 0xfe
-#endif
-
-#endif /* _ARMD1_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h
deleted file mode 100644
index c1f190d..0000000
--- a/arch/arm/include/asm/arch-armada100/cpu.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ARMADA100CPU_H
-#define _ARMADA100CPU_H
-
-#include <asm/io.h>
-#include <asm/system.h>
-
-/*
- * Main Power Management (MPMU) Registers
- * Refer Datasheet Appendix A.8
- */
-struct armd1mpmu_registers {
- u8 pad0[0x08 - 0x00];
- u32 fccr; /*0x0008*/
- u32 pocr; /*0x000c*/
- u32 posr; /*0x0010*/
- u32 succr; /*0x0014*/
- u8 pad1[0x030 - 0x014 - 4];
- u32 gpcr; /*0x0030*/
- u8 pad2[0x200 - 0x030 - 4];
- u32 wdtpcr; /*0x0200*/
- u8 pad3[0x1000 - 0x200 - 4];
- u32 apcr; /*0x1000*/
- u32 apsr; /*0x1004*/
- u8 pad4[0x1020 - 0x1004 - 4];
- u32 aprr; /*0x1020*/
- u32 acgr; /*0x1024*/
- u32 arsr; /*0x1028*/
-};
-
-/*
- * Application Subsystem Power Management
- * Refer Datasheet Appendix A.9
- */
-struct armd1apmu_registers {
- u32 pcr; /* 0x000 */
- u32 ccr; /* 0x004 */
- u32 pad1;
- u32 ccsr; /* 0x00C */
- u32 fc_timer; /* 0x010 */
- u32 pad2;
- u32 ideal_cfg; /* 0x018 */
- u8 pad3[0x04C - 0x018 - 4];
- u32 lcdcrc; /* 0x04C */
- u32 cciccrc; /* 0x050 */
- u32 sd1crc; /* 0x054 */
- u32 sd2crc; /* 0x058 */
- u32 usbcrc; /* 0x05C */
- u32 nfccrc; /* 0x060 */
- u32 dmacrc; /* 0x064 */
- u32 pad4;
- u32 buscrc; /* 0x06C */
- u8 pad5[0x07C - 0x06C - 4];
- u32 wake_clr; /* 0x07C */
- u8 pad6[0x090 - 0x07C - 4];
- u32 core_status; /* 0x090 */
- u32 rfsc; /* 0x094 */
- u32 imr; /* 0x098 */
- u32 irwc; /* 0x09C */
- u32 isr; /* 0x0A0 */
- u8 pad7[0x0B0 - 0x0A0 - 4];
- u32 mhst; /* 0x0B0 */
- u32 msr; /* 0x0B4 */
- u8 pad8[0x0C0 - 0x0B4 - 4];
- u32 msst; /* 0x0C0 */
- u32 pllss; /* 0x0C4 */
- u32 smb; /* 0x0C8 */
- u32 gccrc; /* 0x0CC */
- u8 pad9[0x0D4 - 0x0CC - 4];
- u32 smccrc; /* 0x0D4 */
- u32 pad10;
- u32 xdcrc; /* 0x0DC */
- u32 sd3crc; /* 0x0E0 */
- u32 sd4crc; /* 0x0E4 */
- u8 pad11[0x0F0 - 0x0E4 - 4];
- u32 cfcrc; /* 0x0F0 */
- u32 mspcrc; /* 0x0F4 */
- u32 cmucrc; /* 0x0F8 */
- u32 fecrc; /* 0x0FC */
- u32 pciecrc; /* 0x100 */
- u32 epdcrc; /* 0x104 */
-};
-
-/*
- * APB1 Clock Reset/Control Registers
- * Refer Datasheet Appendix A.10
- */
-struct armd1apb1_registers {
- u32 uart1; /*0x000*/
- u32 uart2; /*0x004*/
- u32 gpio; /*0x008*/
- u32 pwm1; /*0x00c*/
- u32 pwm2; /*0x010*/
- u32 pwm3; /*0x014*/
- u32 pwm4; /*0x018*/
- u8 pad0[0x028 - 0x018 - 4];
- u32 rtc; /*0x028*/
- u32 twsi0; /*0x02c*/
- u32 kpc; /*0x030*/
- u32 timers; /*0x034*/
- u8 pad1[0x03c - 0x034 - 4];
- u32 aib; /*0x03c*/
- u32 sw_jtag; /*0x040*/
- u32 timer1; /*0x044*/
- u32 onewire; /*0x048*/
- u8 pad2[0x050 - 0x048 - 4];
- u32 asfar; /*0x050 AIB Secure First Access Reg*/
- u32 assar; /*0x054 AIB Secure Second Access Reg*/
- u8 pad3[0x06c - 0x054 - 4];
- u32 twsi1; /*0x06c*/
- u32 uart3; /*0x070*/
- u8 pad4[0x07c - 0x070 - 4];
- u32 timer2; /*0x07C*/
- u8 pad5[0x084 - 0x07c - 4];
- u32 ac97; /*0x084*/
-};
-
-/*
-* APB2 Clock Reset/Control Registers
-* Refer Datasheet Appendix A.11
-*/
-struct armd1apb2_registers {
- u32 pad1[0x01C - 0x000];
- u32 ssp1_clkrst; /* 0x01C */
- u32 ssp2_clkrst; /* 0x020 */
- u32 pad2[0x04C - 0x020 - 4];
- u32 ssp3_clkrst; /* 0x04C */
- u32 pad3[0x058 - 0x04C - 4];
- u32 ssp4_clkrst; /* 0x058 */
- u32 ssp5_clkrst; /* 0x05C */
-};
-
-/*
- * CPU Interface Registers
- * Refer Datasheet Appendix A.2
- */
-struct armd1cpu_registers {
- u32 chip_id; /* Chip Id Reg */
- u32 pad;
- u32 cpu_conf; /* CPU Conf Reg */
- u32 pad1;
- u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
- u32 pad2;
- u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
- u32 mcb_conf; /* MCB Conf Reg */
- u32 sys_boot_ctl; /* Sytem Boot Control */
-};
-
-/*
- * Functions
- */
-u32 armd1_sdram_base(int);
-u32 armd1_sdram_size(int);
-
-#endif /* _ARMADA100CPU_H */
diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h
deleted file mode 100644
index 4927abe..0000000
--- a/arch/arm/include/asm/arch-armada100/gpio.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_GPIO_H
-#define _ASM_ARCH_GPIO_H
-
-#include <asm/types.h>
-#include <asm/arch/armada100.h>
-
-#define GPIO_HIGH 1
-#define GPIO_LOW 0
-
-#define GPIO_TO_REG(gp) (gp >> 5)
-#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F))
-#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01)
-
-static inline void *get_gpio_base(int bank)
-{
- const unsigned int offset[4] = {0, 4, 8, 0x100};
- /* gpio register bank offset - refer Appendix A.36 */
- return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
-}
-
-#endif /* _ASM_ARCH_GPIO_H */
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h
deleted file mode 100644
index b918239..0000000
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
- * (C) Copyright 2007
- * Marvell Semiconductor <www.marvell.com>
- * 2007-08-21: eric miao <eric.miao@marvell.com>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ARMADA100_MFP_H
-#define __ARMADA100_MFP_H
-
-/*
- * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
- *
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-/* UART1 */
-#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
-#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
-#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
-#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
-#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* UART2 */
-#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* UART3 */
-#define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* I2c */
-#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-
-/* Fast Ethernet */
-#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-
-/* SPI */
-#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
-#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM)
-#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
-
-/* More macros can be defined here... */
-
-#define MFP_PIN_MAX 117
-
-#endif /* __ARMADA100_MFP_H */
diff --git a/arch/arm/include/asm/arch-armada100/spi.h b/arch/arm/include/asm/arch-armada100/spi.h
deleted file mode 100644
index 9efa1bf..0000000
--- a/arch/arm/include/asm/arch-armada100/spi.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ARMADA100_SPI_H_
-#define __ARMADA100_SPI_H_
-
-#include <asm/arch/armada100.h>
-
-#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE
-#define SSP_REG_BASE(x) CAT_BASE_ADDR(x)
-
-/*
- * SSP Serial Port Registers
- * refer Appendix A.26
- */
-struct ssp_reg {
- u32 sscr0; /* SSP Control Register 0 - 0x000 */
- u32 sscr1; /* SSP Control Register 1 - 0x004 */
- u32 sssr; /* SSP Status Register - 0x008 */
- u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
- u32 ssdr; /* SSP Data Register - 0x010 */
- u32 pad1[5];
- u32 ssto; /* SSP Timeout Register - 0x028 */
- u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
- u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
- u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
- u32 sstss; /* SSP Timeslot Status Register - 0x038 */
-};
-
-#define DEFAULT_WORD_LEN 8
-#define SSP_FLUSH_NUM 0x2000
-#define RX_THRESH_DEF 8
-#define TX_THRESH_DEF 8
-#define TIMEOUT_DEF 1000
-
-#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
-#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
-#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
-#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity
- setting */
-#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
-#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
-#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
-#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */
-
-#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
-#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
-#define SSCR1_TINTE (1 << 19) /* Receiver Time-out
- Interrupt enable */
-
-#define SSCR0_DSS 0x0f /* Data Size Select (mask) */
-#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
-#define SSCR0_FRF 0x30 /* FRame Format (mask) */
-#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
- Peripheral Interface */
-#define SSCR0_TI (0x1 << 4) /* TI's Synchronous
- Serial Protocol (SSP) */
-#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
-#define SSCR0_ECS (1 << 6) /* External clock select */
-#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port
- Enable */
-
-#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
-#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
-#define SSSR_BSY (1 << 4) /* SSP Busy */
-#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
-#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
-#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
-#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
-
-#endif /* __ARMADA100_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-armada100/utmi-armada100.h b/arch/arm/include/asm/arch-armada100/utmi-armada100.h
deleted file mode 100644
index 953dd44..0000000
--- a/arch/arm/include/asm/arch-armada100/utmi-armada100.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2012
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __UTMI_ARMADA100__
-#define __UTMI_ARMADA100__
-
-#define UTMI_PHY_BASE 0xD4206000
-
-/* utmi_ctrl - bits */
-#define INPKT_DELAY_SOF (1 << 28)
-#define PLL_PWR_UP 2
-#define PHY_PWR_UP 1
-
-/* utmi_pll - bits */
-#define PLL_FBDIV_MASK 0x00000FF0
-#define PLL_FBDIV 4
-#define PLL_REFDIV_MASK 0x0000000F
-#define PLL_REFDIV 0
-#define PLL_READY 0x800000
-#define VCOCAL_START (1 << 21)
-
-#define N_DIVIDER 0xEE
-#define M_DIVIDER 0x0B
-
-/* utmi_tx - bits */
-#define CK60_PHSEL 17
-#define PHSEL_VAL 0x4
-#define RCAL_START (1 << 12)
-
-/*
- * USB PHY registers
- * Refer Datasheet Appendix A.21
- */
-struct armd1usb_phy_reg {
- u32 utmi_rev; /* USB PHY Revision */
- u32 utmi_ctrl; /* USB PHY Control register */
- u32 utmi_pll; /* PLL register */
- u32 utmi_tx; /* Tx register */
- u32 utmi_rx; /* Rx register */
- u32 utmi_ivref; /* IVREF register */
- u32 utmi_tst_g0; /* Test group 0 register */
- u32 utmi_tst_g1; /* Test group 1 register */
- u32 utmi_tst_g2; /* Test group 2 register */
- u32 utmi_tst_g3; /* Test group 3 register */
- u32 utmi_tst_g4; /* Test group 4 register */
- u32 utmi_tst_g5; /* Test group 5 register */
- u32 utmi_reserve; /* Reserve Register */
- u32 utmi_usb_int; /* USB interuppt register */
- u32 utmi_dbg_ctl; /* Debug control register */
- u32 utmi_otg_addon; /* OTG addon register */
-};
-
-int utmi_init(void);
-
-#endif /* __UTMI_ARMADA100__ */
diff --git a/board/Marvell/aspenite/Kconfig b/board/Marvell/aspenite/Kconfig
deleted file mode 100644
index 4dd49c4..0000000
--- a/board/Marvell/aspenite/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_ASPENITE
-
-config SYS_BOARD
- default "aspenite"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_SOC
- default "armada100"
-
-config SYS_CONFIG_NAME
- default "aspenite"
-
-endif
diff --git a/board/Marvell/aspenite/MAINTAINERS b/board/Marvell/aspenite/MAINTAINERS
deleted file mode 100644
index a77d30e..0000000
--- a/board/Marvell/aspenite/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ASPENITE BOARD
-M: Prafulla Wadaskar <prafulla@marvell.com>
-S: Maintained
-F: board/Marvell/aspenite/
-F: include/configs/aspenite.h
-F: configs/aspenite_defconfig
diff --git a/board/Marvell/aspenite/Makefile b/board/Marvell/aspenite/Makefile
deleted file mode 100644
index 726d0e4..0000000
--- a/board/Marvell/aspenite/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2010
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-# Contributor: Mahavir Jain <mjain@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := aspenite.o
diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c
deleted file mode 100644
index 24ee679..0000000
--- a/board/Marvell/aspenite/aspenite.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mvmfp.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mfp.h>
-#include <asm/arch/armada100.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- u32 mfp_cfg[] = {
- /* I2C */
- MFP105_CI2C_SDA,
- MFP106_CI2C_SCL,
-
- /* Enable Console on UART1 */
- MFP107_UART1_RXD,
- MFP108_UART1_TXD,
-
- MFP_EOC /*End of configureation*/
- };
- /* configure MFP's */
- mfp_config(mfp_cfg);
- return 0;
-}
-
-int board_init(void)
-{
- /* arch number of Board */
- gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
- return 0;
-}
diff --git a/board/Marvell/gplugd/Kconfig b/board/Marvell/gplugd/Kconfig
deleted file mode 100644
index d944816..0000000
--- a/board/Marvell/gplugd/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_GPLUGD
-
-config SYS_BOARD
- default "gplugd"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_SOC
- default "armada100"
-
-config SYS_CONFIG_NAME
- default "gplugd"
-
-endif
diff --git a/board/Marvell/gplugd/MAINTAINERS b/board/Marvell/gplugd/MAINTAINERS
deleted file mode 100644
index 320bc09..0000000
--- a/board/Marvell/gplugd/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GPLUGD BOARD
-M: Ajay Bhargav <ajay.bhargav@einfochips.com>
-S: Maintained
-F: board/Marvell/gplugd/
-F: include/configs/gplugd.h
-F: configs/gplugd_defconfig
diff --git a/board/Marvell/gplugd/Makefile b/board/Marvell/gplugd/Makefile
deleted file mode 100644
index b384578..0000000
--- a/board/Marvell/gplugd/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# (C) Copyright 2011
-# eInfochips Ltd. <www.einfochips.com>
-# Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
-#
-# Based on Aspenite:
-# (C) Copyright 2010
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-# Contributor: Mahavir Jain <mjain@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := gplugd.o
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
deleted file mode 100644
index 0e8ebcc..0000000
--- a/board/Marvell/gplugd/gplugd.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
- *
- * Based on Aspenite:
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mvmfp.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mfp.h>
-#include <asm/arch/armada100.h>
-#include <asm/gpio.h>
-#include <miiphy.h>
-
-#ifdef CONFIG_ARMADA100_FEC
-#include <net.h>
-#include <netdev.h>
-#endif /* CONFIG_ARMADA100_FEC */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- u32 mfp_cfg[] = {
- /* I2C */
- MFP105_CI2C_SDA,
- MFP106_CI2C_SCL,
-
- /* Enable Console on UART3 */
- MFPO8_UART3_TXD,
- MFPO9_UART3_RXD,
-
- /* Ethernet PHY Interface */
- MFP086_ETH_TXCLK,
- MFP087_ETH_TXEN,
- MFP088_ETH_TXDQ3,
- MFP089_ETH_TXDQ2,
- MFP090_ETH_TXDQ1,
- MFP091_ETH_TXDQ0,
- MFP092_ETH_CRS,
- MFP093_ETH_COL,
- MFP094_ETH_RXCLK,
- MFP095_ETH_RXER,
- MFP096_ETH_RXDQ3,
- MFP097_ETH_RXDQ2,
- MFP098_ETH_RXDQ1,
- MFP099_ETH_RXDQ0,
- MFP100_ETH_MDC,
- MFP101_ETH_MDIO,
- MFP103_ETH_RXDV,
-
- /* SSP2 */
- MFP107_SSP2_RXD,
- MFP108_SSP2_TXD,
- MFP110_SSP2_CS,
- MFP111_SSP2_CLK,
-
- MFP_EOC /*End of configuration*/
- };
- /* configure MFP's */
- mfp_config(mfp_cfg);
- return 0;
-}
-
-int board_init(void)
-{
- struct armd1apb2_registers *apb2_regs =
- (struct armd1apb2_registers *)ARMD1_APBC2_BASE;
-
- /* arch number of Board */
- gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
- /* Assert PHY_RST# */
- gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
- udelay(10);
- /* Deassert PHY_RST# */
- gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
-
- /* Enable SSP2 clock */
- writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
- return 0;
-}
-
-#ifdef CONFIG_ARMADA100_FEC
-int board_eth_init(bd_t *bis)
-{
- struct armd1apmu_registers *apmu_regs =
- (struct armd1apmu_registers *)ARMD1_APMU_BASE;
-
- /* Enable clock of ethernet controller */
- writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
-
- return armada100_fec_register(ARMD1_FEC_BASE);
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and initialize PHY chip 88E3015 */
-void reset_phy(void)
-{
- u16 phy_adr;
- const char *name = "armd-fec0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xff, 0xff, &phy_adr)) {
- printf("Err..%s could not read PHY dev address\n", __func__);
- return;
- }
-
- /* Set Ethernet LED in TX blink mode */
- miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
- miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
-
- /* reset the phy */
- miiphy_reset(name, phy_adr);
- debug("88E3015 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
-#endif /* CONFIG_ARMADA100_FEC */
diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig
deleted file mode 100644
index 0b341d6..0000000
--- a/configs/aspenite_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_ASPENITE=y
diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig
deleted file mode 100644
index ec8f45c..0000000
--- a/configs/gplugd_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_GPLUGD=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index d78dc93..172386a 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+aspenite arm arm926ejs - - Prafulla Wadaskar <prafulla@marvell.com>
+gplugd arm arm926ejs - - Ajay Bhargav <ajay.bhargav@einfochips.com>
a320evb arm arm920t - - Po-Yu Chuang <ratbert@faraday-tech.com>
cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
cm41xx arm arm920t - -
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index da5e2bc..e7fafa8 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -7,7 +7,6 @@
obj-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
-obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
deleted file mode 100644
index a8da6b1..0000000
--- a/drivers/net/armada100_fec.c
+++ /dev/null
@@ -1,726 +0,0 @@
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <malloc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/types.h>
-#include <asm/byteorder.h>
-#include <linux/err.h>
-#include <linux/mii.h>
-#include <asm/io.h>
-#include <asm/arch/armada100.h>
-#include "armada100_fec.h"
-
-#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
-
-#ifdef DEBUG
-static int eth_dump_regs(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- unsigned int i = 0;
-
- printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
- printf("offset: smi, value: 0x%x\n", readl(®s->smi));
- for (i = 0x400; i <= 0x4e4; i += 4)
- printf("offset: 0x%x, value: 0x%x\n",
- i, readl(ARMD1_FEC_BASE + i));
- return 0;
-}
-#endif
-
-static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
-{
- u32 timeout = PHY_WAIT_ITERATIONS;
- u32 reg_val;
-
- while (--timeout) {
- reg_val = readl(reg);
- if (cond && (reg_val & flag))
- break;
- else if (!cond && !(reg_val & flag))
- break;
- udelay(PHY_WAIT_MICRO_SECONDS);
- }
- return !timeout;
-}
-
-static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
- u16 *value)
-{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- u32 val;
-
- if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
- val = readl(®s->phyadr);
- *value = val & 0x1f;
- return 0;
- }
-
- /* check parameters */
- if (phy_addr > PHY_MASK) {
- printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
- __func__, phy_addr);
- return -EINVAL;
- }
- if (phy_reg > PHY_MASK) {
- printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
- __func__, phy_reg);
- return -EINVAL;
- }
-
- /* wait for the SMI register to become available */
- if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
- printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
- return -1;
- }
-
- writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi);
-
- /* now wait for the data to be valid */
- if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) {
- val = readl(®s->smi);
- printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
- __func__, val);
- return -1;
- }
- val = readl(®s->smi);
- *value = val & 0xffff;
-
- return 0;
-}
-
-static int smi_reg_write(const char *devname,
- u8 phy_addr, u8 phy_reg, u16 value)
-{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
-
- if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
- clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f);
- return 0;
- }
-
- /* check parameters */
- if (phy_addr > PHY_MASK) {
- printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
- return -EINVAL;
- }
- if (phy_reg > PHY_MASK) {
- printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
- return -EINVAL;
- }
-
- /* wait for the SMI register to become available */
- if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
- printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
- return -1;
- }
-
- writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff),
- ®s->smi);
- return 0;
-}
-
-/*
- * Abort any transmit and receive operations and put DMA
- * in idle state. AT and AR bits are cleared upon entering
- * in IDLE state. So poll those bits to verify operation.
- */
-static void abortdma(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- int delay;
- int maxretries = 40;
- u32 tmp;
-
- while (--maxretries) {
- writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd);
- udelay(100);
-
- delay = 10;
- while (--delay) {
- tmp = readl(®s->sdma_cmd);
- if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT)))
- break;
- udelay(10);
- }
- if (delay)
- break;
- }
-
- if (!maxretries)
- printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
-}
-
-static inline u32 nibble_swapping_32_bit(u32 x)
-{
- return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4);
-}
-
-static inline u32 nibble_swapping_16_bit(u32 x)
-{
- return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4);
-}
-
-static inline u32 flip_4_bits(u32 x)
-{
- return ((x & 0x01) << 3) | ((x & 0x002) << 1)
- | ((x & 0x04) >> 1) | ((x & 0x008) >> 3);
-}
-
-/*
- * This function will calculate the hash function of the address.
- * depends on the hash mode and hash size.
- * Inputs
- * mach - the 2 most significant bytes of the MAC address.
- * macl - the 4 least significant bytes of the MAC address.
- * Outputs
- * return the calculated entry.
- */
-static u32 hash_function(u32 mach, u32 macl)
-{
- u32 hashresult;
- u32 addrh;
- u32 addrl;
- u32 addr0;
- u32 addr1;
- u32 addr2;
- u32 addr3;
- u32 addrhswapped;
- u32 addrlswapped;
-
- addrh = nibble_swapping_16_bit(mach);
- addrl = nibble_swapping_32_bit(macl);
-
- addrhswapped = flip_4_bits(addrh & 0xf)
- + ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
- + ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
- + ((flip_4_bits((addrh >> 12) & 0xf)) << 12);
-
- addrlswapped = flip_4_bits(addrl & 0xf)
- + ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
- + ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
- + ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
- + ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
- + ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
- + ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
- + ((flip_4_bits((addrl >> 28) & 0xf)) << 28);
-
- addrh = addrhswapped;
- addrl = addrlswapped;
-
- addr0 = (addrl >> 2) & 0x03f;
- addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2);
- addr2 = (addrl >> 15) & 0x1ff;
- addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8);
-
- hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
- hashresult = hashresult & 0x07ff;
- return hashresult;
-}
-
-/*
- * This function will add an entry to the address table.
- * depends on the hash mode and hash size that was initialized.
- * Inputs
- * mach - the 2 most significant bytes of the MAC address.
- * macl - the 4 least significant bytes of the MAC address.
- * skip - if 1, skip this address.
- * rd - the RD field in the address table.
- * Outputs
- * address table entry is added.
- * 0 if success.
- * -ENOSPC if table full
- */
-static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
- u32 macl, u32 rd, u32 skip, int del)
-{
- struct addr_table_entry_t *entry, *start;
- u32 newhi;
- u32 newlo;
- u32 i;
-
- newlo = (((mach >> 4) & 0xf) << 15)
- | (((mach >> 0) & 0xf) << 11)
- | (((mach >> 12) & 0xf) << 7)
- | (((mach >> 8) & 0xf) << 3)
- | (((macl >> 20) & 0x1) << 31)
- | (((macl >> 16) & 0xf) << 27)
- | (((macl >> 28) & 0xf) << 23)
- | (((macl >> 24) & 0xf) << 19)
- | (skip << HTESKIP) | (rd << HTERDBIT)
- | HTEVALID;
-
- newhi = (((macl >> 4) & 0xf) << 15)
- | (((macl >> 0) & 0xf) << 11)
- | (((macl >> 12) & 0xf) << 7)
- | (((macl >> 8) & 0xf) << 3)
- | (((macl >> 21) & 0x7) << 0);
-
- /*
- * Pick the appropriate table, start scanning for free/reusable
- * entries@the index obtained by hashing the specified MAC address
- */
- start = (struct addr_table_entry_t *)(darmdfec->htpr);
- entry = start + hash_function(mach, macl);
- for (i = 0; i < HOP_NUMBER; i++) {
- if (!(entry->lo & HTEVALID)) {
- break;
- } else {
- /* if same address put in same position */
- if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
- && (entry->hi == newhi))
- break;
- }
- if (entry == start + 0x7ff)
- entry = start;
- else
- entry++;
- }
-
- if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
- (entry->hi != newhi) && del)
- return 0;
-
- if (i == HOP_NUMBER) {
- if (!del) {
- printf("ARMD100 FEC: (%s) table section is full\n",
- __func__);
- return -ENOSPC;
- } else {
- return 0;
- }
- }
-
- /*
- * Update the selected entry
- */
- if (del) {
- entry->hi = 0;
- entry->lo = 0;
- } else {
- entry->hi = newhi;
- entry->lo = newlo;
- }
-
- return 0;
-}
-
-/*
- * Create an addressTable entry from MAC address info
- * found in the specifed net_device struct
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- */
-static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
- u8 *oaddr, u8 *addr)
-{
- u32 mach;
- u32 macl;
-
- /* Delete old entry */
- if (oaddr) {
- mach = (oaddr[0] << 8) | oaddr[1];
- macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
- (oaddr[4] << 8) | oaddr[5];
- add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
- }
-
- /* Add new entry */
- mach = (addr[0] << 8) | addr[1];
- macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
- add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
-}
-
-/* Address Table Initialization */
-static void init_hashtable(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
- writel((u32)darmdfec->htpr, ®s->htpr);
-}
-
-/*
- * This detects PHY chip from address 0-31 by reading PHY status
- * registers. PHY chip can be connected at any of this address.
- */
-static int ethernet_phy_detect(struct eth_device *dev)
-{
- u32 val;
- u16 tmp, mii_status;
- u8 addr;
-
- for (addr = 0; addr < 32; addr++) {
- if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0)
- /* try next phy */
- continue;
-
- /* invalid MII status. More validation required here... */
- if (mii_status == 0 || mii_status == 0xffff)
- /* try next phy */
- continue;
-
- if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
- /* try next phy */
- continue;
-
- val = tmp << 16;
- if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
- /* try next phy */
- continue;
-
- val |= tmp;
-
- if ((val & 0xfffffff0) != 0)
- return addr;
- }
- return -1;
-}
-
-static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
-{
- struct rx_desc *p_rx_desc;
- int i;
-
- /* initialize the Rx descriptors ring */
- p_rx_desc = darmdfec->p_rxdesc;
- for (i = 0; i < RINGSZ; i++) {
- p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
- p_rx_desc->buf_size = PKTSIZE_ALIGN;
- p_rx_desc->byte_cnt = 0;
- p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
- if (i == (RINGSZ - 1)) {
- p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
- } else {
- p_rx_desc->nxtdesc_p = (struct rx_desc *)
- ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
- p_rx_desc = p_rx_desc->nxtdesc_p;
- }
- }
- darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
-}
-
-static int armdfec_init(struct eth_device *dev, bd_t *bd)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- int phy_adr;
- u32 temp;
-
- armdfec_init_rx_desc_ring(darmdfec);
-
- /* Disable interrupts */
- writel(0, ®s->im);
- writel(0, ®s->ic);
- /* Write to ICR to clear interrupts. */
- writel(0, ®s->iwc);
-
- /*
- * Abort any transmit and receive operations and put DMA
- * in idle state.
- */
- abortdma(dev);
-
- /* Initialize address hash table */
- init_hashtable(dev);
-
- /* SDMA configuration */
- writel(SDCR_BSZ8 | /* Burst size = 32 bytes */
- SDCR_RIFB | /* Rx interrupt on frame */
- SDCR_BLMT | /* Little endian transmit */
- SDCR_BLMR | /* Little endian receive */
- SDCR_RC_MAX_RETRANS, /* Max retransmit count */
- ®s->sdma_conf);
- /* Port Configuration */
- writel(PCR_HS, ®s->pconf); /* Hash size is 1/2kb */
-
- /* Set extended port configuration */
- writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */
- PCXR_DSCP_EN | /* Enable DSCP in IP */
- PCXR_MFL_1536 | /* Set MTU = 1536 */
- PCXR_FLP | /* do not force link pass */
- PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */
- ®s->pconf_ext);
-
- update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
-
- /* Update TX and RX queue descriptor register */
- temp = (u32)®s->txcdp[TXQ];
- writel((u32)darmdfec->p_txdesc, temp);
- temp = (u32)®s->rxfdp[RXQ];
- writel((u32)darmdfec->p_rxdesc, temp);
- temp = (u32)®s->rxcdp[RXQ];
- writel((u32)darmdfec->p_rxdesc_curr, temp);
-
- /* Enable Interrupts */
- writel(ALL_INTS, ®s->im);
-
- /* Enable Ethernet Port */
- setbits_le32(®s->pconf, PCR_EN);
-
- /* Enable RX DMA engine */
- setbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
-
-#ifdef DEBUG
- eth_dump_regs(dev);
-#endif
-
-#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
-
-#if defined(CONFIG_PHY_BASE_ADR)
- miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
-#else
- /* Search phy address from range 0-31 */
- phy_adr = ethernet_phy_detect(dev);
- if (phy_adr < 0) {
- printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
- return -1;
- } else {
- debug("ARMD100 FEC: PHY detected@addr %d\n", phy_adr);
- miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
- }
-#endif
-
-#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
- /* Wait up to 5s for the link status */
- for (i = 0; i < 5; i++) {
- u16 phy_adr;
-
- miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
- /* Return if we get link up */
- if (miiphy_link(dev->name, phy_adr))
- return 0;
- udelay(1000000);
- }
-
- printf("ARMD100 FEC: No link on %s\n", dev->name);
- return -1;
-#endif
-#endif
- return 0;
-}
-
-static void armdfec_halt(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
-
- /* Stop RX DMA */
- clrbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
-
- /*
- * Abort any transmit and receive operations and put DMA
- * in idle state.
- */
- abortdma(dev);
-
- /* Disable interrupts */
- writel(0, ®s->im);
- writel(0, ®s->ic);
- writel(0, ®s->iwc);
-
- /* Disable Port */
- clrbits_le32(®s->pconf, PCR_EN);
-}
-
-static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- struct tx_desc *p_txdesc = darmdfec->p_txdesc;
- void *p = (void *)dataptr;
- int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
- u32 cmd_sts, temp;
-
- /* Copy buffer if it's misaligned */
- if ((u32)dataptr & 0x07) {
- if (datasize > PKTSIZE_ALIGN) {
- printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
- datasize);
- return -1;
- }
- memcpy(darmdfec->p_aligned_txbuf, p, datasize);
- p = darmdfec->p_aligned_txbuf;
- }
-
- p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC;
- p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC;
- p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA;
- p_txdesc->cmd_sts |= TX_EN_INT;
- p_txdesc->buf_ptr = p;
- p_txdesc->byte_cnt = datasize;
-
- /* Apply send command using high priority TX queue */
- temp = (u32)®s->txcdp[TXQ];
- writel((u32)p_txdesc, temp);
- writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd);
-
- /*
- * wait for packet xmit completion
- */
- cmd_sts = readl(&p_txdesc->cmd_sts);
- while (cmd_sts & BUF_OWNED_BY_DMA) {
- /* return fail if error is detected */
- if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) ==
- (TX_ERROR | TX_LAST_DESC)) {
- printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
- return -1;
- }
- cmd_sts = readl(&p_txdesc->cmd_sts);
- if (!(retry--)) {
- printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
- __func__);
- return -1;
- }
- }
-
- return 0;
-}
-
-static int armdfec_recv(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
- u32 cmd_sts;
- u32 timeout = 0;
- u32 temp;
-
- /* wait untill rx packet available or timeout */
- do {
- if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
- timeout++;
- } else {
- debug("ARMD100 FEC: %s time out...\n", __func__);
- return -1;
- }
- } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);
-
- if (p_rxdesc_curr->byte_cnt != 0) {
- debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
- "(cmd_sts= %08x)\n", __func__,
- (u32)p_rxdesc_curr->byte_cnt,
- (u32)p_rxdesc_curr->buf_ptr,
- (u32)p_rxdesc_curr->cmd_sts);
- }
-
- /*
- * In case received a packet without first/last bits on
- * OR the error summary bit is on,
- * the packets needs to be dropeed.
- */
- cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
-
- if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
- (RX_FIRST_DESC | RX_LAST_DESC)) {
- printf("ARMD100 FEC: (%s) Dropping packet spread on"
- " multiple descriptors\n", __func__);
- } else if (cmd_sts & RX_ERROR) {
- printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
- __func__);
- } else {
- /* !!! call higher layer processing */
- debug("ARMD100 FEC: (%s) Sending Received packet to"
- " upper layer (NetReceive)\n", __func__);
-
- /*
- * let the upper layer handle the packet, subtract offset
- * as two dummy bytes are added in received buffer see
- * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
- */
- NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
- (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
- }
- /*
- * free these descriptors and point next in the ring
- */
- p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
- p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
- p_rxdesc_curr->byte_cnt = 0;
-
- temp = (u32)&darmdfec->p_rxdesc_curr;
- writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
-
- return 0;
-}
-
-int armada100_fec_register(unsigned long base_addr)
-{
- struct armdfec_device *darmdfec;
- struct eth_device *dev;
-
- darmdfec = malloc(sizeof(struct armdfec_device));
- if (!darmdfec)
- goto error;
-
- memset(darmdfec, 0, sizeof(struct armdfec_device));
-
- darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
- if (!darmdfec->htpr)
- goto error1;
-
- darmdfec->p_rxdesc = memalign(PKTALIGN,
- ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
-
- if (!darmdfec->p_rxdesc)
- goto error1;
-
- darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
- if (!darmdfec->p_rxbuf)
- goto error1;
-
- darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
- if (!darmdfec->p_aligned_txbuf)
- goto error1;
-
- darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
- if (!darmdfec->p_txdesc)
- goto error1;
-
- dev = &darmdfec->dev;
- /* Assign ARMADA100 Fast Ethernet Controller Base Address */
- darmdfec->regs = (void *)base_addr;
-
- /* must be less than sizeof(dev->name) */
- strcpy(dev->name, "armd-fec0");
-
- dev->init = armdfec_init;
- dev->halt = armdfec_halt;
- dev->send = armdfec_send;
- dev->recv = armdfec_recv;
-
- eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- miiphy_register(dev->name, smi_reg_read, smi_reg_write);
-#endif
- return 0;
-
-error1:
- free(darmdfec->p_aligned_txbuf);
- free(darmdfec->p_rxbuf);
- free(darmdfec->p_rxdesc);
- free(darmdfec->htpr);
-error:
- free(darmdfec);
- printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
- return -1;
-}
diff --git a/drivers/net/armada100_fec.h b/drivers/net/armada100_fec.h
deleted file mode 100644
index 5a0a3d9..0000000
--- a/drivers/net/armada100_fec.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ARMADA100_FEC_H__
-#define __ARMADA100_FEC_H__
-
-#define PORT_NUM 0x0
-
-/* RX & TX descriptor command */
-#define BUF_OWNED_BY_DMA (1<<31)
-
-/* RX descriptor status */
-#define RX_EN_INT (1<<23)
-#define RX_FIRST_DESC (1<<17)
-#define RX_LAST_DESC (1<<16)
-#define RX_ERROR (1<<15)
-
-/* TX descriptor command */
-#define TX_EN_INT (1<<23)
-#define TX_GEN_CRC (1<<22)
-#define TX_ZERO_PADDING (1<<18)
-#define TX_FIRST_DESC (1<<17)
-#define TX_LAST_DESC (1<<16)
-#define TX_ERROR (1<<15)
-
-/* smi register */
-#define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */
-#define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */
-#define SMI_OP_W (0<<26) /* Write operation */
-#define SMI_OP_R (1<<26) /* Read operation */
-
-#define HASH_ADD 0
-#define HASH_DELETE 1
-#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
-#define HOP_NUMBER 12
-
-#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
-#define PHY_WAIT_MICRO_SECONDS 10
-
-#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
-#define ETH_EXTRA_HEADER (6+6+2+4)
- /* dest+src addr+protocol id+crc */
-#define MAX_PKT_SIZE 1536
-
-
-/* Bit definitions of the SDMA Config Reg */
-#define SDCR_BSZ_OFF 12
-#define SDCR_BSZ8 (3<<SDCR_BSZ_OFF)
-#define SDCR_BSZ4 (2<<SDCR_BSZ_OFF)
-#define SDCR_BSZ2 (1<<SDCR_BSZ_OFF)
-#define SDCR_BSZ1 (0<<SDCR_BSZ_OFF)
-#define SDCR_BLMR (1<<6)
-#define SDCR_BLMT (1<<7)
-#define SDCR_RIFB (1<<9)
-#define SDCR_RC_OFF 2
-#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
-
-/* SDMA_CMD */
-#define SDMA_CMD_AT (1<<31)
-#define SDMA_CMD_TXDL (1<<24)
-#define SDMA_CMD_TXDH (1<<23)
-#define SDMA_CMD_AR (1<<15)
-#define SDMA_CMD_ERD (1<<7)
-
-
-/* Bit definitions of the Port Config Reg */
-#define PCR_HS (1<<12)
-#define PCR_EN (1<<7)
-#define PCR_PM (1<<0)
-
-/* Bit definitions of the Port Config Extend Reg */
-#define PCXR_2BSM (1<<28)
-#define PCXR_DSCP_EN (1<<21)
-#define PCXR_MFL_1518 (0<<14)
-#define PCXR_MFL_1536 (1<<14)
-#define PCXR_MFL_2048 (2<<14)
-#define PCXR_MFL_64K (3<<14)
-#define PCXR_FLP (1<<11)
-#define PCXR_PRIO_TX_OFF 3
-#define PCXR_TX_HIGH_PRI (7<<PCXR_PRIO_TX_OFF)
-
-/*
- * * Bit definitions of the Interrupt Cause Reg
- * * and Interrupt MASK Reg is the same
- * */
-#define ICR_RXBUF (1<<0)
-#define ICR_TXBUF_H (1<<2)
-#define ICR_TXBUF_L (1<<3)
-#define ICR_TXEND_H (1<<6)
-#define ICR_TXEND_L (1<<7)
-#define ICR_RXERR (1<<8)
-#define ICR_TXERR_H (1<<10)
-#define ICR_TXERR_L (1<<11)
-#define ICR_TX_UDR (1<<13)
-#define ICR_MII_CH (1<<28)
-
-#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
- ICR_TXERR_H | ICR_TXERR_L |\
- ICR_TXEND_H | ICR_TXEND_L |\
- ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
-
-#define PHY_MASK 0x0000001f
-
-#define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev)
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \
- (((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN)
-
-#define RX_BUF_OFFSET 0x2
-#define RXQ 0x0 /* RX Queue 0 */
-#define TXQ 0x1 /* TX Queue 1 */
-
-struct addr_table_entry_t {
- u32 lo;
- u32 hi;
-};
-
-/* Bit fields of a Hash Table Entry */
-enum hash_table_entry {
- HTEVALID = 1,
- HTESKIP = 2,
- HTERD = 4,
- HTERDBIT = 2
-};
-
-struct tx_desc {
- u32 cmd_sts; /* Command/status field */
- u16 reserved;
- u16 byte_cnt; /* buffer byte count */
- u8 *buf_ptr; /* pointer to buffer for this descriptor */
- struct tx_desc *nextdesc_p; /* Pointer to next descriptor */
-};
-
-struct rx_desc {
- u32 cmd_sts; /* Descriptor command status */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u16 buf_size; /* Buffer size */
- u8 *buf_ptr; /* Descriptor buffer pointer */
- struct rx_desc *nxtdesc_p; /* Next descriptor pointer */
-};
-
-/*
- * Armada100 Fast Ethernet controller Registers
- * Refer Datasheet Appendix A.22
- */
-struct armdfec_reg {
- u32 phyadr; /* PHY Address */
- u32 pad1[3];
- u32 smi; /* SMI */
- u32 pad2[0xFB];
- u32 pconf; /* Port configuration */
- u32 pad3;
- u32 pconf_ext; /* Port configuration extend */
- u32 pad4;
- u32 pcmd; /* Port Command */
- u32 pad5;
- u32 pstatus; /* Port Status */
- u32 pad6;
- u32 spar; /* Serial Parameters */
- u32 pad7;
- u32 htpr; /* Hash table pointer */
- u32 pad8;
- u32 fcsal; /* Flow control source address low */
- u32 pad9;
- u32 fcsah; /* Flow control source address high */
- u32 pad10;
- u32 sdma_conf; /* SDMA configuration */
- u32 pad11;
- u32 sdma_cmd; /* SDMA command */
- u32 pad12;
- u32 ic; /* Interrupt cause */
- u32 iwc; /* Interrupt write to clear */
- u32 im; /* Interrupt mask */
- u32 pad13;
- u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code
- Point to Priority 0 Low */
- u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */
- u32 pad14[3];
- struct rx_desc *rxfdp[4]; /* Ethernet First Rx Descriptor
- Pointer */
- u32 pad15[4];
- struct rx_desc *rxcdp[4]; /* Ethernet Current Rx Descriptor
- Pointer */
- u32 pad16[0x0C];
- struct tx_desc *txcdp[2]; /* Ethernet Current Tx Descriptor
- Pointer */
-};
-
-struct armdfec_device {
- struct eth_device dev;
- struct armdfec_reg *regs;
- struct tx_desc *p_txdesc;
- struct rx_desc *p_rxdesc;
- struct rx_desc *p_rxdesc_curr;
- u8 *p_rxbuf;
- u8 *p_aligned_txbuf;
- u8 *htpr; /* hash pointer */
-};
-
-#endif /* __ARMADA100_FEC_H__ */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index edbd520..f85e95b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -18,7 +18,6 @@ endif
obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ANDES_SPI) += andes_spi.o
-obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
diff --git a/drivers/spi/armada100_spi.c b/drivers/spi/armada100_spi.c
deleted file mode 100644
index 53aaf95..0000000
--- a/drivers/spi/armada100_spi.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Based on SSP driver
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <malloc.h>
-#include <spi.h>
-
-#include <asm/io.h>
-#include <asm/arch/spi.h>
-#include <asm/gpio.h>
-
-#define to_armd_spi_slave(s) container_of(s, struct armd_spi_slave, slave)
-
-struct armd_spi_slave {
- struct spi_slave slave;
- struct ssp_reg *spi_reg;
- u32 cr0, cr1;
- u32 int_cr1;
- u32 clear_sr;
- const void *tx;
- void *rx;
- int gpio_cs_inverted;
-};
-
-static int spi_armd_write(struct armd_spi_slave *pss)
-{
- int wait_timeout = SSP_FLUSH_NUM;
- while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_TNF))
- ;
- if (!wait_timeout) {
- debug("%s: timeout error\n", __func__);
- return -1;
- }
-
- if (pss->tx != NULL) {
- writel(*(u8 *)pss->tx, &pss->spi_reg->ssdr);
- ++pss->tx;
- } else {
- writel(0, &pss->spi_reg->ssdr);
- }
- return 0;
-}
-
-static int spi_armd_read(struct armd_spi_slave *pss)
-{
- int wait_timeout = SSP_FLUSH_NUM;
- while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_RNE))
- ;
- if (!wait_timeout) {
- debug("%s: timeout error\n", __func__);
- return -1;
- }
-
- if (pss->rx != NULL) {
- *(u8 *)pss->rx = readl(&pss->spi_reg->ssdr);
- ++pss->rx;
- } else {
- readl(&pss->spi_reg->ssdr);
- }
- return 0;
-}
-
-static int spi_armd_flush(struct armd_spi_slave *pss)
-{
- unsigned long limit = SSP_FLUSH_NUM;
-
- do {
- while (readl(&pss->spi_reg->sssr) & SSSR_RNE)
- readl(&pss->spi_reg->ssdr);
- } while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--);
-
- writel(SSSR_ROR, &pss->spi_reg->sssr);
-
- return limit;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct armd_spi_slave *pss = to_armd_spi_slave(slave);
-
- gpio_set_value(slave->cs, pss->gpio_cs_inverted);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct armd_spi_slave *pss = to_armd_spi_slave(slave);
-
- gpio_set_value(slave->cs, !pss->gpio_cs_inverted);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct armd_spi_slave *pss;
-
- pss = spi_alloc_slave(struct armd_spi_slave, bus, cs);
- if (!pss)
- return NULL;
-
- pss->spi_reg = (struct ssp_reg *)SSP_REG_BASE(CONFIG_SYS_SSP_PORT);
-
- pss->cr0 = SSCR0_MOTO | SSCR0_DATASIZE(DEFAULT_WORD_LEN) | SSCR0_SSE;
-
- pss->cr1 = (SSCR1_RXTRESH(RX_THRESH_DEF) & SSCR1_RFT) |
- (SSCR1_TXTRESH(TX_THRESH_DEF) & SSCR1_TFT);
- pss->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
- pss->cr1 |= (((mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
- | (((mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
-
- pss->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
- pss->clear_sr = SSSR_ROR | SSSR_TINT;
-
- pss->gpio_cs_inverted = mode & SPI_CS_HIGH;
- gpio_set_value(cs, !pss->gpio_cs_inverted);
-
- return &pss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct armd_spi_slave *pss = to_armd_spi_slave(slave);
-
- free(pss);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct armd_spi_slave *pss = to_armd_spi_slave(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- if (spi_armd_flush(pss) == 0)
- return -1;
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct armd_spi_slave *pss = to_armd_spi_slave(slave);
- uint bytes = bitlen / 8;
- unsigned long limit;
- int ret = 0;
-
- if (bitlen == 0)
- goto done;
-
- /* we can only do 8 bit transfers */
- if (bitlen % 8) {
- flags |= SPI_XFER_END;
- goto done;
- }
-
- pss->tx = dout;
- pss->rx = din;
-
- if (flags & SPI_XFER_BEGIN) {
- spi_cs_activate(slave);
- writel(pss->cr1 | pss->int_cr1, &pss->spi_reg->sscr1);
- writel(TIMEOUT_DEF, &pss->spi_reg->ssto);
- writel(pss->cr0, &pss->spi_reg->sscr0);
- }
-
- while (bytes--) {
- limit = SSP_FLUSH_NUM;
- ret = spi_armd_write(pss);
- if (ret)
- break;
-
- while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--)
- udelay(1);
-
- ret = spi_armd_read(pss);
- if (ret)
- break;
- }
-
- done:
- if (flags & SPI_XFER_END) {
- /* Stop SSP */
- writel(pss->clear_sr, &pss->spi_reg->sssr);
- clrbits_le32(&pss->spi_reg->sscr1, pss->int_cr1);
- writel(0, &pss->spi_reg->ssto);
- spi_cs_deactivate(slave);
- }
-
- return ret;
-}
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index c11b551..c1e7953 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -17,7 +17,6 @@ obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
# echi
obj-$(CONFIG_USB_EHCI) += ehci-hcd.o
-obj-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o
obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o
ifdef CONFIG_MPC512X
obj-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
diff --git a/drivers/usb/host/ehci-armada100.c b/drivers/usb/host/ehci-armada100.c
deleted file mode 100644
index 012eb3a..0000000
--- a/drivers/usb/host/ehci-armada100.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2012
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
- *
- * This driver is based on Kirkwood echi driver
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <usb.h>
-#include "ehci.h"
-#include <asm/arch/cpu.h>
-#include <asm/arch/armada100.h>
-#include <asm/arch/utmi-armada100.h>
-
-/*
- * EHCI host controller init
- */
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- if (utmi_init() < 0)
- return -1;
-
- *hccr = (struct ehci_hccr *)(ARMD1_USB_HOST_BASE + 0x100);
- *hcor = (struct ehci_hcor *)((uint32_t) *hccr
- + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
- debug("armada100-ehci: init hccr %x and hcor %x hc_length %d\n",
- (uint32_t)*hccr, (uint32_t)*hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
- return 0;
-}
-
-/*
- * EHCI host controller stop
- */
-int ehci_hcd_stop(int index)
-{
- return 0;
-}
diff --git a/drivers/usb/host/utmi-armada100.c b/drivers/usb/host/utmi-armada100.c
deleted file mode 100644
index 1e87828..0000000
--- a/drivers/usb/host/utmi-armada100.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * (C) Copyright 2012
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <usb.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/armada100.h>
-#include <asm/arch/utmi-armada100.h>
-
-static int utmi_phy_init(void)
-{
- struct armd1usb_phy_reg *phy_regs =
- (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
- int timeout;
-
- setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
- udelay(1000);
- setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
-
- clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
- setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
-
- setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
-
- /* Calibrate pll */
- timeout = 10000;
- while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
- ;
- if (!timeout)
- return -1;
-
- udelay(200);
- setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
- udelay(400);
- clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
-
- udelay(200);
- setbits_le32(&phy_regs->utmi_tx, RCAL_START);
- udelay(400);
- clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
-
- timeout = 10000;
- while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
- ;
- if (!timeout)
- return -1;
-
- return 0;
-}
-
-/*
- * Initialize USB host controller's UTMI Physical interface
- */
-int utmi_init(void)
-{
- struct armd1mpmu_registers *mpmu_regs =
- (struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
-
- struct armd1apmu_registers *apmu_regs =
- (struct armd1apmu_registers *)ARMD1_APMU_BASE;
-
- /* Turn on 26Mhz ref clock for UTMI PLL */
- setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
-
- /* USB Clock reset */
- writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
- writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
-
- /* Initialize UTMI transceiver */
- return utmi_phy_init();
-}
diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h
deleted file mode 100644
index 727b14a..0000000
--- a/include/configs/aspenite.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_ASPENITE_H
-#define __CONFIG_ASPENITE_H
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-Aspenite DB"
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
-#define CONFIG_ARMADA100 1 /* SOC Family Name */
-#define CONFIG_ARMADA168 1 /* SOC Used on this Board */
-#define CONFIG_MACH_ASPENITE /* Machine type */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * There is no internal RAM in ARMADA100, using DRAM
- * TBD: dcache to be used for this
- */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
-#define CONFIG_NR_DRAM_BANKS_MAX 2
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_I2C
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-#undef CONFIG_ARCH_MISC_INIT
-
-/*
- * Environment variables configurations
- */
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
-#define CONFIG_ENV_SIZE 0x20000 /* 64k */
-
-#endif /* __CONFIG_ASPENITE_H */
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
deleted file mode 100644
index 404c56a..0000000
--- a/include/configs/gplugd.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
- *
- * Based on Aspenite:
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_GPLUGD_H
-#define __CONFIG_GPLUGD_H
-
-/*
- * FIXME: fix for error caused due to recent update to mach-types.h
- */
-#include <asm/mach-types.h>
-#ifdef MACH_TYPE_SHEEVAD
-#error "MACH_TYPE_SHEEVAD has been defined properly, please remove this."
-#else
-#define MACH_TYPE_SHEEVAD 2625
-#endif
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-gplugD"
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
-#define CONFIG_ARMADA100 1 /* SOC Family Name */
-#define CONFIG_ARMADA168 1 /* SOC Used on this Board */
-#define CONFIG_MACH_TYPE MACH_TYPE_SHEEVAD /* Machine type */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-#define CONFIG_SYS_TEXT_BASE 0x00f00000
-
-/*
- * There is no internal RAM in ARMADA100, using DRAM
- * TBD: dcache to be used for this
- */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
-#define CONFIG_NR_DRAM_BANKS_MAX 2
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_I2C
-#undef CONFIG_CMD_FPGA
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
-/* Disable DCACHE */
-#define CONFIG_SYS_DCACHE_OFF
-
-/* Network configuration */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_ARMADA100_FEC
-
-/* DHCP Support */
-#define CONFIG_CMD_DHCP
-#define CONFIG_BOOTP_DHCP_REQUEST_DELAY 50000
-#endif /* CONFIG_CMD_NET */
-
-/* GPIO Support */
-#define CONFIG_MARVELL_GPIO
-
-/* PHY configuration */
-#define CONFIG_MII
-#define CONFIG_CMD_MII
-#define CONFIG_RESET_PHY_R
-/* 88E3015 register definition */
-#define PHY_LED_PAR_SEL_REG 22
-#define PHY_LED_MAN_REG 25
-#define PHY_LED_VAL 0x5b /* LINK LED1, ACT LED2 */
-/* GPIO Configuration for PHY */
-#define CONFIG_SYS_GPIO_PHY_RST 104 /* GPIO104 */
-
-/* SPI Support */
-#define CONFIG_ARMADA100_SPI
-#define CONFIG_ENV_SPI_CS 110
-#define CONFIG_SYS_SSP_PORT 2
-
-/* Flash Support */
-#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_ATMEL
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-#undef CONFIG_ARCH_MISC_INIT
-
-#ifdef CONFIG_SYS_NS16550_COM1
-#undef CONFIG_SYS_NS16550_COM1
-#endif /* CONFIG_SYS_NS16550_COM1 */
-
-#define CONFIG_SYS_NS16550_COM1 ARMD1_UART3_BASE
-
-/*
- * Environment variables configurations
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x4000
-#define CONFIG_ENV_SIZE 0x4000
-#define CONFIG_ENV_OFFSET 0x07C000
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_EDITENV
-#define CONFIG_CMD_SAVEENV
-
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_ARMADA100
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#endif /* CONFIG_CMD_USB */
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_SUPPORT_VFAT
-
-#endif /* __CONFIG_GPLUGD_H */
diff --git a/include/netdev.h b/include/netdev.h
index 90140bd..b2bd7c3 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -83,7 +83,6 @@ int sunxi_gmac_initialize(bd_t *bis);
int tsi108_eth_initialize(bd_t *bis);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
-int armada100_fec_register(unsigned long base_addr);
int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
unsigned long dma_addr);
int xilinx_emaclite_of_init(const void *blob);
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 10/11] ARM: remove tnetv107x board support
2015-02-10 4:44 [U-Boot] [PATCH 0/11] ARM: remove non-generic boards Masahiro Yamada
` (8 preceding siblings ...)
2015-02-10 4:44 ` [U-Boot] [PATCH 09/11] ARM: armada100: remove aspenite and gplugd " Masahiro Yamada
@ 2015-02-10 4:44 ` Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 11/11] ARM: davinci: remove hawkboard support Masahiro Yamada
10 siblings, 0 replies; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 4:44 UTC (permalink / raw)
To: u-boot
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chan-Taek Park <c-park@ti.com>
---
arch/arm/Kconfig | 5 -
arch/arm/cpu/arm1176/Makefile | 1 -
arch/arm/cpu/arm1176/start.S | 22 --
arch/arm/cpu/arm1176/tnetv107x/Makefile | 6 -
arch/arm/cpu/arm1176/tnetv107x/aemif.c | 78 -----
arch/arm/cpu/arm1176/tnetv107x/clock.c | 432 -------------------------
arch/arm/cpu/arm1176/tnetv107x/init.c | 22 --
arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S | 10 -
arch/arm/cpu/arm1176/tnetv107x/mux.c | 319 ------------------
arch/arm/cpu/arm1176/tnetv107x/timer.c | 93 ------
arch/arm/include/asm/arch-tnetv107x/clock.h | 53 ---
arch/arm/include/asm/arch-tnetv107x/hardware.h | 160 ---------
arch/arm/include/asm/arch-tnetv107x/mux.h | 291 -----------------
board/ti/tnetv107xevm/Kconfig | 15 -
board/ti/tnetv107xevm/MAINTAINERS | 6 -
board/ti/tnetv107xevm/Makefile | 5 -
board/ti/tnetv107xevm/config.mk | 5 -
board/ti/tnetv107xevm/sdb_board.c | 134 --------
configs/tnetv107x_evm_defconfig | 2 -
doc/README.scrapyard | 1 +
drivers/watchdog/Makefile | 1 -
drivers/watchdog/tnetv107x_wdt.c | 165 ----------
include/configs/tnetv107x_evm.h | 139 --------
23 files changed, 1 insertion(+), 1964 deletions(-)
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/Makefile
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/aemif.c
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/clock.c
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/init.c
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/mux.c
delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/timer.c
delete mode 100644 arch/arm/include/asm/arch-tnetv107x/clock.h
delete mode 100644 arch/arm/include/asm/arch-tnetv107x/hardware.h
delete mode 100644 arch/arm/include/asm/arch-tnetv107x/mux.h
delete mode 100644 board/ti/tnetv107xevm/Kconfig
delete mode 100644 board/ti/tnetv107xevm/MAINTAINERS
delete mode 100644 board/ti/tnetv107xevm/Makefile
delete mode 100644 board/ti/tnetv107xevm/config.mk
delete mode 100644 board/ti/tnetv107xevm/sdb_board.c
delete mode 100644 configs/tnetv107x_evm_defconfig
delete mode 100644 drivers/watchdog/tnetv107x_wdt.c
delete mode 100644 include/configs/tnetv107x_evm.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 702302f..48d6964 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -367,10 +367,6 @@ config TARGET_RPI
bool "Support rpi"
select CPU_ARM1176
-config TARGET_TNETV107X_EVM
- bool "Support tnetv107x_evm"
- select CPU_ARM1176
-
config TARGET_INTEGRATORAP_CM946ES
bool "Support integratorap_cm946es"
select CPU_ARM946ES
@@ -933,7 +929,6 @@ source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
-source "board/ti/tnetv107xevm/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/trizepsiv/Kconfig"
diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile
index ead2303..480e130 100644
--- a/arch/arm/cpu/arm1176/Makefile
+++ b/arch/arm/cpu/arm1176/Makefile
@@ -12,4 +12,3 @@ extra-y = start.o
obj-y = cpu.o
obj-$(CONFIG_BCM2835) += bcm2835/
-obj-$(CONFIG_TNETV107X) += tnetv107x/
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 0704bdd..ac937bf 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -96,28 +96,6 @@ mmu_disable:
mov pc, r2
mmu_disable_phys:
-#ifdef CONFIG_DISABLE_TCM
- /*
- * Disable the TCMs
- */
- mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
- cmp r0, #0
- beq skip_tcmdisable
- mov r1, #0
- mov r2, #1
- tst r0, r2
- mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
- tst r0, r2, LSL #16
- mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
-skip_tcmdisable:
-#endif
-#endif
-
-#ifdef CONFIG_PERIPORT_REMAP
- /* Peri port setup */
- ldr r0, =CONFIG_PERIPORT_BASE
- orr r0, r0, #CONFIG_PERIPORT_SIZE
- mcr p15,0,r0,c15,c2,4
#endif
/*
diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile
deleted file mode 100644
index a4c1edf..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += aemif.o clock.o init.o mux.o timer.o
-obj-y += lowlevel_init.o
diff --git a/arch/arm/cpu/arm1176/tnetv107x/aemif.c b/arch/arm/cpu/arm1176/tnetv107x/aemif.c
deleted file mode 100644
index a0f5728..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/aemif.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * TNETV107X: Asynchronous EMIF Configuration
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define ASYNC_EMIF_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
-#define ASYNC_EMIF_CONFIG(cs) (ASYNC_EMIF_BASE+0x10+(cs)*4)
-#define ASYNC_EMIF_ONENAND_CONTROL (ASYNC_EMIF_BASE+0x5c)
-#define ASYNC_EMIF_NAND_CONTROL (ASYNC_EMIF_BASE+0x60)
-#define ASYNC_EMIF_WAITCYCLE_CONFIG (ASYNC_EMIF_BASE+0x4)
-
-#define CONFIG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
-#define CONFIG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
-#define CONFIG_WR_SETUP(v) (((v) & 0x0f) << 26)
-#define CONFIG_WR_STROBE(v) (((v) & 0x3f) << 20)
-#define CONFIG_WR_HOLD(v) (((v) & 0x07) << 17)
-#define CONFIG_RD_SETUP(v) (((v) & 0x0f) << 13)
-#define CONFIG_RD_STROBE(v) (((v) & 0x3f) << 7)
-#define CONFIG_RD_HOLD(v) (((v) & 0x07) << 4)
-#define CONFIG_TURN_AROUND(v) (((v) & 0x03) << 2)
-#define CONFIG_WIDTH(v) (((v) & 0x03) << 0)
-
-#define NUM_CS 4
-
-#define set_config_field(reg, field, val) \
- do { \
- if (val != -1) { \
- reg &= ~CONFIG_##field(0xffffffff); \
- reg |= CONFIG_##field(val); \
- } \
- } while (0)
-
-void configure_async_emif(int cs, struct async_emif_config *cfg)
-{
- unsigned long tmp;
-
- if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
- tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
- tmp |= (1 << cs);
- __raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
-
- } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
- tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
- tmp |= (1 << cs);
- __raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
- }
-
- tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
-
- set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
- set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
- set_config_field(tmp, WR_SETUP, cfg->wr_setup);
- set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
- set_config_field(tmp, WR_HOLD, cfg->wr_hold);
- set_config_field(tmp, RD_SETUP, cfg->rd_setup);
- set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
- set_config_field(tmp, RD_HOLD, cfg->rd_hold);
- set_config_field(tmp, TURN_AROUND, cfg->turn_around);
- set_config_field(tmp, WIDTH, cfg->width);
-
- __raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
-}
-
-void init_async_emif(int num_cs, struct async_emif_config *config)
-{
- int cs;
-
- clk_enable(TNETV107X_LPSC_AEMIF);
-
- for (cs = 0; cs < num_cs; cs++)
- configure_async_emif(cs, config + cs);
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c
deleted file mode 100644
index 7ba28d3..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/clock.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * TNETV107X: Clock management APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/arch/clock.h>
-
-#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE
-#define PSC_BASE TNETV107X_PSC_BASE
-
-#define BIT(x) (1 << (x))
-
-#define MAX_PREDIV 64
-#define MAX_POSTDIV 8UL
-#define MAX_MULT 512
-#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV)
-
-/* LPSC registers */
-#define PSC_PTCMD 0x120
-#define PSC_PTSTAT 0x128
-#define PSC_MDSTAT(n) (0x800 + (n) * 4)
-#define PSC_MDCTL(n) (0xA00 + (n) * 4)
-
-#define PSC_MDCTL_LRSTZ BIT(8)
-
-#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg)))
-#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg)))
-
-/* SSPLL registers */
-struct sspll_regs {
- u32 modes;
- u32 postdiv;
- u32 prediv;
- u32 mult_factor;
- u32 divider_range;
- u32 bw_divider;
- u32 spr_amount;
- u32 spr_rate_div;
- u32 diag;
-};
-
-/* SSPLL base addresses */
-static struct sspll_regs *sspll_regs[] = {
- (struct sspll_regs *)(CLOCK_BASE + 0x040),
- (struct sspll_regs *)(CLOCK_BASE + 0x080),
- (struct sspll_regs *)(CLOCK_BASE + 0x0c0),
-};
-
-#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg))
-#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg))
-#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg))
-
-
-/* PLL Control Registers */
-struct pllctl_regs {
- u32 ctl; /* 00 */
- u32 ocsel; /* 04 */
- u32 secctl; /* 08 */
- u32 __pad0;
- u32 mult; /* 10 */
- u32 prediv; /* 14 */
- u32 div1; /* 18 */
- u32 div2; /* 1c */
- u32 div3; /* 20 */
- u32 oscdiv1; /* 24 */
- u32 postdiv; /* 28 */
- u32 bpdiv; /* 2c */
- u32 wakeup; /* 30 */
- u32 __pad1;
- u32 cmd; /* 38 */
- u32 stat; /* 3c */
- u32 alnctl; /* 40 */
- u32 dchange; /* 44 */
- u32 cken; /* 48 */
- u32 ckstat; /* 4c */
- u32 systat; /* 50 */
- u32 ckctl; /* 54 */
- u32 __pad2[2];
- u32 div4; /* 60 */
- u32 div5; /* 64 */
- u32 div6; /* 68 */
- u32 div7; /* 6c */
- u32 div8; /* 70 */
-};
-
-struct lpsc_map {
- int pll, div;
-};
-
-static struct pllctl_regs *pllctl_regs[] = {
- (struct pllctl_regs *)(CLOCK_BASE + 0x700),
- (struct pllctl_regs *)(CLOCK_BASE + 0x300),
- (struct pllctl_regs *)(CLOCK_BASE + 0x500),
-};
-
-#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
-#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
-#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
-
-#define pllctl_reg_rmw(pll, reg, mask, val) \
- pllctl_reg_write(pll, reg, \
- (pllctl_reg_read(pll, reg) & ~(mask)) | val)
-
-#define pllctl_reg_setbits(pll, reg, mask) \
- pllctl_reg_rmw(pll, reg, 0, mask)
-
-#define pllctl_reg_clrbits(pll, reg, mask) \
- pllctl_reg_rmw(pll, reg, mask, 0)
-
-/* PLLCTL Bits */
-#define PLLCTL_CLKMODE BIT(8)
-#define PLLCTL_PLLSELB BIT(7)
-#define PLLCTL_PLLENSRC BIT(5)
-#define PLLCTL_PLLDIS BIT(4)
-#define PLLCTL_PLLRST BIT(3)
-#define PLLCTL_PLLPWRDN BIT(1)
-#define PLLCTL_PLLEN BIT(0)
-
-#define PLLDIV_ENABLE BIT(15)
-
-static int pll_div_offset[] = {
-#define div_offset(reg) offsetof(struct pllctl_regs, reg)
- div_offset(div1), div_offset(div2), div_offset(div3),
- div_offset(div4), div_offset(div5), div_offset(div6),
- div_offset(div7), div_offset(div8),
-};
-
-static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
-static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
-
-/* Mappings from PLL+DIV to subsystem clocks */
-#define sys_arm1176_clk {SYS_PLL, 0}
-#define sys_dsp_clk {SYS_PLL, 1}
-#define sys_ddr_clk {SYS_PLL, 2}
-#define sys_full_clk {SYS_PLL, 3}
-#define sys_lcd_clk {SYS_PLL, 4}
-#define sys_vlynq_ref_clk {SYS_PLL, 5}
-#define sys_tsc_clk {SYS_PLL, 6}
-#define sys_half_clk {SYS_PLL, 7}
-
-#define eth_clk_5 {ETH_PLL, 0}
-#define eth_clk_50 {ETH_PLL, 1}
-#define eth_clk_125 {ETH_PLL, 2}
-#define eth_clk_250 {ETH_PLL, 3}
-#define eth_clk_25 {ETH_PLL, 4}
-
-#define tdm_clk {TDM_PLL, 0}
-#define tdm_extra_clk {TDM_PLL, 1}
-#define tdm1_clk {TDM_PLL, 2}
-
-static const struct lpsc_map lpsc_clk_map[] = {
- [TNETV107X_LPSC_ARM] = sys_arm1176_clk,
- [TNETV107X_LPSC_GEM] = sys_dsp_clk,
- [TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk,
- [TNETV107X_LPSC_TPCC] = sys_full_clk,
- [TNETV107X_LPSC_TPTC0] = sys_full_clk,
- [TNETV107X_LPSC_TPTC1] = sys_full_clk,
- [TNETV107X_LPSC_RAM] = sys_full_clk,
- [TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk,
- [TNETV107X_LPSC_LCD] = sys_lcd_clk,
- [TNETV107X_LPSC_ETHSS] = eth_clk_125,
- [TNETV107X_LPSC_AEMIF] = sys_full_clk,
- [TNETV107X_LPSC_CHIP_CFG] = sys_half_clk,
- [TNETV107X_LPSC_TSC] = sys_tsc_clk,
- [TNETV107X_LPSC_ROM] = sys_half_clk,
- [TNETV107X_LPSC_UART2] = sys_half_clk,
- [TNETV107X_LPSC_PKTSEC] = sys_half_clk,
- [TNETV107X_LPSC_SECCTL] = sys_half_clk,
- [TNETV107X_LPSC_KEYMGR] = sys_half_clk,
- [TNETV107X_LPSC_KEYPAD] = sys_half_clk,
- [TNETV107X_LPSC_GPIO] = sys_half_clk,
- [TNETV107X_LPSC_MDIO] = sys_half_clk,
- [TNETV107X_LPSC_SDIO0] = sys_half_clk,
- [TNETV107X_LPSC_UART0] = sys_half_clk,
- [TNETV107X_LPSC_UART1] = sys_half_clk,
- [TNETV107X_LPSC_TIMER0] = sys_half_clk,
- [TNETV107X_LPSC_TIMER1] = sys_half_clk,
- [TNETV107X_LPSC_WDT_ARM] = sys_half_clk,
- [TNETV107X_LPSC_WDT_DSP] = sys_half_clk,
- [TNETV107X_LPSC_SSP] = sys_half_clk,
- [TNETV107X_LPSC_TDM0] = tdm_clk,
- [TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk,
- [TNETV107X_LPSC_MCDMA] = sys_half_clk,
- [TNETV107X_LPSC_USB0] = sys_half_clk,
- [TNETV107X_LPSC_TDM1] = tdm1_clk,
- [TNETV107X_LPSC_DEBUGSS] = sys_half_clk,
- [TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250,
- [TNETV107X_LPSC_SYSTEM] = sys_half_clk,
- [TNETV107X_LPSC_IMCOP] = sys_dsp_clk,
- [TNETV107X_LPSC_SPARE] = sys_half_clk,
- [TNETV107X_LPSC_SDIO1] = sys_half_clk,
- [TNETV107X_LPSC_USB1] = sys_half_clk,
- [TNETV107X_LPSC_USBSS] = sys_half_clk,
- [TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk,
- [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk,
-};
-
-static const unsigned long pll_ext_freq[] = {
- [SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
- [ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
- [TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
-};
-
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, postdiv = 1;
- unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
- unsigned long ret;
- u32 bypass;
-
- bypass = __raw_readl((u32 *)(CLOCK_BASE));
- if (!(bypass & pll_bypass_mask[pll])) {
- mult = sspll_reg_read(pll, mult_factor);
- prediv = sspll_reg_read(pll, prediv) + 1;
- postdiv = sspll_reg_read(pll, postdiv) + 1;
- }
-
- if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
- ref = pll_ext_freq[pll];
-
- if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
- return ref;
-
- ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
- ret /= (prediv * postdiv);
-
- return ret;
-}
-
-static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
- int div)
-{
- int divider = 1;
- unsigned long divreg;
-
- divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
-
- if (divreg & PLLDIV_ENABLE)
- divider = (divreg & pll_div_mask[pll]) + 1;
-
- return fpll / divider;
-}
-
-static unsigned long pll_div_freq_get(int pll, int div)
-{
- unsigned int fpll = pll_freq_get(pll);
-
- return __pll_div_freq_get(pll, fpll, div);
-}
-
-static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
- unsigned long hz)
-{
- int divider = (fpll / hz - 1);
-
- divider &= pll_div_mask[pll];
- divider |= PLLDIV_ENABLE;
-
- __raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
- pllctl_reg_setbits(pll, alnctl, (1 << div));
- pllctl_reg_setbits(pll, dchange, (1 << div));
-}
-
-static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
-{
- unsigned int fpll = pll_freq_get(pll);
-
- __pll_div_freq_set(pll, fpll, div, hz);
-
- pllctl_reg_write(pll, cmd, 1);
-
- /* Wait until new divider takes effect */
- while (pllctl_reg_read(pll, stat) & 0x01);
-
- return __pll_div_freq_get(pll, fpll, div);
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
-}
-
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
-{
- unsigned long fpll, divider, pll;
-
- pll = lpsc_clk_map[clk].pll;
- fpll = pll_freq_get(pll);
- divider = (fpll / hz - 1);
- divider &= pll_div_mask[pll];
-
- return fpll / (divider + 1);
-}
-
-int clk_set_rate(unsigned int clk, unsigned long _hz)
-{
- unsigned long hz;
-
- hz = clk_round_rate(clk, _hz);
- if (hz != _hz)
- return -EINVAL; /* Cannot set to target freq */
-
- pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
- return 0;
-}
-
-void lpsc_control(int mod, unsigned long state, int lrstz)
-{
- u32 mdctl;
-
- mdctl = psc_reg_read(PSC_MDCTL(mod));
- mdctl &= ~0x1f;
- mdctl |= state;
-
- if (lrstz == 0)
- mdctl &= ~PSC_MDCTL_LRSTZ;
- else if (lrstz == 1)
- mdctl |= PSC_MDCTL_LRSTZ;
-
- psc_reg_write(PSC_MDCTL(mod), mdctl);
-
- psc_reg_write(PSC_PTCMD, 1);
-
- /* wait for power domain transition to end */
- while (psc_reg_read(PSC_PTSTAT) & 1);
-
- /* Wait for module state change */
- while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
-}
-
-int lpsc_status(unsigned int id)
-{
- return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
-}
-
-static void init_pll(const struct pll_init_data *data)
-{
- unsigned long fpll;
- unsigned long best_pre = 0, best_post = 0, best_mult = 0;
- unsigned long div, prediv, postdiv, mult;
- unsigned long delta, actual;
- long best_delta = -1;
- int i;
- u32 tmp;
-
- if (data->pll == SYS_PLL)
- return; /* cannot reconfigure system pll on the fly */
-
- tmp = pllctl_reg_read(data->pll, ctl);
- if (data->internal_osc) {
- tmp &= ~PLLCTL_CLKMODE;
- fpll = CONFIG_SYS_INT_OSC_FREQ;
- } else {
- tmp |= PLLCTL_CLKMODE;
- fpll = pll_ext_freq[data->pll];
- }
- pllctl_reg_write(data->pll, ctl, tmp);
-
- mult = data->pll_freq / fpll;
- for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) {
- div = (fpll * mult) / data->pll_freq;
- if (div < 1 || div > MAX_DIV)
- continue;
-
- for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
- prediv = div / postdiv;
- if (prediv < 1 || prediv > MAX_PREDIV)
- continue;
-
- actual = (fpll / prediv) * (mult / postdiv);
- delta = (actual - data->pll_freq);
- if (delta < 0)
- delta = -delta;
- if ((delta < best_delta) || (best_delta == -1)) {
- best_delta = delta;
- best_mult = mult;
- best_pre = prediv;
- best_post = postdiv;
- if (delta == 0)
- goto done;
- }
- }
- }
-done:
-
- if (best_delta == -1) {
- printf("pll cannot derive %lu from %lu\n",
- data->pll_freq, fpll);
- return;
- }
-
- fpll = fpll * best_mult;
- fpll /= best_pre * best_post;
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
-
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
-
- sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8);
- sspll_reg_write(data->pll, prediv, best_pre - 1);
- sspll_reg_write(data->pll, postdiv, best_post - 1);
-
- for (i = 0; i < 10; i++)
- if (data->div_freq[i])
- __pll_div_freq_set(data->pll, fpll, i,
- data->div_freq[i]);
-
- pllctl_reg_write(data->pll, cmd, 1);
-
- /* Wait until pll "go" operation completes */
- while (pllctl_reg_read(data->pll, stat) & 0x01);
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
-}
-
-void init_plls(int num_pll, struct pll_init_data *config)
-{
- int i;
-
- for (i = 0; i < num_pll; i++)
- init_pll(&config[i]);
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/init.c b/arch/arm/cpu/arm1176/tnetv107x/init.c
deleted file mode 100644
index d870826..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/init.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * TNETV107X: Architecture initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-void chip_configuration_unlock(void)
-{
- __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
- __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
-}
-
-int arch_cpu_init(void)
-{
- icache_enable();
- chip_configuration_unlock();
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
deleted file mode 100644
index a8bce47..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * TNETV107X: Low-level pre-relocation initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.globl lowlevel_init
-lowlevel_init:
- /* nothing for now, maybe needed for more exotic boot modes */
- mov pc, lr
diff --git a/arch/arm/cpu/arm1176/tnetv107x/mux.c b/arch/arm/cpu/arm1176/tnetv107x/mux.c
deleted file mode 100644
index 310d84d..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/mux.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * TNETV107X: Pinmux configuration
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define MUX_MODE_1 0x00
-#define MUX_MODE_2 0x04
-#define MUX_MODE_3 0x0c
-#define MUX_MODE_4 0x1c
-
-#define MUX_DEBUG 0
-
-static const struct pin_config pin_table[] = {
- /* reg shift mode */
- TNETV107X_MUX_CFG(0, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 20, MUX_MODE_3),
- TNETV107X_MUX_CFG(4, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(7, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(7, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(8, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(10, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(11, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(11, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(15, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(15, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(16, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(19, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(20, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 20, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 25, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(26, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 25, MUX_MODE_2),
-};
-
-const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
-
-int mux_select_pin(short index)
-{
- const struct pin_config *cfg;
- unsigned long mask, mode, reg;
-
- if (index >= pin_table_size)
- return 0;
-
- cfg = &pin_table[index];
-
- mask = 0x1f << cfg->mask_offset;
- mode = cfg->mode << cfg->mask_offset;
-
- reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
- reg = (reg & ~mask) | mode;
- __raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
-
- return 1;
-}
-
-int mux_select_pins(const short *pins)
-{
- int i, ret = 1;
-
- for (i = 0; pins[i] >= 0; i++)
- ret &= mux_select_pin(pins[i]);
-
- return ret;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/timer.c b/arch/arm/cpu/arm1176/tnetv107x/timer.c
deleted file mode 100644
index 6e0dd0d..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/timer.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * TNETV107X: Timer implementation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-struct timer_regs {
- u_int32_t pid12;
- u_int32_t pad[3];
- u_int32_t tim12;
- u_int32_t tim34;
- u_int32_t prd12;
- u_int32_t prd34;
- u_int32_t tcr;
- u_int32_t tgcr;
- u_int32_t wdtcr;
-};
-
-#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
-
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV 16
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
- clk_enable(TNETV107X_LPSC_TIMER0);
-
- lastinc = timestamp = 0;
-
- /* We are using timer34 in unchained 32-bit mode, full speed */
- __raw_writel(0x0, ®s->tcr);
- __raw_writel(0x0, ®s->tgcr);
- __raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), ®s->tgcr);
- __raw_writel(0x0, ®s->tim34);
- __raw_writel(TIMER_LOAD_VAL, ®s->prd34);
- __raw_writel(2 << 22, ®s->tcr);
-
- return 0;
-}
-
-static ulong get_timer_raw(void)
-{
- ulong now = __raw_readl(®s->tim34);
-
- if (now >= lastinc)
- timestamp += now - lastinc;
- else
- timestamp += now + TIMER_LOAD_VAL - lastinc;
-
- lastinc = now;
-
- return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
- return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-void __udelay(unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- tmo = CONFIG_SYS_HZ_CLOCK / 1000;
- tmo *= usec;
- tmo /= (1000 * TIM_CLK_DIV);
-
- endtime = get_timer_raw() + tmo;
-
- do {
- ulong now = get_timer_raw();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/include/asm/arch-tnetv107x/clock.h b/arch/arm/include/asm/arch-tnetv107x/clock.h
deleted file mode 100644
index dfc3b1b..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/clock.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * TNETV107X: Clock APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0
-#define PSC_MDCTL_NEXT_SYNCRST 0x1
-#define PSC_MDCTL_NEXT_DISABLE 0x2
-#define PSC_MDCTL_NEXT_ENABLE 0x3
-
-#define CONFIG_SYS_INT_OSC_FREQ 24000000
-
-#ifndef __ASSEMBLY__
-
-/* PLL identifiers */
-enum pll_type_e {
- SYS_PLL,
- TDM_PLL,
- ETH_PLL
-};
-
-/* PLL configuration data */
-struct pll_init_data {
- int pll;
- int internal_osc;
- unsigned long pll_freq;
- unsigned long div_freq[10];
-};
-
-void init_plls(int num_pll, struct pll_init_data *config);
-int lpsc_status(unsigned int mod);
-void lpsc_control(int mod, unsigned long state, int lrstz);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
-
-static inline void clk_enable(unsigned int mod)
-{
- lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
-}
-
-static inline void clk_disable(unsigned int mod)
-{
- lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
-}
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h
deleted file mode 100644
index d458e0b..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/hardware.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * TNETV107X: Hardware information
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/sizes.h>
-
-#define ASYNC_EMIF_NUM_CS 4
-#define ASYNC_EMIF_MODE_NOR 0
-#define ASYNC_EMIF_MODE_NAND 1
-#define ASYNC_EMIF_MODE_ONENAND 2
-#define ASYNC_EMIF_PRESERVE -1
-
-struct async_emif_config {
- unsigned mode;
- unsigned select_strobe;
- unsigned extend_wait;
- unsigned wr_setup;
- unsigned wr_strobe;
- unsigned wr_hold;
- unsigned rd_setup;
- unsigned rd_strobe;
- unsigned rd_hold;
- unsigned turn_around;
- enum {
- ASYNC_EMIF_8 = 0,
- ASYNC_EMIF_16 = 1,
- ASYNC_EMIF_32 = 2,
- } width;
-};
-
-void init_async_emif(int num_cs, struct async_emif_config *config);
-
-int wdt_start(unsigned long msecs);
-int wdt_stop(void);
-int wdt_kick(void);
-
-#endif
-
-/* Chip configuration unlock codes and registers */
-#define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
-#define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
-#define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
-#define TNETV107X_KICK0_MAGIC 0x83e70b13
-#define TNETV107X_KICK1_MAGIC 0x95a4f1e0
-
-/* Module base addresses */
-#define TNETV107X_TPCC_BASE 0x01C00000
-#define TNETV107X_TPTC0_BASE 0x01C10000
-#define TNETV107X_TPTC1_BASE 0x01C10400
-#define TNETV107X_INTC_BASE 0x03000000
-#define TNETV107X_LCD_CONTROLLER_BASE 0x08030000
-#define TNETV107X_INTD_BASE 0x08038000
-#define TNETV107X_INTD_IPC_BASE 0x08038000
-#define TNETV107X_INTD_FAST_BASE 0x08039000
-#define TNETV107X_INTD_ASYNC_BASE 0x0803A000
-#define TNETV107X_INTD_SLOW_BASE 0x0803B000
-#define TNETV107X_PKA_BASE 0x08040000
-#define TNETV107X_RNG_BASE 0x08044000
-#define TNETV107X_TIMER0_BASE 0x08086500
-#define TNETV107X_TIMER1_BASE 0x08086600
-#define TNETV107X_WDT0_ARM_BASE 0x08086700
-#define TNETV107X_WDT1_DSP_BASE 0x08086800
-#define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000
-#define TNETV107X_GPIO_BASE 0x08088000
-#define TNETV107X_UART1_BASE 0x08088400
-#define TNETV107X_TOUCHSCREEN_BASE 0x08088500
-#define TNETV107X_SDIO0_BASE 0x08088700
-#define TNETV107X_SDIO1_BASE 0x08088800
-#define TNETV107X_MDIO_BASE 0x08088900
-#define TNETV107X_KEYPAD_BASE 0x08088A00
-#define TNETV107X_SSP_BASE 0x08088C00
-#define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000
-#define TNETV107X_PSC_BASE 0x0808B000
-#define TNETV107X_TDM0_BASE 0x08100000
-#define TNETV107X_TDM1_BASE 0x08100100
-#define TNETV107X_MCDMA_BASE 0x08108000
-#define TNETV107X_UART0_DMA_BASE 0x08108200
-#define TNETV107X_USBSS_BASE 0x08120000
-#define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000
-#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
-#define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000
-#define TNETV107X_IMCOP_BASE 0x01CC0000
-#define TNETV107X_MBX_LITE_BASE 0x07000000
-#define TNETV107X_ETHSS_BASE 0x0803C000
-#define TNETV107X_CPSW_BASE 0x0803C000
-#define TNETV107X_SPF_BASE 0x0803C800
-#define TNETV107X_IOPU_ETHSS_BASE 0x0803D000
-#define TNETV107X_VTP_CNTRL_0 0x0803D800
-#define TNETV107X_VTP_CNTRL_1 0x0803D900
-#define TNETV107X_UART2_DMA_BASE 0x08108400
-#define TNETV107X_INTERNAL_MEMORY 0x20000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
-#define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000
-#define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000
-
-/* LPSC module definitions */
-#define TNETV107X_LPSC_ARM 0
-#define TNETV107X_LPSC_GEM 1
-#define TNETV107X_LPSC_DDR2_PHY 2
-#define TNETV107X_LPSC_TPCC 3
-#define TNETV107X_LPSC_TPTC0 4
-#define TNETV107X_LPSC_TPTC1 5
-#define TNETV107X_LPSC_RAM 6
-#define TNETV107X_LPSC_MBX_LITE 7
-#define TNETV107X_LPSC_LCD 8
-#define TNETV107X_LPSC_ETHSS 9
-#define TNETV107X_LPSC_AEMIF 10
-#define TNETV107X_LPSC_CHIP_CFG 11
-#define TNETV107X_LPSC_TSC 12
-#define TNETV107X_LPSC_ROM 13
-#define TNETV107X_LPSC_UART2 14
-#define TNETV107X_LPSC_PKTSEC 15
-#define TNETV107X_LPSC_SECCTL 16
-#define TNETV107X_LPSC_KEYMGR 17
-#define TNETV107X_LPSC_KEYPAD 18
-#define TNETV107X_LPSC_GPIO 19
-#define TNETV107X_LPSC_MDIO 20
-#define TNETV107X_LPSC_SDIO0 21
-#define TNETV107X_LPSC_UART0 22
-#define TNETV107X_LPSC_UART1 23
-#define TNETV107X_LPSC_TIMER0 24
-#define TNETV107X_LPSC_TIMER1 25
-#define TNETV107X_LPSC_WDT_ARM 26
-#define TNETV107X_LPSC_WDT_DSP 27
-#define TNETV107X_LPSC_SSP 28
-#define TNETV107X_LPSC_TDM0 29
-#define TNETV107X_LPSC_VLYNQ 30
-#define TNETV107X_LPSC_MCDMA 31
-#define TNETV107X_LPSC_USB0 32
-#define TNETV107X_LPSC_TDM1 33
-#define TNETV107X_LPSC_DEBUGSS 34
-#define TNETV107X_LPSC_ETHSS_RGMII 35
-#define TNETV107X_LPSC_SYSTEM 36
-#define TNETV107X_LPSC_IMCOP 37
-#define TNETV107X_LPSC_SPARE 38
-#define TNETV107X_LPSC_SDIO1 39
-#define TNETV107X_LPSC_USB1 40
-#define TNETV107X_LPSC_USBSS 41
-#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
-#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
-#define TNETV107X_LPSC_MAX 44
-
-/* Interrupt controller */
-#define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10)
-#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500)
-#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380)
-
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/mux.h b/arch/arm/include/asm/arch-tnetv107x/mux.h
deleted file mode 100644
index 3f832c4..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/mux.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * TNETV107X: Pinmux APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_MUX_H
-#define __ASM_ARCH_MUX_H
-
-struct pin_config {
- unsigned char reg_index;
- unsigned char mask_offset;
- unsigned char mode;
-};
-
-#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \
- { reg, offset, mux_mode }
-
-int mux_select_pin(short index);
-int mux_select_pins(const short *pins);
-
-enum tnetv107x_pin_mux_index {
- TNETV107X_PIN_ASR_A00,
- TNETV107X_PIN_GPIO32,
- TNETV107X_PIN_ASR_A01,
- TNETV107X_PIN_GPIO33,
- TNETV107X_PIN_ASR_A02,
- TNETV107X_PIN_GPIO34,
- TNETV107X_PIN_ASR_A03,
- TNETV107X_PIN_GPIO35,
- TNETV107X_PIN_ASR_A04,
- TNETV107X_PIN_GPIO36,
- TNETV107X_PIN_ASR_A05,
- TNETV107X_PIN_GPIO37,
- TNETV107X_PIN_ASR_A06,
- TNETV107X_PIN_GPIO38,
- TNETV107X_PIN_ASR_A07,
- TNETV107X_PIN_GPIO39,
- TNETV107X_PIN_ASR_A08,
- TNETV107X_PIN_GPIO40,
- TNETV107X_PIN_ASR_A09,
- TNETV107X_PIN_GPIO41,
- TNETV107X_PIN_ASR_A10,
- TNETV107X_PIN_GPIO42,
- TNETV107X_PIN_ASR_A11,
- TNETV107X_PIN_BOOT_STRP_0,
- TNETV107X_PIN_ASR_A12,
- TNETV107X_PIN_BOOT_STRP_1,
- TNETV107X_PIN_ASR_A13,
- TNETV107X_PIN_GPIO43,
- TNETV107X_PIN_ASR_A14,
- TNETV107X_PIN_GPIO44,
- TNETV107X_PIN_ASR_A15,
- TNETV107X_PIN_GPIO45,
- TNETV107X_PIN_ASR_A16,
- TNETV107X_PIN_GPIO46,
- TNETV107X_PIN_ASR_A17,
- TNETV107X_PIN_GPIO47,
- TNETV107X_PIN_ASR_A18,
- TNETV107X_PIN_GPIO48,
- TNETV107X_PIN_SDIO1_DATA3_0,
- TNETV107X_PIN_ASR_A19,
- TNETV107X_PIN_GPIO49,
- TNETV107X_PIN_SDIO1_DATA2_0,
- TNETV107X_PIN_ASR_A20,
- TNETV107X_PIN_GPIO50,
- TNETV107X_PIN_SDIO1_DATA1_0,
- TNETV107X_PIN_ASR_A21,
- TNETV107X_PIN_GPIO51,
- TNETV107X_PIN_SDIO1_DATA0_0,
- TNETV107X_PIN_ASR_A22,
- TNETV107X_PIN_GPIO52,
- TNETV107X_PIN_SDIO1_CMD_0,
- TNETV107X_PIN_ASR_A23,
- TNETV107X_PIN_GPIO53,
- TNETV107X_PIN_SDIO1_CLK_0,
- TNETV107X_PIN_ASR_BA_1,
- TNETV107X_PIN_GPIO54,
- TNETV107X_PIN_SYS_PLL_CLK,
- TNETV107X_PIN_ASR_CS0,
- TNETV107X_PIN_ASR_CS1,
- TNETV107X_PIN_ASR_CS2,
- TNETV107X_PIN_TDM_PLL_CLK,
- TNETV107X_PIN_ASR_CS3,
- TNETV107X_PIN_ETH_PHY_CLK,
- TNETV107X_PIN_ASR_D00,
- TNETV107X_PIN_GPIO55,
- TNETV107X_PIN_ASR_D01,
- TNETV107X_PIN_GPIO56,
- TNETV107X_PIN_ASR_D02,
- TNETV107X_PIN_GPIO57,
- TNETV107X_PIN_ASR_D03,
- TNETV107X_PIN_GPIO58,
- TNETV107X_PIN_ASR_D04,
- TNETV107X_PIN_GPIO59_0,
- TNETV107X_PIN_ASR_D05,
- TNETV107X_PIN_GPIO60_0,
- TNETV107X_PIN_ASR_D06,
- TNETV107X_PIN_GPIO61_0,
- TNETV107X_PIN_ASR_D07,
- TNETV107X_PIN_GPIO62_0,
- TNETV107X_PIN_ASR_D08,
- TNETV107X_PIN_GPIO63_0,
- TNETV107X_PIN_ASR_D09,
- TNETV107X_PIN_GPIO64_0,
- TNETV107X_PIN_ASR_D10,
- TNETV107X_PIN_SDIO1_DATA3_1,
- TNETV107X_PIN_ASR_D11,
- TNETV107X_PIN_SDIO1_DATA2_1,
- TNETV107X_PIN_ASR_D12,
- TNETV107X_PIN_SDIO1_DATA1_1,
- TNETV107X_PIN_ASR_D13,
- TNETV107X_PIN_SDIO1_DATA0_1,
- TNETV107X_PIN_ASR_D14,
- TNETV107X_PIN_SDIO1_CMD_1,
- TNETV107X_PIN_ASR_D15,
- TNETV107X_PIN_SDIO1_CLK_1,
- TNETV107X_PIN_ASR_OE,
- TNETV107X_PIN_BOOT_STRP_2,
- TNETV107X_PIN_ASR_RNW,
- TNETV107X_PIN_GPIO29_0,
- TNETV107X_PIN_ASR_WAIT,
- TNETV107X_PIN_GPIO30_0,
- TNETV107X_PIN_ASR_WE,
- TNETV107X_PIN_BOOT_STRP_3,
- TNETV107X_PIN_ASR_WE_DQM0,
- TNETV107X_PIN_GPIO31,
- TNETV107X_PIN_LCD_PD17_0,
- TNETV107X_PIN_ASR_WE_DQM1,
- TNETV107X_PIN_ASR_BA0_0,
- TNETV107X_PIN_VLYNQ_CLK,
- TNETV107X_PIN_GPIO14,
- TNETV107X_PIN_LCD_PD19_0,
- TNETV107X_PIN_VLYNQ_RXD0,
- TNETV107X_PIN_GPIO15,
- TNETV107X_PIN_LCD_PD20_0,
- TNETV107X_PIN_VLYNQ_RXD1,
- TNETV107X_PIN_GPIO16,
- TNETV107X_PIN_LCD_PD21_0,
- TNETV107X_PIN_VLYNQ_TXD0,
- TNETV107X_PIN_GPIO17,
- TNETV107X_PIN_LCD_PD22_0,
- TNETV107X_PIN_VLYNQ_TXD1,
- TNETV107X_PIN_GPIO18,
- TNETV107X_PIN_LCD_PD23_0,
- TNETV107X_PIN_SDIO0_CLK,
- TNETV107X_PIN_GPIO19,
- TNETV107X_PIN_SDIO0_CMD,
- TNETV107X_PIN_GPIO20,
- TNETV107X_PIN_SDIO0_DATA0,
- TNETV107X_PIN_GPIO21,
- TNETV107X_PIN_SDIO0_DATA1,
- TNETV107X_PIN_GPIO22,
- TNETV107X_PIN_SDIO0_DATA2,
- TNETV107X_PIN_GPIO23,
- TNETV107X_PIN_SDIO0_DATA3,
- TNETV107X_PIN_GPIO24,
- TNETV107X_PIN_EMU0,
- TNETV107X_PIN_EMU1,
- TNETV107X_PIN_RTCK,
- TNETV107X_PIN_TRST_N,
- TNETV107X_PIN_TCK,
- TNETV107X_PIN_TDI,
- TNETV107X_PIN_TDO,
- TNETV107X_PIN_TMS,
- TNETV107X_PIN_TDM1_CLK,
- TNETV107X_PIN_TDM1_RX,
- TNETV107X_PIN_TDM1_TX,
- TNETV107X_PIN_TDM1_FS,
- TNETV107X_PIN_KEYPAD_R0,
- TNETV107X_PIN_KEYPAD_R1,
- TNETV107X_PIN_KEYPAD_R2,
- TNETV107X_PIN_KEYPAD_R3,
- TNETV107X_PIN_KEYPAD_R4,
- TNETV107X_PIN_KEYPAD_R5,
- TNETV107X_PIN_KEYPAD_R6,
- TNETV107X_PIN_GPIO12,
- TNETV107X_PIN_KEYPAD_R7,
- TNETV107X_PIN_GPIO10,
- TNETV107X_PIN_KEYPAD_C0,
- TNETV107X_PIN_KEYPAD_C1,
- TNETV107X_PIN_KEYPAD_C2,
- TNETV107X_PIN_KEYPAD_C3,
- TNETV107X_PIN_KEYPAD_C4,
- TNETV107X_PIN_KEYPAD_C5,
- TNETV107X_PIN_KEYPAD_C6,
- TNETV107X_PIN_GPIO13,
- TNETV107X_PIN_TEST_CLK_IN,
- TNETV107X_PIN_KEYPAD_C7,
- TNETV107X_PIN_GPIO11,
- TNETV107X_PIN_SSP0_0,
- TNETV107X_PIN_SCC_DCLK,
- TNETV107X_PIN_LCD_PD20_1,
- TNETV107X_PIN_SSP0_1,
- TNETV107X_PIN_SCC_CS_N,
- TNETV107X_PIN_LCD_PD21_1,
- TNETV107X_PIN_SSP0_2,
- TNETV107X_PIN_SCC_D,
- TNETV107X_PIN_LCD_PD22_1,
- TNETV107X_PIN_SSP0_3,
- TNETV107X_PIN_SCC_RESETN,
- TNETV107X_PIN_LCD_PD23_1,
- TNETV107X_PIN_SSP1_0,
- TNETV107X_PIN_GPIO25,
- TNETV107X_PIN_UART2_CTS,
- TNETV107X_PIN_SSP1_1,
- TNETV107X_PIN_GPIO26,
- TNETV107X_PIN_UART2_RD,
- TNETV107X_PIN_SSP1_2,
- TNETV107X_PIN_GPIO27,
- TNETV107X_PIN_UART2_RTS,
- TNETV107X_PIN_SSP1_3,
- TNETV107X_PIN_GPIO28,
- TNETV107X_PIN_UART2_TD,
- TNETV107X_PIN_UART0_CTS,
- TNETV107X_PIN_UART0_RD,
- TNETV107X_PIN_UART0_RTS,
- TNETV107X_PIN_UART0_TD,
- TNETV107X_PIN_UART1_RD,
- TNETV107X_PIN_UART1_TD,
- TNETV107X_PIN_LCD_AC_NCS,
- TNETV107X_PIN_LCD_HSYNC_RNW,
- TNETV107X_PIN_LCD_VSYNC_A0,
- TNETV107X_PIN_LCD_MCLK,
- TNETV107X_PIN_LCD_PD16_0,
- TNETV107X_PIN_LCD_PCLK_E,
- TNETV107X_PIN_LCD_PD00,
- TNETV107X_PIN_LCD_PD01,
- TNETV107X_PIN_LCD_PD02,
- TNETV107X_PIN_LCD_PD03,
- TNETV107X_PIN_LCD_PD04,
- TNETV107X_PIN_LCD_PD05,
- TNETV107X_PIN_LCD_PD06,
- TNETV107X_PIN_LCD_PD07,
- TNETV107X_PIN_LCD_PD08,
- TNETV107X_PIN_GPIO59_1,
- TNETV107X_PIN_LCD_PD09,
- TNETV107X_PIN_GPIO60_1,
- TNETV107X_PIN_LCD_PD10,
- TNETV107X_PIN_ASR_BA0_1,
- TNETV107X_PIN_GPIO61_1,
- TNETV107X_PIN_LCD_PD11,
- TNETV107X_PIN_GPIO62_1,
- TNETV107X_PIN_LCD_PD12,
- TNETV107X_PIN_GPIO63_1,
- TNETV107X_PIN_LCD_PD13,
- TNETV107X_PIN_GPIO64_1,
- TNETV107X_PIN_LCD_PD14,
- TNETV107X_PIN_GPIO29_1,
- TNETV107X_PIN_LCD_PD15,
- TNETV107X_PIN_GPIO30_1,
- TNETV107X_PIN_EINT0,
- TNETV107X_PIN_GPIO08,
- TNETV107X_PIN_EINT1,
- TNETV107X_PIN_GPIO09,
- TNETV107X_PIN_GPIO00,
- TNETV107X_PIN_LCD_PD20_2,
- TNETV107X_PIN_TDM_CLK_IN_2,
- TNETV107X_PIN_GPIO01,
- TNETV107X_PIN_LCD_PD21_2,
- TNETV107X_PIN_24M_CLK_OUT_1,
- TNETV107X_PIN_GPIO02,
- TNETV107X_PIN_LCD_PD22_2,
- TNETV107X_PIN_GPIO03,
- TNETV107X_PIN_LCD_PD23_2,
- TNETV107X_PIN_GPIO04,
- TNETV107X_PIN_LCD_PD16_1,
- TNETV107X_PIN_USB0_RXERR,
- TNETV107X_PIN_GPIO05,
- TNETV107X_PIN_LCD_PD17_1,
- TNETV107X_PIN_TDM_CLK_IN_1,
- TNETV107X_PIN_GPIO06,
- TNETV107X_PIN_LCD_PD18,
- TNETV107X_PIN_24M_CLK_OUT_2,
- TNETV107X_PIN_GPIO07,
- TNETV107X_PIN_LCD_PD19_1,
- TNETV107X_PIN_USB1_RXERR,
- TNETV107X_PIN_ETH_PLL_CLK,
- TNETV107X_PIN_MDIO,
- TNETV107X_PIN_MDC,
- TNETV107X_PIN_AIC_MUTE_STAT_N,
- TNETV107X_PIN_TDM0_CLK,
- TNETV107X_PIN_AIC_HNS_EN_N,
- TNETV107X_PIN_TDM0_FS,
- TNETV107X_PIN_AIC_HDS_EN_STAT_N,
- TNETV107X_PIN_TDM0_TX,
- TNETV107X_PIN_AIC_HNF_EN_STAT_N,
- TNETV107X_PIN_TDM0_RX,
-};
-
-#endif
diff --git a/board/ti/tnetv107xevm/Kconfig b/board/ti/tnetv107xevm/Kconfig
deleted file mode 100644
index 637f20e..0000000
--- a/board/ti/tnetv107xevm/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_TNETV107X_EVM
-
-config SYS_BOARD
- default "tnetv107xevm"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_SOC
- default "tnetv107x"
-
-config SYS_CONFIG_NAME
- default "tnetv107x_evm"
-
-endif
diff --git a/board/ti/tnetv107xevm/MAINTAINERS b/board/ti/tnetv107xevm/MAINTAINERS
deleted file mode 100644
index 8a92c6b..0000000
--- a/board/ti/tnetv107xevm/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TNETV107XEVM BOARD
-#M: Chan-Taek Park <c-park@ti.com>
-S: Orphan (since 2014-06)
-F: board/ti/tnetv107xevm/
-F: include/configs/tnetv107x_evm.h
-F: configs/tnetv107x_evm_defconfig
diff --git a/board/ti/tnetv107xevm/Makefile b/board/ti/tnetv107xevm/Makefile
deleted file mode 100644
index 0a6128f..0000000
--- a/board/ti/tnetv107xevm/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += sdb_board.o
diff --git a/board/ti/tnetv107xevm/config.mk b/board/ti/tnetv107xevm/config.mk
deleted file mode 100644
index 51c2886..0000000
--- a/board/ti/tnetv107xevm/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0x83FC0000
diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c
deleted file mode 100644
index a84ec84..0000000
--- a/board/ti/tnetv107xevm/sdb_board.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * TNETV107X-EVM: Board initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <linux/mtd/nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/mux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
- { /* CS0 */
- .mode = ASYNC_EMIF_MODE_NAND,
- .wr_setup = 5,
- .wr_strobe = 5,
- .wr_hold = 2,
- .rd_setup = 5,
- .rd_strobe = 5,
- .rd_hold = 2,
- .turn_around = 5,
- .width = ASYNC_EMIF_8,
- },
- { /* CS1 */
- .mode = ASYNC_EMIF_MODE_NOR,
- .wr_setup = 2,
- .wr_strobe = 27,
- .wr_hold = 4,
- .rd_setup = 2,
- .rd_strobe = 27,
- .rd_hold = 4,
- .turn_around = 2,
- .width = ASYNC_EMIF_PRESERVE,
- },
- { /* CS2 */
- .mode = ASYNC_EMIF_MODE_NOR,
- .wr_setup = 2,
- .wr_strobe = 27,
- .wr_hold = 4,
- .rd_setup = 2,
- .rd_strobe = 27,
- .rd_hold = 4,
- .turn_around = 2,
- .width = ASYNC_EMIF_PRESERVE,
- },
- { /* CS3 */
- .mode = ASYNC_EMIF_MODE_NOR,
- .wr_setup = 1,
- .wr_strobe = 90,
- .wr_hold = 3,
- .rd_setup = 1,
- .rd_strobe = 26,
- .rd_hold = 3,
- .turn_around = 1,
- .width = ASYNC_EMIF_8,
- },
-};
-
-static struct pll_init_data pll_config[] = {
- {
- .pll = ETH_PLL,
- .internal_osc = 1,
- .pll_freq = 500000000,
- .div_freq = {
- 5000000, 50000000, 125000000, 250000000, 25000000,
- },
- },
-};
-
-static const short sdio1_pins[] = {
- TNETV107X_PIN_SDIO1_CLK_1, TNETV107X_PIN_SDIO1_CMD_1,
- TNETV107X_PIN_SDIO1_DATA0_1, TNETV107X_PIN_SDIO1_DATA1_1,
- TNETV107X_PIN_SDIO1_DATA2_1, TNETV107X_PIN_SDIO1_DATA3_1,
- -1
-};
-
-static const short uart1_pins[] = {
- TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1
-};
-
-static const short ssp_pins[] = {
- TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2,
- TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2,
- TNETV107X_PIN_SSP1_3, -1
-};
-
-int board_init(void)
-{
-#ifndef CONFIG_USE_IRQ
- __raw_writel(0, INTC_GLB_EN); /* Global disable */
- __raw_writel(0, INTC_HINT_EN); /* Disable host ints */
- __raw_writel(0, INTC_EN_CLR0 + 0); /* Clear enable */
- __raw_writel(0, INTC_EN_CLR0 + 4); /* Clear enable */
- __raw_writel(0, INTC_EN_CLR0 + 8); /* Clear enable */
-#endif
-
- gd->bd->bi_arch_number = MACH_TYPE_TNETV107X;
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- init_plls(ARRAY_SIZE(pll_config), pll_config);
-
- init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
-
- mux_select_pin(TNETV107X_PIN_ASR_CS3);
- mux_select_pins(sdio1_pins);
- mux_select_pins(uart1_pins);
- mux_select_pins(ssp_pins);
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-#ifdef CONFIG_NAND_DAVINCI
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
-
- return 0;
-}
-#endif
diff --git a/configs/tnetv107x_evm_defconfig b/configs/tnetv107x_evm_defconfig
deleted file mode 100644
index b0915d2..0000000
--- a/configs/tnetv107x_evm_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_TNETV107X_EVM=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 172386a..59f5b2d 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+tnetv107x arm arm1176 - - Chan-Taek Park <c-park@ti.com>
aspenite arm arm926ejs - - Prafulla Wadaskar <prafulla@marvell.com>
gplugd arm arm926ejs - - Ajay Bhargav <ajay.bhargav@einfochips.com>
a320evb arm arm920t - - Po-Yu Chuang <ratbert@faraday-tech.com>
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 1dc0f5a..482a4bd 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -10,7 +10,6 @@ obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa))
obj-y += imx_watchdog.o
endif
-obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
diff --git a/drivers/watchdog/tnetv107x_wdt.c b/drivers/watchdog/tnetv107x_wdt.c
deleted file mode 100644
index 3d3f366..0000000
--- a/drivers/watchdog/tnetv107x_wdt.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * TNETV107X: Watchdog timer implementation (for reset)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-#define MAX_DIV 0xFFFE0001
-
-struct wdt_regs {
- u32 kick_lock;
-#define KICK_LOCK_1 0x5555
-#define KICK_LOCK_2 0xaaaa
- u32 kick;
-
- u32 change_lock;
-#define CHANGE_LOCK_1 0x6666
-#define CHANGE_LOCK_2 0xbbbb
- u32 change;
-
- u32 disable_lock;
-#define DISABLE_LOCK_1 0x7777
-#define DISABLE_LOCK_2 0xcccc
-#define DISABLE_LOCK_3 0xdddd
- u32 disable;
-
- u32 prescale_lock;
-#define PRESCALE_LOCK_1 0x5a5a
-#define PRESCALE_LOCK_2 0xa5a5
- u32 prescale;
-};
-
-static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
-
-#define wdt_reg_read(reg) __raw_readl(®s->reg)
-#define wdt_reg_write(reg, val) __raw_writel((val), ®s->reg)
-
-static int write_prescale_reg(unsigned long prescale_value)
-{
- wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
- if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
- return -1;
-
- wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
- if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
- return -1;
-
- wdt_reg_write(prescale, prescale_value);
-
- return 0;
-}
-
-static int write_change_reg(unsigned long initial_timer_value)
-{
- wdt_reg_write(change_lock, CHANGE_LOCK_1);
- if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
- return -1;
-
- wdt_reg_write(change_lock, CHANGE_LOCK_2);
- if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
- return -1;
-
- wdt_reg_write(change, initial_timer_value);
-
- return 0;
-}
-
-static int wdt_control(unsigned long disable_value)
-{
- wdt_reg_write(disable_lock, DISABLE_LOCK_1);
- if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
- return -1;
-
- wdt_reg_write(disable_lock, DISABLE_LOCK_2);
- if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
- return -1;
-
- wdt_reg_write(disable_lock, DISABLE_LOCK_3);
- if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
- return -1;
-
- wdt_reg_write(disable, disable_value);
- return 0;
-}
-
-static int wdt_set_period(unsigned long msec)
-{
- unsigned long change_value, count_value;
- unsigned long prescale_value = 1;
- unsigned long refclk_khz, maxdiv;
- int ret;
-
- refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
- maxdiv = (MAX_DIV / refclk_khz);
-
- if ((!msec) || (msec > maxdiv))
- return -1;
-
- count_value = refclk_khz * msec;
- if (count_value > 0xffff) {
- change_value = count_value / 0xffff + 1;
- prescale_value = count_value / change_value;
- } else {
- change_value = count_value;
- }
-
- ret = write_prescale_reg(prescale_value - 1);
- if (ret)
- return ret;
-
- ret = write_change_reg(change_value);
- if (ret)
- return ret;
-
- return 0;
-}
-
-unsigned long last_wdt = -1;
-
-int wdt_start(unsigned long msecs)
-{
- int ret;
- ret = wdt_control(0);
- if (ret)
- return ret;
- ret = wdt_set_period(msecs);
- if (ret)
- return ret;
- ret = wdt_control(1);
- if (ret)
- return ret;
- ret = wdt_kick();
- last_wdt = msecs;
- return ret;
-}
-
-int wdt_stop(void)
-{
- last_wdt = -1;
- return wdt_control(0);
-}
-
-int wdt_kick(void)
-{
- wdt_reg_write(kick_lock, KICK_LOCK_1);
- if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
- return -1;
-
- wdt_reg_write(kick_lock, KICK_LOCK_2);
- if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
- return -1;
-
- wdt_reg_write(kick, 1);
- return 0;
-}
-
-void reset_cpu(ulong addr)
-{
- clk_enable(TNETV107X_LPSC_WDT_ARM);
- wdt_start(1);
- wdt_kick();
-}
diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h
deleted file mode 100644
index 00a1a9e..0000000
--- a/include/configs/tnetv107x_evm.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
- *
- * Based on davinci_dvevm.h. Original Copyrights follow:
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-
-/* Architecture, CPU, etc */
-#define CONFIG_TNETV107X
-#define CONFIG_TNETV107X_EVM
-#define CONFIG_TNETV107X_WATCHDOG
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_DISABLE_TCM
-#define CONFIG_PERIPORT_REMAP
-#define CONFIG_PERIPORT_BASE 0x2000000
-#define CONFIG_PERIPORT_SIZE 0x10
-#define CONFIG_SYS_CLK_FREQ clk_get_rate(TNETV107X_LPSC_ARM)
-
-#define CONFIG_SYS_TIMERBASE TNETV107X_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get_rate(TNETV107X_LPSC_TIMER0)
-
-#define CONFIG_PLL_SYS_EXT_FREQ 25000000
-#define CONFIG_PLL_TDM_EXT_FREQ 19200000
-#define CONFIG_PLL_ETH_EXT_FREQ 25000000
-
-/* Memory Info */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024)
-#define PHYS_SDRAM_1 TNETV107X_DDR_EMIF_DATA_BASE
-#define PHYS_SDRAM_1_SIZE 0x04000000
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024)
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-/* Serial Driver Info */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 TNETV107X_UART1_BASE
-#define CONFIG_SYS_NS16550_CLK clk_get_rate(TNETV107X_LPSC_UART1)
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Flash and environment info */
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE (SZ_128K)
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_NAND_1BIT_ECC
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_BASE TNETV107X_ASYNC_EMIF_DATA_CE0_BASE
-#define CONFIG_SYS_NAND_MASK_CLE 0x10
-#define CONFIG_SYS_NAND_MASK_ALE 0x8
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_JFFS2_NAND
-#define CONFIG_ENV_OFFSET 0x180000
-
-/*
- * davinci_nand is a bit of a misnomer since this particular EMIF block is
- * commonly used across multiple TI devices. Unfortunately, this misnomer
- * (amongst others) carries forward into the kernel too. Consequently, if we
- * use a different device name here, the mtdparts variable won't be usable as
- * a kernel command-line argument.
- */
-#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
-#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
- "1536k(uboot)ro," \
- "128k(params)ro," \
- "4m(kernel)," \
- "-(filesystem)"
-
-/* General U-Boot configuration */
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_SYS_PROMPT "U-Boot > "
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + \
- 0x700000)
-#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS "mem=32M console=ttyS1,115200n8 " \
- "root=/dev/mmcblk0p1 rw noinitrd"
-#define CONFIG_BOOTCOMMAND ""
-#define CONFIG_BOOTDELAY 1
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EDITENV
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_ITEST
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_JFFS2
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 11/11] ARM: davinci: remove hawkboard support
2015-02-10 4:44 [U-Boot] [PATCH 0/11] ARM: remove non-generic boards Masahiro Yamada
` (9 preceding siblings ...)
2015-02-10 4:44 ` [U-Boot] [PATCH 10/11] ARM: remove tnetv107x " Masahiro Yamada
@ 2015-02-10 4:44 ` Masahiro Yamada
10 siblings, 0 replies; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 4:44 UTC (permalink / raw)
To: u-boot
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Syed Mohammed Khasim <sm.khasim@gmail.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
---
arch/arm/cpu/arm926ejs/davinci/Kconfig | 4 -
board/davinci/da8xxevm/Kconfig | 13 --
board/davinci/da8xxevm/MAINTAINERS | 8 -
board/davinci/da8xxevm/Makefile | 1 -
board/davinci/da8xxevm/README.hawkboard | 92 -----------
board/davinci/da8xxevm/hawkboard-ais-nand.cfg | 4 -
board/davinci/da8xxevm/hawkboard.c | 120 --------------
board/davinci/da8xxevm/u-boot-spl-hawk.lds | 69 --------
configs/hawkboard_defconfig | 4 -
configs/hawkboard_uart_defconfig | 5 -
doc/README.scrapyard | 1 +
include/configs/hawkboard.h | 220 --------------------------
12 files changed, 1 insertion(+), 540 deletions(-)
delete mode 100644 board/davinci/da8xxevm/README.hawkboard
delete mode 100644 board/davinci/da8xxevm/hawkboard-ais-nand.cfg
delete mode 100644 board/davinci/da8xxevm/hawkboard.c
delete mode 100644 board/davinci/da8xxevm/u-boot-spl-hawk.lds
delete mode 100644 configs/hawkboard_defconfig
delete mode 100644 configs/hawkboard_uart_defconfig
delete mode 100644 include/configs/hawkboard.h
diff --git a/arch/arm/cpu/arm926ejs/davinci/Kconfig b/arch/arm/cpu/arm926ejs/davinci/Kconfig
index 613f04d..6827721 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Kconfig
+++ b/arch/arm/cpu/arm926ejs/davinci/Kconfig
@@ -21,10 +21,6 @@ config TARGET_CAM_ENC_4XX
bool "CAM ENC 4xx board"
select SUPPORT_SPL
-config TARGET_HAWKBOARD
- bool "Hawkboard"
- select SUPPORT_SPL
-
config TARGET_DAVINCI_DM355EVM
bool "DM355 EVM board"
diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig
index 1a841ce..1108e4b 100644
--- a/board/davinci/da8xxevm/Kconfig
+++ b/board/davinci/da8xxevm/Kconfig
@@ -23,16 +23,3 @@ config SYS_CONFIG_NAME
default "da850evm"
endif
-
-if TARGET_HAWKBOARD
-
-config SYS_BOARD
- default "da8xxevm"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "hawkboard"
-
-endif
diff --git a/board/davinci/da8xxevm/MAINTAINERS b/board/davinci/da8xxevm/MAINTAINERS
index dd66f07..10c4e2f 100644
--- a/board/davinci/da8xxevm/MAINTAINERS
+++ b/board/davinci/da8xxevm/MAINTAINERS
@@ -12,11 +12,3 @@ F: include/configs/da850evm.h
F: configs/da850_am18xxevm_defconfig
F: configs/da850evm_defconfig
F: configs/da850evm_direct_nor_defconfig
-
-HAWKBOARD BOARD
-M: Syed Mohammed Khasim <sm.khasim@gmail.com>
-M: Sughosh Ganu <urwithsughosh@gmail.com>
-S: Maintained
-F: include/configs/hawkboard.h
-F: configs/hawkboard_defconfig
-F: configs/hawkboard_uart_defconfig
diff --git a/board/davinci/da8xxevm/Makefile b/board/davinci/da8xxevm/Makefile
index d3acacc..4da509b 100644
--- a/board/davinci/da8xxevm/Makefile
+++ b/board/davinci/da8xxevm/Makefile
@@ -9,4 +9,3 @@
obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o
obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o
-obj-$(CONFIG_MACH_DAVINCI_HAWK) += hawkboard.o
diff --git a/board/davinci/da8xxevm/README.hawkboard b/board/davinci/da8xxevm/README.hawkboard
deleted file mode 100644
index d6ae02e..0000000
--- a/board/davinci/da8xxevm/README.hawkboard
+++ /dev/null
@@ -1,92 +0,0 @@
-Summary
-=======
-The README is for the boot procedure used for TI's OMAP-L138 based
-hawkboard. The hawkboard comes with a 128MiB Nand flash and a 128MiB
-DDR SDRAM along with a host of other controllers.
-
-The hawkboard is booted in three stages. The initial bootloader which
-executes upon reset is the Rom Boot Loader(RBL) which sits in the
-internal ROM of the omap. The RBL initialises the memory and the nand
-controller, and copies the image stored at a predefined location(block
-1) of the nand flash. The image loaded by the RBL to the memory is the
-AIS signed spl image. This, in turns copies the u-boot binary from the
-nand flash to the memory and jumps to the u-boot entry point.
-
-AIS is an image format defined by TI for the images that are to be
-loaded to memory by the RBL. The image is divided into a series of
-sections and the image's entry point is specified. Each section comes
-with meta data like the target address the section is to be copied to
-and the size of the section, which is used by the RBL to load the
-image. At the end of the image the RBL jumps to the image entry
-point.
-
-The secondary stage bootloader(spl) which is loaded by the RBL then
-loads the u-boot from a predefined location in the nand to the memory
-and jumps to the u-boot entry point.
-
-The reason a secondary stage bootloader is used is because the ECC
-layout expected by the RBL is not the same as that used by
-u-boot/linux. This also implies that for flashing the spl image,we
-need to use the u-boot which uses the ECC layout expected by the
-RBL[1]. Booting u-boot over UART(UART boot) is explained here[2].
-
-
-Compilation
-===========
-Three images might be needed
-
-* spl - This is the secondary bootloader which boots the u-boot
- binary.
-
-* u-boot binary - This is the image flashed to the nand and copied to
- the memory by the spl.
-
- Both the images get compiled with hawkboard_config, with the TOPDIR
- containing the u-boot images, and the spl image under the spl
- directory.
-
- The spl image needs to be processed with the AISGen tool for
- generating the AIS signed image to be flashed. Steps for generating
- the AIS image are explained here[3].
-
-* u-boot for uart boot - This is same as the u-boot binary generated
- above, with the sole difference of the CONFIG_SYS_TEXT_BASE being
- 0xc1080000, as expected by the RBL.
-
- hawkboard_uart_config
-
-
-Flashing the images to Nand
-===========================
-The spl AIS image needs to be flashed to the block 1 of the Nand
-flash, as that is the location the RBL expects the image[4]. For
-flashing the spl, boot over the u-boot specified in [1], and flash the
-image
-
-=> tftpboot 0xc0700000 <nand_spl_ais.bin>
-=> nand erase 0x20000 0x20000
-=> nand write.e 0xc0700000 0x20000 <nand_spl_size>
-
-The u-boot binary is flashed at location 0xe0000(block 6) of the nand
-flash. The spl loader expects the u-boot at this location. For
-flashing the u-boot binary
-
-=> tftpboot 0xc0700000 u-boot.bin
-=> nand erase 0xe0000 0x40000
-=> nand write.e 0xc0700000 0xe0000 <u-boot-size>
-
-
-Links
-=====
-
-[1]
- http://code.google.com/p/hawkboard/downloads/detail?name=u-boot_uart_ais_v1.bin
-
-[2]
- http://elinux.org/Hawkboard#Booting_u-boot_over_UART
-
-[3]
- http://elinux.org/Hawkboard#Signing_u-boot_for_UART_boot
-
-[4]
- http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program#RBL_booting_from_NAND_and_ECC.2FBad_blocks
diff --git a/board/davinci/da8xxevm/hawkboard-ais-nand.cfg b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg
deleted file mode 100644
index 2b12b6c..0000000
--- a/board/davinci/da8xxevm/hawkboard-ais-nand.cfg
+++ /dev/null
@@ -1,4 +0,0 @@
-# PLL0CFG0 PLL0CFG1
-PLL0 0x00180001 0x00000205
-# PLL1CFG0 PLL1CFG1 DRPYC1R SDCR SDTIMR1 SDTIMR2 SDRCR CLK2XSRC
-DDR2 0x15010001 0x00000002 0x00000043 0x00134632 0x26492a09 0x7d13c722 0x00000249 0x00000000
diff --git a/board/davinci/da8xxevm/hawkboard.c b/board/davinci/da8xxevm/hawkboard.c
deleted file mode 100644
index d5992a5..0000000
--- a/board/davinci/da8xxevm/hawkboard.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
- *
- * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2004 Texas Instruments.
- * Copyright (C) 2012 Sughosh Ganu <urwithsughosh@gmail.com>.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/pinmux_defs.h>
-#include <asm/arch/da8xx-usb.h>
-#include <ns16550.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct pinmux_resource pinmuxes[] = {
- PINMUX_ITEM(emac_pins_mii),
- PINMUX_ITEM(emac_pins_mdio),
- PINMUX_ITEM(emifa_pins_cs3),
- PINMUX_ITEM(emifa_pins_cs4),
- PINMUX_ITEM(emifa_pins_nand),
- PINMUX_ITEM(uart2_pins_txrx),
- PINMUX_ITEM(uart2_pins_rtscts),
-};
-
-const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
-
-const struct lpsc_resource lpsc[] = {
- { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
- { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
- { DAVINCI_LPSC_EMAC }, /* image download */
- { DAVINCI_LPSC_UART2 }, /* console */
- { DAVINCI_LPSC_GPIO },
-};
-
-const int lpsc_size = ARRAY_SIZE(lpsc);
-
-int board_init(void)
-{
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_HAWKBOARD;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /*
- * Kick Registers need to be set to allow access to Pin Mux registers
- */
- writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
- writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
-
- /* set cfgchip3 to select mii */
- writel(readl(&davinci_syscfg_regs->cfgchip3) &
- ~(1 << 8), &davinci_syscfg_regs->cfgchip3);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- char buf[32];
-
- printf("ARM Clock : %s MHz\n",
- strmhz(buf, clk_get(DAVINCI_ARM_CLKID)));
-
- return 0;
-}
-
-int usb_phy_on(void)
-{
- u32 timeout;
- u32 cfgchip2;
-
- cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
-
- cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN |
- CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ |
- CFGCHIP2_USB1PHYCLKMUX);
- cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON |
- CFGCHIP2_REFFREQ_24MHZ | CFGCHIP2_USB2PHYCLKMUX |
- CFGCHIP2_USB1SUSPENDM;
-
- writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
-
- /* wait until the usb phy pll locks */
- timeout = DA8XX_USB_OTG_TIMEOUT;
- while (timeout--)
- if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
- return 1;
-
- /* USB phy was not turned on */
- return 0;
-}
-
-void usb_phy_off(void)
-{
- u32 cfgchip2;
-
- /*
- * Power down the on-chip PHY.
- */
- cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
- cfgchip2 &= ~(CFGCHIP2_PHY_PLLON | CFGCHIP2_USB1SUSPENDM);
- cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | CFGCHIP2_RESET;
- writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
-}
diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
deleted file mode 100644
index 5c629db..0000000
--- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0xc1080000;
-
- . = ALIGN(4);
- .text :
- {
- *(.vectors)
- arch/arm/cpu/arm926ejs/start.o (.text*)
- arch/arm/cpu/arm926ejs/built-in.o (.text*)
- drivers/mtd/nand/built-in.o (.text*)
-
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata*) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
- }
-
- . = ALIGN(4);
- __image_copy_end = .;
- __rel_dyn_start = .;
- __rel_dyn_end = .;
-
- __got_start = .;
- . = ALIGN(4);
- .got : { *(.got) }
-
- __got_end = .;
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- .end :
- {
- *(.__end)
- }
-}
diff --git a/configs/hawkboard_defconfig b/configs/hawkboard_defconfig
deleted file mode 100644
index 4084f9c..0000000
--- a/configs/hawkboard_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_HAWKBOARD=y
diff --git a/configs/hawkboard_uart_defconfig b/configs/hawkboard_uart_defconfig
deleted file mode 100644
index d7eeae7..0000000
--- a/configs/hawkboard_uart_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="UART_U_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_HAWKBOARD=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 59f5b2d..6028f98 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+hawkboard arm arm926ejs - - Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
tnetv107x arm arm1176 - - Chan-Taek Park <c-park@ti.com>
aspenite arm arm926ejs - - Prafulla Wadaskar <prafulla@marvell.com>
gplugd arm arm926ejs - - Ajay Bhargav <ajay.bhargav@einfochips.com>
diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h
deleted file mode 100644
index 1d78e72..0000000
--- a/include/configs/hawkboard.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on davinci_dvevm.h. Original Copyrights follow:
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Board
- */
-#define CONFIG_SYS_USE_NAND 1
-
-/*
- * SoC Configuration
- */
-#define CONFIG_MACH_DAVINCI_HAWK
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_AIS_CONFIG_FILE "board/$(BOARDDIR)/hawkboard-ais-nand.cfg"
-
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
- DAVINCI_SYSCFG_SUSPSRC_EMAC | \
- DAVINCI_SYSCFG_SUSPSRC_I2C | \
- DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
- DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
- DAVINCI_SYSCFG_SUSPSRC_UART2)
-
-#if defined(CONFIG_UART_U_BOOT)
-#define CONFIG_SYS_TEXT_BASE 0xc1080000
-#elif !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_TEXT_BASE 0xc1180000
-#endif
-
-/* Spl */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_LIBGENERIC_SUPPORT /* for udelay and __div64_32 for NAND */
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-hawk.lds"
-#define CONFIG_SPL_TEXT_BASE 0xc1080000
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-
-/*
- * Memory Info
- */
-#define CONFIG_SYS_MALLOC_LEN (1*1024*1024) /* malloc() len */
-#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE
-#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 -\
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN 0x60000
-
-/* memtest start addr */
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1)
-
-/* memtest will be run on 16MB */
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024)
-
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-
-/*
- * Serial Driver info
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Network & Ethernet Configuration
- */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-
-/*
- * Nand Flash
- */
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_CLE_MASK 0x10
-#define CONFIG_ALE_MASK 0x8
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST /* SPL nand driver configuration */
-#define CFG_DAVINCI_STD_NAND_LAYOUT
-#define CONFIG_SYS_NAND_CS 3
-#define CONFIG_SYS_NAND_PAGE_2K
-/* Max number of NAND devices */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE_LIST { 0x62000000, }
-/* Block 0--not used by bootcode */
-#define CONFIG_ENV_OFFSET 0x0
-
-#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xe0000
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1180000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
- CONFIG_SYS_NAND_U_BOOT_SIZE - \
- CONFIG_SYS_MALLOC_LEN - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS { \
- 24, 25, 26, 27, 28, \
- 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
- 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
- 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
- 59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 10
-#define CONFIG_SYS_NAND_OOBSIZE 64
-
-#endif /* CONFIG_SYS_USE_NAND */
-
-/* USB Configs */
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_OHCI_DA8XX
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x01E25000
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "hawkboard"
-
-/*
- * U-Boot general configuration
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "hawkboard > " /* Command Prompt */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/*
- * Linux Information
- */
-#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS \
- "mem=128M console=ttyS2,115200n8 root=/dev/ram0 rw initrd=0xc1180000,"\
- "4M ip=static"
-#define CONFIG_BOOTDELAY 3
-
-/*
- * U-Boot commands
- */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_EXT2
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_SYS_USE_NAND
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#define CONFIG_CMD_NAND
-#endif
-
-#ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PING
-#endif
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 09/11] ARM: armada100: remove aspenite and gplugd board support
2015-02-10 4:44 ` [U-Boot] [PATCH 09/11] ARM: armada100: remove aspenite and gplugd " Masahiro Yamada
@ 2015-02-10 5:06 ` Ajay Bhargav
2015-02-10 5:11 ` Prafulla Wadaskar
2015-02-10 5:13 ` Masahiro Yamada
0 siblings, 2 replies; 15+ messages in thread
From: Ajay Bhargav @ 2015-02-10 5:06 UTC (permalink / raw)
To: u-boot
________________________________________
From: Masahiro Yamada <yamada.m@jp.panasonic.com>
Sent: Tuesday, February 10, 2015 10:14 AM
To: u-boot at lists.denx.de
Cc: Tom Rini; Albert Aribaud; Masahiro Yamada; Prafulla Wadaskar; Ajay Bhargav; Roman Byshko; Matthias Fuchs; Marek Vasut; Ivan Khoronzhuk; Jiandong Zheng; Oleksandr Tymoshenko; Jagannadha Sutradharudu Teki; Joe Hershberger; Sergey Kostanbaev; Steve Rae; WingMan Kwok; Siva Durga Prasad Paladugu; Stefan Roese; Michal Simek; Nobuhiro Iwamatsu; Simon Glass; Wolfgang Denk; Ian Campbell; Georges Savoundararadj; Daniel Schwierzeck
Subject: [PATCH 09/11] ARM: armada100: remove aspenite and gplugd board support
These are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Ajay Bhargav <ajay.bhargav@einfochips.com>
---
arch/arm/Kconfig | 10 -
arch/arm/cpu/arm926ejs/Makefile | 1 -
arch/arm/cpu/arm926ejs/armada100/Makefile | 9 -
arch/arm/cpu/arm926ejs/armada100/cpu.c | 92 ---
arch/arm/cpu/arm926ejs/armada100/dram.c | 116 ----
arch/arm/cpu/arm926ejs/armada100/timer.c | 194 ------
arch/arm/include/asm/arch-armada100/armada100.h | 60 --
arch/arm/include/asm/arch-armada100/config.h | 42 --
arch/arm/include/asm/arch-armada100/cpu.h | 162 -----
arch/arm/include/asm/arch-armada100/gpio.h | 32 -
arch/arm/include/asm/arch-armada100/mfp.h | 80 ---
arch/arm/include/asm/arch-armada100/spi.h | 79 ---
.../include/asm/arch-armada100/utmi-armada100.h | 63 --
board/Marvell/aspenite/Kconfig | 15 -
board/Marvell/aspenite/MAINTAINERS | 6 -
board/Marvell/aspenite/Makefile | 10 -
board/Marvell/aspenite/aspenite.c | 43 --
board/Marvell/gplugd/Kconfig | 15 -
board/Marvell/gplugd/MAINTAINERS | 6 -
board/Marvell/gplugd/Makefile | 15 -
board/Marvell/gplugd/gplugd.c | 130 ----
configs/aspenite_defconfig | 2 -
configs/gplugd_defconfig | 2 -
doc/README.scrapyard | 2 +
drivers/net/Makefile | 1 -
drivers/net/armada100_fec.c | 726 ---------------------
drivers/net/armada100_fec.h | 209 ------
drivers/spi/Makefile | 1 -
drivers/spi/armada100_spi.c | 203 ------
drivers/usb/host/Makefile | 1 -
drivers/usb/host/ehci-armada100.c | 48 --
drivers/usb/host/utmi-armada100.c | 80 ---
include/configs/aspenite.h | 55 --
include/configs/gplugd.h | 134 ----
include/netdev.h | 1 -
35 files changed, 2 insertions(+), 2643 deletions(-)
delete mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile
delete mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c
delete mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c
delete mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c
delete mode 100644 arch/arm/include/asm/arch-armada100/armada100.h
delete mode 100644 arch/arm/include/asm/arch-armada100/config.h
delete mode 100644 arch/arm/include/asm/arch-armada100/cpu.h
delete mode 100644 arch/arm/include/asm/arch-armada100/gpio.h
delete mode 100644 arch/arm/include/asm/arch-armada100/mfp.h
delete mode 100644 arch/arm/include/asm/arch-armada100/spi.h
delete mode 100644 arch/arm/include/asm/arch-armada100/utmi-armada100.h
delete mode 100644 board/Marvell/aspenite/Kconfig
delete mode 100644 board/Marvell/aspenite/MAINTAINERS
delete mode 100644 board/Marvell/aspenite/Makefile
delete mode 100644 board/Marvell/aspenite/aspenite.c
delete mode 100644 board/Marvell/gplugd/Kconfig
delete mode 100644 board/Marvell/gplugd/MAINTAINERS
delete mode 100644 board/Marvell/gplugd/Makefile
delete mode 100644 board/Marvell/gplugd/gplugd.c
delete mode 100644 configs/aspenite_defconfig
delete mode 100644 configs/gplugd_defconfig
delete mode 100644 drivers/net/armada100_fec.c
delete mode 100644 drivers/net/armada100_fec.h
delete mode 100644 drivers/spi/armada100_spi.c
delete mode 100644 drivers/usb/host/ehci-armada100.c
delete mode 100644 drivers/usb/host/utmi-armada100.c
delete mode 100644 include/configs/aspenite.h
delete mode 100644 include/configs/gplugd.h
Is it late to send patch for these boards? These boards are generic boards but SYS_GENERIC_BOARD config is not enabled for them. Sorry for being late but Can I send patches now to keep this alive?
Regards,
Ajay Bhargav
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 09/11] ARM: armada100: remove aspenite and gplugd board support
2015-02-10 5:06 ` Ajay Bhargav
@ 2015-02-10 5:11 ` Prafulla Wadaskar
2015-02-10 5:13 ` Masahiro Yamada
1 sibling, 0 replies; 15+ messages in thread
From: Prafulla Wadaskar @ 2015-02-10 5:11 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Ajay Bhargav [mailto:ajay.bhargav at einfochips.com]
> Sent: 10 February 2015 10:37
> To: Masahiro Yamada; u-boot at lists.denx.de
> Cc: Tom Rini; Albert Aribaud; Prafulla Wadaskar; Roman Byshko; Matthias
> Fuchs; Marek Vasut; Ivan Khoronzhuk; Jiandong Zheng; Oleksandr Tymoshenko;
> Jagannadha Sutradharudu Teki; Joe Hershberger; Sergey Kostanbaev; Steve
> Rae; WingMan Kwok; Siva Durga Prasad Paladugu; Stefan Roese; Michal Simek;
> Nobuhiro Iwamatsu; Simon Glass; Wolfgang Denk; Ian Campbell; Georges
> Savoundararadj; Daniel Schwierzeck
> Subject: Re: [PATCH 09/11] ARM: armada100: remove aspenite and gplugd
> board support
>
>
> ________________________________________
> From: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Sent: Tuesday, February 10, 2015 10:14 AM
> To: u-boot at lists.denx.de
> Cc: Tom Rini; Albert Aribaud; Masahiro Yamada; Prafulla Wadaskar; Ajay
> Bhargav; Roman Byshko; Matthias Fuchs; Marek Vasut; Ivan Khoronzhuk;
> Jiandong Zheng; Oleksandr Tymoshenko; Jagannadha Sutradharudu Teki; Joe
> Hershberger; Sergey Kostanbaev; Steve Rae; WingMan Kwok; Siva Durga Prasad
> Paladugu; Stefan Roese; Michal Simek; Nobuhiro Iwamatsu; Simon Glass;
> Wolfgang Denk; Ian Campbell; Georges Savoundararadj; Daniel Schwierzeck
> Subject: [PATCH 09/11] ARM: armada100: remove aspenite and gplugd board
> support
>
> These are still non-generic boards.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Prafulla Wadaskar <prafulla@marvell.com>
> Cc: Ajay Bhargav <ajay.bhargav@einfochips.com>
> ---
>
> arch/arm/Kconfig | 10 -
> arch/arm/cpu/arm926ejs/Makefile | 1 -
> arch/arm/cpu/arm926ejs/armada100/Makefile | 9 -
> arch/arm/cpu/arm926ejs/armada100/cpu.c | 92 ---
> arch/arm/cpu/arm926ejs/armada100/dram.c | 116 ----
> arch/arm/cpu/arm926ejs/armada100/timer.c | 194 ------
> arch/arm/include/asm/arch-armada100/armada100.h | 60 --
> arch/arm/include/asm/arch-armada100/config.h | 42 --
> arch/arm/include/asm/arch-armada100/cpu.h | 162 -----
> arch/arm/include/asm/arch-armada100/gpio.h | 32 -
> arch/arm/include/asm/arch-armada100/mfp.h | 80 ---
> arch/arm/include/asm/arch-armada100/spi.h | 79 ---
> .../include/asm/arch-armada100/utmi-armada100.h | 63 --
> board/Marvell/aspenite/Kconfig | 15 -
> board/Marvell/aspenite/MAINTAINERS | 6 -
> board/Marvell/aspenite/Makefile | 10 -
> board/Marvell/aspenite/aspenite.c | 43 --
> board/Marvell/gplugd/Kconfig | 15 -
> board/Marvell/gplugd/MAINTAINERS | 6 -
> board/Marvell/gplugd/Makefile | 15 -
> board/Marvell/gplugd/gplugd.c | 130 ----
> configs/aspenite_defconfig | 2 -
> configs/gplugd_defconfig | 2 -
> doc/README.scrapyard | 2 +
> drivers/net/Makefile | 1 -
> drivers/net/armada100_fec.c | 726 ----------------
> -----
> drivers/net/armada100_fec.h | 209 ------
> drivers/spi/Makefile | 1 -
> drivers/spi/armada100_spi.c | 203 ------
> drivers/usb/host/Makefile | 1 -
> drivers/usb/host/ehci-armada100.c | 48 --
> drivers/usb/host/utmi-armada100.c | 80 ---
> include/configs/aspenite.h | 55 --
> include/configs/gplugd.h | 134 ----
> include/netdev.h | 1 -
> 35 files changed, 2 insertions(+), 2643 deletions(-) delete mode 100644
> arch/arm/cpu/arm926ejs/armada100/Makefile
> delete mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c
> delete mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c
> delete mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c
> delete mode 100644 arch/arm/include/asm/arch-armada100/armada100.h
> delete mode 100644 arch/arm/include/asm/arch-armada100/config.h
> delete mode 100644 arch/arm/include/asm/arch-armada100/cpu.h
> delete mode 100644 arch/arm/include/asm/arch-armada100/gpio.h
> delete mode 100644 arch/arm/include/asm/arch-armada100/mfp.h
> delete mode 100644 arch/arm/include/asm/arch-armada100/spi.h
> delete mode 100644 arch/arm/include/asm/arch-armada100/utmi-armada100.h
> delete mode 100644 board/Marvell/aspenite/Kconfig delete mode 100644
> board/Marvell/aspenite/MAINTAINERS
> delete mode 100644 board/Marvell/aspenite/Makefile delete mode 100644
> board/Marvell/aspenite/aspenite.c delete mode 100644
> board/Marvell/gplugd/Kconfig delete mode 100644
> board/Marvell/gplugd/MAINTAINERS delete mode 100644
> board/Marvell/gplugd/Makefile delete mode 100644
> board/Marvell/gplugd/gplugd.c delete mode 100644
> configs/aspenite_defconfig delete mode 100644 configs/gplugd_defconfig
> delete mode 100644 drivers/net/armada100_fec.c delete mode 100644
> drivers/net/armada100_fec.h delete mode 100644
> drivers/spi/armada100_spi.c delete mode 100644 drivers/usb/host/ehci-
> armada100.c delete mode 100644 drivers/usb/host/utmi-armada100.c delete
> mode 100644 include/configs/aspenite.h delete mode 100644
> include/configs/gplugd.h
>
> Is it late to send patch for these boards? These boards are generic boards
> but SYS_GENERIC_BOARD config is not enabled for them. Sorry for being late
> but Can I send patches now to keep this alive?
Dear Ajay,
I feel we must maintain them, if they are alive.
You are not blocked to send the patches. Patches are always welcomed.
Regards...
Prafulla . . .
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 09/11] ARM: armada100: remove aspenite and gplugd board support
2015-02-10 5:06 ` Ajay Bhargav
2015-02-10 5:11 ` Prafulla Wadaskar
@ 2015-02-10 5:13 ` Masahiro Yamada
1 sibling, 0 replies; 15+ messages in thread
From: Masahiro Yamada @ 2015-02-10 5:13 UTC (permalink / raw)
To: u-boot
Hi Ajay,
On Tue, 10 Feb 2015 05:06:45 +0000
Ajay Bhargav <ajay.bhargav@einfochips.com> wrote:
>
> ________________________________________
> From: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Sent: Tuesday, February 10, 2015 10:14 AM
> To: u-boot at lists.denx.de
> Cc: Tom Rini; Albert Aribaud; Masahiro Yamada; Prafulla Wadaskar; Ajay Bhargav; Roman Byshko; Matthias Fuchs; Marek Vasut; Ivan Khoronzhuk; Jiandong Zheng; Oleksandr Tymoshenko; Jagannadha Sutradharudu Teki; Joe Hershberger; Sergey Kostanbaev; Steve Rae; WingMan Kwok; Siva Durga Prasad Paladugu; Stefan Roese; Michal Simek; Nobuhiro Iwamatsu; Simon Glass; Wolfgang Denk; Ian Campbell; Georges Savoundararadj; Daniel Schwierzeck
> Subject: [PATCH 09/11] ARM: armada100: remove aspenite and gplugd board support
>
> These are still non-generic boards.
>
> Is it late to send patch for these boards? These boards are generic boards but SYS_GENERIC_BOARD config is not enabled for them. Sorry for being late but Can I send patches now to keep this alive?
Thanks for your reply.
It is not too late at all.
Please send a patch to keep these boards.
And then I will take back this patch.
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2015-02-10 5:13 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-02-10 4:44 [U-Boot] [PATCH 0/11] ARM: remove non-generic boards Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 01/11] ARM: remove mx31ads board support Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 02/11] ARM: mx31: remove imx31_phycore board Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 03/11] ARM: remove jadecpu board support Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 04/11] ARM: remove zmx25 " Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 05/11] ARM: remove devkit3250 " Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 06/11] ARM: remove dkb " Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 07/11] ARM: remove cm4008 and cm41xx " Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 08/11] ARM: remove a320evb " Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 09/11] ARM: armada100: remove aspenite and gplugd " Masahiro Yamada
2015-02-10 5:06 ` Ajay Bhargav
2015-02-10 5:11 ` Prafulla Wadaskar
2015-02-10 5:13 ` Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 10/11] ARM: remove tnetv107x " Masahiro Yamada
2015-02-10 4:44 ` [U-Boot] [PATCH 11/11] ARM: davinci: remove hawkboard support Masahiro Yamada
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