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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: rth@twiddle.net
Subject: [Qemu-devel] [PATCH v2 1/6] target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper
Date: Wed, 11 Feb 2015 16:48:58 +0000	[thread overview]
Message-ID: <1423673343-25688-2-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1423673343-25688-1-git-send-email-kbastian@mail.uni-paderborn.de>

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index a73b700..cfd6a77 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -4183,10 +4183,10 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
 
     switch (op1) {
     case OPC1_32_RLC_ADDI:
-        gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
+        gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
         break;
     case OPC1_32_RLC_ADDIH:
-        gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
+        gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
         break;
     case OPC1_32_RLC_ADDIH_A:
         tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
-- 
2.3.0

  reply	other threads:[~2015-02-11 15:48 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-11 16:48 [Qemu-devel] [PATCH v2 0/6] TriCore: Add RRR1 and RRR2 instructions Bastian Koppelmann
2015-02-11 16:48 ` Bastian Koppelmann [this message]
2015-02-11 16:48 ` [Qemu-devel] [PATCH v2 2/6] target-tricore: fix msub32_suov return wrong results Bastian Koppelmann
2015-02-11 16:49 ` [Qemu-devel] [PATCH v2 3/6] target-tricore: Add instructions of RRR2 opcode format Bastian Koppelmann
2015-02-17 19:56   ` Richard Henderson
2015-02-18  0:06     ` Bastian Koppelmann
2015-02-11 16:49 ` [Qemu-devel] [PATCH v2 4/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode Bastian Koppelmann
2015-02-11 16:49 ` [Qemu-devel] [PATCH v2 5/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x43 " Bastian Koppelmann
2015-02-11 16:49 ` [Qemu-devel] [PATCH v2 6/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 " Bastian Koppelmann
2015-02-17 13:17 ` [Qemu-devel] [PATCH v2 0/6] TriCore: Add RRR1 and RRR2 instructions Bastian Koppelmann
2015-02-17 20:12 ` Richard Henderson

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