[PATCH 00/12] drm/i915: Redo VLV/CHV watermark code

[PATCH 00/12] drm/i915: Redo VLV/CHV watermark code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The main motivation behind this series is to get the display to be stable
on CHV. Some new memory power savings features got enabled on later
steppings/BIOS versions which caused all kinds of display troubles
with our current code.

There are still a few known (at least known to me) display blink issues
left after this series, but those have something to do with the PHY, and
I'll post another series to address them.

Vidya Srinivas (1):
  drm/i915: Program PFI credits for VLV

Ville Syrjälä (11):
  drm/i915: Reduce CHV DDL multiplier to 16/8
  drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines
  drm/i915: Simplify VLV drain latency computation
  drm/i915: Hide VLV DDL precision handling
  drm/i915: Reorganize VLV DDL setup
  drm/i915: Pass plane to vlv_compute_drain_latency()
  drm/i915: Read out display FIFO size on VLV/CHV
  drm/i915: Make sure PND deadline mode is enabled on VLV/CHV
  drm/i915: Rewrite VLV/CHV watermark code
  drm/i915: Support maxfifo with two planes on CHV
  drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV

 drivers/gpu/drm/i915/i915_drv.h      |  20 ++
 drivers/gpu/drm/i915/i915_reg.h      |  32 ++-
 drivers/gpu/drm/i915/intel_display.c |  33 +++
 drivers/gpu/drm/i915/intel_pm.c      | 537 ++++++++++++++++++++---------------
 4 files changed, 385 insertions(+), 237 deletions(-)

-- 
2.0.5

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[PATCH 01/12] drm/i915: Reduce CHV DDL multiplier to 16/8

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Apparently we must yet halve the DDL drain latency from what we're
using currently. This little nugget is not in any spec, but came
down through the grapevine.

This makes the displays a bit more stable. Not quite fully stable but at
least they don't fall over immediately on driver load.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 6 +++---
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4ee1964..d8a0205 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4166,6 +4166,7 @@ enum skl_disp_power_wells {
 #define   DSPFW_PLANEA_WM1_HI_MASK	(1<<0)
 
 /* drain latency register values*/
+#define DRAIN_LATENCY_PRECISION_8	8
 #define DRAIN_LATENCY_PRECISION_16	16
 #define DRAIN_LATENCY_PRECISION_32	32
 #define DRAIN_LATENCY_PRECISION_64	64
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3c64810..a70bce4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -728,8 +728,8 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
 
 	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
 	if (IS_CHERRYVIEW(dev))
-		*prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 :
-					       DRAIN_LATENCY_PRECISION_16;
+		*prec_mult = (entries > 32) ? DRAIN_LATENCY_PRECISION_16 :
+					      DRAIN_LATENCY_PRECISION_8;
 	else
 		*prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
 					       DRAIN_LATENCY_PRECISION_32;
@@ -759,7 +759,7 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
 	enum pipe pipe = intel_crtc->pipe;
 	int plane_prec, prec_mult, plane_dl;
 	const int high_precision = IS_CHERRYVIEW(dev) ?
-		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
+		DRAIN_LATENCY_PRECISION_16 : DRAIN_LATENCY_PRECISION_64;
 
 	plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
 		   DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
-- 
2.0.5

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Re: [PATCH 01/12] drm/i915: Reduce CHV DDL multiplier to 16/8

[Jesse Barnes]

On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Apparently we must yet halve the DDL drain latency from what we're
> using currently. This little nugget is not in any spec, but came
> down through the grapevine.
> 
> This makes the displays a bit more stable. Not quite fully stable but at
> least they don't fall over immediately on driver load.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  drivers/gpu/drm/i915/intel_pm.c | 6 +++---
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4ee1964..d8a0205 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4166,6 +4166,7 @@ enum skl_disp_power_wells {
>  #define   DSPFW_PLANEA_WM1_HI_MASK	(1<<0)
>  
>  /* drain latency register values*/
> +#define DRAIN_LATENCY_PRECISION_8	8
>  #define DRAIN_LATENCY_PRECISION_16	16
>  #define DRAIN_LATENCY_PRECISION_32	32
>  #define DRAIN_LATENCY_PRECISION_64	64
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3c64810..a70bce4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -728,8 +728,8 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
>  
>  	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
>  	if (IS_CHERRYVIEW(dev))
> -		*prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 :
> -					       DRAIN_LATENCY_PRECISION_16;
> +		*prec_mult = (entries > 32) ? DRAIN_LATENCY_PRECISION_16 :
> +					      DRAIN_LATENCY_PRECISION_8;
>  	else
>  		*prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
>  					       DRAIN_LATENCY_PRECISION_32;
> @@ -759,7 +759,7 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
>  	enum pipe pipe = intel_crtc->pipe;
>  	int plane_prec, prec_mult, plane_dl;
>  	const int high_precision = IS_CHERRYVIEW(dev) ?
> -		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
> +		DRAIN_LATENCY_PRECISION_16 : DRAIN_LATENCY_PRECISION_64;
>  
>  	plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
>  		   DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
> 

You're also changing the entries threshold; is that due to the reduced
drain latency precsion also?

Would be good to file a bspec bug on this so we don't lose it.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 01/12] drm/i915: Reduce CHV DDL multiplier to 16/8

[Ville Syrjälä]

On Fri, Feb 27, 2015 at 09:36:58AM -0800, Jesse Barnes wrote:
> On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Apparently we must yet halve the DDL drain latency from what we're
> > using currently. This little nugget is not in any spec, but came
> > down through the grapevine.
> > 
> > This makes the displays a bit more stable. Not quite fully stable but at
> > least they don't fall over immediately on driver load.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 1 +
> >  drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> >  2 files changed, 4 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 4ee1964..d8a0205 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4166,6 +4166,7 @@ enum skl_disp_power_wells {
> >  #define   DSPFW_PLANEA_WM1_HI_MASK	(1<<0)
> >  
> >  /* drain latency register values*/
> > +#define DRAIN_LATENCY_PRECISION_8	8
> >  #define DRAIN_LATENCY_PRECISION_16	16
> >  #define DRAIN_LATENCY_PRECISION_32	32
> >  #define DRAIN_LATENCY_PRECISION_64	64
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 3c64810..a70bce4 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -728,8 +728,8 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
> >  
> >  	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
> >  	if (IS_CHERRYVIEW(dev))
> > -		*prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 :
> > -					       DRAIN_LATENCY_PRECISION_16;
> > +		*prec_mult = (entries > 32) ? DRAIN_LATENCY_PRECISION_16 :
> > +					      DRAIN_LATENCY_PRECISION_8;
> >  	else
> >  		*prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
> >  					       DRAIN_LATENCY_PRECISION_32;
> > @@ -759,7 +759,7 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
> >  	enum pipe pipe = intel_crtc->pipe;
> >  	int plane_prec, prec_mult, plane_dl;
> >  	const int high_precision = IS_CHERRYVIEW(dev) ?
> > -		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
> > +		DRAIN_LATENCY_PRECISION_16 : DRAIN_LATENCY_PRECISION_64;
> >  
> >  	plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
> >  		   DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
> > 
> 
> You're also changing the entries threshold; is that due to the reduced
> drain latency precsion also?
> 
> Would be good to file a bspec bug on this so we don't lose it.

The spec just says we should choose the precision so that we don't exceed
7bits in the final value. So the 128 was just needleslly large and we
were just throwing away a useful bit by choosing to use the smaller precision
factor when we didn't have to. But I'm killing off these constants anyway
in a later patch to make the code less confusing.

> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 01/12] drm/i915: Reduce CHV DDL multiplier to 16/8

[Arun R Murthy]

>
> From: Ville Syrjälä<ville.syrjala@linux.intel.com>
>
> Apparently we must yet halve the DDL drain latency from what we're
> using currently. This little nugget is not in any spec, but came
> down through the grapevine.
>
> This makes the displays a bit more stable. Not quite fully stable but at
> least they don't fall over immediately on driver load.
>
> Signed-off-by: Ville Syrjälä<ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 1 +
>   drivers/gpu/drm/i915/intel_pm.c | 6 +++---
>   2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4ee1964..d8a0205 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4166,6 +4166,7 @@ enum skl_disp_power_wells {
>   #define   DSPFW_PLANEA_WM1_HI_MASK	(1<<0)
>   
>   /* drain latency register values*/
> +#define DRAIN_LATENCY_PRECISION_8	8
>   #define DRAIN_LATENCY_PRECISION_16	16
>   #define DRAIN_LATENCY_PRECISION_32	32
>   #define DRAIN_LATENCY_PRECISION_64	64
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3c64810..a70bce4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -728,8 +728,8 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
>   
>   	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
>   	if (IS_CHERRYVIEW(dev))
> -		*prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 :
> -					       DRAIN_LATENCY_PRECISION_16;
> +		*prec_mult = (entries > 32) ? DRAIN_LATENCY_PRECISION_16 :
> +					      DRAIN_LATENCY_PRECISION_8;
>   	else
>   		*prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
>   					       DRAIN_LATENCY_PRECISION_32;
> @@ -759,7 +759,7 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
>   	enum pipe pipe = intel_crtc->pipe;
>   	int plane_prec, prec_mult, plane_dl;
>   	const int high_precision = IS_CHERRYVIEW(dev) ?
> -		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
The spec says that the drain latency precision are 32 and 16.
But just to be safe and have a stable environment, we further divide the
calculated DDL by 2 but precision remains the same 32 and 16.

Thanks and Regards,
Arun R Murthy
-------------------

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[PATCH 02/12] drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Kill the silly DRAIN_LATENCY_PRECISION_* defines and just use the raw
number instead.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  4 ----
 drivers/gpu/drm/i915/intel_pm.c | 12 ++++--------
 2 files changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d8a0205..230320b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4166,10 +4166,6 @@ enum skl_disp_power_wells {
 #define   DSPFW_PLANEA_WM1_HI_MASK	(1<<0)
 
 /* drain latency register values*/
-#define DRAIN_LATENCY_PRECISION_8	8
-#define DRAIN_LATENCY_PRECISION_16	16
-#define DRAIN_LATENCY_PRECISION_32	32
-#define DRAIN_LATENCY_PRECISION_64	64
 #define VLV_DDL(pipe)			(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
 #define DDL_CURSOR_PRECISION_HIGH	(1<<31)
 #define DDL_CURSOR_PRECISION_LOW	(0<<31)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a70bce4..0f0281a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -728,11 +728,9 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
 
 	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
 	if (IS_CHERRYVIEW(dev))
-		*prec_mult = (entries > 32) ? DRAIN_LATENCY_PRECISION_16 :
-					      DRAIN_LATENCY_PRECISION_8;
+		*prec_mult = (entries > 32) ? 16 : 8;
 	else
-		*prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
-					       DRAIN_LATENCY_PRECISION_32;
+		*prec_mult = (entries > 128) ? 64 : 32;
 	*drain_latency = (64 * (*prec_mult) * 4) / entries;
 
 	if (*drain_latency > DRAIN_LATENCY_MASK)
@@ -758,8 +756,7 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
 	int drain_latency;
 	enum pipe pipe = intel_crtc->pipe;
 	int plane_prec, prec_mult, plane_dl;
-	const int high_precision = IS_CHERRYVIEW(dev) ?
-		DRAIN_LATENCY_PRECISION_16 : DRAIN_LATENCY_PRECISION_64;
+	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
 
 	plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
 		   DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
@@ -957,8 +954,7 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
 	int plane_prec;
 	int sprite_dl;
 	int prec_mult;
-	const int high_precision = IS_CHERRYVIEW(dev) ?
-		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
+	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
 
 	sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) |
 		    (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
-- 
2.0.5

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Re: [PATCH 02/12] drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines

[Jesse Barnes]

On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> @@ -957,8 +954,7 @@ static void valleyview_update_sprite_wm(struct
drm_plane *plane,
>  	int plane_prec;
>  	int sprite_dl;
>  	int prec_mult;
> -	const int high_precision = IS_CHERRYVIEW(dev) ?
> -		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
> +	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
>  
>  	sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) |
>  		    (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
> 

This hunk changes things; did it belong in the earlier patch?

With that explained:
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 02/12] drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines

[Ville Syrjälä]

On Fri, Feb 27, 2015 at 09:38:10AM -0800, Jesse Barnes wrote:
> On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> > @@ -957,8 +954,7 @@ static void valleyview_update_sprite_wm(struct
> drm_plane *plane,
> >  	int plane_prec;
> >  	int sprite_dl;
> >  	int prec_mult;
> > -	const int high_precision = IS_CHERRYVIEW(dev) ?
> > -		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
> > +	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
> >  
> >  	sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) |
> >  		    (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
> > 
> 
> This hunk changes things; did it belong in the earlier patch?

Yeah that should have been part of patch 1 already. I'll respin.

> 
> With that explained:
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Ville Syrjälä
Intel OTC
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[PATCH 03/12] drm/i915: Simplify VLV drain latency computation

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The current drain lantency computation relies on hardcoded limits to
determine when the to use the low vs. high precision multiplier.
Rewrite the code to use a more straightforward approach.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0f0281a..d6c6c1b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -727,12 +727,15 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
 		return false;
 
 	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
-	if (IS_CHERRYVIEW(dev))
-		*prec_mult = (entries > 32) ? 16 : 8;
-	else
-		*prec_mult = (entries > 128) ? 64 : 32;
+
+	*prec_mult = IS_CHERRYVIEW(dev) ? 16 : 64;
 	*drain_latency = (64 * (*prec_mult) * 4) / entries;
 
+	if (*drain_latency > DRAIN_LATENCY_MASK) {
+		*prec_mult /= 2;
+		*drain_latency = (64 * (*prec_mult) * 4) / entries;
+	}
+
 	if (*drain_latency > DRAIN_LATENCY_MASK)
 		*drain_latency = DRAIN_LATENCY_MASK;
 
-- 
2.0.5

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Re: [PATCH 03/12] drm/i915: Simplify VLV drain latency computation

[Jesse Barnes]

On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The current drain lantency computation relies on hardcoded limits to
> determine when the to use the low vs. high precision multiplier.
> Rewrite the code to use a more straightforward approach.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0f0281a..d6c6c1b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -727,12 +727,15 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
>  		return false;
>  
>  	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
> -	if (IS_CHERRYVIEW(dev))
> -		*prec_mult = (entries > 32) ? 16 : 8;
> -	else
> -		*prec_mult = (entries > 128) ? 64 : 32;
> +
> +	*prec_mult = IS_CHERRYVIEW(dev) ? 16 : 64;
>  	*drain_latency = (64 * (*prec_mult) * 4) / entries;
>  
> +	if (*drain_latency > DRAIN_LATENCY_MASK) {
> +		*prec_mult /= 2;
> +		*drain_latency = (64 * (*prec_mult) * 4) / entries;
> +	}
> +
>  	if (*drain_latency > DRAIN_LATENCY_MASK)
>  		*drain_latency = DRAIN_LATENCY_MASK;
>  
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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[PATCH 04/12] drm/i915: Hide VLV DDL precision handling

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move the DDL precision handling into vlv_compute_drain_latency() so the
callers don't have to duplicate the same code to deal with it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  8 ++---
 drivers/gpu/drm/i915/intel_pm.c | 74 +++++++++++++++--------------------------
 2 files changed, 28 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 230320b..b35aaf3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4167,15 +4167,11 @@ enum skl_disp_power_wells {
 
 /* drain latency register values*/
 #define VLV_DDL(pipe)			(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
-#define DDL_CURSOR_PRECISION_HIGH	(1<<31)
-#define DDL_CURSOR_PRECISION_LOW	(0<<31)
 #define DDL_CURSOR_SHIFT		24
-#define DDL_SPRITE_PRECISION_HIGH(sprite)	(1<<(15+8*(sprite)))
-#define DDL_SPRITE_PRECISION_LOW(sprite)	(0<<(15+8*(sprite)))
 #define DDL_SPRITE_SHIFT(sprite)	(8+8*(sprite))
-#define DDL_PLANE_PRECISION_HIGH	(1<<7)
-#define DDL_PLANE_PRECISION_LOW		(0<<7)
 #define DDL_PLANE_SHIFT			0
+#define DDL_PRECISION_HIGH		(1<<7)
+#define DDL_PRECISION_LOW		(0<<7)
 #define DRAIN_LATENCY_MASK		0x7f
 
 /* FIFO watermark sizes etc */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d6c6c1b..c4c2317 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -711,35 +711,35 @@ static bool g4x_compute_srwm(struct drm_device *dev,
 			      display, cursor);
 }
 
-static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
-				      int pixel_size,
-				      int *prec_mult,
-				      int *drain_latency)
+static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
+					 int pixel_size)
 {
 	struct drm_device *dev = crtc->dev;
-	int entries;
+	int entries, prec_mult, drain_latency;
 	int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
+	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
 
 	if (WARN(clock == 0, "Pixel clock is zero!\n"))
-		return false;
+		return 0;
 
 	if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
-		return false;
+		return 0;
 
 	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
 
-	*prec_mult = IS_CHERRYVIEW(dev) ? 16 : 64;
-	*drain_latency = (64 * (*prec_mult) * 4) / entries;
+	prec_mult = high_precision;
+	drain_latency = 64 * prec_mult * 4 / entries;
 
-	if (*drain_latency > DRAIN_LATENCY_MASK) {
-		*prec_mult /= 2;
-		*drain_latency = (64 * (*prec_mult) * 4) / entries;
+	if (drain_latency > DRAIN_LATENCY_MASK) {
+		prec_mult /= 2;
+		drain_latency = 64 * prec_mult * 4 / entries;
 	}
 
-	if (*drain_latency > DRAIN_LATENCY_MASK)
-		*drain_latency = DRAIN_LATENCY_MASK;
+	if (drain_latency > DRAIN_LATENCY_MASK)
+		drain_latency = DRAIN_LATENCY_MASK;
 
-	return true;
+	return drain_latency | (prec_mult == high_precision ?
+				DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
 }
 
 /*
@@ -756,14 +756,12 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pixel_size;
-	int drain_latency;
 	enum pipe pipe = intel_crtc->pipe;
-	int plane_prec, prec_mult, plane_dl;
-	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
+	int plane_dl;
 
-	plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
-		   DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
-		   (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
+	plane_dl = I915_READ(VLV_DDL(pipe)) &
+		~(((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << DDL_CURSOR_SHIFT) |
+		  ((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << DDL_PLANE_SHIFT));
 
 	if (!intel_crtc_active(crtc)) {
 		I915_WRITE(VLV_DDL(pipe), plane_dl);
@@ -772,12 +770,7 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
 
 	/* Primary plane Drain Latency */
 	pixel_size = crtc->primary->fb->bits_per_pixel / 8;	/* BPP */
-	if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
-		plane_prec = (prec_mult == high_precision) ?
-					   DDL_PLANE_PRECISION_HIGH :
-					   DDL_PLANE_PRECISION_LOW;
-		plane_dl |= plane_prec | drain_latency;
-	}
+	plane_dl = vlv_compute_drain_latency(crtc, pixel_size) << DDL_PLANE_SHIFT;
 
 	/* Cursor Drain Latency
 	 * BPP is always 4 for cursor
@@ -785,13 +778,8 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
 	pixel_size = 4;
 
 	/* Program cursor DL only if it is enabled */
-	if (intel_crtc->cursor_base &&
-	    vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
-		plane_prec = (prec_mult == high_precision) ?
-					   DDL_CURSOR_PRECISION_HIGH :
-					   DDL_CURSOR_PRECISION_LOW;
-		plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
-	}
+	if (intel_crtc->cursor_base)
+		plane_dl |= vlv_compute_drain_latency(crtc, pixel_size) << DDL_CURSOR_SHIFT;
 
 	I915_WRITE(VLV_DDL(pipe), plane_dl);
 }
@@ -953,23 +941,13 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe = to_intel_plane(plane)->pipe;
 	int sprite = to_intel_plane(plane)->plane;
-	int drain_latency;
-	int plane_prec;
 	int sprite_dl;
-	int prec_mult;
-	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
 
-	sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) |
-		    (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
+	sprite_dl = I915_READ(VLV_DDL(pipe)) &
+		~((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << DDL_SPRITE_SHIFT(sprite));
 
-	if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
-						 &drain_latency)) {
-		plane_prec = (prec_mult == high_precision) ?
-					   DDL_SPRITE_PRECISION_HIGH(sprite) :
-					   DDL_SPRITE_PRECISION_LOW(sprite);
-		sprite_dl |= plane_prec |
-			     (drain_latency << DDL_SPRITE_SHIFT(sprite));
-	}
+	if (enabled)
+		sprite_dl |= vlv_compute_drain_latency(crtc, pixel_size) << DDL_SPRITE_SHIFT(sprite);
 
 	I915_WRITE(VLV_DDL(pipe), sprite_dl);
 }
-- 
2.0.5

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Re: [PATCH 04/12] drm/i915: Hide VLV DDL precision handling

[Jesse Barnes]

On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Move the DDL precision handling into vlv_compute_drain_latency() so the
> callers don't have to duplicate the same code to deal with it.

A little painful due to the addition of the #define changes, but I think
it's right, and will actually be easier to fix if wrong anyway due to
the removal of duplication.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

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[PATCH 05/12] drm/i915: Reorganize VLV DDL setup

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Introduce struct vlv_wm_values to house VLV watermark/drain latency
values. We start by using it when computing the drain latency values.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  9 ++++++++
 drivers/gpu/drm/i915/intel_pm.c | 46 +++++++++++++++++++++++++++--------------
 2 files changed, 40 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 26ffe8b..5de69a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1514,6 +1514,14 @@ struct ilk_wm_values {
 	enum intel_ddb_partitioning partitioning;
 };
 
+struct vlv_wm_values {
+	struct {
+		uint8_t cursor;
+		uint8_t sprite[2];
+		uint8_t primary;
+	} ddl[3];
+};
+
 struct skl_ddb_entry {
 	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
 };
@@ -1870,6 +1878,7 @@ struct drm_i915_private {
 		union {
 			struct ilk_wm_values hw;
 			struct skl_wm_values skl_hw;
+			struct vlv_wm_values vlv;
 		};
 	} wm;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c4c2317..5515d10 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -711,6 +711,21 @@ static bool g4x_compute_srwm(struct drm_device *dev,
 			      display, cursor);
 }
 
+static void vlv_write_wm_values(struct intel_crtc *crtc,
+				const struct vlv_wm_values *wm)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+
+	I915_WRITE(VLV_DDL(pipe),
+		   (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
+		   (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
+		   (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
+		   (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
+
+	dev_priv->wm.vlv = *wm;
+}
+
 static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
 					 int pixel_size)
 {
@@ -757,20 +772,19 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pixel_size;
 	enum pipe pipe = intel_crtc->pipe;
-	int plane_dl;
+	struct vlv_wm_values wm = dev_priv->wm.vlv;
 
-	plane_dl = I915_READ(VLV_DDL(pipe)) &
-		~(((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << DDL_CURSOR_SHIFT) |
-		  ((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << DDL_PLANE_SHIFT));
+	wm.ddl[pipe].primary = 0;
+	wm.ddl[pipe].cursor = 0;
 
 	if (!intel_crtc_active(crtc)) {
-		I915_WRITE(VLV_DDL(pipe), plane_dl);
+		vlv_write_wm_values(intel_crtc, &wm);
 		return;
 	}
 
 	/* Primary plane Drain Latency */
 	pixel_size = crtc->primary->fb->bits_per_pixel / 8;	/* BPP */
-	plane_dl = vlv_compute_drain_latency(crtc, pixel_size) << DDL_PLANE_SHIFT;
+	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, pixel_size);
 
 	/* Cursor Drain Latency
 	 * BPP is always 4 for cursor
@@ -779,9 +793,10 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
 
 	/* Program cursor DL only if it is enabled */
 	if (intel_crtc->cursor_base)
-		plane_dl |= vlv_compute_drain_latency(crtc, pixel_size) << DDL_CURSOR_SHIFT;
+		wm.ddl[pipe].cursor =
+			vlv_compute_drain_latency(crtc, pixel_size);
 
-	I915_WRITE(VLV_DDL(pipe), plane_dl);
+	vlv_write_wm_values(intel_crtc, &wm);
 }
 
 #define single_plane_enabled(mask) is_power_of_2(mask)
@@ -939,17 +954,18 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int pipe = to_intel_plane(plane)->pipe;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum pipe pipe = intel_crtc->pipe;
 	int sprite = to_intel_plane(plane)->plane;
-	int sprite_dl;
-
-	sprite_dl = I915_READ(VLV_DDL(pipe)) &
-		~((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << DDL_SPRITE_SHIFT(sprite));
+	struct vlv_wm_values wm = dev_priv->wm.vlv;
 
 	if (enabled)
-		sprite_dl |= vlv_compute_drain_latency(crtc, pixel_size) << DDL_SPRITE_SHIFT(sprite);
+		wm.ddl[pipe].sprite[sprite] =
+			vlv_compute_drain_latency(crtc, pixel_size);
+	else
+		wm.ddl[pipe].sprite[sprite] = 0;
 
-	I915_WRITE(VLV_DDL(pipe), sprite_dl);
+	vlv_write_wm_values(intel_crtc, &wm);
 }
 
 static void g4x_update_wm(struct drm_crtc *crtc)
-- 
2.0.5

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Re: [PATCH 05/12] drm/i915: Reorganize VLV DDL setup

[Jesse Barnes]

On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Introduce struct vlv_wm_values to house VLV watermark/drain latency
> values. We start by using it when computing the drain latency values.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  9 ++++++++
>  drivers/gpu/drm/i915/intel_pm.c | 46 +++++++++++++++++++++++++++--------------
>  2 files changed, 40 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 26ffe8b..5de69a0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1514,6 +1514,14 @@ struct ilk_wm_values {
>  	enum intel_ddb_partitioning partitioning;
>  };
>  
> +struct vlv_wm_values {
> +	struct {
> +		uint8_t cursor;
> +		uint8_t sprite[2];
> +		uint8_t primary;
> +	} ddl[3];
> +};
> +
>  struct skl_ddb_entry {
>  	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
>  };
> @@ -1870,6 +1878,7 @@ struct drm_i915_private {
>  		union {
>  			struct ilk_wm_values hw;
>  			struct skl_wm_values skl_hw;
> +			struct vlv_wm_values vlv;
>  		};
>  	} wm;
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c4c2317..5515d10 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -711,6 +711,21 @@ static bool g4x_compute_srwm(struct drm_device *dev,
>  			      display, cursor);
>  }
>  
> +static void vlv_write_wm_values(struct intel_crtc *crtc,
> +				const struct vlv_wm_values *wm)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
> +
> +	I915_WRITE(VLV_DDL(pipe),
> +		   (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
> +		   (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
> +		   (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
> +		   (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
> +
> +	dev_priv->wm.vlv = *wm;
> +}
> +
>  static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
>  					 int pixel_size)
>  {
> @@ -757,20 +772,19 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	int pixel_size;
>  	enum pipe pipe = intel_crtc->pipe;
> -	int plane_dl;
> +	struct vlv_wm_values wm = dev_priv->wm.vlv;
>  
> -	plane_dl = I915_READ(VLV_DDL(pipe)) &
> -		~(((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << DDL_CURSOR_SHIFT) |
> -		  ((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << DDL_PLANE_SHIFT));
> +	wm.ddl[pipe].primary = 0;
> +	wm.ddl[pipe].cursor = 0;
>  
>  	if (!intel_crtc_active(crtc)) {
> -		I915_WRITE(VLV_DDL(pipe), plane_dl);
> +		vlv_write_wm_values(intel_crtc, &wm);
>  		return;
>  	}
>  
>  	/* Primary plane Drain Latency */
>  	pixel_size = crtc->primary->fb->bits_per_pixel / 8;	/* BPP */
> -	plane_dl = vlv_compute_drain_latency(crtc, pixel_size) << DDL_PLANE_SHIFT;
> +	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, pixel_size);
>  
>  	/* Cursor Drain Latency
>  	 * BPP is always 4 for cursor
> @@ -779,9 +793,10 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
>  
>  	/* Program cursor DL only if it is enabled */
>  	if (intel_crtc->cursor_base)
> -		plane_dl |= vlv_compute_drain_latency(crtc, pixel_size) << DDL_CURSOR_SHIFT;
> +		wm.ddl[pipe].cursor =
> +			vlv_compute_drain_latency(crtc, pixel_size);
>  
> -	I915_WRITE(VLV_DDL(pipe), plane_dl);
> +	vlv_write_wm_values(intel_crtc, &wm);
>  }
>  
>  #define single_plane_enabled(mask) is_power_of_2(mask)
> @@ -939,17 +954,18 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
>  {
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int pipe = to_intel_plane(plane)->pipe;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	enum pipe pipe = intel_crtc->pipe;
>  	int sprite = to_intel_plane(plane)->plane;
> -	int sprite_dl;
> -
> -	sprite_dl = I915_READ(VLV_DDL(pipe)) &
> -		~((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << DDL_SPRITE_SHIFT(sprite));
> +	struct vlv_wm_values wm = dev_priv->wm.vlv;
>  
>  	if (enabled)
> -		sprite_dl |= vlv_compute_drain_latency(crtc, pixel_size) << DDL_SPRITE_SHIFT(sprite);
> +		wm.ddl[pipe].sprite[sprite] =
> +			vlv_compute_drain_latency(crtc, pixel_size);
> +	else
> +		wm.ddl[pipe].sprite[sprite] = 0;
>  
> -	I915_WRITE(VLV_DDL(pipe), sprite_dl);
> +	vlv_write_wm_values(intel_crtc, &wm);
>  }
>  
>  static void g4x_update_wm(struct drm_crtc *crtc)
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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[PATCH 06/12] drm/i915: Pass plane to vlv_compute_drain_latency()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that we have drm_planes for the cursor and primary we can move the
pixel_size handling into vlv_compute_drain_latency() and just pass the
appropriate plane to it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 42 ++++++++++++++++-------------------------
 1 file changed, 16 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5515d10..fffcf64 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -727,16 +727,26 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
 }
 
 static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
-					 int pixel_size)
+					 struct drm_plane *plane)
 {
 	struct drm_device *dev = crtc->dev;
-	int entries, prec_mult, drain_latency;
-	int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int entries, prec_mult, drain_latency, pixel_size;
+	int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
 	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
 
+	/*
+	 * FIXME the plane might have an fb
+	 * but be invisible (eg. due to clipping)
+	 */
+	if (!intel_crtc->active || !plane->fb)
+		return 0;
+
 	if (WARN(clock == 0, "Pixel clock is zero!\n"))
 		return 0;
 
+	pixel_size = drm_format_plane_cpp(plane->fb->pixel_format, 0);
+
 	if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
 		return 0;
 
@@ -770,31 +780,11 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int pixel_size;
 	enum pipe pipe = intel_crtc->pipe;
 	struct vlv_wm_values wm = dev_priv->wm.vlv;
 
-	wm.ddl[pipe].primary = 0;
-	wm.ddl[pipe].cursor = 0;
-
-	if (!intel_crtc_active(crtc)) {
-		vlv_write_wm_values(intel_crtc, &wm);
-		return;
-	}
-
-	/* Primary plane Drain Latency */
-	pixel_size = crtc->primary->fb->bits_per_pixel / 8;	/* BPP */
-	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, pixel_size);
-
-	/* Cursor Drain Latency
-	 * BPP is always 4 for cursor
-	 */
-	pixel_size = 4;
-
-	/* Program cursor DL only if it is enabled */
-	if (intel_crtc->cursor_base)
-		wm.ddl[pipe].cursor =
-			vlv_compute_drain_latency(crtc, pixel_size);
+	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
+	wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
 
 	vlv_write_wm_values(intel_crtc, &wm);
 }
@@ -961,7 +951,7 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
 
 	if (enabled)
 		wm.ddl[pipe].sprite[sprite] =
-			vlv_compute_drain_latency(crtc, pixel_size);
+			vlv_compute_drain_latency(crtc, plane);
 	else
 		wm.ddl[pipe].sprite[sprite] = 0;
 
-- 
2.0.5

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Re: [PATCH 06/12] drm/i915: Pass plane to vlv_compute_drain_latency()

[Jesse Barnes]

On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Now that we have drm_planes for the cursor and primary we can move the
> pixel_size handling into vlv_compute_drain_latency() and just pass the
> appropriate plane to it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 42 ++++++++++++++++-------------------------
>  1 file changed, 16 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5515d10..fffcf64 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -727,16 +727,26 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
>  }
>  
>  static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
> -					 int pixel_size)
> +					 struct drm_plane *plane)
>  {
>  	struct drm_device *dev = crtc->dev;
> -	int entries, prec_mult, drain_latency;
> -	int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	int entries, prec_mult, drain_latency, pixel_size;
> +	int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
>  	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
>  
> +	/*
> +	 * FIXME the plane might have an fb
> +	 * but be invisible (eg. due to clipping)
> +	 */
> +	if (!intel_crtc->active || !plane->fb)
> +		return 0;
> +
>  	if (WARN(clock == 0, "Pixel clock is zero!\n"))
>  		return 0;
>  
> +	pixel_size = drm_format_plane_cpp(plane->fb->pixel_format, 0);
> +
>  	if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
>  		return 0;
>  
> @@ -770,31 +780,11 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	int pixel_size;
>  	enum pipe pipe = intel_crtc->pipe;
>  	struct vlv_wm_values wm = dev_priv->wm.vlv;
>  
> -	wm.ddl[pipe].primary = 0;
> -	wm.ddl[pipe].cursor = 0;
> -
> -	if (!intel_crtc_active(crtc)) {
> -		vlv_write_wm_values(intel_crtc, &wm);
> -		return;
> -	}
> -
> -	/* Primary plane Drain Latency */
> -	pixel_size = crtc->primary->fb->bits_per_pixel / 8;	/* BPP */
> -	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, pixel_size);
> -
> -	/* Cursor Drain Latency
> -	 * BPP is always 4 for cursor
> -	 */
> -	pixel_size = 4;
> -
> -	/* Program cursor DL only if it is enabled */
> -	if (intel_crtc->cursor_base)
> -		wm.ddl[pipe].cursor =
> -			vlv_compute_drain_latency(crtc, pixel_size);
> +	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
> +	wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
>  
>  	vlv_write_wm_values(intel_crtc, &wm);
>  }
> @@ -961,7 +951,7 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
>  
>  	if (enabled)
>  		wm.ddl[pipe].sprite[sprite] =
> -			vlv_compute_drain_latency(crtc, pixel_size);
> +			vlv_compute_drain_latency(crtc, plane);
>  	else
>  		wm.ddl[pipe].sprite[sprite] = 0;
>  
> 

Nice.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 06/12] drm/i915: Pass plane to vlv_compute_drain_latency()

[Ville Syrjälä]

On Fri, Feb 27, 2015 at 09:57:20AM -0800, Jesse Barnes wrote:
> On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Now that we have drm_planes for the cursor and primary we can move the
> > pixel_size handling into vlv_compute_drain_latency() and just pass the
> > appropriate plane to it.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 42 ++++++++++++++++-------------------------
> >  1 file changed, 16 insertions(+), 26 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 5515d10..fffcf64 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -727,16 +727,26 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
> >  }
> >  
> >  static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
> > -					 int pixel_size)
> > +					 struct drm_plane *plane)
> >  {
> >  	struct drm_device *dev = crtc->dev;
> > -	int entries, prec_mult, drain_latency;
> > -	int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > +	int entries, prec_mult, drain_latency, pixel_size;
> > +	int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
> >  	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
> >  
> > +	/*
> > +	 * FIXME the plane might have an fb
> > +	 * but be invisible (eg. due to clipping)
> > +	 */
> > +	if (!intel_crtc->active || !plane->fb)
> > +		return 0;
> > +
> >  	if (WARN(clock == 0, "Pixel clock is zero!\n"))
> >  		return 0;
> >  
> > +	pixel_size = drm_format_plane_cpp(plane->fb->pixel_format, 0);
> > +
> >  	if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
> >  		return 0;
> >  
> > @@ -770,31 +780,11 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
> >  	struct drm_device *dev = crtc->dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -	int pixel_size;
> >  	enum pipe pipe = intel_crtc->pipe;
> >  	struct vlv_wm_values wm = dev_priv->wm.vlv;
> >  
> > -	wm.ddl[pipe].primary = 0;
> > -	wm.ddl[pipe].cursor = 0;
> > -
> > -	if (!intel_crtc_active(crtc)) {
> > -		vlv_write_wm_values(intel_crtc, &wm);
> > -		return;
> > -	}
> > -
> > -	/* Primary plane Drain Latency */
> > -	pixel_size = crtc->primary->fb->bits_per_pixel / 8;	/* BPP */
> > -	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, pixel_size);
> > -
> > -	/* Cursor Drain Latency
> > -	 * BPP is always 4 for cursor
> > -	 */
> > -	pixel_size = 4;
> > -
> > -	/* Program cursor DL only if it is enabled */
> > -	if (intel_crtc->cursor_base)
> > -		wm.ddl[pipe].cursor =
> > -			vlv_compute_drain_latency(crtc, pixel_size);
> > +	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
> > +	wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
> >  
> >  	vlv_write_wm_values(intel_crtc, &wm);
> >  }
> > @@ -961,7 +951,7 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
> >  
> >  	if (enabled)
> >  		wm.ddl[pipe].sprite[sprite] =
> > -			vlv_compute_drain_latency(crtc, pixel_size);
> > +			vlv_compute_drain_latency(crtc, plane);
> >  	else
> >  		wm.ddl[pipe].sprite[sprite] = 0;
> >  
> > 
> 
> Nice.

Actually this is going to have issues now that atomic is partially in.
We'd need to look at plane->state->fb now, but that steps on the same
turf as Matt's latest patches.

> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 06/12] drm/i915: Pass plane to vlv_compute_drain_latency()

[Jesse Barnes]

On 02/27/2015 10:09 AM, Ville Syrjälä wrote:
> On Fri, Feb 27, 2015 at 09:57:20AM -0800, Jesse Barnes wrote:
>> On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> Now that we have drm_planes for the cursor and primary we can move the
>>> pixel_size handling into vlv_compute_drain_latency() and just pass the
>>> appropriate plane to it.
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/intel_pm.c | 42 ++++++++++++++++-------------------------
>>>  1 file changed, 16 insertions(+), 26 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index 5515d10..fffcf64 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -727,16 +727,26 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
>>>  }
>>>  
>>>  static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
>>> -					 int pixel_size)
>>> +					 struct drm_plane *plane)
>>>  {
>>>  	struct drm_device *dev = crtc->dev;
>>> -	int entries, prec_mult, drain_latency;
>>> -	int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
>>> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>> +	int entries, prec_mult, drain_latency, pixel_size;
>>> +	int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
>>>  	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
>>>  
>>> +	/*
>>> +	 * FIXME the plane might have an fb
>>> +	 * but be invisible (eg. due to clipping)
>>> +	 */
>>> +	if (!intel_crtc->active || !plane->fb)
>>> +		return 0;
>>> +
>>>  	if (WARN(clock == 0, "Pixel clock is zero!\n"))
>>>  		return 0;
>>>  
>>> +	pixel_size = drm_format_plane_cpp(plane->fb->pixel_format, 0);
>>> +
>>>  	if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
>>>  		return 0;
>>>  
>>> @@ -770,31 +780,11 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
>>>  	struct drm_device *dev = crtc->dev;
>>>  	struct drm_i915_private *dev_priv = dev->dev_private;
>>>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>> -	int pixel_size;
>>>  	enum pipe pipe = intel_crtc->pipe;
>>>  	struct vlv_wm_values wm = dev_priv->wm.vlv;
>>>  
>>> -	wm.ddl[pipe].primary = 0;
>>> -	wm.ddl[pipe].cursor = 0;
>>> -
>>> -	if (!intel_crtc_active(crtc)) {
>>> -		vlv_write_wm_values(intel_crtc, &wm);
>>> -		return;
>>> -	}
>>> -
>>> -	/* Primary plane Drain Latency */
>>> -	pixel_size = crtc->primary->fb->bits_per_pixel / 8;	/* BPP */
>>> -	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, pixel_size);
>>> -
>>> -	/* Cursor Drain Latency
>>> -	 * BPP is always 4 for cursor
>>> -	 */
>>> -	pixel_size = 4;
>>> -
>>> -	/* Program cursor DL only if it is enabled */
>>> -	if (intel_crtc->cursor_base)
>>> -		wm.ddl[pipe].cursor =
>>> -			vlv_compute_drain_latency(crtc, pixel_size);
>>> +	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
>>> +	wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
>>>  
>>>  	vlv_write_wm_values(intel_crtc, &wm);
>>>  }
>>> @@ -961,7 +951,7 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
>>>  
>>>  	if (enabled)
>>>  		wm.ddl[pipe].sprite[sprite] =
>>> -			vlv_compute_drain_latency(crtc, pixel_size);
>>> +			vlv_compute_drain_latency(crtc, plane);
>>>  	else
>>>  		wm.ddl[pipe].sprite[sprite] = 0;
>>>  
>>>
>>
>> Nice.
> 
> Actually this is going to have issues now that atomic is partially in.
> We'd need to look at plane->state->fb now, but that steps on the same
> turf as Matt's latest patches.

Yeah there's some overlap, but mostly it looked like these would make
things a little easier by removing duplication and clearing things up
(not to mention the bug fixes).

Jesse

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Re: [PATCH 06/12] drm/i915: Pass plane to vlv_compute_drain_latency()

[Daniel Vetter]

On Fri, Feb 27, 2015 at 08:09:20PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 27, 2015 at 09:57:20AM -0800, Jesse Barnes wrote:
> > On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Now that we have drm_planes for the cursor and primary we can move the
> > > pixel_size handling into vlv_compute_drain_latency() and just pass the
> > > appropriate plane to it.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 42 ++++++++++++++++-------------------------
> > >  1 file changed, 16 insertions(+), 26 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 5515d10..fffcf64 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -727,16 +727,26 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
> > >  }
> > >  
> > >  static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
> > > -					 int pixel_size)
> > > +					 struct drm_plane *plane)
> > >  {
> > >  	struct drm_device *dev = crtc->dev;
> > > -	int entries, prec_mult, drain_latency;
> > > -	int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
> > > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > +	int entries, prec_mult, drain_latency, pixel_size;
> > > +	int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
> > >  	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
> > >  
> > > +	/*
> > > +	 * FIXME the plane might have an fb
> > > +	 * but be invisible (eg. due to clipping)
> > > +	 */
> > > +	if (!intel_crtc->active || !plane->fb)
> > > +		return 0;
> > > +
> > >  	if (WARN(clock == 0, "Pixel clock is zero!\n"))
> > >  		return 0;
> > >  
> > > +	pixel_size = drm_format_plane_cpp(plane->fb->pixel_format, 0);
> > > +
> > >  	if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
> > >  		return 0;
> > >  
> > > @@ -770,31 +780,11 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
> > >  	struct drm_device *dev = crtc->dev;
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > -	int pixel_size;
> > >  	enum pipe pipe = intel_crtc->pipe;
> > >  	struct vlv_wm_values wm = dev_priv->wm.vlv;
> > >  
> > > -	wm.ddl[pipe].primary = 0;
> > > -	wm.ddl[pipe].cursor = 0;
> > > -
> > > -	if (!intel_crtc_active(crtc)) {
> > > -		vlv_write_wm_values(intel_crtc, &wm);
> > > -		return;
> > > -	}
> > > -
> > > -	/* Primary plane Drain Latency */
> > > -	pixel_size = crtc->primary->fb->bits_per_pixel / 8;	/* BPP */
> > > -	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, pixel_size);
> > > -
> > > -	/* Cursor Drain Latency
> > > -	 * BPP is always 4 for cursor
> > > -	 */
> > > -	pixel_size = 4;
> > > -
> > > -	/* Program cursor DL only if it is enabled */
> > > -	if (intel_crtc->cursor_base)
> > > -		wm.ddl[pipe].cursor =
> > > -			vlv_compute_drain_latency(crtc, pixel_size);
> > > +	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
> > > +	wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
> > >  
> > >  	vlv_write_wm_values(intel_crtc, &wm);
> > >  }
> > > @@ -961,7 +951,7 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
> > >  
> > >  	if (enabled)
> > >  		wm.ddl[pipe].sprite[sprite] =
> > > -			vlv_compute_drain_latency(crtc, pixel_size);
> > > +			vlv_compute_drain_latency(crtc, plane);
> > >  	else
> > >  		wm.ddl[pipe].sprite[sprite] = 0;
> > >  
> > > 
> > 
> > Nice.
> 
> Actually this is going to have issues now that atomic is partially in.
> We'd need to look at plane->state->fb now, but that steps on the same
> turf as Matt's latest patches.

All the wm computation needs to be moved over to look at plane states, not
plane->state - we need to do all this in the check phase when state
objects haven't been commited yet. Which is a lot more work and probably
best done separately in one go than all over the place and inconsistently.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 06/12] drm/i915: Pass plane to vlv_compute_drain_latency()

[Ville Syrjälä]

On Mon, Mar 02, 2015 at 03:44:58PM +0100, Daniel Vetter wrote:
> On Fri, Feb 27, 2015 at 08:09:20PM +0200, Ville Syrjälä wrote:
> > On Fri, Feb 27, 2015 at 09:57:20AM -0800, Jesse Barnes wrote:
> > > On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > Now that we have drm_planes for the cursor and primary we can move the
> > > > pixel_size handling into vlv_compute_drain_latency() and just pass the
> > > > appropriate plane to it.
> > > > 
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_pm.c | 42 ++++++++++++++++-------------------------
> > > >  1 file changed, 16 insertions(+), 26 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index 5515d10..fffcf64 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -727,16 +727,26 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
> > > >  }
> > > >  
> > > >  static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
> > > > -					 int pixel_size)
> > > > +					 struct drm_plane *plane)
> > > >  {
> > > >  	struct drm_device *dev = crtc->dev;
> > > > -	int entries, prec_mult, drain_latency;
> > > > -	int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
> > > > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > > +	int entries, prec_mult, drain_latency, pixel_size;
> > > > +	int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
> > > >  	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
> > > >  
> > > > +	/*
> > > > +	 * FIXME the plane might have an fb
> > > > +	 * but be invisible (eg. due to clipping)
> > > > +	 */
> > > > +	if (!intel_crtc->active || !plane->fb)
> > > > +		return 0;
> > > > +
> > > >  	if (WARN(clock == 0, "Pixel clock is zero!\n"))
> > > >  		return 0;
> > > >  
> > > > +	pixel_size = drm_format_plane_cpp(plane->fb->pixel_format, 0);
> > > > +
> > > >  	if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
> > > >  		return 0;
> > > >  
> > > > @@ -770,31 +780,11 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
> > > >  	struct drm_device *dev = crtc->dev;
> > > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > > >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > > -	int pixel_size;
> > > >  	enum pipe pipe = intel_crtc->pipe;
> > > >  	struct vlv_wm_values wm = dev_priv->wm.vlv;
> > > >  
> > > > -	wm.ddl[pipe].primary = 0;
> > > > -	wm.ddl[pipe].cursor = 0;
> > > > -
> > > > -	if (!intel_crtc_active(crtc)) {
> > > > -		vlv_write_wm_values(intel_crtc, &wm);
> > > > -		return;
> > > > -	}
> > > > -
> > > > -	/* Primary plane Drain Latency */
> > > > -	pixel_size = crtc->primary->fb->bits_per_pixel / 8;	/* BPP */
> > > > -	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, pixel_size);
> > > > -
> > > > -	/* Cursor Drain Latency
> > > > -	 * BPP is always 4 for cursor
> > > > -	 */
> > > > -	pixel_size = 4;
> > > > -
> > > > -	/* Program cursor DL only if it is enabled */
> > > > -	if (intel_crtc->cursor_base)
> > > > -		wm.ddl[pipe].cursor =
> > > > -			vlv_compute_drain_latency(crtc, pixel_size);
> > > > +	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
> > > > +	wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
> > > >  
> > > >  	vlv_write_wm_values(intel_crtc, &wm);
> > > >  }
> > > > @@ -961,7 +951,7 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
> > > >  
> > > >  	if (enabled)
> > > >  		wm.ddl[pipe].sprite[sprite] =
> > > > -			vlv_compute_drain_latency(crtc, pixel_size);
> > > > +			vlv_compute_drain_latency(crtc, plane);
> > > >  	else
> > > >  		wm.ddl[pipe].sprite[sprite] = 0;
> > > >  
> > > > 
> > > 
> > > Nice.
> > 
> > Actually this is going to have issues now that atomic is partially in.
> > We'd need to look at plane->state->fb now, but that steps on the same
> > turf as Matt's latest patches.
> 
> All the wm computation needs to be moved over to look at plane states, not
> plane->state - we need to do all this in the check phase when state
> objects haven't been commited yet. Which is a lot more work and probably
> best done separately in one go than all over the place and inconsistently.

Sure, but the quick "keep things sort of working" fix is to look at
plane->state since we currently do the wm calculation from commit.

-- 
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Intel OTC
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Re: [PATCH 06/12] drm/i915: Pass plane to vlv_compute_drain_latency()

[Daniel Vetter]

On Mon, Mar 02, 2015 at 04:49:31PM +0200, Ville Syrjälä wrote:
> On Mon, Mar 02, 2015 at 03:44:58PM +0100, Daniel Vetter wrote:
> > On Fri, Feb 27, 2015 at 08:09:20PM +0200, Ville Syrjälä wrote:
> > > Actually this is going to have issues now that atomic is partially in.
> > > We'd need to look at plane->state->fb now, but that steps on the same
> > > turf as Matt's latest patches.
> > 
> > All the wm computation needs to be moved over to look at plane states, not
> > plane->state - we need to do all this in the check phase when state
> > objects haven't been commited yet. Which is a lot more work and probably
> > best done separately in one go than all over the place and inconsistently.
> 
> Sure, but the quick "keep things sort of working" fix is to look at
> plane->state since we currently do the wm calculation from commit.

Yeah my reply was just with your comment about stepping onto Matt's turf.
The minimal change to look at plane->state->fb is obviously needed and we
can't avoid such conflicts really. Just figured we shouldn't charge ahead
with changing interfaces all over the place.
-Daniel
-- 
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[PATCH 07/12] drm/i915: Read out display FIFO size on VLV/CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

VLV/CHV have similar DSPARB registers as older platforms, just more of
them due to more planes. Add a bit of code to read out the current FIFO
split from the registers. Will be useful later when we improve the WM
calculations.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 drivers/gpu/drm/i915/intel_pm.c | 55 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b35aaf3..433d7e7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4034,6 +4034,9 @@ enum skl_disp_power_wells {
 #define   DSPARB_BEND_SHIFT	9 /* on 855 */
 #define   DSPARB_AEND_SHIFT	0
 
+#define DSPARB2			(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
+#define DSPARB3			(VLV_DISPLAY_BASE + 0x7006c) /* chv */
+
 /* pnv/gen4/g4x/vlv/chv */
 #define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
 #define   DSPFW_SR_SHIFT		23
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fffcf64..e53038e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -280,6 +280,61 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
  */
 static const int pessimal_latency_ns = 5000;
 
+#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
+	((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
+
+static int vlv_get_fifo_size(struct drm_device *dev,
+			      enum pipe pipe, int plane)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int sprite0_start, sprite1_start, size;
+
+	switch (pipe) {
+		uint32_t dsparb, dsparb2, dsparb3;
+	case PIPE_A:
+		dsparb = I915_READ(DSPARB);
+		dsparb2 = I915_READ(DSPARB2);
+		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
+		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
+		break;
+	case PIPE_B:
+		dsparb = I915_READ(DSPARB);
+		dsparb2 = I915_READ(DSPARB2);
+		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
+		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
+		break;
+	case PIPE_C:
+		dsparb2 = I915_READ(DSPARB2);
+		dsparb3 = I915_READ(DSPARB3);
+		sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
+		sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
+		break;
+	default:
+		return 0;
+	}
+
+	switch (plane) {
+	case 0:
+		size = sprite0_start;
+		break;
+	case 1:
+		size = sprite1_start - sprite0_start;
+		break;
+	case 2:
+		size = 512 - 1 - sprite1_start;
+		break;
+	default:
+		return 0;
+	}
+
+	DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
+		      pipe_name(pipe), plane == 0 ? "primary" : "sprite",
+		      plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
+		      size);
+
+	return size;
+}
+
 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-- 
2.0.5

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[PATCH v2 07/12] drm/i915: Read out display FIFO size on VLV/CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

VLV/CHV have similar DSPARB registers as older platforms, just more of
them due to more planes. Add a bit of code to read out the current FIFO
split from the registers. Will be useful later when we improve the WM
calculations.

v2: Add display_mmio_offset to DSPARB

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  5 +++-
 drivers/gpu/drm/i915/intel_pm.c | 55 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b35aaf3..3b48f4b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4026,7 +4026,7 @@ enum skl_disp_power_wells {
 #define   DPINVGTT_STATUS_MASK			0xff
 #define   DPINVGTT_STATUS_MASK_CHV		0xfff
 
-#define DSPARB			0x70030
+#define DSPARB			(dev_priv->info.display_mmio_offset + 0x70030)
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
 #define   DSPARB_CSTART_SHIFT	7
 #define   DSPARB_BSTART_MASK	(0x7f)
@@ -4034,6 +4034,9 @@ enum skl_disp_power_wells {
 #define   DSPARB_BEND_SHIFT	9 /* on 855 */
 #define   DSPARB_AEND_SHIFT	0
 
+#define DSPARB2			(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
+#define DSPARB3			(VLV_DISPLAY_BASE + 0x7006c) /* chv */
+
 /* pnv/gen4/g4x/vlv/chv */
 #define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
 #define   DSPFW_SR_SHIFT		23
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fffcf64..e53038e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -280,6 +280,61 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
  */
 static const int pessimal_latency_ns = 5000;
 
+#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
+	((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
+
+static int vlv_get_fifo_size(struct drm_device *dev,
+			      enum pipe pipe, int plane)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int sprite0_start, sprite1_start, size;
+
+	switch (pipe) {
+		uint32_t dsparb, dsparb2, dsparb3;
+	case PIPE_A:
+		dsparb = I915_READ(DSPARB);
+		dsparb2 = I915_READ(DSPARB2);
+		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
+		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
+		break;
+	case PIPE_B:
+		dsparb = I915_READ(DSPARB);
+		dsparb2 = I915_READ(DSPARB2);
+		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
+		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
+		break;
+	case PIPE_C:
+		dsparb2 = I915_READ(DSPARB2);
+		dsparb3 = I915_READ(DSPARB3);
+		sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
+		sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
+		break;
+	default:
+		return 0;
+	}
+
+	switch (plane) {
+	case 0:
+		size = sprite0_start;
+		break;
+	case 1:
+		size = sprite1_start - sprite0_start;
+		break;
+	case 2:
+		size = 512 - 1 - sprite1_start;
+		break;
+	default:
+		return 0;
+	}
+
+	DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
+		      pipe_name(pipe), plane == 0 ? "primary" : "sprite",
+		      plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
+		      size);
+
+	return size;
+}
+
 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-- 
2.0.5

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Re: [PATCH v2 07/12] drm/i915: Read out display FIFO size on VLV/CHV

[Jesse Barnes]

On 02/12/2015 10:59 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> VLV/CHV have similar DSPARB registers as older platforms, just more of
> them due to more planes. Add a bit of code to read out the current FIFO
> split from the registers. Will be useful later when we improve the WM
> calculations.
> 
> v2: Add display_mmio_offset to DSPARB
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  5 +++-
>  drivers/gpu/drm/i915/intel_pm.c | 55 +++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 59 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b35aaf3..3b48f4b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4026,7 +4026,7 @@ enum skl_disp_power_wells {
>  #define   DPINVGTT_STATUS_MASK			0xff
>  #define   DPINVGTT_STATUS_MASK_CHV		0xfff
>  
> -#define DSPARB			0x70030
> +#define DSPARB			(dev_priv->info.display_mmio_offset + 0x70030)
>  #define   DSPARB_CSTART_MASK	(0x7f << 7)
>  #define   DSPARB_CSTART_SHIFT	7
>  #define   DSPARB_BSTART_MASK	(0x7f)
> @@ -4034,6 +4034,9 @@ enum skl_disp_power_wells {
>  #define   DSPARB_BEND_SHIFT	9 /* on 855 */
>  #define   DSPARB_AEND_SHIFT	0
>  
> +#define DSPARB2			(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
> +#define DSPARB3			(VLV_DISPLAY_BASE + 0x7006c) /* chv */
> +
>  /* pnv/gen4/g4x/vlv/chv */
>  #define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
>  #define   DSPFW_SR_SHIFT		23
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fffcf64..e53038e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -280,6 +280,61 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
>   */
>  static const int pessimal_latency_ns = 5000;
>  
> +#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
> +	((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
> +
> +static int vlv_get_fifo_size(struct drm_device *dev,
> +			      enum pipe pipe, int plane)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int sprite0_start, sprite1_start, size;
> +
> +	switch (pipe) {
> +		uint32_t dsparb, dsparb2, dsparb3;
> +	case PIPE_A:
> +		dsparb = I915_READ(DSPARB);
> +		dsparb2 = I915_READ(DSPARB2);
> +		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
> +		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
> +		break;
> +	case PIPE_B:
> +		dsparb = I915_READ(DSPARB);
> +		dsparb2 = I915_READ(DSPARB2);
> +		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
> +		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
> +		break;
> +	case PIPE_C:
> +		dsparb2 = I915_READ(DSPARB2);
> +		dsparb3 = I915_READ(DSPARB3);
> +		sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
> +		sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
> +		break;
> +	default:
> +		return 0;
> +	}
> +
> +	switch (plane) {
> +	case 0:
> +		size = sprite0_start;
> +		break;
> +	case 1:
> +		size = sprite1_start - sprite0_start;
> +		break;
> +	case 2:
> +		size = 512 - 1 - sprite1_start;
> +		break;
> +	default:
> +		return 0;
> +	}
> +
> +	DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
> +		      pipe_name(pipe), plane == 0 ? "primary" : "sprite",
> +		      plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
> +		      size);
> +
> +	return size;
> +}
> +
>  static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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[PATCH 08/12] drm/i915: Make sure PND deadline mode is enabled on VLV/CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Poke at the CBR1_VLV register during init_clock_gating to make sure the
PND deadline scheme is used.

The hardware has two modes of operation wrt. watermarks:

1) PND deadline mode:
 - memory request deadline is calculated from actual FIFO level * DDL
 - WM1 watermark values are unused (AFAIK)
 - WM watermark level defines when to start fetching data from memory
   (assuming trickle feed is not used)

2) backup mode
 - deadline is based on FIFO status, DDL is unused
 - FIFO split into three regions with WM and WM1 watermarks, each
   part specifying a different FIFO status

We want to use the PND deadline mode, so let's make sure the chicken
bit is in the correct position on init.

Also take the opportunity to refactor the shared code between VLV and
CHV to a shared function.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++------
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 433d7e7..5d377df 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4177,6 +4177,9 @@ enum skl_disp_power_wells {
 #define DDL_PRECISION_LOW		(0<<7)
 #define DRAIN_LATENCY_MASK		0x7f
 
+#define CBR1_VLV			(VLV_DISPLAY_BASE + 0x70400)
+#define  CBR_PND_DEADLINE_DISABLE	(1<<31)
+
 /* FIFO watermark sizes etc */
 #define G4X_FIFO_LINE_SIZE	64
 #define I915_FIFO_LINE_SIZE	64
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e53038e..c021e92 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6197,11 +6197,22 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	gen6_check_mch_setup(dev);
 }
 
+static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
+
+	/*
+	 * Disable trickle feed and enable pnd deadline calculation
+	 */
+	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+	I915_WRITE(CBR1_VLV, 0);
+}
+
 static void valleyview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
+	vlv_init_display_clock_gating(dev_priv);
 
 	/* WaDisableEarlyCull:vlv */
 	I915_WRITE(_3D_CHICKEN3,
@@ -6249,8 +6260,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_UCGCTL4,
 		   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
 
-	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
-
 	/*
 	 * BSpec says this must be set, even though
 	 * WaDisable4x2SubspanOptimization isn't listed for VLV.
@@ -6287,9 +6296,7 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
-
-	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+	vlv_init_display_clock_gating(dev_priv);
 
 	/* WaVSRefCountFullforceMissDisable:chv */
 	/* WaDSRefCountFullforceMissDisable:chv */
-- 
2.0.5

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Re: [PATCH 08/12] drm/i915: Make sure PND deadline mode is enabled on VLV/CHV

[Jesse Barnes]

On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Poke at the CBR1_VLV register during init_clock_gating to make sure the
> PND deadline scheme is used.
> 
> The hardware has two modes of operation wrt. watermarks:
> 
> 1) PND deadline mode:
>  - memory request deadline is calculated from actual FIFO level * DDL
>  - WM1 watermark values are unused (AFAIK)
>  - WM watermark level defines when to start fetching data from memory
>    (assuming trickle feed is not used)
> 
> 2) backup mode
>  - deadline is based on FIFO status, DDL is unused
>  - FIFO split into three regions with WM and WM1 watermarks, each
>    part specifying a different FIFO status
> 
> We want to use the PND deadline mode, so let's make sure the chicken
> bit is in the correct position on init.
> 
> Also take the opportunity to refactor the shared code between VLV and
> CHV to a shared function.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++------
>  2 files changed, 16 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 433d7e7..5d377df 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4177,6 +4177,9 @@ enum skl_disp_power_wells {
>  #define DDL_PRECISION_LOW		(0<<7)
>  #define DRAIN_LATENCY_MASK		0x7f
>  
> +#define CBR1_VLV			(VLV_DISPLAY_BASE + 0x70400)
> +#define  CBR_PND_DEADLINE_DISABLE	(1<<31)
> +
>  /* FIFO watermark sizes etc */
>  #define G4X_FIFO_LINE_SIZE	64
>  #define I915_FIFO_LINE_SIZE	64
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e53038e..c021e92 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6197,11 +6197,22 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  	gen6_check_mch_setup(dev);
>  }
>  
> +static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
> +{
> +	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> +
> +	/*
> +	 * Disable trickle feed and enable pnd deadline calculation
> +	 */
> +	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> +	I915_WRITE(CBR1_VLV, 0);
> +}
> +
>  static void valleyview_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> +	vlv_init_display_clock_gating(dev_priv);
>  
>  	/* WaDisableEarlyCull:vlv */
>  	I915_WRITE(_3D_CHICKEN3,
> @@ -6249,8 +6260,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_UCGCTL4,
>  		   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
>  
> -	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> -
>  	/*
>  	 * BSpec says this must be set, even though
>  	 * WaDisable4x2SubspanOptimization isn't listed for VLV.
> @@ -6287,9 +6296,7 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> -
> -	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> +	vlv_init_display_clock_gating(dev_priv);
>  
>  	/* WaVSRefCountFullforceMissDisable:chv */
>  	/* WaDSRefCountFullforceMissDisable:chv */
> 

Is the deadline mode preference documented somewhere?  Do we need
another bspec bug filed?

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 08/12] drm/i915: Make sure PND deadline mode is enabled on VLV/CHV

[Ville Syrjälä]

On Fri, Feb 27, 2015 at 12:38:44PM -0800, Jesse Barnes wrote:
> On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Poke at the CBR1_VLV register during init_clock_gating to make sure the
> > PND deadline scheme is used.
> > 
> > The hardware has two modes of operation wrt. watermarks:
> > 
> > 1) PND deadline mode:
> >  - memory request deadline is calculated from actual FIFO level * DDL
> >  - WM1 watermark values are unused (AFAIK)
> >  - WM watermark level defines when to start fetching data from memory
> >    (assuming trickle feed is not used)
> > 
> > 2) backup mode
> >  - deadline is based on FIFO status, DDL is unused
> >  - FIFO split into three regions with WM and WM1 watermarks, each
> >    part specifying a different FIFO status
> > 
> > We want to use the PND deadline mode, so let's make sure the chicken
> > bit is in the correct position on init.
> > 
> > Also take the opportunity to refactor the shared code between VLV and
> > CHV to a shared function.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |  3 +++
> >  drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++------
> >  2 files changed, 16 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 433d7e7..5d377df 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4177,6 +4177,9 @@ enum skl_disp_power_wells {
> >  #define DDL_PRECISION_LOW		(0<<7)
> >  #define DRAIN_LATENCY_MASK		0x7f
> >  
> > +#define CBR1_VLV			(VLV_DISPLAY_BASE + 0x70400)
> > +#define  CBR_PND_DEADLINE_DISABLE	(1<<31)
> > +
> >  /* FIFO watermark sizes etc */
> >  #define G4X_FIFO_LINE_SIZE	64
> >  #define I915_FIFO_LINE_SIZE	64
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index e53038e..c021e92 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6197,11 +6197,22 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> >  	gen6_check_mch_setup(dev);
> >  }
> >  
> > +static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
> > +{
> > +	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> > +
> > +	/*
> > +	 * Disable trickle feed and enable pnd deadline calculation
> > +	 */
> > +	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> > +	I915_WRITE(CBR1_VLV, 0);
> > +}
> > +
> >  static void valleyview_init_clock_gating(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> > +	vlv_init_display_clock_gating(dev_priv);
> >  
> >  	/* WaDisableEarlyCull:vlv */
> >  	I915_WRITE(_3D_CHICKEN3,
> > @@ -6249,8 +6260,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> >  	I915_WRITE(GEN7_UCGCTL4,
> >  		   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
> >  
> > -	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> > -
> >  	/*
> >  	 * BSpec says this must be set, even though
> >  	 * WaDisable4x2SubspanOptimization isn't listed for VLV.
> > @@ -6287,9 +6296,7 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> > -
> > -	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> > +	vlv_init_display_clock_gating(dev_priv);
> >  
> >  	/* WaVSRefCountFullforceMissDisable:chv */
> >  	/* WaDSRefCountFullforceMissDisable:chv */
> > 
> 
> Is the deadline mode preference documented somewhere?  Do we need
> another bspec bug filed?

VLV display cluster HAS had a fairly good description. We can at least
hope it works well enough on VLV. Sadly it doesn't actually work the
way you'd expect on CHV, but that's a whole other story.

> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Ville Syrjälä
Intel OTC
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[PATCH 09/12] drm/i915: Rewrite VLV/CHV watermark code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Assuming the PND deadline mechanism works reasonably we should do
memory requests as early as possible so that PND has schedule the
requests more intelligently. Currently we're still calculating
the watermarks as if VLV/CHV are identical to g4x, which isn't
the case.

The current code also seems to calculate insufficient watermarks
and hence we're seeing some underruns, especially on high resolution
displays.

To fix it just rip out the current code and replace is with something
that tries to utilize PND as efficiently as possible.

We now calculate the WM watermark to trigger when the FIFO still has
256us worth of data. 256us is the maximum deadline value supoorted by
PND, so issuing memory requests earlier would mean we probably couldn't
utilize the full FIFO as PND would attempt to return the data at
least in at least 256us. We also clamp the watermark to at least 8
cachelines as that's the magic watermark that enabling trickle feed
would also impose. I'm assuming it matches some burst size.

In theory we could just enable trickle feed and ignore the WM values,
except trickle feed doesn't work with max fifo mode anyway, so we'd
still need to calculate the SR watermarks. It seems cleaner to just
disable trickle feed and calculate all watermarks the same way. Also
trickle feed wouldn't account for the 256us max deadline value, thoguh
that may be a moot point in non-max fifo mode sicne the FIFOs are fairly
small.

On VLV max fifo mode can be used with either primary or sprite planes.
So the code now also checks all the planes (apart from the cursor)
when calculating the SR plane watermark.

We don't have to worry about the WM1 watermarks since we're using the
PND deadline scheme which means the hardware ignores WM1 values.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  11 ++
 drivers/gpu/drm/i915/i915_reg.h |   4 +-
 drivers/gpu/drm/i915/intel_pm.c | 327 +++++++++++++++++++++-------------------
 3 files changed, 185 insertions(+), 157 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5de69a0..b191b12 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1516,6 +1516,17 @@ struct ilk_wm_values {
 
 struct vlv_wm_values {
 	struct {
+		uint16_t primary;
+		uint16_t sprite[2];
+		uint8_t cursor;
+	} pipe[3];
+
+	struct {
+		uint16_t plane;
+		uint8_t cursor;
+	} sr;
+
+	struct {
 		uint8_t cursor;
 		uint8_t sprite[2];
 		uint8_t primary;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d377df..aacf90b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4127,7 +4127,7 @@ enum skl_disp_power_wells {
 /* vlv/chv high order bits */
 #define DSPHOWM			(VLV_DISPLAY_BASE + 0x70064)
 #define   DSPFW_SR_HI_SHIFT		24
-#define   DSPFW_SR_HI_MASK		(1<<24)
+#define   DSPFW_SR_HI_MASK		(3<<24) /* 2 bits for chv, 1 for vlv */
 #define   DSPFW_SPRITEF_HI_SHIFT	23
 #define   DSPFW_SPRITEF_HI_MASK		(1<<23)
 #define   DSPFW_SPRITEE_HI_SHIFT	22
@@ -4148,7 +4148,7 @@ enum skl_disp_power_wells {
 #define   DSPFW_PLANEA_HI_MASK		(1<<0)
 #define DSPHOWM1		(VLV_DISPLAY_BASE + 0x70068)
 #define   DSPFW_SR_WM1_HI_SHIFT		24
-#define   DSPFW_SR_WM1_HI_MASK		(1<<24)
+#define   DSPFW_SR_WM1_HI_MASK		(3<<24) /* 2 bits for chv, 1 for vlv */
 #define   DSPFW_SPRITEF_WM1_HI_SHIFT	23
 #define   DSPFW_SPRITEF_WM1_HI_MASK	(1<<23)
 #define   DSPFW_SPRITEE_WM1_HI_SHIFT	22
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c021e92..d29c02c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -778,6 +778,55 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
 		   (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 		   (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 
+	I915_WRITE(DSPFW1,
+		   ((wm->sr.plane << DSPFW_SR_SHIFT) & DSPFW_SR_MASK) |
+		   ((wm->pipe[PIPE_B].cursor << DSPFW_CURSORB_SHIFT) & DSPFW_CURSORB_MASK) |
+		   ((wm->pipe[PIPE_B].primary << DSPFW_PLANEB_SHIFT) & DSPFW_PLANEB_MASK_VLV) |
+		   ((wm->pipe[PIPE_A].primary << DSPFW_PLANEA_SHIFT) & DSPFW_PLANEA_MASK_VLV));
+	I915_WRITE(DSPFW2,
+		   ((wm->pipe[PIPE_A].sprite[1] << DSPFW_SPRITEB_SHIFT) & DSPFW_SPRITEB_MASK_VLV) |
+		   ((wm->pipe[PIPE_A].cursor << DSPFW_CURSORA_SHIFT) & DSPFW_CURSORA_MASK) |
+		   ((wm->pipe[PIPE_A].sprite[0] << DSPFW_SPRITEA_SHIFT) & DSPFW_SPRITEA_MASK_VLV));
+	I915_WRITE(DSPFW3,
+		   ((wm->sr.cursor << DSPFW_CURSOR_SR_SHIFT) & DSPFW_CURSOR_SR_MASK));
+
+	if (IS_CHERRYVIEW(dev_priv)) {
+		I915_WRITE(DSPFW7_CHV,
+			   ((wm->pipe[PIPE_B].sprite[1] << DSPFW_SPRITED_SHIFT) & DSPFW_SPRITED_MASK) |
+			   ((wm->pipe[PIPE_B].sprite[0] << DSPFW_SPRITEC_SHIFT) & DSPFW_SPRITEC_MASK));
+		I915_WRITE(DSPFW8_CHV,
+			   ((wm->pipe[PIPE_C].sprite[1] << DSPFW_SPRITEF_SHIFT) & DSPFW_SPRITEF_MASK) |
+			   ((wm->pipe[PIPE_C].sprite[0] << DSPFW_SPRITEE_SHIFT) & DSPFW_SPRITEE_MASK));
+		I915_WRITE(DSPFW9_CHV,
+			   ((wm->pipe[PIPE_C].primary << DSPFW_PLANEC_SHIFT) & DSPFW_PLANEC_MASK) |
+			   ((wm->pipe[PIPE_C].cursor << DSPFW_CURSORC_SHIFT) & DSPFW_CURSORC_MASK));
+		I915_WRITE(DSPHOWM,
+			   (((wm->sr.plane >> 9) << DSPFW_SR_HI_SHIFT) & DSPFW_SR_HI_MASK) |
+			   (((wm->pipe[PIPE_C].sprite[1] >> 8) << DSPFW_SPRITEF_HI_SHIFT) & DSPFW_SPRITEF_HI_MASK) |
+			   (((wm->pipe[PIPE_C].sprite[0] >> 8) << DSPFW_SPRITEE_HI_SHIFT) & DSPFW_SPRITEE_HI_MASK) |
+			   (((wm->pipe[PIPE_C].primary >> 8) << DSPFW_PLANEC_HI_SHIFT) & DSPFW_PLANEC_HI_MASK) |
+			   (((wm->pipe[PIPE_B].sprite[1] >> 8) << DSPFW_SPRITED_HI_SHIFT) & DSPFW_SPRITED_HI_MASK) |
+			   (((wm->pipe[PIPE_B].sprite[0] >> 8) << DSPFW_SPRITEC_HI_SHIFT) & DSPFW_SPRITEC_HI_MASK) |
+			   (((wm->pipe[PIPE_B].primary >> 8) << DSPFW_PLANEB_HI_SHIFT) & DSPFW_PLANEB_HI_MASK) |
+			   (((wm->pipe[PIPE_A].sprite[1] >> 8) << DSPFW_SPRITEB_HI_SHIFT) & DSPFW_SPRITEB_HI_MASK) |
+			   (((wm->pipe[PIPE_A].sprite[0] >> 8) << DSPFW_SPRITEA_HI_SHIFT) & DSPFW_SPRITEA_HI_MASK) |
+			   (((wm->pipe[PIPE_A].primary >> 8) << DSPFW_PLANEA_HI_SHIFT) & DSPFW_PLANEA_HI_MASK));
+	} else {
+		I915_WRITE(DSPFW7,
+			   ((wm->pipe[PIPE_B].sprite[1] << DSPFW_SPRITED_SHIFT) & DSPFW_SPRITED_MASK) |
+			   ((wm->pipe[PIPE_B].sprite[0] << DSPFW_SPRITEC_SHIFT) & DSPFW_SPRITEC_MASK));
+		I915_WRITE(DSPHOWM,
+			   (((wm->sr.plane >> 9) << DSPFW_SR_HI_SHIFT) & DSPFW_SR_HI_MASK) |
+			   (((wm->pipe[PIPE_B].sprite[1] >> 8) << DSPFW_SPRITED_HI_SHIFT) & DSPFW_SPRITED_HI_MASK) |
+			   (((wm->pipe[PIPE_B].sprite[0] >> 8) << DSPFW_SPRITEC_HI_SHIFT) & DSPFW_SPRITEC_HI_MASK) |
+			   (((wm->pipe[PIPE_B].primary >> 8) << DSPFW_PLANEB_HI_SHIFT) & DSPFW_PLANEB_HI_MASK) |
+			   (((wm->pipe[PIPE_A].sprite[1] >> 8) << DSPFW_SPRITEB_HI_SHIFT) & DSPFW_SPRITEB_HI_MASK) |
+			   (((wm->pipe[PIPE_A].sprite[0] >> 8) << DSPFW_SPRITEA_HI_SHIFT) & DSPFW_SPRITEA_HI_MASK) |
+			   (((wm->pipe[PIPE_A].primary >> 8) << DSPFW_PLANEA_HI_SHIFT) & DSPFW_PLANEA_HI_MASK));
+	}
+
+	POSTING_READ(DSPFW1);
+
 	dev_priv->wm.vlv = *wm;
 }
 
@@ -822,169 +871,110 @@ static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
 				DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
 }
 
-/*
- * Update drain latency registers of memory arbiter
- *
- * Valleyview SoC has a new memory arbiter and needs drain latency registers
- * to be programmed. Each plane has a drain latency multiplier and a drain
- * latency value.
- */
-
-static void vlv_update_drain_latency(struct drm_crtc *crtc)
+static int vlv_compute_wm(struct intel_crtc *crtc,
+			  struct intel_plane *plane,
+			  int fifo_size)
+{
+	int clock, entries, pixel_size;
+
+	/* FIXME the plane might an fb but be invisible (eg. due to clipping) */
+	if (!crtc->active || !plane->base.fb)
+		return 0;
+
+	pixel_size = drm_format_plane_cpp(plane->base.fb->pixel_format, 0);
+	clock = crtc->config->base.adjusted_mode.crtc_clock;
+
+	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
+
+	/*
+	 * Set up the watermark such that we don't start issuing memory
+	 * requests until we are within PND's max deadline value (256us).
+	 * Idea being to be idle as long as possible while still taking
+	 * advatange of PND's deadline scheduling. The limit of 8
+	 * cachelines (used when the FIFO will anyway drain in less time
+	 * than 256us) should match what we would be done if trickle
+	 * feed were enabled.
+	 */
+	return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
+}
+
+static bool vlv_compute_sr_wm(struct drm_device *dev,
+			      struct vlv_wm_values *wm)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_crtc *crtc;
+	enum pipe pipe = INVALID_PIPE;
+	int num_planes = 0;
+	int fifo_size = 0;
+	struct intel_plane *plane;
+
+	wm->sr.cursor = wm->sr.plane = 0;
+
+	crtc = single_enabled_crtc(dev);
+	/* maxfifo not supported on pipe C */
+	if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
+		pipe = to_intel_crtc(crtc)->pipe;
+		num_planes = !!wm->pipe[pipe].primary +
+			!!wm->pipe[pipe].sprite[0] +
+			!!wm->pipe[pipe].sprite[1];
+		fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
+	}
+
+	if (fifo_size == 0 || num_planes > 1)
+		return false;
+
+	wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
+				       to_intel_plane(crtc->cursor), 0x3f);
+
+	list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
+		if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
+			continue;
+
+		if (plane->pipe != pipe)
+			continue;
+
+		wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
+					      plane, fifo_size);
+		if (wm->sr.plane != 0)
+			break;
+	}
+
+	return true;
+}
+
+static void valleyview_update_wm(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum pipe pipe = intel_crtc->pipe;
+	bool cxsr_enabled;
 	struct vlv_wm_values wm = dev_priv->wm.vlv;
 
 	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
+	wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
+					       to_intel_plane(crtc->primary),
+					       vlv_get_fifo_size(dev, pipe, 0));
+
 	wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
+	wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
+					      to_intel_plane(crtc->cursor),
+					      0x3f);
+
+	cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
+
+	if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
+		return;
+
+	DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
+		      "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
+		      wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
+		      wm.sr.plane, wm.sr.cursor);
+
+	if (!cxsr_enabled)
+		intel_set_memory_cxsr(dev_priv, false);
 
 	vlv_write_wm_values(intel_crtc, &wm);
-}
-
-#define single_plane_enabled(mask) is_power_of_2(mask)
-
-static void valleyview_update_wm(struct drm_crtc *crtc)
-{
-	struct drm_device *dev = crtc->dev;
-	static const int sr_latency_ns = 12000;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
-	int plane_sr, cursor_sr;
-	int ignore_plane_sr, ignore_cursor_sr;
-	unsigned int enabled = 0;
-	bool cxsr_enabled;
-
-	vlv_update_drain_latency(crtc);
-
-	if (g4x_compute_wm0(dev, PIPE_A,
-			    &valleyview_wm_info, pessimal_latency_ns,
-			    &valleyview_cursor_wm_info, pessimal_latency_ns,
-			    &planea_wm, &cursora_wm))
-		enabled |= 1 << PIPE_A;
-
-	if (g4x_compute_wm0(dev, PIPE_B,
-			    &valleyview_wm_info, pessimal_latency_ns,
-			    &valleyview_cursor_wm_info, pessimal_latency_ns,
-			    &planeb_wm, &cursorb_wm))
-		enabled |= 1 << PIPE_B;
-
-	if (single_plane_enabled(enabled) &&
-	    g4x_compute_srwm(dev, ffs(enabled) - 1,
-			     sr_latency_ns,
-			     &valleyview_wm_info,
-			     &valleyview_cursor_wm_info,
-			     &plane_sr, &ignore_cursor_sr) &&
-	    g4x_compute_srwm(dev, ffs(enabled) - 1,
-			     2*sr_latency_ns,
-			     &valleyview_wm_info,
-			     &valleyview_cursor_wm_info,
-			     &ignore_plane_sr, &cursor_sr)) {
-		cxsr_enabled = true;
-	} else {
-		cxsr_enabled = false;
-		intel_set_memory_cxsr(dev_priv, false);
-		plane_sr = cursor_sr = 0;
-	}
-
-	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
-		      "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
-		      planea_wm, cursora_wm,
-		      planeb_wm, cursorb_wm,
-		      plane_sr, cursor_sr);
-
-	I915_WRITE(DSPFW1,
-		   (plane_sr << DSPFW_SR_SHIFT) |
-		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
-		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
-		   (planea_wm << DSPFW_PLANEA_SHIFT));
-	I915_WRITE(DSPFW2,
-		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
-		   (cursora_wm << DSPFW_CURSORA_SHIFT));
-	I915_WRITE(DSPFW3,
-		   (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
-		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
-
-	if (cxsr_enabled)
-		intel_set_memory_cxsr(dev_priv, true);
-}
-
-static void cherryview_update_wm(struct drm_crtc *crtc)
-{
-	struct drm_device *dev = crtc->dev;
-	static const int sr_latency_ns = 12000;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	int planea_wm, planeb_wm, planec_wm;
-	int cursora_wm, cursorb_wm, cursorc_wm;
-	int plane_sr, cursor_sr;
-	int ignore_plane_sr, ignore_cursor_sr;
-	unsigned int enabled = 0;
-	bool cxsr_enabled;
-
-	vlv_update_drain_latency(crtc);
-
-	if (g4x_compute_wm0(dev, PIPE_A,
-			    &valleyview_wm_info, pessimal_latency_ns,
-			    &valleyview_cursor_wm_info, pessimal_latency_ns,
-			    &planea_wm, &cursora_wm))
-		enabled |= 1 << PIPE_A;
-
-	if (g4x_compute_wm0(dev, PIPE_B,
-			    &valleyview_wm_info, pessimal_latency_ns,
-			    &valleyview_cursor_wm_info, pessimal_latency_ns,
-			    &planeb_wm, &cursorb_wm))
-		enabled |= 1 << PIPE_B;
-
-	if (g4x_compute_wm0(dev, PIPE_C,
-			    &valleyview_wm_info, pessimal_latency_ns,
-			    &valleyview_cursor_wm_info, pessimal_latency_ns,
-			    &planec_wm, &cursorc_wm))
-		enabled |= 1 << PIPE_C;
-
-	if (single_plane_enabled(enabled) &&
-	    g4x_compute_srwm(dev, ffs(enabled) - 1,
-			     sr_latency_ns,
-			     &valleyview_wm_info,
-			     &valleyview_cursor_wm_info,
-			     &plane_sr, &ignore_cursor_sr) &&
-	    g4x_compute_srwm(dev, ffs(enabled) - 1,
-			     2*sr_latency_ns,
-			     &valleyview_wm_info,
-			     &valleyview_cursor_wm_info,
-			     &ignore_plane_sr, &cursor_sr)) {
-		cxsr_enabled = true;
-	} else {
-		cxsr_enabled = false;
-		intel_set_memory_cxsr(dev_priv, false);
-		plane_sr = cursor_sr = 0;
-	}
-
-	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
-		      "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
-		      "SR: plane=%d, cursor=%d\n",
-		      planea_wm, cursora_wm,
-		      planeb_wm, cursorb_wm,
-		      planec_wm, cursorc_wm,
-		      plane_sr, cursor_sr);
-
-	I915_WRITE(DSPFW1,
-		   (plane_sr << DSPFW_SR_SHIFT) |
-		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
-		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
-		   (planea_wm << DSPFW_PLANEA_SHIFT));
-	I915_WRITE(DSPFW2,
-		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
-		   (cursora_wm << DSPFW_CURSORA_SHIFT));
-	I915_WRITE(DSPFW3,
-		   (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
-		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
-	I915_WRITE(DSPFW9_CHV,
-		   (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
-					      DSPFW_CURSORC_MASK)) |
-		   (planec_wm << DSPFW_PLANEC_SHIFT) |
-		   (cursorc_wm << DSPFW_CURSORC_SHIFT));
 
 	if (cxsr_enabled)
 		intel_set_memory_cxsr(dev_priv, true);
@@ -1002,17 +992,44 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum pipe pipe = intel_crtc->pipe;
 	int sprite = to_intel_plane(plane)->plane;
+	bool cxsr_enabled;
 	struct vlv_wm_values wm = dev_priv->wm.vlv;
 
-	if (enabled)
+	if (enabled) {
 		wm.ddl[pipe].sprite[sprite] =
 			vlv_compute_drain_latency(crtc, plane);
-	else
+
+		wm.pipe[pipe].sprite[sprite] =
+			vlv_compute_wm(intel_crtc,
+				       to_intel_plane(plane),
+				       vlv_get_fifo_size(dev, pipe, sprite+1));
+	} else {
 		wm.ddl[pipe].sprite[sprite] = 0;
+		wm.pipe[pipe].sprite[sprite] = 0;
+	}
+
+	cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
+
+	if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
+		return;
+
+	DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
+		      "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
+		      sprite_name(pipe, sprite),
+		      wm.pipe[pipe].sprite[sprite],
+		      wm.sr.plane, wm.sr.cursor);
+
+	if (!cxsr_enabled)
+		intel_set_memory_cxsr(dev_priv, false);
 
 	vlv_write_wm_values(intel_crtc, &wm);
+
+	if (cxsr_enabled)
+		intel_set_memory_cxsr(dev_priv, true);
 }
 
+#define single_plane_enabled(mask) is_power_of_2(mask)
+
 static void g4x_update_wm(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
@@ -6485,7 +6502,7 @@ void intel_init_pm(struct drm_device *dev)
 		else if (INTEL_INFO(dev)->gen == 8)
 			dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
 	} else if (IS_CHERRYVIEW(dev)) {
-		dev_priv->display.update_wm = cherryview_update_wm;
+		dev_priv->display.update_wm = valleyview_update_wm;
 		dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
 		dev_priv->display.init_clock_gating =
 			cherryview_init_clock_gating;
-- 
2.0.5

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Re: [PATCH 09/12] drm/i915: Rewrite VLV/CHV watermark code

[Ville Syrjälä]

On Tue, Feb 10, 2015 at 03:28:26PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Assuming the PND deadline mechanism works reasonably we should do
> memory requests as early as possible so that PND has schedule the
> requests more intelligently. Currently we're still calculating
> the watermarks as if VLV/CHV are identical to g4x, which isn't
> the case.
> 
> The current code also seems to calculate insufficient watermarks
> and hence we're seeing some underruns, especially on high resolution
> displays.
> 
> To fix it just rip out the current code and replace is with something
> that tries to utilize PND as efficiently as possible.
> 
> We now calculate the WM watermark to trigger when the FIFO still has
> 256us worth of data. 256us is the maximum deadline value supoorted by
> PND, so issuing memory requests earlier would mean we probably couldn't
> utilize the full FIFO as PND would attempt to return the data at
> least in at least 256us. We also clamp the watermark to at least 8
> cachelines as that's the magic watermark that enabling trickle feed
> would also impose. I'm assuming it matches some burst size.
> 
> In theory we could just enable trickle feed and ignore the WM values,
> except trickle feed doesn't work with max fifo mode anyway, so we'd
> still need to calculate the SR watermarks. It seems cleaner to just
> disable trickle feed and calculate all watermarks the same way. Also
> trickle feed wouldn't account for the 256us max deadline value, thoguh
> that may be a moot point in non-max fifo mode sicne the FIFOs are fairly
> small.
> 
> On VLV max fifo mode can be used with either primary or sprite planes.
> So the code now also checks all the planes (apart from the cursor)
> when calculating the SR plane watermark.
> 
> We don't have to worry about the WM1 watermarks since we're using the
> PND deadline scheme which means the hardware ignores WM1 values.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

This patch still lacks review. Any takers?

-- 
Ville Syrjälä
Intel OTC
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[PATCH 10/12] drm/i915: Support maxfifo with two planes on CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV supposedly does maxfifo mode even with two enabled
(primary/sprite) planes. Lets try to support that by halving the FIFO
size for the calculations and picking the smallest calculcated
watermark from the enabled planes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d29c02c..e6cbc24 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -907,6 +907,8 @@ static bool vlv_compute_sr_wm(struct drm_device *dev,
 	int num_planes = 0;
 	int fifo_size = 0;
 	struct intel_plane *plane;
+	/* CHV supports max fifo with two planes (1:1 split) */
+	int max_planes = IS_CHERRYVIEW(dev) ? 2 : 1;
 
 	wm->sr.cursor = wm->sr.plane = 0;
 
@@ -920,23 +922,33 @@ static bool vlv_compute_sr_wm(struct drm_device *dev,
 		fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
 	}
 
-	if (fifo_size == 0 || num_planes > 1)
+	if (fifo_size == 0 || num_planes > max_planes)
 		return false;
 
+	if (num_planes)
+		fifo_size /= num_planes;
+
 	wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
 				       to_intel_plane(crtc->cursor), 0x3f);
 
 	list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
+		uint16_t sr_wm;
+
 		if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 			continue;
 
 		if (plane->pipe != pipe)
 			continue;
 
-		wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
-					      plane, fifo_size);
-		if (wm->sr.plane != 0)
-			break;
+		sr_wm = vlv_compute_wm(to_intel_crtc(crtc),
+				       plane, fifo_size);
+		if (sr_wm == 0)
+			continue;
+
+		if (wm->sr.plane == 0)
+			wm->sr.plane = sr_wm;
+		else
+			wm->sr.plane = min(wm->sr.plane, sr_wm);
 	}
 
 	return true;
-- 
2.0.5

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Re: [PATCH 10/12] drm/i915: Support maxfifo with two planes on CHV

[Purushothaman, Vijay A]

On 2/10/2015 6:58 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CHV supposedly does maxfifo mode even with two enabled
> (primary/sprite) planes. Lets try to support that by halving the FIFO
> size for the calculations and picking the smallest calculcated
> watermark from the enabled planes.
Where is this mentioned in the spec? My understanding is MaxFIFO can be 
enabled when only one plane is active (either ARGB or YUV). I do 
remember some TR task that was talking about enabling MaxFIFO for two 
planes. But i didn't get any confirmation that this can be enabled. We 
have not enabled this for CHT in any other OS (Windows / Android).

Other features like PM2 / PM5 / DVFS can be enabled for multi plane 
scenarios

Thanks,
Vijay
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 22 +++++++++++++++++-----
>   1 file changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d29c02c..e6cbc24 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -907,6 +907,8 @@ static bool vlv_compute_sr_wm(struct drm_device *dev,
>   	int num_planes = 0;
>   	int fifo_size = 0;
>   	struct intel_plane *plane;
> +	/* CHV supports max fifo with two planes (1:1 split) */
> +	int max_planes = IS_CHERRYVIEW(dev) ? 2 : 1;
>   
>   	wm->sr.cursor = wm->sr.plane = 0;
>   
> @@ -920,23 +922,33 @@ static bool vlv_compute_sr_wm(struct drm_device *dev,
>   		fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
>   	}
>   
> -	if (fifo_size == 0 || num_planes > 1)
> +	if (fifo_size == 0 || num_planes > max_planes)
>   		return false;
>   
> +	if (num_planes)
> +		fifo_size /= num_planes;
> +
>   	wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
>   				       to_intel_plane(crtc->cursor), 0x3f);
>   
>   	list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
> +		uint16_t sr_wm;
> +
>   		if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
>   			continue;
>   
>   		if (plane->pipe != pipe)
>   			continue;
>   
> -		wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
> -					      plane, fifo_size);
> -		if (wm->sr.plane != 0)
> -			break;
> +		sr_wm = vlv_compute_wm(to_intel_crtc(crtc),
> +				       plane, fifo_size);
> +		if (sr_wm == 0)
> +			continue;
> +
> +		if (wm->sr.plane == 0)
> +			wm->sr.plane = sr_wm;
> +		else
> +			wm->sr.plane = min(wm->sr.plane, sr_wm);
>   	}
>   
>   	return true;

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Re: [PATCH 10/12] drm/i915: Support maxfifo with two planes on CHV

[Ville Syrjälä]

On Wed, Mar 04, 2015 at 07:34:50PM +0530, Purushothaman, Vijay A wrote:
> On 2/10/2015 6:58 PM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > CHV supposedly does maxfifo mode even with two enabled
> > (primary/sprite) planes. Lets try to support that by halving the FIFO
> > size for the calculations and picking the smallest calculcated
> > watermark from the enabled planes.
> Where is this mentioned in the spec? My understanding is MaxFIFO can be 
> enabled when only one plane is active (either ARGB or YUV). I do 
> remember some TR task that was talking about enabling MaxFIFO for two 
> planes. But i didn't get any confirmation that this can be enabled.

It was mentioned in the display cluster HAS (also maybe some version of 
the PUNIT HAS), but I wasn't sure it's actually there. IIRC the answer
I got in one DDR DVFS meeting was that yes it does exit. But I've not
actually confirmed whether it seems to work on real hardware. The
annoying thing is that there doesn't seem to be any kind of status bit
to tell me if it has entered maxfifo or not, so it would need to be
deduced from some other facts.

Anyway, we can just skip this patch as it's still somewhat unclear if
this can be used or not.

> We 
> have not enabled this for CHT in any other OS (Windows / Android).
> 
> Other features like PM2 / PM5 / DVFS can be enabled for multi plane 
> scenarios

As far as I know we can't even control PM2. So the only thing we can
influence is whether it will enter PM2 or PM5 when things are
sufficiently idle. So we must always tolerate the PM2 latency, and
if we can tolerate the extra PM5 latency we can then choose PM5 over
PM2.

Previously I thought the something would check if the display is in
maxfifo or not before entering PM2/PM5, but now I can't see anything to
back that up. So I suppose we must always verify that even the
non-maxfifo FIFO sizes can tolerate the latency, whether or not we have
enable maxfifo or not (since we can't force maxfifo entry, and instead
the hardware just decides that by itself).

> 
> Thanks,
> Vijay
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_pm.c | 22 +++++++++++++++++-----
> >   1 file changed, 17 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index d29c02c..e6cbc24 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -907,6 +907,8 @@ static bool vlv_compute_sr_wm(struct drm_device *dev,
> >   	int num_planes = 0;
> >   	int fifo_size = 0;
> >   	struct intel_plane *plane;
> > +	/* CHV supports max fifo with two planes (1:1 split) */
> > +	int max_planes = IS_CHERRYVIEW(dev) ? 2 : 1;
> >   
> >   	wm->sr.cursor = wm->sr.plane = 0;
> >   
> > @@ -920,23 +922,33 @@ static bool vlv_compute_sr_wm(struct drm_device *dev,
> >   		fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
> >   	}
> >   
> > -	if (fifo_size == 0 || num_planes > 1)
> > +	if (fifo_size == 0 || num_planes > max_planes)
> >   		return false;
> >   
> > +	if (num_planes)
> > +		fifo_size /= num_planes;
> > +
> >   	wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
> >   				       to_intel_plane(crtc->cursor), 0x3f);
> >   
> >   	list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
> > +		uint16_t sr_wm;
> > +
> >   		if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
> >   			continue;
> >   
> >   		if (plane->pipe != pipe)
> >   			continue;
> >   
> > -		wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
> > -					      plane, fifo_size);
> > -		if (wm->sr.plane != 0)
> > -			break;
> > +		sr_wm = vlv_compute_wm(to_intel_crtc(crtc),
> > +				       plane, fifo_size);
> > +		if (sr_wm == 0)
> > +			continue;
> > +
> > +		if (wm->sr.plane == 0)
> > +			wm->sr.plane = sr_wm;
> > +		else
> > +			wm->sr.plane = min(wm->sr.plane, sr_wm);
> >   	}
> >   
> >   	return true;
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[PATCH 11/12] drm/i915: Program PFI credits for VLV

[ville.syrjala]

From: Vidya Srinivas <vidya.srinivas@intel.com>

PFI credit programming is required when CD clock (related to data flow from
display pipeline to end display) is greater than CZ clock (related to data
flow from memory to display plane). This programming should be done when all
planes are OFF to avoid intermittent hangs while accessing memory even from
different Gfx units (not just display).

If cdclk/czclk >=1, PFI credits could be set as any number. To get better
performance, larger PFI credit can be assigned to PND. Otherwise if
cdclk/czclk<1, the default PFI credit of 8 should be set.

v2:
    - Change log to lower log level instead of DRM_ERROR
    - Change function name to valleyview_program_pfi_credits
    - Move program PFI credits to modeset_init instead of intel_set_mode
    - Change magic numbers to logical constants

[vsyrjala v3:
 - only program in response to cdclk update
 - program the credits also when cdclk<czclk
 - add CHV bits]

Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  8 ++++++++
 drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aacf90b..a0a7688 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2061,6 +2061,14 @@ enum skl_disp_power_wells {
 #define   CDCLK_FREQ_SHIFT	4
 #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
 #define   CZCLK_FREQ_MASK	0xf
+
+#define GCI_CONTROL		(VLV_DISPLAY_BASE + 0x650C)
+#define   PFI_CREDIT_63		(9 << 28)		/* chv only */
+#define   PFI_CREDIT_31		(8 << 28)		/* chv only */
+#define   PFI_CREDIT(x)		(((x) - 8) << 28)	/* 8-15 */
+#define   PFI_CREDIT_RESEND	(1 << 27)
+#define   VGA_FAST_MODE_DISABLE	(1 << 14)
+
 #define GMBUSFREQ_VLV		(VLV_DISPLAY_BASE + 0x6510)
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3fe9598..9dcab4b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4987,6 +4987,37 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
 			*prepare_pipes |= (1 << intel_crtc->pipe);
 }
 
+static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
+{
+	unsigned int credits;
+
+	if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
+		/* CHV suggested value is 31 or 63 */
+		if (IS_CHERRYVIEW(dev_priv))
+			credits = PFI_CREDIT_31;
+		else
+			credits = PFI_CREDIT(15);
+	} else {
+		credits = PFI_CREDIT(8);
+	}
+
+	/*
+	 * WA - write default credits before re-programming
+	 * FIXME: should we also set the resend bit here?
+	 */
+	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
+		   PFI_CREDIT(8));
+
+	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
+		   credits | PFI_CREDIT_RESEND);
+
+	/*
+	 * FIXME is this guaranteed to clear
+	 * immediately or should we poll for it?
+	 */
+	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
+}
+
 static void valleyview_modeset_global_resources(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5010,6 +5041,8 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
 		else
 			valleyview_set_cdclk(dev, req_cdclk);
 
+		vlv_program_pfi_credits(dev_priv);
+
 		intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 	}
 }
-- 
2.0.5

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Re: [PATCH 11/12] drm/i915: Program PFI credits for VLV

[Purushothaman, Vijay A]

On 2/10/2015 6:58 PM, ville.syrjala@linux.intel.com wrote:
> From: Vidya Srinivas <vidya.srinivas@intel.com>
>
> PFI credit programming is required when CD clock (related to data flow from
> display pipeline to end display) is greater than CZ clock (related to data
> flow from memory to display plane). This programming should be done when all
> planes are OFF to avoid intermittent hangs while accessing memory even from
> different Gfx units (not just display).
>
> If cdclk/czclk >=1, PFI credits could be set as any number. To get better
> performance, larger PFI credit can be assigned to PND. Otherwise if
> cdclk/czclk<1, the default PFI credit of 8 should be set.
>
> v2:
>      - Change log to lower log level instead of DRM_ERROR
>      - Change function name to valleyview_program_pfi_credits
>      - Move program PFI credits to modeset_init instead of intel_set_mode
>      - Change magic numbers to logical constants
>
> [vsyrjala v3:
>   - only program in response to cdclk update
>   - program the credits also when cdclk<czclk
>   - add CHV bits]
>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h      |  8 ++++++++
>   drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++++++++++++
>   2 files changed, 41 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index aacf90b..a0a7688 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2061,6 +2061,14 @@ enum skl_disp_power_wells {
>   #define   CDCLK_FREQ_SHIFT	4
>   #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
>   #define   CZCLK_FREQ_MASK	0xf
> +
> +#define GCI_CONTROL		(VLV_DISPLAY_BASE + 0x650C)
> +#define   PFI_CREDIT_63		(9 << 28)		/* chv only */
> +#define   PFI_CREDIT_31		(8 << 28)		/* chv only */
> +#define   PFI_CREDIT(x)		(((x) - 8) << 28)	/* 8-15 */
> +#define   PFI_CREDIT_RESEND	(1 << 27)
> +#define   VGA_FAST_MODE_DISABLE	(1 << 14)
> +
>   #define GMBUSFREQ_VLV		(VLV_DISPLAY_BASE + 0x6510)
>   
>   /*
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3fe9598..9dcab4b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4987,6 +4987,37 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
>   			*prepare_pipes |= (1 << intel_crtc->pipe);
>   }
>   
> +static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
> +{
> +	unsigned int credits;
> +
> +	if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
> +		/* CHV suggested value is 31 or 63 */
> +		if (IS_CHERRYVIEW(dev_priv))
> +			credits = PFI_CREDIT_31;
> +		else
> +			credits = PFI_CREDIT(15);
> +	} else {
> +		credits = PFI_CREDIT(8);
The default value should be 4 credits for CHV and 0 for VLV.

> +	}
> +
> +	/*
> +	 * WA - write default credits before re-programming
> +	 * FIXME: should we also set the resend bit here?
> +	 */
> +	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
> +		   PFI_CREDIT(8));
Default credit should be 4 credits for CHV.  PFI_CREDIT(12). Document 
update is pending. But this is the latest recommendation to windows team.

Thanks,
Vijay

> +
> +	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
> +		   credits | PFI_CREDIT_RESEND);
> +
> +	/*
> +	 * FIXME is this guaranteed to clear
> +	 * immediately or should we poll for it?
> +	 */
> +	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
> +}
> +
>   static void valleyview_modeset_global_resources(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -5010,6 +5041,8 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
>   		else
>   			valleyview_set_cdclk(dev, req_cdclk);
>   
> +		vlv_program_pfi_credits(dev_priv);
> +
>   		intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
>   	}
>   }

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Re: [PATCH 11/12] drm/i915: Program PFI credits for VLV

[Ville Syrjälä]

On Wed, Mar 04, 2015 at 07:55:21PM +0530, Purushothaman, Vijay A wrote:
> On 2/10/2015 6:58 PM, ville.syrjala@linux.intel.com wrote:
> > From: Vidya Srinivas <vidya.srinivas@intel.com>
> >
> > PFI credit programming is required when CD clock (related to data flow from
> > display pipeline to end display) is greater than CZ clock (related to data
> > flow from memory to display plane). This programming should be done when all
> > planes are OFF to avoid intermittent hangs while accessing memory even from
> > different Gfx units (not just display).
> >
> > If cdclk/czclk >=1, PFI credits could be set as any number. To get better
> > performance, larger PFI credit can be assigned to PND. Otherwise if
> > cdclk/czclk<1, the default PFI credit of 8 should be set.
> >
> > v2:
> >      - Change log to lower log level instead of DRM_ERROR
> >      - Change function name to valleyview_program_pfi_credits
> >      - Move program PFI credits to modeset_init instead of intel_set_mode
> >      - Change magic numbers to logical constants
> >
> > [vsyrjala v3:
> >   - only program in response to cdclk update
> >   - program the credits also when cdclk<czclk
> >   - add CHV bits]
> >
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_reg.h      |  8 ++++++++
> >   drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++++++++++++
> >   2 files changed, 41 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index aacf90b..a0a7688 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2061,6 +2061,14 @@ enum skl_disp_power_wells {
> >   #define   CDCLK_FREQ_SHIFT	4
> >   #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
> >   #define   CZCLK_FREQ_MASK	0xf
> > +
> > +#define GCI_CONTROL		(VLV_DISPLAY_BASE + 0x650C)
> > +#define   PFI_CREDIT_63		(9 << 28)		/* chv only */
> > +#define   PFI_CREDIT_31		(8 << 28)		/* chv only */
> > +#define   PFI_CREDIT(x)		(((x) - 8) << 28)	/* 8-15 */
> > +#define   PFI_CREDIT_RESEND	(1 << 27)
> > +#define   VGA_FAST_MODE_DISABLE	(1 << 14)
> > +
> >   #define GMBUSFREQ_VLV		(VLV_DISPLAY_BASE + 0x6510)
> >   
> >   /*
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 3fe9598..9dcab4b 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4987,6 +4987,37 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
> >   			*prepare_pipes |= (1 << intel_crtc->pipe);
> >   }
> >   
> > +static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
> > +{
> > +	unsigned int credits;
> > +
> > +	if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
> > +		/* CHV suggested value is 31 or 63 */
> > +		if (IS_CHERRYVIEW(dev_priv))
> > +			credits = PFI_CREDIT_31;
> > +		else
> > +			credits = PFI_CREDIT(15);
> > +	} else {
> > +		credits = PFI_CREDIT(8);
> The default value should be 4 credits for CHV and 0 for VLV.

8 is the minimum. So I think on CHV we actually want PFI_CREDIT(12).

The reason the CHV value is wrong here is because I wrote the patch
based on the spec, and sadly the new recommended value isn't in the
spec.

> 
> > +	}
> > +
> > +	/*
> > +	 * WA - write default credits before re-programming
> > +	 * FIXME: should we also set the resend bit here?
> > +	 */
> > +	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
> > +		   PFI_CREDIT(8));
> Default credit should be 4 credits for CHV.  PFI_CREDIT(12). Document 
> update is pending. But this is the latest recommendation to windows team.

Right. So exactly as I thought too. I'll respin the patch with the new
value.

> 
> Thanks,
> Vijay
> 
> > +
> > +	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
> > +		   credits | PFI_CREDIT_RESEND);
> > +
> > +	/*
> > +	 * FIXME is this guaranteed to clear
> > +	 * immediately or should we poll for it?
> > +	 */
> > +	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
> > +}
> > +
> >   static void valleyview_modeset_global_resources(struct drm_device *dev)
> >   {
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -5010,6 +5041,8 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
> >   		else
> >   			valleyview_set_cdclk(dev, req_cdclk);
> >   
> > +		vlv_program_pfi_credits(dev_priv);
> > +
> >   		intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
> >   	}
> >   }
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
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Re: [PATCH 11/12] drm/i915: Program PFI credits for VLV

[Ville Syrjälä]

On Wed, Mar 04, 2015 at 07:55:21PM +0530, Purushothaman, Vijay A wrote:
> On 2/10/2015 6:58 PM, ville.syrjala@linux.intel.com wrote:
> > From: Vidya Srinivas <vidya.srinivas@intel.com>
> >
> > PFI credit programming is required when CD clock (related to data flow from
> > display pipeline to end display) is greater than CZ clock (related to data
> > flow from memory to display plane). This programming should be done when all
> > planes are OFF to avoid intermittent hangs while accessing memory even from
> > different Gfx units (not just display).
> >
> > If cdclk/czclk >=1, PFI credits could be set as any number. To get better
> > performance, larger PFI credit can be assigned to PND. Otherwise if
> > cdclk/czclk<1, the default PFI credit of 8 should be set.
> >
> > v2:
> >      - Change log to lower log level instead of DRM_ERROR
> >      - Change function name to valleyview_program_pfi_credits
> >      - Move program PFI credits to modeset_init instead of intel_set_mode
> >      - Change magic numbers to logical constants
> >
> > [vsyrjala v3:
> >   - only program in response to cdclk update
> >   - program the credits also when cdclk<czclk
> >   - add CHV bits]
> >
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_reg.h      |  8 ++++++++
> >   drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++++++++++++
> >   2 files changed, 41 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index aacf90b..a0a7688 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2061,6 +2061,14 @@ enum skl_disp_power_wells {
> >   #define   CDCLK_FREQ_SHIFT	4
> >   #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
> >   #define   CZCLK_FREQ_MASK	0xf
> > +
> > +#define GCI_CONTROL		(VLV_DISPLAY_BASE + 0x650C)
> > +#define   PFI_CREDIT_63		(9 << 28)		/* chv only */
> > +#define   PFI_CREDIT_31		(8 << 28)		/* chv only */
> > +#define   PFI_CREDIT(x)		(((x) - 8) << 28)	/* 8-15 */
> > +#define   PFI_CREDIT_RESEND	(1 << 27)
> > +#define   VGA_FAST_MODE_DISABLE	(1 << 14)
> > +
> >   #define GMBUSFREQ_VLV		(VLV_DISPLAY_BASE + 0x6510)
> >   
> >   /*
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 3fe9598..9dcab4b 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4987,6 +4987,37 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
> >   			*prepare_pipes |= (1 << intel_crtc->pipe);
> >   }
> >   
> > +static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
> > +{
> > +	unsigned int credits;
> > +
> > +	if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
> > +		/* CHV suggested value is 31 or 63 */
> > +		if (IS_CHERRYVIEW(dev_priv))
> > +			credits = PFI_CREDIT_31;
> > +		else
> > +			credits = PFI_CREDIT(15);
> > +	} else {
> > +		credits = PFI_CREDIT(8);
> The default value should be 4 credits for CHV and 0 for VLV.
> 
> > +	}
> > +
> > +	/*
> > +	 * WA - write default credits before re-programming
> > +	 * FIXME: should we also set the resend bit here?
> > +	 */
> > +	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
> > +		   PFI_CREDIT(8));
> Default credit should be 4 credits for CHV.  PFI_CREDIT(12). Document 
> update is pending. But this is the latest recommendation to windows team.

BTW do you have any specific information about this workaround? I asked
Vandana about it when she first submitted the patch and she said she'd
get back to me on that, but I don't think I ever got an actual answer.
The FIXMEs in particular would need to be answered.

Also if we still need this workaround on CHV, I don't know if we should
set the credits to 8 or 12 here. Any ideas?

> 
> Thanks,
> Vijay
> 
> > +
> > +	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
> > +		   credits | PFI_CREDIT_RESEND);
> > +
> > +	/*
> > +	 * FIXME is this guaranteed to clear
> > +	 * immediately or should we poll for it?
> > +	 */
> > +	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
> > +}
> > +
> >   static void valleyview_modeset_global_resources(struct drm_device *dev)
> >   {
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -5010,6 +5041,8 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
> >   		else
> >   			valleyview_set_cdclk(dev, req_cdclk);
> >   
> > +		vlv_program_pfi_credits(dev_priv);
> > +
> >   		intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
> >   	}
> >   }
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH 12/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV has a new knob in Punit to select between some memory power savings
modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
enabled, so let's do so in the hopes for moar power savings.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0a7688..2196e57 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -552,6 +552,9 @@
 #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
 #define   DSPFREQGUAR_SHIFT			14
 #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
+#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
+#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
+#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
 #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
 #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
 #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e6cbc24..4e11552 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -240,7 +240,18 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 	struct drm_device *dev = dev_priv->dev;
 	u32 val;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_CHERRYVIEW(dev)) {
+		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
+
+		mutex_lock(&dev_priv->rps.hw_lock);
+		val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+		if (enable)
+			val |= DSP_MAXFIFO_PM5_ENABLE;
+		else
+			val &= ~DSP_MAXFIFO_PM5_ENABLE;
+		vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+	} else if (IS_VALLEYVIEW(dev)) {
 		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
-- 
2.0.5

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Re: [PATCH 12/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5748
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV              +3                 275/283              278/283
ILK              +1-2              310/315              309/315
SNB              +3                 320/346              323/346
IVB                 -1              380/384              379/384
BYT                                  296/296              296/296
HSW              +3                 422/428              425/428
BDW                                  318/333              318/333
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt_gem_userptr_blits_coherency-sync      CRASH(3, M7)PASS(2, M7)      PASS(1, M7)
 PNV  igt_gem_userptr_blits_coherency-unsync      CRASH(3, M7)PASS(3, M7)      PASS(1, M7)
 PNV  igt_gem_userptr_blits_create-destroy-sync      NRUN(1, M7)PASS(5, M7)      PASS(1, M7)
 PNV  igt_gen3_render_tiledx_blits      FAIL(2, M7)TIMEOUT(1, M7)PASS(3, M7)      FAIL(1, M7)
 ILK  igt_gem_fenced_exec_thrash_no-spare-fences-busy-interruptible      DMESG_WARN(1, M26)PASS(1, M26)      DMESG_WARN(1, M26)
*ILK  igt_gem_unfence_active_buffers      PASS(3, M26)      DMESG_WARN(1, M26)
*ILK  igt_drv_suspend_forcewake      DMESG_WARN(3, M26)      PASS(1, M26)
*SNB  igt_kms_flip_bo-too-big      BLACKLIST(1, M35)      PASS(1, M35)
*SNB  igt_kms_flip_bo-too-big-interruptible      BLACKLIST(1, M35)      PASS(1, M35)
*SNB  igt_kms_flip_event_leak      NSPT(5, M35)      PASS(1, M35)
 IVB  igt_gem_storedw_batches_loop_normal      DMESG_WARN(1, M4)PASS(4, M4)      DMESG_WARN(1, M4)
*HSW  igt_kms_flip_bo-too-big      BLACKLIST(1, M40)      PASS(1, M40)
*HSW  igt_kms_flip_bo-too-big-interruptible      BLACKLIST(1, M40)      PASS(1, M40)
 HSW  igt_kms_flip_plain-flip-fb-recreate-interruptible      TIMEOUT(5, M40)PASS(2, M40)      PASS(1, M40)
Note: You need to pay more attention to line start with '*'
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[PATCH v2 12/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV has a new knob in Punit to select between some memory power savings
modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
enabled, so let's do so in the hopes for moar power savings.

v2: Put the thing into a separate function to avoid churn later

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 drivers/gpu/drm/i915/intel_pm.c | 19 ++++++++++++++++++-
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 145f0d4..5a20f58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -552,6 +552,9 @@
 #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
 #define   DSPFREQGUAR_SHIFT			14
 #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
+#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
+#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
+#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
 #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
 #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
 #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e6cbc24..f603dac 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -235,13 +235,30 @@ static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 	return NULL;
 }
 
+static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
+{
+	u32 val;
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+	if (enable)
+		val |= DSP_MAXFIFO_PM5_ENABLE;
+	else
+		val &= ~DSP_MAXFIFO_PM5_ENABLE;
+	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
+
+	mutex_unlock(&dev_priv->rps.hw_lock);
+}
+
 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 {
 	struct drm_device *dev = dev_priv->dev;
 	u32 val;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_CHERRYVIEW(dev)) {
 		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
+		chv_set_memory_pm5(dev_priv, enable);
 	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 	} else if (IS_PINEVIEW(dev)) {
-- 
2.0.5

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Re: [PATCH 12/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV

[Purushothaman, Vijay A]

On 2/10/2015 6:58 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CHV has a new knob in Punit to select between some memory power savings
> modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
> enabled, so let's do so in the hopes for moar power savings.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h |  3 +++
>   drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++++-
>   2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a0a7688..2196e57 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -552,6 +552,9 @@
>   #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
>   #define   DSPFREQGUAR_SHIFT			14
>   #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
> +#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
> +#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
> +#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
>   #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
>   #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
>   #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e6cbc24..4e11552 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -240,7 +240,18 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
>   	struct drm_device *dev = dev_priv->dev;
>   	u32 val;
>   
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_CHERRYVIEW(dev)) {
> +		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> +
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> +		if (enable)
> +			val |= DSP_MAXFIFO_PM5_ENABLE;
> +		else
> +			val &= ~DSP_MAXFIFO_PM5_ENABLE;
> +		vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +	} else if (IS_VALLEYVIEW(dev)) {
>   		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
>   	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
>   		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
Since you are enabling MaxFIFO for multi plane in one of the previous 
patches, i guess PM5 will also be enabled when more than one plane is 
active in this flow.
Let's enable MaxFIFO and PM5 when only one plane is active for now. This 
is the only validated scenario by SV.

With this addressed,
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>

Thanks,
Vijay


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Re: [PATCH 12/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV

[Ville Syrjälä]

On Wed, Mar 04, 2015 at 07:58:50PM +0530, Purushothaman, Vijay A wrote:
> On 2/10/2015 6:58 PM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > CHV has a new knob in Punit to select between some memory power savings
> > modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
> > enabled, so let's do so in the hopes for moar power savings.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_reg.h |  3 +++
> >   drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++++-
> >   2 files changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index a0a7688..2196e57 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -552,6 +552,9 @@
> >   #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
> >   #define   DSPFREQGUAR_SHIFT			14
> >   #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
> > +#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
> > +#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
> > +#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
> >   #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
> >   #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
> >   #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index e6cbc24..4e11552 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -240,7 +240,18 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
> >   	struct drm_device *dev = dev_priv->dev;
> >   	u32 val;
> >   
> > -	if (IS_VALLEYVIEW(dev)) {
> > +	if (IS_CHERRYVIEW(dev)) {
> > +		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> > +
> > +		mutex_lock(&dev_priv->rps.hw_lock);
> > +		val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> > +		if (enable)
> > +			val |= DSP_MAXFIFO_PM5_ENABLE;
> > +		else
> > +			val &= ~DSP_MAXFIFO_PM5_ENABLE;
> > +		vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> > +		mutex_unlock(&dev_priv->rps.hw_lock);
> > +	} else if (IS_VALLEYVIEW(dev)) {
> >   		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> >   	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
> >   		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
> Since you are enabling MaxFIFO for multi plane in one of the previous 
> patches, i guess PM5 will also be enabled when more than one plane is 
> active in this flow.
> Let's enable MaxFIFO and PM5 when only one plane is active for now. This 
> is the only validated scenario by SV.

Yep that's good enough for me.

> 
> With this addressed,
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> 
> Thanks,
> Vijay
> 
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
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[PATCH v2 00/12] drm/i915: Redo VLV/CHV watermark code (v2)

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Here's an updated version of the series to redo the VLV/CHV watermark
code. The most important thing is that this makes the display stable
on BSW with the fancy new memory PM features enabled by the firmware.

Changes since v1:
* Drop the two plane maxfifo mode patch (Vijay)
* Move one the misplaced hunk to the right patch (Jesse)
* Use the right amount of PFI credits for the cdclk<czclk case (Vijay)
* Drop the extra drain latency multipler frobbing as it no longer
  seems to be necessary to get a stable picture with multiple 4k
  displays. Not really sure if this was due to a BIOS update or what.
* Use plane->state->fb instead of plane->fb in the wm/ddl calculations.
* Don't break VLV maxfifo enable/disable. Noticed this one myself while
  going through the patches

I'm still missing a review on
"drm/i915: Rewrite VLV/CHV watermark code" and "drm/i915: Disable DDR DVFS on CHV"
The rest have r-bs now. I kept Jesses r-b on "drm/i915: Pass plane to
vlv_compute_drain_latency()" even though v2 is a slightly different that
v1 due to the plane->state changes.

Vidya Srinivas (1):
  drm/i915: Program PFI credits for VLV

Ville Syrjälä (11):
  drm/i915: Reduce CHV DDL multiplier to 16/8
  drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines
  drm/i915: Simplify VLV drain latency computation
  drm/i915: Hide VLV DDL precision handling
  drm/i915: Reorganize VLV DDL setup
  drm/i915: Pass plane to vlv_compute_drain_latency()
  drm/i915: Read out display FIFO size on VLV/CHV
  drm/i915: Make sure PND deadline mode is enabled on VLV/CHV
  drm/i915: Rewrite VLV/CHV watermark code
  drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV
  drm/i915: Disable DDR DVFS on CHV

 drivers/gpu/drm/i915/i915_drv.h      |  20 ++
 drivers/gpu/drm/i915/i915_reg.h      |  39 ++-
 drivers/gpu/drm/i915/intel_display.c |  38 +++
 drivers/gpu/drm/i915/intel_pm.c      | 577 +++++++++++++++++++++--------------
 4 files changed, 432 insertions(+), 242 deletions(-)

-- 
2.0.5

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[PATCH v2 07/12] drm/i915: Read out display FIFO size on VLV/CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

VLV/CHV have similar DSPARB registers as older platforms, just more of
them due to more planes. Add a bit of code to read out the current FIFO
split from the registers. Will be useful later when we improve the WM
calculations.

v2: Add display_mmio_offset to DSPARB

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  5 +++-
 drivers/gpu/drm/i915/intel_pm.c | 55 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b35aaf3..3b48f4b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4026,7 +4026,7 @@ enum skl_disp_power_wells {
 #define   DPINVGTT_STATUS_MASK			0xff
 #define   DPINVGTT_STATUS_MASK_CHV		0xfff
 
-#define DSPARB			0x70030
+#define DSPARB			(dev_priv->info.display_mmio_offset + 0x70030)
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
 #define   DSPARB_CSTART_SHIFT	7
 #define   DSPARB_BSTART_MASK	(0x7f)
@@ -4034,6 +4034,9 @@ enum skl_disp_power_wells {
 #define   DSPARB_BEND_SHIFT	9 /* on 855 */
 #define   DSPARB_AEND_SHIFT	0
 
+#define DSPARB2			(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
+#define DSPARB3			(VLV_DISPLAY_BASE + 0x7006c) /* chv */
+
 /* pnv/gen4/g4x/vlv/chv */
 #define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
 #define   DSPFW_SR_SHIFT		23
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f8f6cee..27ce40c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -280,6 +280,61 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
  */
 static const int pessimal_latency_ns = 5000;
 
+#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
+	((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
+
+static int vlv_get_fifo_size(struct drm_device *dev,
+			      enum pipe pipe, int plane)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int sprite0_start, sprite1_start, size;
+
+	switch (pipe) {
+		uint32_t dsparb, dsparb2, dsparb3;
+	case PIPE_A:
+		dsparb = I915_READ(DSPARB);
+		dsparb2 = I915_READ(DSPARB2);
+		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
+		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
+		break;
+	case PIPE_B:
+		dsparb = I915_READ(DSPARB);
+		dsparb2 = I915_READ(DSPARB2);
+		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
+		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
+		break;
+	case PIPE_C:
+		dsparb2 = I915_READ(DSPARB2);
+		dsparb3 = I915_READ(DSPARB3);
+		sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
+		sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
+		break;
+	default:
+		return 0;
+	}
+
+	switch (plane) {
+	case 0:
+		size = sprite0_start;
+		break;
+	case 1:
+		size = sprite1_start - sprite0_start;
+		break;
+	case 2:
+		size = 512 - 1 - sprite1_start;
+		break;
+	default:
+		return 0;
+	}
+
+	DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
+		      pipe_name(pipe), plane == 0 ? "primary" : "sprite",
+		      plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
+		      size);
+
+	return size;
+}
+
 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-- 
2.0.5

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