[U-Boot] [PATCH 0/4] ARM / OMAP5 / DRA7 : Enable proper l2actl configuration

[U-Boot] [PATCH 0/4] ARM / OMAP5 / DRA7 : Enable proper l2actl configuration

[Nishanth Menon]

Hi,

Triggered by a user report, it was seen that recommended errata
workaround and performance trade-offs as recommended by TI architects
for ARM configuration was not being followed in OMAP5+ ARM A15
platforms in u-boot configuration. Note OMAP5, DRA7 all share the
same cortex A15 revision (ID=0x412fc0f2) and the workarounds and
improvement configurations apply equally.

Certain errata workaround done in this series obviously have the
controversy potential considering that each of the SoCs implement
workaround based on secure monitor calls, but both the service
requested and the parameters of secure monitor calls can be widely
variant. Examples:
OMAP family of processors have quite the family of SMC calls:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mach-omap2/omap-smc.S
meanwhile Exynos has a much simpler invocation:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mach-exynos/exynos-smc.S

To maintain some resemblance of symmetry the following series
introduces a arch/machine dependent errata macro which must be enabled
prior to any of such workarounds can be implemented.

I am open to better ways of doing this which might benefit others in
ARM community with similar needs. Lets discuss.

These patches are based on: v2015.04-rc1 but also apply on latest master.

Testing:

AM5728 based Beagleboard-X15: http://pastebin.ubuntu.com/10280020/
DRA722 based Evm: http://pastebin.ubuntu.com/10280074/
DRA742 based Evm: http://pastebin.ubuntu.com/10280115/
OMAP5432 uEVM: http://pastebin.ubuntu.com/10280176/
OMAP4460 PandaBoard-ES: http://pastebin.ubuntu.com/10280208/ (just sanity)

Appropriate CP15 configuration was cross verified by Lauterbach or by
a custom kernel patch (http://paste.ubuntu.org.cn/2410711).

Angela Stegmaier (1):
  configs: ti_omap5_common: Enable workaround for ARM errata 798870

Nishanth Menon (2):
  ARM: OMAP: Change set_pl310_ctrl_reg to be generic
  ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended
    configuration

Praveen Rao (1):
  ARM / OMAP5: Add workaround for ARM errata 798870

 arch/arm/cpu/armv7/omap-common/lowlevel_init.S |    8 ++++--
 arch/arm/cpu/armv7/omap4/hwinit.c              |    4 +--
 arch/arm/cpu/armv7/omap5/hwinit.c              |   16 +++++++++++
 arch/arm/cpu/armv7/omap5/lowlevel_init.S       |   35 ++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h    |    5 +++-
 arch/arm/include/asm/arch-omap5/sys_proto.h    |    4 +++
 include/configs/ti_omap5_common.h              |    4 +++
 7 files changed, 70 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap5/lowlevel_init.S

-- 
1.7.9.5

Regards,
Nishanth Menon

[U-Boot] [PATCH 1/4] ARM: OMAP: Change set_pl310_ctrl_reg to be generic

[Nishanth Menon]

set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The
only difference being the service being invoked for the function.

So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add
a data barrier which is necessary as per recommendation.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S |    8 +++++---
 arch/arm/cpu/armv7/omap4/hwinit.c              |    4 ++--
 arch/arm/include/asm/arch-omap4/sys_proto.h    |    5 ++++-
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 86c0e4217478..cc3603d798e9 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -22,11 +22,13 @@ ENTRY(save_boot_params)
 	bx	lr
 ENDPROC(save_boot_params)
 
-ENTRY(set_pl310_ctrl_reg)
+ENTRY(omap_smc1)
 	PUSH	{r4-r11, lr}	@ save registers - ROM code may pollute
 				@ our registers
-	LDR	r12, =0x102	@ Set PL310 control register - value in R0
+	MOV	r12, r0		@ Service
+	MOV	r0, r1		@ Argument
+	DSB
 	.word	0xe1600070	@ SMC #0 - hand assembled because -march=armv5
 				@ call ROM Code API to set control register
 	POP	{r4-r11, pc}
-ENDPROC(set_pl310_ctrl_reg)
+ENDPROC(omap_smc1)
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index db16548fac49..9792761d40a0 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -159,11 +159,11 @@ void init_omap_revision(void)
 #ifndef CONFIG_SYS_L2CACHE_OFF
 void v7_outer_cache_enable(void)
 {
-	set_pl310_ctrl_reg(1);
+	omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
 }
 
 void v7_outer_cache_disable(void)
 {
-	set_pl310_ctrl_reg(0);
+	omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
 }
 #endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index e19975efaf50..f425e3af54f5 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -37,7 +37,7 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void set_pl310_ctrl_reg(u32 val);
+void omap_smc1(u32 service, u32 val);
 void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 const base);
@@ -57,4 +57,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
 void setup_warmreset_time(void);
+
+#define OMAP4_SERVICE_PL310_CONTROL_REG_SET	0x102
+
 #endif
-- 
1.7.9.5

[U-Boot] [PATCH 2/4] ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration

[Nishanth Menon]

Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.

These apply to both OMAP5 and DRA7.

Reported-by: Vivek Chengalvala <vchengalvala@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/cpu/armv7/omap5/hwinit.c           |   16 ++++++++++++++++
 arch/arm/include/asm/arch-omap5/sys_proto.h |    4 ++++
 2 files changed, 20 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index a8a474a88be9..632df4f0bfae 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -304,6 +304,21 @@ void config_data_eye_leveling_samples(u32 emif_base)
 		       (*ctrl)->control_emif2_sdram_config_ext);
 }
 
+void init_cpu_configuration(void)
+{
+	u32 l2actlr;
+
+	asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
+	/*
+	 * L2ACTLR: Ensure to enable the following:
+	 * 3: Disable clean/evict push to external
+	 * 4: Disable WriteUnique and WriteLineUnique transactions from master
+	 * 8: Disable DVM/CMO message broadcast
+	 */
+	l2actlr |= 0x118;
+	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
+}
+
 void init_omap_revision(void)
 {
 	/*
@@ -342,6 +357,7 @@ void init_omap_revision(void)
 	default:
 		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 	}
+	init_cpu_configuration();
 }
 
 void reset_cpu(ulong ignored)
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 103830319a41..e2e186859373 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -56,6 +56,7 @@ void force_emif_self_refresh(void);
 void get_ioregs(const struct ctrl_ioregs **regs);
 void srcomp_enable(void);
 void setup_warmreset_time(void);
+void omap_smc1(u32 service, u32 val);
 
 static inline u32 div_round_up(u32 num, u32 den)
 {
@@ -66,4 +67,7 @@ static inline u32 usec_to_32k(u32 usec)
 {
 	return div_round_up(32768 * usec, 1000000);
 }
+
+#define OMAP5_SERVICE_L2ACTLR_SET    0x104
+
 #endif
-- 
1.7.9.5

[U-Boot] [PATCH 3/4] ARM / OMAP5: Add workaround for ARM errata 798870

[Nishanth Menon]

From: Praveen Rao <prao@ti.com>

This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Note: Every SoC has slightly different manner of setting up access
to L2ACLR and similar registers since the Secure Monitor handling
of Secure Monitor Call(smc) is diverse. Hence an ARCH specific
macro is introduced to implement SoC specific errata workaround
implementations.

An intial implementation for OMAP5 and DRA7 is introduced here as well.
Obviously, implementations for other SoC families such as Exynos etc
will be widely different.

Signed-off-by: Praveen Rao <prao@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/cpu/armv7/omap5/lowlevel_init.S |   35 ++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/omap5/lowlevel_init.S

diff --git a/arch/arm/cpu/armv7/omap5/lowlevel_init.S b/arch/arm/cpu/armv7/omap5/lowlevel_init.S
new file mode 100644
index 000000000000..1cc3c7af5fe2
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/lowlevel_init.S
@@ -0,0 +1,35 @@
+/*
+ * Board specific misc setup
+ *
+ * (C) Copyright 2015
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+#include <asm/arch/spl.h>
+#include <linux/linkage.h>
+
+#ifdef CONFIG_ARM_ARCH_CP15_ERRATA
+	.globl	arch_cp15_errata_workaround
+ENTRY(arch_cp15_errata_workaround)
+	push	{r4-r11, lr}	@ save registers - ROM code may pollute
+
+#ifdef CONFIG_ARM_ERRATA_798870
+	mrc     p15, 0, r0, c0, c0, 0   @ Read Main ID Register (MIDR)
+	and     r0, r0, #0x000000f0     @ check rev
+	cmp     r0, #0x000000f0         @ compare rev
+	bne     skip_errata_798870      @ skip if not affected rev
+	mrc     p15, 1, r1, c15, c0, 0  @ read l2 aux ctrl reg
+	orr     r1, r1, #1 << 7         @ set bit #7
+	ldr     r0, =OMAP5_SERVICE_L2ACTLR_SET    @ Set L2 Cache Auxiliary control register - value in R0
+	b omap_smc1
+skip_errata_798870:
+#endif
+	pop	{r4-r11, pc}
+ENDPROC(arch_cp15_errata_workaround)
+
+#endif
-- 
1.7.9.5

[U-Boot] [PATCH 4/4] configs: ti_omap5_common: Enable workaround for ARM errata 798870

[Nishanth Menon]

From: Angela Stegmaier <angelabaker@ti.com>

Enable the workaround for ARM errata 798870 for OMAP5
and DRA7xx since they are Coretx-A15 r2.

Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 include/configs/ti_omap5_common.h |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 925cb42dd38d..bce9a505cbb3 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -21,6 +21,10 @@
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_ARCH_CPU_INIT
 
+/* Common ARM Erratas */
+#define CONFIG_ARM_ARCH_CP15_ERRATA
+#define CONFIG_ARM_ERRATA_798870
+
 #define CONFIG_SYS_CACHELINE_SIZE	64
 
 /* Use General purpose timer 1 */
-- 
1.7.9.5