[PATCH 2/7] drm/i915/skl: Updated the gen6_set_rps function

[PATCH 2/7] drm/i915/skl: Updated the gen6_set_rps function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

On SKL, the frequency programmed in RPNSWREQ (A008) register
has to be in units of 16.66 MHZ. So updated the gen6_set_rps
function, as per this change.

Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Lespiau, Damien <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bebefe7..1df3fbd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3764,7 +3764,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
 	if (val != dev_priv->rps.cur_freq) {
 		gen6_set_rps_thresholds(dev_priv, val);
 
-		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		if (IS_GEN9(dev))
+			I915_WRITE(GEN6_RPNSWREQ,
+				GEN9_FREQUENCY(val * GEN9_FREQ_SCALER));
+		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 			I915_WRITE(GEN6_RPNSWREQ,
 				   HSW_FREQUENCY(val));
 		else
-- 
1.9.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/7] drm/i915/skl: Enabling processing of Turbo interrupts

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Earlier Turbo interrupts were not being processed for SKL,
as something was amiss in turbo programming for SKL.
Now missing changes have been added, so enabling the Turbo
interrupt processing for SKL.

Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Lespiau, Damien <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e6342da..333c0f8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1745,11 +1745,6 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
  * the work queue. */
 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
 {
-	/* TODO: RPS on GEN9+ is not supported yet. */
-	if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
-		      "GEN9+: unexpected RPS IRQ\n"))
-		return;
-
 	if (pm_iir & dev_priv->pm_rps_events) {
 		spin_lock(&dev_priv->irq_lock);
 		gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
-- 
1.9.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 0/7] Added missing changes for Turbo feature on SKL

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

This patch series add missing changes, required for proper functioning of the
Turbo feature on SKL.
Addressed review comments from Damien & Chris. 

Akash Goel (7):
  drm/i915/skl: Added new macros
  drm/i915/skl: Updated the gen6_set_rps function
  drm/i915/skl: Restructured the gen6_set_rps_thresholds function
  drm/i915/skl: Updated the gen6_rps_limits function
  drm/i915/skl: Updated the gen9_enable_rps function
  drm/i915/skl: Updated the 'i915_frequency_info' debugs function
  drm/i915/skl: Enabling processing of Turbo interrupts

 drivers/gpu/drm/i915/i915_debugfs.c |  25 ++++---
 drivers/gpu/drm/i915/i915_drv.h     |   1 +
 drivers/gpu/drm/i915/i915_irq.c     |   5 --
 drivers/gpu/drm/i915/i915_reg.h     |   9 +++
 drivers/gpu/drm/i915/intel_pm.c     | 130 ++++++++++++++++++++++--------------
 5 files changed, 106 insertions(+), 64 deletions(-)

-- 
1.9.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 1/5] drm/i915/skl: Added new macros

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C)
have changed slightly. Also on SKL, frequency is specified in
units of 16.66 MHZ, compared to 50 MHZ for most of the earlier
platforms and the time values are expressed in units of 1.33 us,
compared to 1.28 us for earlier platforms.
Added new macros for the aforementioned changes.

v2: Renamed the GT_FREQ_FROM_PERIOD macro to GT_INTERVAL_FROM_US (Damien)

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ca64b99..529b9b2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2485,6 +2485,7 @@ struct drm_i915_cmd_table {
 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
 
 #define GT_FREQUENCY_MULTIPLIER 50
+#define GEN9_FREQ_SCALER 3
 
 #include "i915_trace.h"
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cd3430f9..a82436d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2389,6 +2389,12 @@ enum skl_disp_power_wells {
 #define GEN6_RP_STATE_LIMITS	(MCHBAR_MIRROR_BASE_SNB + 0x5994)
 #define GEN6_RP_STATE_CAP	(MCHBAR_MIRROR_BASE_SNB + 0x5998)
 
+#define INTERVAL_1_28_US(us)	(((us) * 100) >> 7)
+#define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
+#define GT_INTERVAL_FROM_US(us) (IS_GEN9(dev_priv->dev) ? \
+				INTERVAL_1_33_US(us) : \
+				INTERVAL_1_28_US(us))
+
 /*
  * Logical Context regs
  */
@@ -6023,6 +6029,7 @@ enum skl_disp_power_wells {
 #define   GEN6_TURBO_DISABLE			(1<<31)
 #define   GEN6_FREQUENCY(x)			((x)<<25)
 #define   HSW_FREQUENCY(x)			((x)<<24)
+#define   GEN9_FREQUENCY(x)			((x)<<23)
 #define   GEN6_OFFSET(x)			((x)<<19)
 #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
 #define GEN6_RC_VIDEO_FREQ			0xA00C
@@ -6041,8 +6048,10 @@ enum skl_disp_power_wells {
 #define GEN6_RPSTAT1				0xA01C
 #define   GEN6_CAGF_SHIFT			8
 #define   HSW_CAGF_SHIFT			7
+#define   GEN9_CAGF_SHIFT			23
 #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
 #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
+#define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
 #define GEN6_RP_CONTROL				0xA024
 #define   GEN6_RP_MEDIA_TURBO			(1<<11)
 #define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
-- 
1.9.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 3/5] drm/i915/skl: Restructured the gen6_set_rps_thresholds function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Prior to SKL, the time period programmed in Up/Down EI & Up/Down
threshold registers was in units of 1.28 micro seconds. But for
SKL, the units have changed (1.333 micro seconds).
Have generalized the implementation of gen6_set_rps_thresholds function,
by removing the hard coding done in it as per 1.28 micro seconds.

v2: Renamed the local variables & removed superfluous comments (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 68 +++++++++++++++++++----------------------
 1 file changed, 32 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1df3fbd..78b4d62 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3643,6 +3643,8 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
 {
 	int new_power;
+	u32 threshold_up = 0, threshold_down = 0; /* in % */
+	u32 ei_up = 0, ei_down = 0;
 
 	new_power = dev_priv->rps.power;
 	switch (dev_priv->rps.power) {
@@ -3675,59 +3677,53 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
 	switch (new_power) {
 	case LOW_POWER:
 		/* Upclock if more than 95% busy over 16ms */
-		I915_WRITE(GEN6_RP_UP_EI, 12500);
-		I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
+		ei_up = 16000;
+		threshold_up = 95;
 
 		/* Downclock if less than 85% busy over 32ms */
-		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
-		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
-
-		I915_WRITE(GEN6_RP_CONTROL,
-			   GEN6_RP_MEDIA_TURBO |
-			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-			   GEN6_RP_MEDIA_IS_GFX |
-			   GEN6_RP_ENABLE |
-			   GEN6_RP_UP_BUSY_AVG |
-			   GEN6_RP_DOWN_IDLE_AVG);
+		ei_down = 32000;
+		threshold_down = 85;
 		break;
 
 	case BETWEEN:
 		/* Upclock if more than 90% busy over 13ms */
-		I915_WRITE(GEN6_RP_UP_EI, 10250);
-		I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
+		ei_up = 13000;
+		threshold_up = 90;
 
 		/* Downclock if less than 75% busy over 32ms */
-		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
-		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
-
-		I915_WRITE(GEN6_RP_CONTROL,
-			   GEN6_RP_MEDIA_TURBO |
-			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-			   GEN6_RP_MEDIA_IS_GFX |
-			   GEN6_RP_ENABLE |
-			   GEN6_RP_UP_BUSY_AVG |
-			   GEN6_RP_DOWN_IDLE_AVG);
+		ei_down = 32000;
+		threshold_down = 75;
 		break;
 
 	case HIGH_POWER:
 		/* Upclock if more than 85% busy over 10ms */
-		I915_WRITE(GEN6_RP_UP_EI, 8000);
-		I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
+		ei_up = 10000;
+		threshold_up = 85;
 
 		/* Downclock if less than 60% busy over 32ms */
-		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
-		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
-
-		I915_WRITE(GEN6_RP_CONTROL,
-			   GEN6_RP_MEDIA_TURBO |
-			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-			   GEN6_RP_MEDIA_IS_GFX |
-			   GEN6_RP_ENABLE |
-			   GEN6_RP_UP_BUSY_AVG |
-			   GEN6_RP_DOWN_IDLE_AVG);
+		ei_down = 32000;
+		threshold_down = 60;
 		break;
 	}
 
+	I915_WRITE(GEN6_RP_UP_EI,
+		GT_INTERVAL_FROM_US(ei_up));
+	I915_WRITE(GEN6_RP_UP_THRESHOLD,
+		GT_INTERVAL_FROM_US((ei_up * threshold_up / 100)));
+
+	I915_WRITE(GEN6_RP_DOWN_EI,
+		GT_INTERVAL_FROM_US(ei_down));
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
+		GT_INTERVAL_FROM_US((ei_down * threshold_down / 100)));
+
+	 I915_WRITE(GEN6_RP_CONTROL,
+		    GEN6_RP_MEDIA_TURBO |
+		    GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		    GEN6_RP_MEDIA_IS_GFX |
+		    GEN6_RP_ENABLE |
+		    GEN6_RP_UP_BUSY_AVG |
+		    GEN6_RP_DOWN_IDLE_AVG);
+
 	dev_priv->rps.power = new_power;
 	dev_priv->rps.last_adj = 0;
 }
-- 
1.9.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 4/5] drm/i915/skl: Updated the gen6_rps_limits function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

RP Interrupt Up/Down Frequency Limits register (A014) definition
has changed for SKL. Updated the gen6_rps_limits function as per that

v2: Renamed the function to intel_rps_limits (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Lespiau, Damien <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 78b4d62..e08a710 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3623,7 +3623,7 @@ static void ironlake_disable_drps(struct drm_device *dev)
  * ourselves, instead of doing a rmw cycle (which might result in us clearing
  * all limits and the gpu stuck at whatever frequency it is at atm).
  */
-static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
+static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 {
 	u32 limits;
 
@@ -3633,9 +3633,15 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 	 * the hw runs at the minimal clock before selecting the desired
 	 * frequency, if the down threshold expires in that window we will not
 	 * receive a down interrupt. */
-	limits = dev_priv->rps.max_freq_softlimit << 24;
-	if (val <= dev_priv->rps.min_freq_softlimit)
-		limits |= dev_priv->rps.min_freq_softlimit << 16;
+	if (IS_GEN9(dev_priv->dev)) {
+		limits = (dev_priv->rps.max_freq_softlimit * GEN9_FREQ_SCALER) << 23;
+		if (val <= dev_priv->rps.min_freq_softlimit)
+			limits |= (dev_priv->rps.min_freq_softlimit * GEN9_FREQ_SCALER) << 14;
+	} else {
+		limits = dev_priv->rps.max_freq_softlimit << 24;
+		if (val <= dev_priv->rps.min_freq_softlimit)
+			limits |= dev_priv->rps.min_freq_softlimit << 16;
+	}
 
 	return limits;
 }
@@ -3776,7 +3782,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
 	/* Make sure we continue to get interrupts
 	 * until we hit the minimum or maximum frequencies.
 	 */
-	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
+	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
 	I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
 
 	POSTING_READ(GEN6_RPNSWREQ);
-- 
1.9.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 5/5] drm/i915/skl: Updated the gen9_enable_rps function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

On SKL, GT frequency is programmed in units of 16.66 MHZ units compared
to 50 MHZ for older platforms. Also the time value specified for Up/Down EI &
Up/Down thresholds are expressed in units of 1.33 us, compared to 1.28
us for older platforms. So updated the gen9_enable_rps function as per that.

v2: Updated to use new macro GT_INTERVAL_FROM_US

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 41 ++++++++++++++++++++++++++++++++---------
 1 file changed, 32 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e08a710..6532060 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4035,27 +4035,50 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
 static void gen9_enable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 threshold_up, threshold_down; /* in % */
+	u32 ei_up, ei_down;
 
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 	gen6_init_rps_frequencies(dev);
 
-	I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
-	I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
+	/* Program defaults and thresholds for RPS*/
+	I915_WRITE(GEN6_RPNSWREQ,
+		GEN9_FREQUENCY(dev_priv->rps.rp1_freq * GEN9_FREQ_SCALER));
+	I915_WRITE(GEN6_RC_VIDEO_FREQ,
+		GEN9_FREQUENCY(dev_priv->rps.rp1_freq * GEN9_FREQ_SCALER));
+
+	ei_up = 84480; /* 84.48ms */
+	ei_down = 448000;
+	threshold_up = 90;
+	threshold_down = 70;
+
+	I915_WRITE(GEN6_RP_UP_EI,
+		GT_INTERVAL_FROM_US(ei_up));
+	I915_WRITE(GEN6_RP_UP_THRESHOLD,
+		GT_INTERVAL_FROM_US((ei_up * threshold_up / 100)));
+
+	I915_WRITE(GEN6_RP_DOWN_EI,
+		GT_INTERVAL_FROM_US(ei_down));
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
+		GT_INTERVAL_FROM_US((ei_down * threshold_down / 100)));
+
+	/* 1 second timeout*/
+	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, GT_INTERVAL_FROM_US(1000000));
+
+	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
+		(dev_priv->rps.max_freq_softlimit * GEN9_FREQ_SCALER) << 23 |
+		(dev_priv->rps.min_freq_softlimit * GEN9_FREQ_SCALER) << 14);
 
-	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
-	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);
-	I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
-	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
-	I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
-	I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
 	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
-	I915_WRITE(GEN6_PMINTRMSK, 0x6);
 	I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
 		   GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
 		   GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
 		   GEN6_RP_DOWN_IDLE_AVG);
 
+	dev_priv->rps.power = HIGH_POWER; /* force a reset */
+	gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
+
 	gen6_enable_rps_interrupts(dev);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
-- 
1.9.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 6/7] drm/i915/skl: Updated the 'i915_frequency_info' debugs function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Added support for SKL in the 'i915_frequency_info' debugfs function

v2: Added missing conversion to 50MHZ for reqf & cagf (Damien)

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 9af17fb..5fb0121 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1089,7 +1089,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_printf(m, "Current P-state: %d\n",
 			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
-		   IS_BROADWELL(dev)) {
+		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
 		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
@@ -1108,11 +1108,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 		reqf = I915_READ(GEN6_RPNSWREQ);
-		reqf &= ~GEN6_TURBO_DISABLE;
-		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
-			reqf >>= 24;
-		else
-			reqf >>= 25;
+		if (IS_GEN9(dev)) {
+			reqf >>= 23;
+			/* Convert to 50 MHZ units from 16.667 MHZ */
+			reqf /= GEN9_FREQ_SCALER;
+		} else {
+			reqf &= ~GEN6_TURBO_DISABLE;
+			if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+				reqf >>= 24;
+			else
+				reqf >>= 25;
+		}
 		reqf = intel_gpu_freq(dev_priv, reqf);
 
 		rpmodectl = I915_READ(GEN6_RP_CONTROL);
@@ -1128,7 +1134,10 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
 		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
-		else
+		else if (IS_GEN9(dev)) {
+			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
+			cagf /= GEN9_FREQ_SCALER;
+		} else
 			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
 		cagf = intel_gpu_freq(dev_priv, cagf);
 
@@ -1152,7 +1161,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
 		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 		seq_printf(m, "Render p-state ratio: %d\n",
-			   (gt_perf_status & 0xff00) >> 8);
+			   (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
 		seq_printf(m, "Render p-state VID: %d\n",
 			   gt_perf_status & 0xff);
 		seq_printf(m, "Render p-state limit: %d\n",
-- 
1.9.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 5/5] drm/i915/skl: Updated the gen9_enable_rps function

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5789
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -4              277/277              273/277
ILK                                  313/313              313/313
SNB                 -1              309/309              308/309
IVB                 -1              382/382              381/382
BYT                                  296/296              296/296
HSW                 -2              425/425              423/425
BDW                 -1              318/318              317/318
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gem_fence_thrash_bo-write-verify-none      NRUN(1)PASS(3)      FAIL(1)NRUN(1)
*PNV  igt_gem_fence_thrash_bo-write-verify-x      PASS(4)      FAIL(1)PASS(1)
*PNV  igt_gem_fence_thrash_bo-write-verify-y      NO_RESULT(1)PASS(3)      FAIL(1)PASS(1)
 PNV  igt_gem_userptr_blits_coherency-sync      NO_RESULT(1)CRASH(1)PASS(3)      CRASH(1)PASS(1)
*SNB  igt_kms_pipe_crc_basic_read-crc-pipe-B      PASS(2)      TIMEOUT(1)PASS(1)
*IVB  igt_gem_pwrite_pread_uncached-copy-performance      PASS(2)      DMESG_WARN(1)PASS(1)
*HSW  igt_gem_pwrite_pread_snooped-copy-performance      PASS(2)      DMESG_WARN(1)PASS(1)
*HSW  igt_kms_flip_dpms-off-confusion      PASS(2)      TIMEOUT(1)PASS(1)
*BDW  igt_gem_gtt_hog      PASS(7)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 1/5] drm/i915/skl: Added new macros

[Damien Lespiau]

On Wed, Feb 18, 2015 at 07:31:14PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C)
> have changed slightly. Also on SKL, frequency is specified in
> units of 16.66 MHZ, compared to 50 MHZ for most of the earlier
> platforms and the time values are expressed in units of 1.33 us,
> compared to 1.28 us for earlier platforms.
> Added new macros for the aforementioned changes.
> 
> v2: Renamed the GT_FREQ_FROM_PERIOD macro to GT_INTERVAL_FROM_US (Damien)
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ca64b99..529b9b2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2485,6 +2485,7 @@ struct drm_i915_cmd_table {
>  #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
>  
>  #define GT_FREQUENCY_MULTIPLIER 50
> +#define GEN9_FREQ_SCALER 3
>  
>  #include "i915_trace.h"
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cd3430f9..a82436d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2389,6 +2389,12 @@ enum skl_disp_power_wells {
>  #define GEN6_RP_STATE_LIMITS	(MCHBAR_MIRROR_BASE_SNB + 0x5994)
>  #define GEN6_RP_STATE_CAP	(MCHBAR_MIRROR_BASE_SNB + 0x5998)
>  
> +#define INTERVAL_1_28_US(us)	(((us) * 100) >> 7)
> +#define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
> +#define GT_INTERVAL_FROM_US(us) (IS_GEN9(dev_priv->dev) ? \
> +				INTERVAL_1_33_US(us) : \
> +				INTERVAL_1_28_US(us))
> +
>  /*
>   * Logical Context regs
>   */
> @@ -6023,6 +6029,7 @@ enum skl_disp_power_wells {
>  #define   GEN6_TURBO_DISABLE			(1<<31)
>  #define   GEN6_FREQUENCY(x)			((x)<<25)
>  #define   HSW_FREQUENCY(x)			((x)<<24)
> +#define   GEN9_FREQUENCY(x)			((x)<<23)
>  #define   GEN6_OFFSET(x)			((x)<<19)
>  #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
>  #define GEN6_RC_VIDEO_FREQ			0xA00C
> @@ -6041,8 +6048,10 @@ enum skl_disp_power_wells {
>  #define GEN6_RPSTAT1				0xA01C
>  #define   GEN6_CAGF_SHIFT			8
>  #define   HSW_CAGF_SHIFT			7
> +#define   GEN9_CAGF_SHIFT			23
>  #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
>  #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
> +#define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
>  #define GEN6_RP_CONTROL				0xA024
>  #define   GEN6_RP_MEDIA_TURBO			(1<<11)
>  #define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
> -- 
> 1.9.2
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 3/5] drm/i915/skl: Restructured the gen6_set_rps_thresholds function

[Damien Lespiau]

On Wed, Feb 18, 2015 at 07:31:15PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Prior to SKL, the time period programmed in Up/Down EI & Up/Down
> threshold registers was in units of 1.28 micro seconds. But for
> SKL, the units have changed (1.333 micro seconds).
> Have generalized the implementation of gen6_set_rps_thresholds function,
> by removing the hard coding done in it as per 1.28 micro seconds.
> 
> v2: Renamed the local variables & removed superfluous comments (Chris)
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 68 +++++++++++++++++++----------------------
>  1 file changed, 32 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1df3fbd..78b4d62 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3643,6 +3643,8 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
>  static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
>  {
>  	int new_power;
> +	u32 threshold_up = 0, threshold_down = 0; /* in % */
> +	u32 ei_up = 0, ei_down = 0;
>  
>  	new_power = dev_priv->rps.power;
>  	switch (dev_priv->rps.power) {
> @@ -3675,59 +3677,53 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
>  	switch (new_power) {
>  	case LOW_POWER:
>  		/* Upclock if more than 95% busy over 16ms */
> -		I915_WRITE(GEN6_RP_UP_EI, 12500);
> -		I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
> +		ei_up = 16000;
> +		threshold_up = 95;
>  
>  		/* Downclock if less than 85% busy over 32ms */
> -		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
> -		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
> -
> -		I915_WRITE(GEN6_RP_CONTROL,
> -			   GEN6_RP_MEDIA_TURBO |
> -			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
> -			   GEN6_RP_MEDIA_IS_GFX |
> -			   GEN6_RP_ENABLE |
> -			   GEN6_RP_UP_BUSY_AVG |
> -			   GEN6_RP_DOWN_IDLE_AVG);
> +		ei_down = 32000;
> +		threshold_down = 85;
>  		break;
>  
>  	case BETWEEN:
>  		/* Upclock if more than 90% busy over 13ms */
> -		I915_WRITE(GEN6_RP_UP_EI, 10250);
> -		I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
> +		ei_up = 13000;
> +		threshold_up = 90;
>  
>  		/* Downclock if less than 75% busy over 32ms */
> -		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
> -		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
> -
> -		I915_WRITE(GEN6_RP_CONTROL,
> -			   GEN6_RP_MEDIA_TURBO |
> -			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
> -			   GEN6_RP_MEDIA_IS_GFX |
> -			   GEN6_RP_ENABLE |
> -			   GEN6_RP_UP_BUSY_AVG |
> -			   GEN6_RP_DOWN_IDLE_AVG);
> +		ei_down = 32000;
> +		threshold_down = 75;
>  		break;
>  
>  	case HIGH_POWER:
>  		/* Upclock if more than 85% busy over 10ms */
> -		I915_WRITE(GEN6_RP_UP_EI, 8000);
> -		I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
> +		ei_up = 10000;
> +		threshold_up = 85;
>  
>  		/* Downclock if less than 60% busy over 32ms */
> -		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
> -		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
> -
> -		I915_WRITE(GEN6_RP_CONTROL,
> -			   GEN6_RP_MEDIA_TURBO |
> -			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
> -			   GEN6_RP_MEDIA_IS_GFX |
> -			   GEN6_RP_ENABLE |
> -			   GEN6_RP_UP_BUSY_AVG |
> -			   GEN6_RP_DOWN_IDLE_AVG);
> +		ei_down = 32000;
> +		threshold_down = 60;
>  		break;
>  	}
>  
> +	I915_WRITE(GEN6_RP_UP_EI,
> +		GT_INTERVAL_FROM_US(ei_up));
> +	I915_WRITE(GEN6_RP_UP_THRESHOLD,
> +		GT_INTERVAL_FROM_US((ei_up * threshold_up / 100)));
> +
> +	I915_WRITE(GEN6_RP_DOWN_EI,
> +		GT_INTERVAL_FROM_US(ei_down));
> +	I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
> +		GT_INTERVAL_FROM_US((ei_down * threshold_down / 100)));
> +
> +	 I915_WRITE(GEN6_RP_CONTROL,
> +		    GEN6_RP_MEDIA_TURBO |
> +		    GEN6_RP_MEDIA_HW_NORMAL_MODE |
> +		    GEN6_RP_MEDIA_IS_GFX |
> +		    GEN6_RP_ENABLE |
> +		    GEN6_RP_UP_BUSY_AVG |
> +		    GEN6_RP_DOWN_IDLE_AVG);
> +
>  	dev_priv->rps.power = new_power;
>  	dev_priv->rps.last_adj = 0;
>  }
> -- 
> 1.9.2
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 6/7] drm/i915/skl: Updated the 'i915_frequency_info' debugs function

[Damien Lespiau]

On Wed, Feb 18, 2015 at 07:31:18PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Added support for SKL in the 'i915_frequency_info' debugfs function
> 
> v2: Added missing conversion to 50MHZ for reqf & cagf (Damien)
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

>  drivers/gpu/drm/i915/i915_debugfs.c | 25 +++++++++++++++++--------
>  1 file changed, 17 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 9af17fb..5fb0121 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1089,7 +1089,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		seq_printf(m, "Current P-state: %d\n",
>  			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
>  	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
> -		   IS_BROADWELL(dev)) {
> +		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
>  		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
>  		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
>  		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> @@ -1108,11 +1108,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  		reqf = I915_READ(GEN6_RPNSWREQ);
> -		reqf &= ~GEN6_TURBO_DISABLE;
> -		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> -			reqf >>= 24;
> -		else
> -			reqf >>= 25;
> +		if (IS_GEN9(dev)) {
> +			reqf >>= 23;
> +			/* Convert to 50 MHZ units from 16.667 MHZ */
> +			reqf /= GEN9_FREQ_SCALER;
> +		} else {
> +			reqf &= ~GEN6_TURBO_DISABLE;
> +			if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +				reqf >>= 24;
> +			else
> +				reqf >>= 25;
> +		}
>  		reqf = intel_gpu_freq(dev_priv, reqf);
>  
>  		rpmodectl = I915_READ(GEN6_RP_CONTROL);
> @@ -1128,7 +1134,10 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
>  		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> -		else
> +		else if (IS_GEN9(dev)) {
> +			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> +			cagf /= GEN9_FREQ_SCALER;
> +		} else
>  			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
>  		cagf = intel_gpu_freq(dev_priv, cagf);
>  
> @@ -1152,7 +1161,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
>  		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
>  		seq_printf(m, "Render p-state ratio: %d\n",
> -			   (gt_perf_status & 0xff00) >> 8);
> +			   (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
>  		seq_printf(m, "Render p-state VID: %d\n",
>  			   gt_perf_status & 0xff);
>  		seq_printf(m, "Render p-state limit: %d\n",
> -- 
> 1.9.2
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/7] drm/i915/skl: Updated the gen6_set_rps function

[Daniel Vetter]

On Wed, Feb 18, 2015 at 07:31:11PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> On SKL, the frequency programmed in RPNSWREQ (A008) register
> has to be in units of 16.66 MHZ. So updated the gen6_set_rps
> function, as per this change.
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> Reviewed-by: Lespiau, Damien <damien.lespiau@intel.com>

I guess you've manually frobbed with the patch series that git
format-patch has created. Whatever it is, the thing is out-of-order now
and a bit a mess.

Can you please resend without doing that?

Thanks, Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bebefe7..1df3fbd 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3764,7 +3764,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
>  	if (val != dev_priv->rps.cur_freq) {
>  		gen6_set_rps_thresholds(dev_priv, val);
>  
> -		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +		if (IS_GEN9(dev))
> +			I915_WRITE(GEN6_RPNSWREQ,
> +				GEN9_FREQUENCY(val * GEN9_FREQ_SCALER));
> +		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  			I915_WRITE(GEN6_RPNSWREQ,
>  				   HSW_FREQUENCY(val));
>  		else
> -- 
> 1.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 5/5] drm/i915/skl: Updated the gen9_enable_rps function

[Damien Lespiau]

On Wed, Feb 18, 2015 at 07:31:17PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> On SKL, GT frequency is programmed in units of 16.66 MHZ units compared
> to 50 MHZ for older platforms. Also the time value specified for Up/Down EI &
> Up/Down thresholds are expressed in units of 1.33 us, compared to 1.28
> us for older platforms. So updated the gen9_enable_rps function as per that.
> 
> v2: Updated to use new macro GT_INTERVAL_FROM_US
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Ok, we might as well throw away the init sequence from the PM guide if
it's to reuse code that is easier to read. While what you're doing seems
correct, we might as well go full on and reuse gen6_set_rps() entirely?

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 41 ++++++++++++++++++++++++++++++++---------
>  1 file changed, 32 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e08a710..6532060 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4035,27 +4035,50 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
>  static void gen9_enable_rps(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 threshold_up, threshold_down; /* in % */
> +	u32 ei_up, ei_down;
>  
>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  	gen6_init_rps_frequencies(dev);
>  
> -	I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
> -	I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
> +	/* Program defaults and thresholds for RPS*/
> +	I915_WRITE(GEN6_RPNSWREQ,
> +		GEN9_FREQUENCY(dev_priv->rps.rp1_freq * GEN9_FREQ_SCALER));

This register is going to be overridde by gen6_set_rps() very soon, how
about letting that function do it? (cur_freq should be 0 at this point
so set_rps() should do something).

> +	I915_WRITE(GEN6_RC_VIDEO_FREQ,
> +		GEN9_FREQUENCY(dev_priv->rps.rp1_freq * GEN9_FREQ_SCALER));

Note that we don't seem to use video turbo in the rest of the driver,
gen6_set_rps() will set GEN6_RP_MEDIA_HW_NORMAL_MODE, which ignores the
both the turbo bit and the requested freq from the video turbo register.
Seems fine to initialize it to RP1 though.

> +
> +	ei_up = 84480; /* 84.48ms */
> +	ei_down = 448000;
> +	threshold_up = 90;
> +	threshold_down = 70;
> +
> +	I915_WRITE(GEN6_RP_UP_EI,
> +		GT_INTERVAL_FROM_US(ei_up));
> +	I915_WRITE(GEN6_RP_UP_THRESHOLD,
> +		GT_INTERVAL_FROM_US((ei_up * threshold_up / 100)));

Those 2 are going to be overridden by gen6_set_rps().

> +
> +	I915_WRITE(GEN6_RP_DOWN_EI,
> +		GT_INTERVAL_FROM_US(ei_down));
> +	I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
> +		GT_INTERVAL_FROM_US((ei_down * threshold_down / 100)));

Those 2 are going to be overridden by gen6_set_rps().

> +
> +	/* 1 second timeout*/
> +	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, GT_INTERVAL_FROM_US(1000000));

This one need to stay here.

> +	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
> +		(dev_priv->rps.max_freq_softlimit * GEN9_FREQ_SCALER) << 23 |
> +		(dev_priv->rps.min_freq_softlimit * GEN9_FREQ_SCALER) << 14);

This one are going to be overridden by gen6_set_rps().

> -	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
> -	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);
> -	I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
> -	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
> -	I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
> -	I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
>  	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);

This one need to stay here indeed.

> -	I915_WRITE(GEN6_PMINTRMSK, 0x6);
>  	I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
>  		   GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
>  		   GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
>  		   GEN6_RP_DOWN_IDLE_AVG);

This is going to be overridden by gen6_set_rps(), including the media
turbo mode that is just going to use the normal freq.

> +	dev_priv->rps.power = HIGH_POWER; /* force a reset */
> +	gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
> +
>  	gen6_enable_rps_interrupts(dev);
>  
>  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> -- 
> 1.9.2
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 0/7] Added missing changes for Turbo feature on SKL

[Damien Lespiau]

On Wed, Feb 18, 2015 at 07:31:13PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> This patch series add missing changes, required for proper functioning of the
> Turbo feature on SKL.
> Addressed review comments from Damien & Chris. 

Another item on the TODO list (for whoever is going to fix this), it
seems it'd be advisable to change gen9_enable_rc6() to use the new
GT_INTERVAL_FROM_US() macro.

-- 
Damien
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/7] drm/i915/skl: Updated the gen6_set_rps function

[Damien Lespiau]

On Wed, Feb 18, 2015 at 07:31:11PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> On SKL, the frequency programmed in RPNSWREQ (A008) register
> has to be in units of 16.66 MHZ. So updated the gen6_set_rps
> function, as per this change.
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> Reviewed-by: Lespiau, Damien <damien.lespiau@intel.com>

Please don't use the Outlook way "lastname, firstname" here :)

-- 
Damien

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 6/7] drm/i915/skl: Updated the 'i915_frequency_info' debugs function

[Ville Syrjälä]

On Wed, Feb 18, 2015 at 07:31:18PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Added support for SKL in the 'i915_frequency_info' debugfs function
> 
> v2: Added missing conversion to 50MHZ for reqf & cagf (Damien)
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 25 +++++++++++++++++--------
>  1 file changed, 17 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 9af17fb..5fb0121 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1089,7 +1089,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		seq_printf(m, "Current P-state: %d\n",
>  			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
>  	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
> -		   IS_BROADWELL(dev)) {
> +		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
>  		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
>  		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
>  		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> @@ -1108,11 +1108,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  		reqf = I915_READ(GEN6_RPNSWREQ);
> -		reqf &= ~GEN6_TURBO_DISABLE;
> -		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> -			reqf >>= 24;
> -		else
> -			reqf >>= 25;
> +		if (IS_GEN9(dev)) {
> +			reqf >>= 23;
> +			/* Convert to 50 MHZ units from 16.667 MHZ */
> +			reqf /= GEN9_FREQ_SCALER;
> +		} else {
> +			reqf &= ~GEN6_TURBO_DISABLE;
> +			if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +				reqf >>= 24;
> +			else
> +				reqf >>= 25;
> +		}
>  		reqf = intel_gpu_freq(dev_priv, reqf);
>  
>  		rpmodectl = I915_READ(GEN6_RP_CONTROL);
> @@ -1128,7 +1134,10 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
>  		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> -		else
> +		else if (IS_GEN9(dev)) {
> +			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> +			cagf /= GEN9_FREQ_SCALER;
> +		} else
>  			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;


I would put gen9 first, then hsw/bsw, then gen6.

Also there's now a gt_act_freq_mhz_show() that needs some love too.

>  		cagf = intel_gpu_freq(dev_priv, cagf);
>  
> @@ -1152,7 +1161,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
>  		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
>  		seq_printf(m, "Render p-state ratio: %d\n",
> -			   (gt_perf_status & 0xff00) >> 8);
> +			   (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
>  		seq_printf(m, "Render p-state VID: %d\n",
>  			   gt_perf_status & 0xff);
>  		seq_printf(m, "Render p-state limit: %d\n",
> -- 
> 1.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 6/7] drm/i915/skl: Updated the 'i915_frequency_info' debugs function

[Ville Syrjälä]

On Wed, Feb 18, 2015 at 07:31:18PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Added support for SKL in the 'i915_frequency_info' debugfs function
> 
> v2: Added missing conversion to 50MHZ for reqf & cagf (Damien)
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 25 +++++++++++++++++--------
>  1 file changed, 17 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 9af17fb..5fb0121 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1089,7 +1089,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		seq_printf(m, "Current P-state: %d\n",
>  			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
>  	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
> -		   IS_BROADWELL(dev)) {
> +		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
>  		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
>  		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
>  		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> @@ -1108,11 +1108,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  		reqf = I915_READ(GEN6_RPNSWREQ);
> -		reqf &= ~GEN6_TURBO_DISABLE;
> -		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> -			reqf >>= 24;
> -		else
> -			reqf >>= 25;
> +		if (IS_GEN9(dev)) {
> +			reqf >>= 23;
> +			/* Convert to 50 MHZ units from 16.667 MHZ */
> +			reqf /= GEN9_FREQ_SCALER;

Oh, and all this GEN9_FREQ_SCALER mul/div stuff should be killed and
instead you should just make intel_gpu_freq() and intel_freq_opcode()
handle the conversion properly.

> +		} else {
> +			reqf &= ~GEN6_TURBO_DISABLE;
> +			if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +				reqf >>= 24;
> +			else
> +				reqf >>= 25;
> +		}
>  		reqf = intel_gpu_freq(dev_priv, reqf);
>  
>  		rpmodectl = I915_READ(GEN6_RP_CONTROL);
> @@ -1128,7 +1134,10 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
>  		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> -		else
> +		else if (IS_GEN9(dev)) {
> +			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> +			cagf /= GEN9_FREQ_SCALER;
> +		} else
>  			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
>  		cagf = intel_gpu_freq(dev_priv, cagf);
>  
> @@ -1152,7 +1161,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
>  		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
>  		seq_printf(m, "Render p-state ratio: %d\n",
> -			   (gt_perf_status & 0xff00) >> 8);
> +			   (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
>  		seq_printf(m, "Render p-state VID: %d\n",
>  			   gt_perf_status & 0xff);
>  		seq_printf(m, "Render p-state limit: %d\n",
> -- 
> 1.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/7] drm/i915/skl: Updated the gen6_set_rps function

[Daniel Vetter]

On Tue, Feb 24, 2015 at 03:22:54PM +0000, Damien Lespiau wrote:
> On Wed, Feb 18, 2015 at 07:31:11PM +0530, akash.goel@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> > 
> > On SKL, the frequency programmed in RPNSWREQ (A008) register
> > has to be in units of 16.66 MHZ. So updated the gen6_set_rps
> > function, as per this change.
> > 
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > Reviewed-by: Lespiau, Damien <damien.lespiau@intel.com>
> 
> Please don't use the Outlook way "lastname, firstname" here :)

Another one: r-b tags should be treated like signatures and only perfectly
copypasted. Writing your own is considered forgery ;-) Just another reason
to use exactly the string provided.

So same strict rules as with sob really.

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 6/7] drm/i915/skl: Updated the 'i915_frequency_info' debugs function

[Akash Goel]

On Tue, 2015-02-24 at 18:10 +0200, Ville Syrjälä wrote:
> On Wed, Feb 18, 2015 at 07:31:18PM +0530, akash.goel@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> > 
> > Added support for SKL in the 'i915_frequency_info' debugfs function
> > 
> > v2: Added missing conversion to 50MHZ for reqf & cagf (Damien)
> > 
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 25 +++++++++++++++++--------
> >  1 file changed, 17 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 9af17fb..5fb0121 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1089,7 +1089,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >  		seq_printf(m, "Current P-state: %d\n",
> >  			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
> >  	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
> > -		   IS_BROADWELL(dev)) {
> > +		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
> >  		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
> >  		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> >  		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> > @@ -1108,11 +1108,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >  		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> >  
> >  		reqf = I915_READ(GEN6_RPNSWREQ);
> > -		reqf &= ~GEN6_TURBO_DISABLE;
> > -		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> > -			reqf >>= 24;
> > -		else
> > -			reqf >>= 25;
> > +		if (IS_GEN9(dev)) {
> > +			reqf >>= 23;
> > +			/* Convert to 50 MHZ units from 16.667 MHZ */
> > +			reqf /= GEN9_FREQ_SCALER;
> > +		} else {
> > +			reqf &= ~GEN6_TURBO_DISABLE;
> > +			if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> > +				reqf >>= 24;
> > +			else
> > +				reqf >>= 25;
> > +		}
> >  		reqf = intel_gpu_freq(dev_priv, reqf);
> >  
> >  		rpmodectl = I915_READ(GEN6_RP_CONTROL);
> > @@ -1128,7 +1134,10 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >  		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
> >  		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> >  			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> > -		else
> > +		else if (IS_GEN9(dev)) {
> > +			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> > +			cagf /= GEN9_FREQ_SCALER;
> > +		} else
> >  			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
> 
> 
> I would put gen9 first, then hsw/bsw, then gen6.
> 
> Also there's now a gt_act_freq_mhz_show() that needs some love too.

Thanks,  will update the gt_act_freq_mhz_show() also.

> 
> >  		cagf = intel_gpu_freq(dev_priv, cagf);
> >  
> > @@ -1152,7 +1161,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >  			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
> >  		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> >  		seq_printf(m, "Render p-state ratio: %d\n",
> > -			   (gt_perf_status & 0xff00) >> 8);
> > +			   (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
> >  		seq_printf(m, "Render p-state VID: %d\n",
> >  			   gt_perf_status & 0xff);
> >  		seq_printf(m, "Render p-state limit: %d\n",
> > -- 
> > 1.9.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/7] drm/i915/skl: Updated the gen6_set_rps function

[Damien Lespiau]

On Tue, Feb 17, 2015 at 02:31:08PM +0000, Damien Lespiau wrote:
> On Fri, Feb 06, 2015 at 08:26:33PM +0530, akash.goel@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> > 
> > On SKL, the frequency programmed in RPNSWREQ (A008) register
> > has to be in units of 16.66 MHZ. So updated the gen6_set_rps
> > function, as per this change.
> > 
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > ---
> 
> Right, we suppose here that val in in 16.66 Mhz units. At the very least
> we need update the trace point:
> 
>   trace_intel_gpu_freq_change(val * 50);
> 
> Then val is passed to gen6_rps_limits(). The values of 0xA014 are also
> in 16.66 Mhz units, so that part is fine, but the fields of that
> register have changed a bit so we also need to update gen6_rps_limits()
> for gen9 (if not done by a later patch).

I managed to get quite confused, I blame the lack of sleep. From
RP_STATE_CAP, we get all the limits in 50Mhz and we store them like
this. So everything is done in units of 50Mhz and then converted to
units of 16.66Mhz at write time. Took me the whole series to realize
that, sorry.

So:

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/7] drm/i915/skl: Updated the gen6_set_rps function

[Damien Lespiau]

On Fri, Feb 06, 2015 at 08:26:33PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> On SKL, the frequency programmed in RPNSWREQ (A008) register
> has to be in units of 16.66 MHZ. So updated the gen6_set_rps
> function, as per this change.
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---

Right, we suppose here that val in in 16.66 Mhz units. At the very least
we need update the trace point:

  trace_intel_gpu_freq_change(val * 50);

Then val is passed to gen6_rps_limits(). The values of 0xA014 are also
in 16.66 Mhz units, so that part is fine, but the fields of that
register have changed a bit so we also need to update gen6_rps_limits()
for gen9 (if not done by a later patch).

-- 
Damien

>  drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bebefe7..58c8c0e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3764,7 +3764,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
>  	if (val != dev_priv->rps.cur_freq) {
>  		gen6_set_rps_thresholds(dev_priv, val);
>  
> -		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +		if (IS_GEN9(dev))
> +                        I915_WRITE(GEN6_RPNSWREQ,
> +                                   GEN9_FREQUENCY(val * GEN9_FREQ_SCALER));
> +		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  			I915_WRITE(GEN6_RPNSWREQ,
>  				   HSW_FREQUENCY(val));
>  		else
> -- 
> 1.9.2
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/7] drm/i915/skl: Updated the gen6_set_rps function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

On SKL, the frequency programmed in RPNSWREQ (A008) register
has to be in units of 16.66 MHZ. So updated the gen6_set_rps
function, as per this change.

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bebefe7..58c8c0e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3764,7 +3764,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
 	if (val != dev_priv->rps.cur_freq) {
 		gen6_set_rps_thresholds(dev_priv, val);
 
-		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		if (IS_GEN9(dev))
+                        I915_WRITE(GEN6_RPNSWREQ,
+                                   GEN9_FREQUENCY(val * GEN9_FREQ_SCALER));
+		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 			I915_WRITE(GEN6_RPNSWREQ,
 				   HSW_FREQUENCY(val));
 		else
-- 
1.9.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx