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* [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code
@ 2015-02-23 11:03 Daniel Vetter
  2015-02-23 11:03 ` [PATCH 2/7] drm/i915: Remove DRIVER_MODESET checks from suspend/resume code Daniel Vetter
                   ` (6 more replies)
  0 siblings, 7 replies; 19+ messages in thread
From: Daniel Vetter @ 2015-02-23 11:03 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter, Daniel Vetter

UMS is gone, this is dead code.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 95 ++++++++++++++++-------------------------
 1 file changed, 37 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 5804aa5f9df0..63a001b6abed 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -638,17 +638,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	info = (struct intel_device_info *) flags;
 
-	/* Refuse to load on gen6+ without kms enabled. */
-	if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
-		DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
-		DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
-		return -ENODEV;
-	}
-
-	/* UMS needs agp support. */
-	if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
-		return -EINVAL;
-
 	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 	if (dev_priv == NULL)
 		return -ENOMEM;
@@ -718,20 +707,18 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	if (ret)
 		goto out_regs;
 
-	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-		/* WARNING: Apparently we must kick fbdev drivers before vgacon,
-		 * otherwise the vga fbdev driver falls over. */
-		ret = i915_kick_out_firmware_fb(dev_priv);
-		if (ret) {
-			DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
-			goto out_gtt;
-		}
+	/* WARNING: Apparently we must kick fbdev drivers before vgacon,
+	 * otherwise the vga fbdev driver falls over. */
+	ret = i915_kick_out_firmware_fb(dev_priv);
+	if (ret) {
+		DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
+		goto out_gtt;
+	}
 
-		ret = i915_kick_out_vgacon(dev_priv);
-		if (ret) {
-			DRM_ERROR("failed to remove conflicting VGA console\n");
-			goto out_gtt;
-		}
+	ret = i915_kick_out_vgacon(dev_priv);
+	if (ret) {
+		DRM_ERROR("failed to remove conflicting VGA console\n");
+		goto out_gtt;
 	}
 
 	pci_set_master(dev->pdev);
@@ -835,12 +822,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	intel_power_domains_init(dev_priv);
 
-	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-		ret = i915_load_modeset_init(dev);
-		if (ret < 0) {
-			DRM_ERROR("failed to init modeset\n");
-			goto out_power_well;
-		}
+	ret = i915_load_modeset_init(dev);
+	if (ret < 0) {
+		DRM_ERROR("failed to init modeset\n");
+		goto out_power_well;
 	}
 
 	/*
@@ -929,28 +914,25 @@ int i915_driver_unload(struct drm_device *dev)
 
 	acpi_video_unregister();
 
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		intel_fbdev_fini(dev);
+	intel_fbdev_fini(dev);
 
 	drm_vblank_cleanup(dev);
 
-	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-		intel_modeset_cleanup(dev);
-
-		/*
-		 * free the memory space allocated for the child device
-		 * config parsed from VBT
-		 */
-		if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
-			kfree(dev_priv->vbt.child_dev);
-			dev_priv->vbt.child_dev = NULL;
-			dev_priv->vbt.child_dev_num = 0;
-		}
+	intel_modeset_cleanup(dev);
 
-		vga_switcheroo_unregister_client(dev->pdev);
-		vga_client_register(dev->pdev, NULL, NULL, NULL);
+	/*
+	 * free the memory space allocated for the child device
+	 * config parsed from VBT
+	 */
+	if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
+		kfree(dev_priv->vbt.child_dev);
+		dev_priv->vbt.child_dev = NULL;
+		dev_priv->vbt.child_dev_num = 0;
 	}
 
+	vga_switcheroo_unregister_client(dev->pdev);
+	vga_client_register(dev->pdev, NULL, NULL, NULL);
+
 	/* Free error state after interrupts are fully disabled. */
 	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
 	i915_destroy_error_state(dev);
@@ -960,17 +942,15 @@ int i915_driver_unload(struct drm_device *dev)
 
 	intel_opregion_fini(dev);
 
-	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-		/* Flush any outstanding unpin_work. */
-		flush_workqueue(dev_priv->wq);
+	/* Flush any outstanding unpin_work. */
+	flush_workqueue(dev_priv->wq);
 
-		mutex_lock(&dev->struct_mutex);
-		i915_gem_cleanup_ringbuffer(dev);
-		i915_gem_batch_pool_fini(&dev_priv->mm.batch_pool);
-		i915_gem_context_fini(dev);
-		mutex_unlock(&dev->struct_mutex);
-		i915_gem_cleanup_stolen(dev);
-	}
+	mutex_lock(&dev->struct_mutex);
+	i915_gem_cleanup_ringbuffer(dev);
+	i915_gem_batch_pool_fini(&dev_priv->mm.batch_pool);
+	i915_gem_context_fini(dev);
+	mutex_unlock(&dev->struct_mutex);
+	i915_gem_cleanup_stolen(dev);
 
 	intel_teardown_gmbus(dev);
 	intel_teardown_mchbar(dev);
@@ -1031,8 +1011,7 @@ void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
 	i915_gem_release(dev, file);
 	mutex_unlock(&dev->struct_mutex);
 
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		intel_modeset_preclose(dev, file);
+	intel_modeset_preclose(dev, file);
 }
 
 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
-- 
2.1.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH 2/7] drm/i915: Remove DRIVER_MODESET checks from suspend/resume code
  2015-02-23 11:03 [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code Daniel Vetter
@ 2015-02-23 11:03 ` Daniel Vetter
  2015-02-27  1:06   ` Rodrigo Vivi
  2015-02-23 11:03 ` [PATCH 3/7] drm/i915: Remove DRIVER_MODESET checks in the gpu reset code Daniel Vetter
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 19+ messages in thread
From: Daniel Vetter @ 2015-02-23 11:03 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter, Daniel Vetter

UMS is dead, yay!

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 113 ++++++++++++++++++----------------------
 1 file changed, 52 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ba6862f5b6b2..c1a5377caff0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -574,6 +574,7 @@ static int i915_drm_suspend(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	pci_power_t opregion_target_state;
+	int error;
 
 	/* ignore lid events during suspend */
 	mutex_lock(&dev_priv->modeset_restore_lock);
@@ -588,37 +589,32 @@ static int i915_drm_suspend(struct drm_device *dev)
 
 	pci_save_state(dev->pdev);
 
-	/* If KMS is active, we do the leavevt stuff here */
-	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-		int error;
-
-		error = i915_gem_suspend(dev);
-		if (error) {
-			dev_err(&dev->pdev->dev,
-				"GEM idle failed, resume might fail\n");
-			return error;
-		}
+	error = i915_gem_suspend(dev);
+	if (error) {
+		dev_err(&dev->pdev->dev,
+			"GEM idle failed, resume might fail\n");
+		return error;
+	}
 
-		intel_suspend_gt_powersave(dev);
+	intel_suspend_gt_powersave(dev);
 
-		/*
-		 * Disable CRTCs directly since we want to preserve sw state
-		 * for _thaw. Also, power gate the CRTC power wells.
-		 */
-		drm_modeset_lock_all(dev);
-		for_each_crtc(dev, crtc)
-			intel_crtc_control(crtc, false);
-		drm_modeset_unlock_all(dev);
+	/*
+	 * Disable CRTCs directly since we want to preserve sw state
+	 * for _thaw. Also, power gate the CRTC power wells.
+	 */
+	drm_modeset_lock_all(dev);
+	for_each_crtc(dev, crtc)
+		intel_crtc_control(crtc, false);
+	drm_modeset_unlock_all(dev);
 
-		intel_dp_mst_suspend(dev);
+	intel_dp_mst_suspend(dev);
 
-		intel_runtime_pm_disable_interrupts(dev_priv);
-		intel_hpd_cancel_work(dev_priv);
+	intel_runtime_pm_disable_interrupts(dev_priv);
+	intel_hpd_cancel_work(dev_priv);
 
-		intel_suspend_encoders(dev_priv);
+	intel_suspend_encoders(dev_priv);
 
-		intel_suspend_hw(dev);
-	}
+	intel_suspend_hw(dev);
 
 	i915_gem_suspend_gtt_mappings(dev);
 
@@ -690,53 +686,48 @@ static int i915_drm_resume(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-		mutex_lock(&dev->struct_mutex);
-		i915_gem_restore_gtt_mappings(dev);
-		mutex_unlock(&dev->struct_mutex);
-	}
+	mutex_lock(&dev->struct_mutex);
+	i915_gem_restore_gtt_mappings(dev);
+	mutex_unlock(&dev->struct_mutex);
 
 	i915_restore_state(dev);
 	intel_opregion_setup(dev);
 
-	/* KMS EnterVT equivalent */
-	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-		intel_init_pch_refclk(dev);
-		drm_mode_config_reset(dev);
+	intel_init_pch_refclk(dev);
+	drm_mode_config_reset(dev);
 
-		mutex_lock(&dev->struct_mutex);
-		if (i915_gem_init_hw(dev)) {
-			DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
-			atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
-		}
-		mutex_unlock(&dev->struct_mutex);
+	mutex_lock(&dev->struct_mutex);
+	if (i915_gem_init_hw(dev)) {
+		DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
+		atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
+	}
+	mutex_unlock(&dev->struct_mutex);
 
-		/* We need working interrupts for modeset enabling ... */
-		intel_runtime_pm_enable_interrupts(dev_priv);
+	/* We need working interrupts for modeset enabling ... */
+	intel_runtime_pm_enable_interrupts(dev_priv);
 
-		intel_modeset_init_hw(dev);
+	intel_modeset_init_hw(dev);
 
-		spin_lock_irq(&dev_priv->irq_lock);
-		if (dev_priv->display.hpd_irq_setup)
-			dev_priv->display.hpd_irq_setup(dev);
-		spin_unlock_irq(&dev_priv->irq_lock);
+	spin_lock_irq(&dev_priv->irq_lock);
+	if (dev_priv->display.hpd_irq_setup)
+		dev_priv->display.hpd_irq_setup(dev);
+	spin_unlock_irq(&dev_priv->irq_lock);
 
-		drm_modeset_lock_all(dev);
-		intel_modeset_setup_hw_state(dev, true);
-		drm_modeset_unlock_all(dev);
+	drm_modeset_lock_all(dev);
+	intel_modeset_setup_hw_state(dev, true);
+	drm_modeset_unlock_all(dev);
 
-		intel_dp_mst_resume(dev);
+	intel_dp_mst_resume(dev);
 
-		/*
-		 * ... but also need to make sure that hotplug processing
-		 * doesn't cause havoc. Like in the driver load code we don't
-		 * bother with the tiny race here where we might loose hotplug
-		 * notifications.
-		 * */
-		intel_hpd_init(dev_priv);
-		/* Config may have changed between suspend and resume */
-		drm_helper_hpd_irq_event(dev);
-	}
+	/*
+	 * ... but also need to make sure that hotplug processing
+	 * doesn't cause havoc. Like in the driver load code we don't
+	 * bother with the tiny race here where we might loose hotplug
+	 * notifications.
+	 * */
+	intel_hpd_init(dev_priv);
+	/* Config may have changed between suspend and resume */
+	drm_helper_hpd_irq_event(dev);
 
 	intel_opregion_init(dev);
 
-- 
2.1.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH 3/7] drm/i915: Remove DRIVER_MODESET checks in the gpu reset code
  2015-02-23 11:03 [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code Daniel Vetter
  2015-02-23 11:03 ` [PATCH 2/7] drm/i915: Remove DRIVER_MODESET checks from suspend/resume code Daniel Vetter
@ 2015-02-23 11:03 ` Daniel Vetter
  2015-02-27  1:06   ` Rodrigo Vivi
  2015-02-23 11:03 ` [PATCH 4/7] drm/i915: Remove irq-related FIXME in " Daniel Vetter
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 19+ messages in thread
From: Daniel Vetter @ 2015-02-23 11:03 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter, Daniel Vetter

Again, good riddance to UMS!

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 49 +++++++++++++++++++----------------------
 1 file changed, 23 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c1a5377caff0..cc6c51107047 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -863,38 +863,35 @@ int i915_reset(struct drm_device *dev)
 	 * was running at the time of the reset (i.e. we weren't VT
 	 * switched away).
 	 */
-	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-		/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
-		dev_priv->gpu_error.reload_in_reset = true;
 
-		ret = i915_gem_init_hw(dev);
+	/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
+	dev_priv->gpu_error.reload_in_reset = true;
 
-		dev_priv->gpu_error.reload_in_reset = false;
+	ret = i915_gem_init_hw(dev);
 
-		mutex_unlock(&dev->struct_mutex);
-		if (ret) {
-			DRM_ERROR("Failed hw init on reset %d\n", ret);
-			return ret;
-		}
-
-		/*
-		 * FIXME: This races pretty badly against concurrent holders of
-		 * ring interrupts. This is possible since we've started to drop
-		 * dev->struct_mutex in select places when waiting for the gpu.
-		 */
+	dev_priv->gpu_error.reload_in_reset = false;
 
-		/*
-		 * rps/rc6 re-init is necessary to restore state lost after the
-		 * reset and the re-install of gt irqs. Skip for ironlake per
-		 * previous concerns that it doesn't respond well to some forms
-		 * of re-init after reset.
-		 */
-		if (INTEL_INFO(dev)->gen > 5)
-			intel_enable_gt_powersave(dev);
-	} else {
-		mutex_unlock(&dev->struct_mutex);
+	mutex_unlock(&dev->struct_mutex);
+	if (ret) {
+		DRM_ERROR("Failed hw init on reset %d\n", ret);
+		return ret;
 	}
 
+	/*
+	 * FIXME: This races pretty badly against concurrent holders of
+	 * ring interrupts. This is possible since we've started to drop
+	 * dev->struct_mutex in select places when waiting for the gpu.
+	 */
+
+	/*
+	 * rps/rc6 re-init is necessary to restore state lost after the
+	 * reset and the re-install of gt irqs. Skip for ironlake per
+	 * previous concerns that it doesn't respond well to some forms
+	 * of re-init after reset.
+	 */
+	if (INTEL_INFO(dev)->gen > 5)
+		intel_enable_gt_powersave(dev);
+
 	return 0;
 }
 
-- 
2.1.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH 4/7] drm/i915: Remove irq-related FIXME in reset code
  2015-02-23 11:03 [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code Daniel Vetter
  2015-02-23 11:03 ` [PATCH 2/7] drm/i915: Remove DRIVER_MODESET checks from suspend/resume code Daniel Vetter
  2015-02-23 11:03 ` [PATCH 3/7] drm/i915: Remove DRIVER_MODESET checks in the gpu reset code Daniel Vetter
@ 2015-02-23 11:03 ` Daniel Vetter
  2015-02-27  1:11   ` Rodrigo Vivi
  2015-02-23 11:03 ` [PATCH 5/7] drm/i915: Remove DRIVER_MODESET checks from gem code Daniel Vetter
                   ` (3 subsequent siblings)
  6 siblings, 1 reply; 19+ messages in thread
From: Daniel Vetter @ 2015-02-23 11:03 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter, Daniel Vetter

With the two-step reset counter increments which braket the actual
reset code and the subsequent wake-up we're guaranteeing that all the
lockless waiters _will_ be woken up. And since we unconditionally bail
out of waits with -EAGAIN (or -EIO) in that case there is not risk of
lost interrupt enabling bits when the lockless wait code races against
a gpu reset.

Let's remove this FIXME as resolved then.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index cc6c51107047..89741e6e2d08 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -878,12 +878,6 @@ int i915_reset(struct drm_device *dev)
 	}
 
 	/*
-	 * FIXME: This races pretty badly against concurrent holders of
-	 * ring interrupts. This is possible since we've started to drop
-	 * dev->struct_mutex in select places when waiting for the gpu.
-	 */
-
-	/*
 	 * rps/rc6 re-init is necessary to restore state lost after the
 	 * reset and the re-install of gt irqs. Skip for ironlake per
 	 * previous concerns that it doesn't respond well to some forms
-- 
2.1.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH 5/7] drm/i915: Remove DRIVER_MODESET checks from gem code
  2015-02-23 11:03 [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code Daniel Vetter
                   ` (2 preceding siblings ...)
  2015-02-23 11:03 ` [PATCH 4/7] drm/i915: Remove irq-related FIXME in " Daniel Vetter
@ 2015-02-23 11:03 ` Daniel Vetter
  2015-02-27  1:12   ` Rodrigo Vivi
  2015-02-23 11:03 ` [PATCH 6/7] drm/i915: Remove regfile code&data for UMS suspend/resume Daniel Vetter
                   ` (2 subsequent siblings)
  6 siblings, 1 reply; 19+ messages in thread
From: Daniel Vetter @ 2015-02-23 11:03 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter, Daniel Vetter

Hooray!

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f28f0dea6c96..4e05f57b9c54 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4606,10 +4606,6 @@ i915_gem_suspend(struct drm_device *dev)
 
 	i915_gem_retire_requests(dev);
 
-	/* Under UMS, be paranoid and evict. */
-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-		i915_gem_evict_everything(dev);
-
 	i915_gem_stop_ringbuffers(dev);
 	mutex_unlock(&dev->struct_mutex);
 
@@ -4973,18 +4969,8 @@ i915_gem_load(struct drm_device *dev)
 			  i915_gem_idle_work_handler);
 	init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
 
-	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
-	if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
-		I915_WRITE(MI_ARB_STATE,
-			   _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
-	}
-
 	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 
-	/* Old X drivers will take 0-2 for front, back, depth buffers */
-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-		dev_priv->fence_reg_start = 3;
-
 	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
 		dev_priv->num_fence_regs = 32;
 	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-- 
2.1.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH 6/7] drm/i915: Remove regfile code&data for UMS suspend/resume
  2015-02-23 11:03 [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code Daniel Vetter
                   ` (3 preceding siblings ...)
  2015-02-23 11:03 ` [PATCH 5/7] drm/i915: Remove DRIVER_MODESET checks from gem code Daniel Vetter
@ 2015-02-23 11:03 ` Daniel Vetter
  2015-02-27  1:16   ` Rodrigo Vivi
  2015-02-23 11:03 ` [PATCH 7/7] drm/i915: Remove DRIVER_MODESET checks from modeset code Daniel Vetter
  2015-02-27  1:06 ` [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code Rodrigo Vivi
  6 siblings, 1 reply; 19+ messages in thread
From: Daniel Vetter @ 2015-02-23 11:03 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter, Daniel Vetter

Lots of lines to remove!

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h     | 133 ---------
 drivers/gpu/drm/i915/i915_suspend.c | 215 +-------------
 drivers/gpu/drm/i915/i915_ums.c     | 552 ------------------------------------
 3 files changed, 2 insertions(+), 898 deletions(-)
 delete mode 100644 drivers/gpu/drm/i915/i915_ums.c

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3f210aa7652e..e4a988ef7f16 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -889,150 +889,21 @@ struct intel_gmbus {
 };
 
 struct i915_suspend_saved_registers {
-	u8 saveLBB;
-	u32 saveDSPACNTR;
-	u32 saveDSPBCNTR;
 	u32 saveDSPARB;
-	u32 savePIPEACONF;
-	u32 savePIPEBCONF;
-	u32 savePIPEASRC;
-	u32 savePIPEBSRC;
-	u32 saveFPA0;
-	u32 saveFPA1;
-	u32 saveDPLL_A;
-	u32 saveDPLL_A_MD;
-	u32 saveHTOTAL_A;
-	u32 saveHBLANK_A;
-	u32 saveHSYNC_A;
-	u32 saveVTOTAL_A;
-	u32 saveVBLANK_A;
-	u32 saveVSYNC_A;
-	u32 saveBCLRPAT_A;
-	u32 saveTRANSACONF;
-	u32 saveTRANS_HTOTAL_A;
-	u32 saveTRANS_HBLANK_A;
-	u32 saveTRANS_HSYNC_A;
-	u32 saveTRANS_VTOTAL_A;
-	u32 saveTRANS_VBLANK_A;
-	u32 saveTRANS_VSYNC_A;
-	u32 savePIPEASTAT;
-	u32 saveDSPASTRIDE;
-	u32 saveDSPASIZE;
-	u32 saveDSPAPOS;
-	u32 saveDSPAADDR;
-	u32 saveDSPASURF;
-	u32 saveDSPATILEOFF;
-	u32 savePFIT_PGM_RATIOS;
-	u32 saveBLC_HIST_CTL;
-	u32 saveBLC_PWM_CTL;
-	u32 saveBLC_PWM_CTL2;
-	u32 saveBLC_CPU_PWM_CTL;
-	u32 saveBLC_CPU_PWM_CTL2;
-	u32 saveFPB0;
-	u32 saveFPB1;
-	u32 saveDPLL_B;
-	u32 saveDPLL_B_MD;
-	u32 saveHTOTAL_B;
-	u32 saveHBLANK_B;
-	u32 saveHSYNC_B;
-	u32 saveVTOTAL_B;
-	u32 saveVBLANK_B;
-	u32 saveVSYNC_B;
-	u32 saveBCLRPAT_B;
-	u32 saveTRANSBCONF;
-	u32 saveTRANS_HTOTAL_B;
-	u32 saveTRANS_HBLANK_B;
-	u32 saveTRANS_HSYNC_B;
-	u32 saveTRANS_VTOTAL_B;
-	u32 saveTRANS_VBLANK_B;
-	u32 saveTRANS_VSYNC_B;
-	u32 savePIPEBSTAT;
-	u32 saveDSPBSTRIDE;
-	u32 saveDSPBSIZE;
-	u32 saveDSPBPOS;
-	u32 saveDSPBADDR;
-	u32 saveDSPBSURF;
-	u32 saveDSPBTILEOFF;
-	u32 saveVGA0;
-	u32 saveVGA1;
-	u32 saveVGA_PD;
-	u32 saveVGACNTRL;
-	u32 saveADPA;
 	u32 saveLVDS;
 	u32 savePP_ON_DELAYS;
 	u32 savePP_OFF_DELAYS;
-	u32 saveDVOA;
-	u32 saveDVOB;
-	u32 saveDVOC;
 	u32 savePP_ON;
 	u32 savePP_OFF;
 	u32 savePP_CONTROL;
 	u32 savePP_DIVISOR;
-	u32 savePFIT_CONTROL;
-	u32 save_palette_a[256];
-	u32 save_palette_b[256];
 	u32 saveFBC_CONTROL;
-	u32 saveIER;
-	u32 saveIIR;
-	u32 saveIMR;
-	u32 saveDEIER;
-	u32 saveDEIMR;
-	u32 saveGTIER;
-	u32 saveGTIMR;
-	u32 saveFDI_RXA_IMR;
-	u32 saveFDI_RXB_IMR;
 	u32 saveCACHE_MODE_0;
 	u32 saveMI_ARB_STATE;
 	u32 saveSWF0[16];
 	u32 saveSWF1[16];
 	u32 saveSWF2[3];
-	u8 saveMSR;
-	u8 saveSR[8];
-	u8 saveGR[25];
-	u8 saveAR_INDEX;
-	u8 saveAR[21];
-	u8 saveDACMASK;
-	u8 saveCR[37];
 	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
-	u32 saveCURACNTR;
-	u32 saveCURAPOS;
-	u32 saveCURABASE;
-	u32 saveCURBCNTR;
-	u32 saveCURBPOS;
-	u32 saveCURBBASE;
-	u32 saveCURSIZE;
-	u32 saveDP_B;
-	u32 saveDP_C;
-	u32 saveDP_D;
-	u32 savePIPEA_GMCH_DATA_M;
-	u32 savePIPEB_GMCH_DATA_M;
-	u32 savePIPEA_GMCH_DATA_N;
-	u32 savePIPEB_GMCH_DATA_N;
-	u32 savePIPEA_DP_LINK_M;
-	u32 savePIPEB_DP_LINK_M;
-	u32 savePIPEA_DP_LINK_N;
-	u32 savePIPEB_DP_LINK_N;
-	u32 saveFDI_RXA_CTL;
-	u32 saveFDI_TXA_CTL;
-	u32 saveFDI_RXB_CTL;
-	u32 saveFDI_TXB_CTL;
-	u32 savePFA_CTL_1;
-	u32 savePFB_CTL_1;
-	u32 savePFA_WIN_SZ;
-	u32 savePFB_WIN_SZ;
-	u32 savePFA_WIN_POS;
-	u32 savePFB_WIN_POS;
-	u32 savePCH_DREF_CONTROL;
-	u32 saveDISP_ARB_CTL;
-	u32 savePIPEA_DATA_M1;
-	u32 savePIPEA_DATA_N1;
-	u32 savePIPEA_LINK_M1;
-	u32 savePIPEA_LINK_N1;
-	u32 savePIPEB_DATA_M1;
-	u32 savePIPEB_DATA_N1;
-	u32 savePIPEB_LINK_M1;
-	u32 savePIPEB_LINK_N1;
-	u32 saveMCHBAR_RENDER_STANDBY;
 	u32 savePCH_PORT_HOTPLUG;
 	u16 saveGCDGMBUS;
 };
@@ -3124,10 +2995,6 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
 extern int i915_save_state(struct drm_device *dev);
 extern int i915_restore_state(struct drm_device *dev);
 
-/* i915_ums.c */
-void i915_save_display_reg(struct drm_device *dev);
-void i915_restore_display_reg(struct drm_device *dev);
-
 /* i915_sysfs.c */
 void i915_setup_sysfs(struct drm_device *dev_priv);
 void i915_teardown_sysfs(struct drm_device *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 9f19ed38cdc3..cf67f82f7b7f 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -29,166 +29,6 @@
 #include "intel_drv.h"
 #include "i915_reg.h"
 
-static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	I915_WRITE8(index_port, reg);
-	return I915_READ8(data_port);
-}
-
-static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	I915_READ8(st01);
-	I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
-	return I915_READ8(VGA_AR_DATA_READ);
-}
-
-static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	I915_READ8(st01);
-	I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
-	I915_WRITE8(VGA_AR_DATA_WRITE, val);
-}
-
-static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	I915_WRITE8(index_port, reg);
-	I915_WRITE8(data_port, val);
-}
-
-static void i915_save_vga(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	int i;
-	u16 cr_index, cr_data, st01;
-
-	/* VGA state */
-	dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
-	dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
-	dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
-	dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
-
-	/* VGA color palette registers */
-	dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
-
-	/* MSR bits */
-	dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
-	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
-		cr_index = VGA_CR_INDEX_CGA;
-		cr_data = VGA_CR_DATA_CGA;
-		st01 = VGA_ST01_CGA;
-	} else {
-		cr_index = VGA_CR_INDEX_MDA;
-		cr_data = VGA_CR_DATA_MDA;
-		st01 = VGA_ST01_MDA;
-	}
-
-	/* CRT controller regs */
-	i915_write_indexed(dev, cr_index, cr_data, 0x11,
-			   i915_read_indexed(dev, cr_index, cr_data, 0x11) &
-			   (~0x80));
-	for (i = 0; i <= 0x24; i++)
-		dev_priv->regfile.saveCR[i] =
-			i915_read_indexed(dev, cr_index, cr_data, i);
-	/* Make sure we don't turn off CR group 0 writes */
-	dev_priv->regfile.saveCR[0x11] &= ~0x80;
-
-	/* Attribute controller registers */
-	I915_READ8(st01);
-	dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
-	for (i = 0; i <= 0x14; i++)
-		dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
-	I915_READ8(st01);
-	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
-	I915_READ8(st01);
-
-	/* Graphics controller registers */
-	for (i = 0; i < 9; i++)
-		dev_priv->regfile.saveGR[i] =
-			i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
-
-	dev_priv->regfile.saveGR[0x10] =
-		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
-	dev_priv->regfile.saveGR[0x11] =
-		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
-	dev_priv->regfile.saveGR[0x18] =
-		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
-
-	/* Sequencer registers */
-	for (i = 0; i < 8; i++)
-		dev_priv->regfile.saveSR[i] =
-			i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
-}
-
-static void i915_restore_vga(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	int i;
-	u16 cr_index, cr_data, st01;
-
-	/* VGA state */
-	I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
-
-	I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
-	I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
-	I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
-	POSTING_READ(VGA_PD);
-	udelay(150);
-
-	/* MSR bits */
-	I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
-	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
-		cr_index = VGA_CR_INDEX_CGA;
-		cr_data = VGA_CR_DATA_CGA;
-		st01 = VGA_ST01_CGA;
-	} else {
-		cr_index = VGA_CR_INDEX_MDA;
-		cr_data = VGA_CR_DATA_MDA;
-		st01 = VGA_ST01_MDA;
-	}
-
-	/* Sequencer registers, don't write SR07 */
-	for (i = 0; i < 7; i++)
-		i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
-				   dev_priv->regfile.saveSR[i]);
-
-	/* CRT controller regs */
-	/* Enable CR group 0 writes */
-	i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
-	for (i = 0; i <= 0x24; i++)
-		i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
-
-	/* Graphics controller regs */
-	for (i = 0; i < 9; i++)
-		i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
-				   dev_priv->regfile.saveGR[i]);
-
-	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
-			   dev_priv->regfile.saveGR[0x10]);
-	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
-			   dev_priv->regfile.saveGR[0x11]);
-	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
-			   dev_priv->regfile.saveGR[0x18]);
-
-	/* Attribute controller registers */
-	I915_READ8(st01); /* switch back to index mode */
-	for (i = 0; i <= 0x14; i++)
-		i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
-	I915_READ8(st01); /* switch back to index mode */
-	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
-	I915_READ8(st01);
-
-	/* VGA color palette registers */
-	I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
-}
-
 static void i915_save_display(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -197,11 +37,6 @@ static void i915_save_display(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen <= 4)
 		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
 
-	/* This is only meaningful in non-KMS mode */
-	/* Don't regfile.save them in KMS mode */
-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-		i915_save_display_reg(dev);
-
 	/* LVDS state */
 	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
 		dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
@@ -224,9 +59,6 @@ static void i915_save_display(struct drm_device *dev)
 	/* save FBC interval */
 	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
 		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
-
-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-		i915_save_vga(dev);
 }
 
 static void i915_restore_display(struct drm_device *dev)
@@ -238,11 +70,7 @@ static void i915_restore_display(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen <= 4)
 		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
 
-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-		i915_restore_display_reg(dev);
-
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		mask = ~LVDS_PORT_EN;
+	mask = ~LVDS_PORT_EN;
 
 	/* LVDS state */
 	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
@@ -270,10 +98,7 @@ static void i915_restore_display(struct drm_device *dev)
 	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
 		I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
 
-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-		i915_restore_vga(dev);
-	else
-		i915_redisable_vga(dev);
+	i915_redisable_vga(dev);
 }
 
 int i915_save_state(struct drm_device *dev)
@@ -285,24 +110,6 @@ int i915_save_state(struct drm_device *dev)
 
 	i915_save_display(dev);
 
-	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
-		/* Interrupt state */
-		if (HAS_PCH_SPLIT(dev)) {
-			dev_priv->regfile.saveDEIER = I915_READ(DEIER);
-			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
-			dev_priv->regfile.saveGTIER = I915_READ(GTIER);
-			dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
-			dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
-			dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
-			dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
-				I915_READ(RSTDBYCTL);
-			dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
-		} else {
-			dev_priv->regfile.saveIER = I915_READ(IER);
-			dev_priv->regfile.saveIMR = I915_READ(IMR);
-		}
-	}
-
 	if (IS_GEN4(dev))
 		pci_read_config_word(dev->pdev, GCDGMBUS,
 				     &dev_priv->regfile.saveGCDGMBUS);
@@ -341,24 +148,6 @@ int i915_restore_state(struct drm_device *dev)
 				      dev_priv->regfile.saveGCDGMBUS);
 	i915_restore_display(dev);
 
-	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
-		/* Interrupt state */
-		if (HAS_PCH_SPLIT(dev)) {
-			I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
-			I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
-			I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
-			I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
-			I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
-			I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
-			I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
-			I915_WRITE(RSTDBYCTL,
-				   dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
-		} else {
-			I915_WRITE(IER, dev_priv->regfile.saveIER);
-			I915_WRITE(IMR, dev_priv->regfile.saveIMR);
-		}
-	}
-
 	/* Cache mode state */
 	if (INTEL_INFO(dev)->gen < 7)
 		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
deleted file mode 100644
index d10fe3e9c49f..000000000000
--- a/drivers/gpu/drm/i915/i915_ums.c
+++ /dev/null
@@ -1,552 +0,0 @@
-/*
- *
- * Copyright 2008 (c) Intel Corporation
- *   Jesse Barnes <jbarnes@virtuousgeek.org>
- * Copyright 2013 (c) Intel Corporation
- *   Daniel Vetter <daniel.vetter@ffwll.ch>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <drm/drmP.h>
-#include <drm/i915_drm.h>
-#include "intel_drv.h"
-#include "i915_reg.h"
-
-static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32	dpll_reg;
-
-	/* On IVB, 3rd pipe shares PLL with another one */
-	if (pipe > 1)
-		return false;
-
-	if (HAS_PCH_SPLIT(dev))
-		dpll_reg = PCH_DPLL(pipe);
-	else
-		dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
-
-	return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
-}
-
-static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
-	u32 *array;
-	int i;
-
-	if (!i915_pipe_enabled(dev, pipe))
-		return;
-
-	if (HAS_PCH_SPLIT(dev))
-		reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
-
-	if (pipe == PIPE_A)
-		array = dev_priv->regfile.save_palette_a;
-	else
-		array = dev_priv->regfile.save_palette_b;
-
-	for (i = 0; i < 256; i++)
-		array[i] = I915_READ(reg + (i << 2));
-}
-
-static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
-	u32 *array;
-	int i;
-
-	if (!i915_pipe_enabled(dev, pipe))
-		return;
-
-	if (HAS_PCH_SPLIT(dev))
-		reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
-
-	if (pipe == PIPE_A)
-		array = dev_priv->regfile.save_palette_a;
-	else
-		array = dev_priv->regfile.save_palette_b;
-
-	for (i = 0; i < 256; i++)
-		I915_WRITE(reg + (i << 2), array[i]);
-}
-
-void i915_save_display_reg(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	int i;
-
-	/* Cursor state */
-	dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
-	dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
-	dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
-	dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
-	dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
-	dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
-	if (IS_GEN2(dev))
-		dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
-
-	if (HAS_PCH_SPLIT(dev)) {
-		dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
-		dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
-	}
-
-	/* Pipe & plane A info */
-	dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
-	dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
-	if (HAS_PCH_SPLIT(dev)) {
-		dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
-		dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
-		dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
-	} else {
-		dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
-		dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
-		dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
-	}
-	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
-		dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
-	dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
-	dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
-	dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
-	dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
-	dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
-	dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
-	if (!HAS_PCH_SPLIT(dev))
-		dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
-
-	if (HAS_PCH_SPLIT(dev)) {
-		dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
-		dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
-		dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
-		dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
-
-		dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
-		dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
-
-		dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
-		dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
-		dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
-
-		dev_priv->regfile.saveTRANSACONF = I915_READ(_PCH_TRANSACONF);
-		dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_PCH_TRANS_HTOTAL_A);
-		dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_PCH_TRANS_HBLANK_A);
-		dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_PCH_TRANS_HSYNC_A);
-		dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_PCH_TRANS_VTOTAL_A);
-		dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_PCH_TRANS_VBLANK_A);
-		dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_PCH_TRANS_VSYNC_A);
-	}
-
-	dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
-	dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
-	dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
-	dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
-	dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
-	if (INTEL_INFO(dev)->gen >= 4) {
-		dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
-		dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
-	}
-	i915_save_palette(dev, PIPE_A);
-	dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
-
-	/* Pipe & plane B info */
-	dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
-	dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
-	if (HAS_PCH_SPLIT(dev)) {
-		dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
-		dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
-		dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
-	} else {
-		dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
-		dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
-		dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
-	}
-	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
-		dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
-	dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
-	dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
-	dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
-	dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
-	dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
-	dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
-	if (!HAS_PCH_SPLIT(dev))
-		dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
-
-	if (HAS_PCH_SPLIT(dev)) {
-		dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
-		dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
-		dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
-		dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
-
-		dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
-		dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
-
-		dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
-		dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
-		dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
-
-		dev_priv->regfile.saveTRANSBCONF = I915_READ(_PCH_TRANSBCONF);
-		dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_PCH_TRANS_HTOTAL_B);
-		dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_PCH_TRANS_HBLANK_B);
-		dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_PCH_TRANS_HSYNC_B);
-		dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_PCH_TRANS_VTOTAL_B);
-		dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_PCH_TRANS_VBLANK_B);
-		dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_PCH_TRANS_VSYNC_B);
-	}
-
-	dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
-	dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
-	dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
-	dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
-	dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
-	if (INTEL_INFO(dev)->gen >= 4) {
-		dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
-		dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
-	}
-	i915_save_palette(dev, PIPE_B);
-	dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
-
-	/* Fences */
-	switch (INTEL_INFO(dev)->gen) {
-	case 7:
-	case 6:
-		for (i = 0; i < 16; i++)
-			dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
-		break;
-	case 5:
-	case 4:
-		for (i = 0; i < 16; i++)
-			dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
-		break;
-	case 3:
-		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-			for (i = 0; i < 8; i++)
-				dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
-	case 2:
-		for (i = 0; i < 8; i++)
-			dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
-		break;
-	}
-
-	/* CRT state */
-	if (HAS_PCH_SPLIT(dev))
-		dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
-	else
-		dev_priv->regfile.saveADPA = I915_READ(ADPA);
-
-	/* Display Port state */
-	if (SUPPORTS_INTEGRATED_DP(dev)) {
-		dev_priv->regfile.saveDP_B = I915_READ(DP_B);
-		dev_priv->regfile.saveDP_C = I915_READ(DP_C);
-		dev_priv->regfile.saveDP_D = I915_READ(DP_D);
-		dev_priv->regfile.savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_DATA_M_G4X);
-		dev_priv->regfile.savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_DATA_M_G4X);
-		dev_priv->regfile.savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_DATA_N_G4X);
-		dev_priv->regfile.savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_DATA_N_G4X);
-		dev_priv->regfile.savePIPEA_DP_LINK_M = I915_READ(_PIPEA_LINK_M_G4X);
-		dev_priv->regfile.savePIPEB_DP_LINK_M = I915_READ(_PIPEB_LINK_M_G4X);
-		dev_priv->regfile.savePIPEA_DP_LINK_N = I915_READ(_PIPEA_LINK_N_G4X);
-		dev_priv->regfile.savePIPEB_DP_LINK_N = I915_READ(_PIPEB_LINK_N_G4X);
-	}
-	/* FIXME: regfile.save TV & SDVO state */
-
-	/* Panel fitter */
-	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) {
-		dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
-		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
-	}
-
-	/* Backlight */
-	if (INTEL_INFO(dev)->gen <= 4)
-		pci_read_config_byte(dev->pdev, PCI_LBPC,
-				     &dev_priv->regfile.saveLBB);
-
-	if (HAS_PCH_SPLIT(dev)) {
-		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
-		dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
-		dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
-		dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
-	} else {
-		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
-		if (INTEL_INFO(dev)->gen >= 4)
-			dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
-		dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
-	}
-
-	return;
-}
-
-void i915_restore_display_reg(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	int dpll_a_reg, fpa0_reg, fpa1_reg;
-	int dpll_b_reg, fpb0_reg, fpb1_reg;
-	int i;
-
-	/* Backlight */
-	if (INTEL_INFO(dev)->gen <= 4)
-		pci_write_config_byte(dev->pdev, PCI_LBPC,
-				      dev_priv->regfile.saveLBB);
-
-	if (HAS_PCH_SPLIT(dev)) {
-		I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
-		I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
-		/* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
-		 * otherwise we get blank eDP screen after S3 on some machines
-		 */
-		I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
-		I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
-	} else {
-		if (INTEL_INFO(dev)->gen >= 4)
-			I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
-		I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
-		I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
-	}
-
-	/* Panel fitter */
-	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) {
-		I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
-		I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
-	}
-
-	/* Display port ratios (must be done before clock is set) */
-	if (SUPPORTS_INTEGRATED_DP(dev)) {
-		I915_WRITE(_PIPEA_DATA_M_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
-		I915_WRITE(_PIPEB_DATA_M_G4X, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
-		I915_WRITE(_PIPEA_DATA_N_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
-		I915_WRITE(_PIPEB_DATA_N_G4X, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
-		I915_WRITE(_PIPEA_LINK_M_G4X, dev_priv->regfile.savePIPEA_DP_LINK_M);
-		I915_WRITE(_PIPEB_LINK_M_G4X, dev_priv->regfile.savePIPEB_DP_LINK_M);
-		I915_WRITE(_PIPEA_LINK_N_G4X, dev_priv->regfile.savePIPEA_DP_LINK_N);
-		I915_WRITE(_PIPEB_LINK_N_G4X, dev_priv->regfile.savePIPEB_DP_LINK_N);
-	}
-
-	/* Fences */
-	switch (INTEL_INFO(dev)->gen) {
-	case 7:
-	case 6:
-		for (i = 0; i < 16; i++)
-			I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
-		break;
-	case 5:
-	case 4:
-		for (i = 0; i < 16; i++)
-			I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
-		break;
-	case 3:
-	case 2:
-		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-			for (i = 0; i < 8; i++)
-				I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
-		for (i = 0; i < 8; i++)
-			I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
-		break;
-	}
-
-
-	if (HAS_PCH_SPLIT(dev)) {
-		dpll_a_reg = _PCH_DPLL_A;
-		dpll_b_reg = _PCH_DPLL_B;
-		fpa0_reg = _PCH_FPA0;
-		fpb0_reg = _PCH_FPB0;
-		fpa1_reg = _PCH_FPA1;
-		fpb1_reg = _PCH_FPB1;
-	} else {
-		dpll_a_reg = _DPLL_A;
-		dpll_b_reg = _DPLL_B;
-		fpa0_reg = _FPA0;
-		fpb0_reg = _FPB0;
-		fpa1_reg = _FPA1;
-		fpb1_reg = _FPB1;
-	}
-
-	if (HAS_PCH_SPLIT(dev)) {
-		I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
-		I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
-	}
-
-	/* Pipe & plane A info */
-	/* Prime the clock */
-	if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
-		I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
-			   ~DPLL_VCO_ENABLE);
-		POSTING_READ(dpll_a_reg);
-		udelay(150);
-	}
-	I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
-	I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
-	/* Actually enable it */
-	I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
-	POSTING_READ(dpll_a_reg);
-	udelay(150);
-	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
-		I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
-		POSTING_READ(_DPLL_A_MD);
-	}
-	udelay(150);
-
-	/* Restore mode */
-	I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
-	I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
-	I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
-	I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
-	I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
-	I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
-	if (!HAS_PCH_SPLIT(dev))
-		I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
-
-	if (HAS_PCH_SPLIT(dev)) {
-		I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
-		I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
-		I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
-		I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
-
-		I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
-		I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
-
-		I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
-		I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
-		I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
-
-		I915_WRITE(_PCH_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
-		I915_WRITE(_PCH_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
-		I915_WRITE(_PCH_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
-		I915_WRITE(_PCH_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
-		I915_WRITE(_PCH_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
-		I915_WRITE(_PCH_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
-		I915_WRITE(_PCH_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
-	}
-
-	/* Restore plane info */
-	I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
-	I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
-	I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
-	I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
-	I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
-	if (INTEL_INFO(dev)->gen >= 4) {
-		I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
-		I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
-	}
-
-	I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
-
-	i915_restore_palette(dev, PIPE_A);
-	/* Enable the plane */
-	I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
-	I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
-
-	/* Pipe & plane B info */
-	if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
-		I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
-			   ~DPLL_VCO_ENABLE);
-		POSTING_READ(dpll_b_reg);
-		udelay(150);
-	}
-	I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
-	I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
-	/* Actually enable it */
-	I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
-	POSTING_READ(dpll_b_reg);
-	udelay(150);
-	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
-		I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
-		POSTING_READ(_DPLL_B_MD);
-	}
-	udelay(150);
-
-	/* Restore mode */
-	I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
-	I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
-	I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
-	I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
-	I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
-	I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
-	if (!HAS_PCH_SPLIT(dev))
-		I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
-
-	if (HAS_PCH_SPLIT(dev)) {
-		I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
-		I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
-		I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
-		I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
-
-		I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
-		I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
-
-		I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
-		I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
-		I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
-
-		I915_WRITE(_PCH_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
-		I915_WRITE(_PCH_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
-		I915_WRITE(_PCH_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
-		I915_WRITE(_PCH_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
-		I915_WRITE(_PCH_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
-		I915_WRITE(_PCH_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
-		I915_WRITE(_PCH_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
-	}
-
-	/* Restore plane info */
-	I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
-	I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
-	I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
-	I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
-	I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
-	if (INTEL_INFO(dev)->gen >= 4) {
-		I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
-		I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
-	}
-
-	I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
-
-	i915_restore_palette(dev, PIPE_B);
-	/* Enable the plane */
-	I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
-	I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
-
-	/* Cursor state */
-	I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
-	I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
-	I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
-	I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
-	I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
-	I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
-	if (IS_GEN2(dev))
-		I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
-
-	/* CRT state */
-	if (HAS_PCH_SPLIT(dev))
-		I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
-	else
-		I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
-
-	/* Display Port state */
-	if (SUPPORTS_INTEGRATED_DP(dev)) {
-		I915_WRITE(DP_B, dev_priv->regfile.saveDP_B);
-		I915_WRITE(DP_C, dev_priv->regfile.saveDP_C);
-		I915_WRITE(DP_D, dev_priv->regfile.saveDP_D);
-	}
-	/* FIXME: restore TV & SDVO state */
-
-	return;
-}
-- 
2.1.4

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH 7/7] drm/i915: Remove DRIVER_MODESET checks from modeset code
  2015-02-23 11:03 [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code Daniel Vetter
                   ` (4 preceding siblings ...)
  2015-02-23 11:03 ` [PATCH 6/7] drm/i915: Remove regfile code&data for UMS suspend/resume Daniel Vetter
@ 2015-02-23 11:03 ` Daniel Vetter
  2015-02-23 17:13   ` shuang.he
  2015-02-27  1:17   ` Rodrigo Vivi
  2015-02-27  1:06 ` [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code Rodrigo Vivi
  6 siblings, 2 replies; 19+ messages in thread
From: Daniel Vetter @ 2015-02-23 11:03 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter, Daniel Vetter

Mostly just checks in i915-private modeset ioctls.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c  | 3 ---
 drivers/gpu/drm/i915/intel_opregion.c | 6 ++----
 drivers/gpu/drm/i915/intel_overlay.c  | 2 --
 drivers/gpu/drm/i915/intel_sprite.c   | 6 ------
 4 files changed, 2 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3b0fe9f1f3c9..253a201e20dd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12372,9 +12372,6 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 	struct drm_crtc *drmmode_crtc;
 	struct intel_crtc *crtc;
 
-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-		return -ENODEV;
-
 	drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
 
 	if (!drmmode_crtc) {
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index d8de1d5140a7..71e87abdcae7 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -744,10 +744,8 @@ void intel_opregion_init(struct drm_device *dev)
 		return;
 
 	if (opregion->acpi) {
-		if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-			intel_didl_outputs(dev);
-			intel_setup_cadls(dev);
-		}
+		intel_didl_outputs(dev);
+		intel_setup_cadls(dev);
 
 		/* Notify BIOS we are ready to handle ACPI video ext notifs.
 		 * Right now, all the events are handled by the ACPI video module.
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index f93dfc174495..823d1d97a000 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1065,7 +1065,6 @@ int intel_overlay_put_image(struct drm_device *dev, void *data,
 	struct put_image_params *params;
 	int ret;
 
-	/* No need to check for DRIVER_MODESET - we don't set it up then. */
 	overlay = dev_priv->overlay;
 	if (!overlay) {
 		DRM_DEBUG("userspace bug: no overlay\n");
@@ -1261,7 +1260,6 @@ int intel_overlay_attrs(struct drm_device *dev, void *data,
 	struct overlay_registers __iomem *regs;
 	int ret;
 
-	/* No need to check for DRIVER_MODESET - we don't set it up then. */
 	overlay = dev_priv->overlay;
 	if (!overlay) {
 		DRM_DEBUG("userspace bug: no overlay\n");
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index f2d408dd7c15..4f8fa0534954 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1301,9 +1301,6 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 	struct intel_plane *intel_plane;
 	int ret = 0;
 
-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-		return -ENODEV;
-
 	/* Make sure we don't try to enable both src & dest simultaneously */
 	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 		return -EINVAL;
@@ -1332,9 +1329,6 @@ int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 	struct intel_plane *intel_plane;
 	int ret = 0;
 
-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-		return -ENODEV;
-
 	drm_modeset_lock_all(dev);
 
 	plane = drm_plane_find(dev, get->plane_id);
-- 
2.1.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH 7/7] drm/i915: Remove DRIVER_MODESET checks from modeset code
  2015-02-23 11:03 ` [PATCH 7/7] drm/i915: Remove DRIVER_MODESET checks from modeset code Daniel Vetter
@ 2015-02-23 17:13   ` shuang.he
  2015-02-27  1:17   ` Rodrigo Vivi
  1 sibling, 0 replies; 19+ messages in thread
From: shuang.he @ 2015-02-23 17:13 UTC (permalink / raw)
  To: shuang.he, ethan.gao, intel-gfx, daniel.vetter

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5810
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -3              281/281              278/281
ILK                                  308/308              308/308
SNB                                  326/326              326/326
IVB                                  380/380              380/380
BYT                                  294/294              294/294
HSW                                  421/421              421/421
BDW                 -1              316/316              315/316
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt_gem_userptr_blits_minor-normal-sync      DMESG_WARN(1)PASS(1)      DMESG_WARN(1)PASS(1)
*PNV  igt_gen3_render_mixed_blits      PASS(4)      NRUN(1)PASS(1)
*PNV  igt_gen3_render_tiledx_blits      NO_RESULT(1)PASS(4)      CRASH(1)PASS(1)
*BDW  igt_gem_gtt_hog      PASS(3)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code
  2015-02-23 11:03 [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code Daniel Vetter
                   ` (5 preceding siblings ...)
  2015-02-23 11:03 ` [PATCH 7/7] drm/i915: Remove DRIVER_MODESET checks from modeset code Daniel Vetter
@ 2015-02-27  1:06 ` Rodrigo Vivi
  6 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2015-02-27  1:06 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Daniel Vetter, Intel Graphics Development

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Mon, Feb 23, 2015 at 3:03 AM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> UMS is gone, this is dead code.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 95 ++++++++++++++++-------------------------
>  1 file changed, 37 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 5804aa5f9df0..63a001b6abed 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -638,17 +638,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>
>         info = (struct intel_device_info *) flags;
>
> -       /* Refuse to load on gen6+ without kms enabled. */
> -       if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
> -               DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
> -               DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
> -               return -ENODEV;
> -       }
> -
> -       /* UMS needs agp support. */
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
> -               return -EINVAL;
> -
>         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
>         if (dev_priv == NULL)
>                 return -ENOMEM;
> @@ -718,20 +707,18 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>         if (ret)
>                 goto out_regs;
>
> -       if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> -               /* WARNING: Apparently we must kick fbdev drivers before vgacon,
> -                * otherwise the vga fbdev driver falls over. */
> -               ret = i915_kick_out_firmware_fb(dev_priv);
> -               if (ret) {
> -                       DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
> -                       goto out_gtt;
> -               }
> +       /* WARNING: Apparently we must kick fbdev drivers before vgacon,
> +        * otherwise the vga fbdev driver falls over. */
> +       ret = i915_kick_out_firmware_fb(dev_priv);
> +       if (ret) {
> +               DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
> +               goto out_gtt;
> +       }
>
> -               ret = i915_kick_out_vgacon(dev_priv);
> -               if (ret) {
> -                       DRM_ERROR("failed to remove conflicting VGA console\n");
> -                       goto out_gtt;
> -               }
> +       ret = i915_kick_out_vgacon(dev_priv);
> +       if (ret) {
> +               DRM_ERROR("failed to remove conflicting VGA console\n");
> +               goto out_gtt;
>         }
>
>         pci_set_master(dev->pdev);
> @@ -835,12 +822,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>
>         intel_power_domains_init(dev_priv);
>
> -       if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> -               ret = i915_load_modeset_init(dev);
> -               if (ret < 0) {
> -                       DRM_ERROR("failed to init modeset\n");
> -                       goto out_power_well;
> -               }
> +       ret = i915_load_modeset_init(dev);
> +       if (ret < 0) {
> +               DRM_ERROR("failed to init modeset\n");
> +               goto out_power_well;
>         }
>
>         /*
> @@ -929,28 +914,25 @@ int i915_driver_unload(struct drm_device *dev)
>
>         acpi_video_unregister();
>
> -       if (drm_core_check_feature(dev, DRIVER_MODESET))
> -               intel_fbdev_fini(dev);
> +       intel_fbdev_fini(dev);
>
>         drm_vblank_cleanup(dev);
>
> -       if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> -               intel_modeset_cleanup(dev);
> -
> -               /*
> -                * free the memory space allocated for the child device
> -                * config parsed from VBT
> -                */
> -               if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
> -                       kfree(dev_priv->vbt.child_dev);
> -                       dev_priv->vbt.child_dev = NULL;
> -                       dev_priv->vbt.child_dev_num = 0;
> -               }
> +       intel_modeset_cleanup(dev);
>
> -               vga_switcheroo_unregister_client(dev->pdev);
> -               vga_client_register(dev->pdev, NULL, NULL, NULL);
> +       /*
> +        * free the memory space allocated for the child device
> +        * config parsed from VBT
> +        */
> +       if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
> +               kfree(dev_priv->vbt.child_dev);
> +               dev_priv->vbt.child_dev = NULL;
> +               dev_priv->vbt.child_dev_num = 0;
>         }
>
> +       vga_switcheroo_unregister_client(dev->pdev);
> +       vga_client_register(dev->pdev, NULL, NULL, NULL);
> +
>         /* Free error state after interrupts are fully disabled. */
>         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
>         i915_destroy_error_state(dev);
> @@ -960,17 +942,15 @@ int i915_driver_unload(struct drm_device *dev)
>
>         intel_opregion_fini(dev);
>
> -       if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> -               /* Flush any outstanding unpin_work. */
> -               flush_workqueue(dev_priv->wq);
> +       /* Flush any outstanding unpin_work. */
> +       flush_workqueue(dev_priv->wq);
>
> -               mutex_lock(&dev->struct_mutex);
> -               i915_gem_cleanup_ringbuffer(dev);
> -               i915_gem_batch_pool_fini(&dev_priv->mm.batch_pool);
> -               i915_gem_context_fini(dev);
> -               mutex_unlock(&dev->struct_mutex);
> -               i915_gem_cleanup_stolen(dev);
> -       }
> +       mutex_lock(&dev->struct_mutex);
> +       i915_gem_cleanup_ringbuffer(dev);
> +       i915_gem_batch_pool_fini(&dev_priv->mm.batch_pool);
> +       i915_gem_context_fini(dev);
> +       mutex_unlock(&dev->struct_mutex);
> +       i915_gem_cleanup_stolen(dev);
>
>         intel_teardown_gmbus(dev);
>         intel_teardown_mchbar(dev);
> @@ -1031,8 +1011,7 @@ void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
>         i915_gem_release(dev, file);
>         mutex_unlock(&dev->struct_mutex);
>
> -       if (drm_core_check_feature(dev, DRIVER_MODESET))
> -               intel_modeset_preclose(dev, file);
> +       intel_modeset_preclose(dev, file);
>  }
>
>  void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 2/7] drm/i915: Remove DRIVER_MODESET checks from suspend/resume code
  2015-02-23 11:03 ` [PATCH 2/7] drm/i915: Remove DRIVER_MODESET checks from suspend/resume code Daniel Vetter
@ 2015-02-27  1:06   ` Rodrigo Vivi
  0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2015-02-27  1:06 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Daniel Vetter, Intel Graphics Development

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Mon, Feb 23, 2015 at 3:03 AM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> UMS is dead, yay!
>
> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 113 ++++++++++++++++++----------------------
>  1 file changed, 52 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index ba6862f5b6b2..c1a5377caff0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -574,6 +574,7 @@ static int i915_drm_suspend(struct drm_device *dev)
>         struct drm_i915_private *dev_priv = dev->dev_private;
>         struct drm_crtc *crtc;
>         pci_power_t opregion_target_state;
> +       int error;
>
>         /* ignore lid events during suspend */
>         mutex_lock(&dev_priv->modeset_restore_lock);
> @@ -588,37 +589,32 @@ static int i915_drm_suspend(struct drm_device *dev)
>
>         pci_save_state(dev->pdev);
>
> -       /* If KMS is active, we do the leavevt stuff here */
> -       if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> -               int error;
> -
> -               error = i915_gem_suspend(dev);
> -               if (error) {
> -                       dev_err(&dev->pdev->dev,
> -                               "GEM idle failed, resume might fail\n");
> -                       return error;
> -               }
> +       error = i915_gem_suspend(dev);
> +       if (error) {
> +               dev_err(&dev->pdev->dev,
> +                       "GEM idle failed, resume might fail\n");
> +               return error;
> +       }
>
> -               intel_suspend_gt_powersave(dev);
> +       intel_suspend_gt_powersave(dev);
>
> -               /*
> -                * Disable CRTCs directly since we want to preserve sw state
> -                * for _thaw. Also, power gate the CRTC power wells.
> -                */
> -               drm_modeset_lock_all(dev);
> -               for_each_crtc(dev, crtc)
> -                       intel_crtc_control(crtc, false);
> -               drm_modeset_unlock_all(dev);
> +       /*
> +        * Disable CRTCs directly since we want to preserve sw state
> +        * for _thaw. Also, power gate the CRTC power wells.
> +        */
> +       drm_modeset_lock_all(dev);
> +       for_each_crtc(dev, crtc)
> +               intel_crtc_control(crtc, false);
> +       drm_modeset_unlock_all(dev);
>
> -               intel_dp_mst_suspend(dev);
> +       intel_dp_mst_suspend(dev);
>
> -               intel_runtime_pm_disable_interrupts(dev_priv);
> -               intel_hpd_cancel_work(dev_priv);
> +       intel_runtime_pm_disable_interrupts(dev_priv);
> +       intel_hpd_cancel_work(dev_priv);
>
> -               intel_suspend_encoders(dev_priv);
> +       intel_suspend_encoders(dev_priv);
>
> -               intel_suspend_hw(dev);
> -       }
> +       intel_suspend_hw(dev);
>
>         i915_gem_suspend_gtt_mappings(dev);
>
> @@ -690,53 +686,48 @@ static int i915_drm_resume(struct drm_device *dev)
>  {
>         struct drm_i915_private *dev_priv = dev->dev_private;
>
> -       if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> -               mutex_lock(&dev->struct_mutex);
> -               i915_gem_restore_gtt_mappings(dev);
> -               mutex_unlock(&dev->struct_mutex);
> -       }
> +       mutex_lock(&dev->struct_mutex);
> +       i915_gem_restore_gtt_mappings(dev);
> +       mutex_unlock(&dev->struct_mutex);
>
>         i915_restore_state(dev);
>         intel_opregion_setup(dev);
>
> -       /* KMS EnterVT equivalent */
> -       if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> -               intel_init_pch_refclk(dev);
> -               drm_mode_config_reset(dev);
> +       intel_init_pch_refclk(dev);
> +       drm_mode_config_reset(dev);
>
> -               mutex_lock(&dev->struct_mutex);
> -               if (i915_gem_init_hw(dev)) {
> -                       DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
> -                       atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
> -               }
> -               mutex_unlock(&dev->struct_mutex);
> +       mutex_lock(&dev->struct_mutex);
> +       if (i915_gem_init_hw(dev)) {
> +               DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
> +               atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
> +       }
> +       mutex_unlock(&dev->struct_mutex);
>
> -               /* We need working interrupts for modeset enabling ... */
> -               intel_runtime_pm_enable_interrupts(dev_priv);
> +       /* We need working interrupts for modeset enabling ... */
> +       intel_runtime_pm_enable_interrupts(dev_priv);
>
> -               intel_modeset_init_hw(dev);
> +       intel_modeset_init_hw(dev);
>
> -               spin_lock_irq(&dev_priv->irq_lock);
> -               if (dev_priv->display.hpd_irq_setup)
> -                       dev_priv->display.hpd_irq_setup(dev);
> -               spin_unlock_irq(&dev_priv->irq_lock);
> +       spin_lock_irq(&dev_priv->irq_lock);
> +       if (dev_priv->display.hpd_irq_setup)
> +               dev_priv->display.hpd_irq_setup(dev);
> +       spin_unlock_irq(&dev_priv->irq_lock);
>
> -               drm_modeset_lock_all(dev);
> -               intel_modeset_setup_hw_state(dev, true);
> -               drm_modeset_unlock_all(dev);
> +       drm_modeset_lock_all(dev);
> +       intel_modeset_setup_hw_state(dev, true);
> +       drm_modeset_unlock_all(dev);
>
> -               intel_dp_mst_resume(dev);
> +       intel_dp_mst_resume(dev);
>
> -               /*
> -                * ... but also need to make sure that hotplug processing
> -                * doesn't cause havoc. Like in the driver load code we don't
> -                * bother with the tiny race here where we might loose hotplug
> -                * notifications.
> -                * */
> -               intel_hpd_init(dev_priv);
> -               /* Config may have changed between suspend and resume */
> -               drm_helper_hpd_irq_event(dev);
> -       }
> +       /*
> +        * ... but also need to make sure that hotplug processing
> +        * doesn't cause havoc. Like in the driver load code we don't
> +        * bother with the tiny race here where we might loose hotplug
> +        * notifications.
> +        * */
> +       intel_hpd_init(dev_priv);
> +       /* Config may have changed between suspend and resume */
> +       drm_helper_hpd_irq_event(dev);
>
>         intel_opregion_init(dev);
>
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 3/7] drm/i915: Remove DRIVER_MODESET checks in the gpu reset code
  2015-02-23 11:03 ` [PATCH 3/7] drm/i915: Remove DRIVER_MODESET checks in the gpu reset code Daniel Vetter
@ 2015-02-27  1:06   ` Rodrigo Vivi
  0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2015-02-27  1:06 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Daniel Vetter, Intel Graphics Development

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Mon, Feb 23, 2015 at 3:03 AM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Again, good riddance to UMS!
>
> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 49 +++++++++++++++++++----------------------
>  1 file changed, 23 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index c1a5377caff0..cc6c51107047 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -863,38 +863,35 @@ int i915_reset(struct drm_device *dev)
>          * was running at the time of the reset (i.e. we weren't VT
>          * switched away).
>          */
> -       if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> -               /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
> -               dev_priv->gpu_error.reload_in_reset = true;
>
> -               ret = i915_gem_init_hw(dev);
> +       /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
> +       dev_priv->gpu_error.reload_in_reset = true;
>
> -               dev_priv->gpu_error.reload_in_reset = false;
> +       ret = i915_gem_init_hw(dev);
>
> -               mutex_unlock(&dev->struct_mutex);
> -               if (ret) {
> -                       DRM_ERROR("Failed hw init on reset %d\n", ret);
> -                       return ret;
> -               }
> -
> -               /*
> -                * FIXME: This races pretty badly against concurrent holders of
> -                * ring interrupts. This is possible since we've started to drop
> -                * dev->struct_mutex in select places when waiting for the gpu.
> -                */
> +       dev_priv->gpu_error.reload_in_reset = false;
>
> -               /*
> -                * rps/rc6 re-init is necessary to restore state lost after the
> -                * reset and the re-install of gt irqs. Skip for ironlake per
> -                * previous concerns that it doesn't respond well to some forms
> -                * of re-init after reset.
> -                */
> -               if (INTEL_INFO(dev)->gen > 5)
> -                       intel_enable_gt_powersave(dev);
> -       } else {
> -               mutex_unlock(&dev->struct_mutex);
> +       mutex_unlock(&dev->struct_mutex);
> +       if (ret) {
> +               DRM_ERROR("Failed hw init on reset %d\n", ret);
> +               return ret;
>         }
>
> +       /*
> +        * FIXME: This races pretty badly against concurrent holders of
> +        * ring interrupts. This is possible since we've started to drop
> +        * dev->struct_mutex in select places when waiting for the gpu.
> +        */
> +
> +       /*
> +        * rps/rc6 re-init is necessary to restore state lost after the
> +        * reset and the re-install of gt irqs. Skip for ironlake per
> +        * previous concerns that it doesn't respond well to some forms
> +        * of re-init after reset.
> +        */
> +       if (INTEL_INFO(dev)->gen > 5)
> +               intel_enable_gt_powersave(dev);
> +
>         return 0;
>  }
>
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 4/7] drm/i915: Remove irq-related FIXME in reset code
  2015-02-23 11:03 ` [PATCH 4/7] drm/i915: Remove irq-related FIXME in " Daniel Vetter
@ 2015-02-27  1:11   ` Rodrigo Vivi
  2015-02-27 14:04     ` Daniel Vetter
  0 siblings, 1 reply; 19+ messages in thread
From: Rodrigo Vivi @ 2015-02-27  1:11 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Daniel Vetter, Intel Graphics Development

I believe this patch is on the wrong series, right?

I'm afraid I don't know what was this race neither the two-step reset
to be able to review this comment remove.
Please give me some pointers to check that.


On Mon, Feb 23, 2015 at 3:03 AM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> With the two-step reset counter increments which braket the actual
> reset code and the subsequent wake-up we're guaranteeing that all the
> lockless waiters _will_ be woken up. And since we unconditionally bail
> out of waits with -EAGAIN (or -EIO) in that case there is not risk of
> lost interrupt enabling bits when the lockless wait code races against
> a gpu reset.
>
> Let's remove this FIXME as resolved then.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 6 ------
>  1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index cc6c51107047..89741e6e2d08 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -878,12 +878,6 @@ int i915_reset(struct drm_device *dev)
>         }
>
>         /*
> -        * FIXME: This races pretty badly against concurrent holders of
> -        * ring interrupts. This is possible since we've started to drop
> -        * dev->struct_mutex in select places when waiting for the gpu.
> -        */
> -
> -       /*
>          * rps/rc6 re-init is necessary to restore state lost after the
>          * reset and the re-install of gt irqs. Skip for ironlake per
>          * previous concerns that it doesn't respond well to some forms
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 5/7] drm/i915: Remove DRIVER_MODESET checks from gem code
  2015-02-23 11:03 ` [PATCH 5/7] drm/i915: Remove DRIVER_MODESET checks from gem code Daniel Vetter
@ 2015-02-27  1:12   ` Rodrigo Vivi
  0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2015-02-27  1:12 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Daniel Vetter, Intel Graphics Development

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Mon, Feb 23, 2015 at 3:03 AM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Hooray!
>
> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 14 --------------
>  1 file changed, 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index f28f0dea6c96..4e05f57b9c54 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4606,10 +4606,6 @@ i915_gem_suspend(struct drm_device *dev)
>
>         i915_gem_retire_requests(dev);
>
> -       /* Under UMS, be paranoid and evict. */
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET))
> -               i915_gem_evict_everything(dev);
> -
>         i915_gem_stop_ringbuffers(dev);
>         mutex_unlock(&dev->struct_mutex);
>
> @@ -4973,18 +4969,8 @@ i915_gem_load(struct drm_device *dev)
>                           i915_gem_idle_work_handler);
>         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
>
> -       /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
> -               I915_WRITE(MI_ARB_STATE,
> -                          _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
> -       }
> -
>         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
>
> -       /* Old X drivers will take 0-2 for front, back, depth buffers */
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET))
> -               dev_priv->fence_reg_start = 3;
> -
>         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
>                 dev_priv->num_fence_regs = 32;
>         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 6/7] drm/i915: Remove regfile code&data for UMS suspend/resume
  2015-02-23 11:03 ` [PATCH 6/7] drm/i915: Remove regfile code&data for UMS suspend/resume Daniel Vetter
@ 2015-02-27  1:16   ` Rodrigo Vivi
  0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2015-02-27  1:16 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Daniel Vetter, Intel Graphics Development

On Mon, Feb 23, 2015 at 3:03 AM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Lots of lines to remove!

Great clean up! :)

>
> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h     | 133 ---------
>  drivers/gpu/drm/i915/i915_suspend.c | 215 +-------------
>  drivers/gpu/drm/i915/i915_ums.c     | 552 ------------------------------------
>  3 files changed, 2 insertions(+), 898 deletions(-)
>  delete mode 100644 drivers/gpu/drm/i915/i915_ums.c
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3f210aa7652e..e4a988ef7f16 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -889,150 +889,21 @@ struct intel_gmbus {
>  };
>
>  struct i915_suspend_saved_registers {
> -       u8 saveLBB;
> -       u32 saveDSPACNTR;
> -       u32 saveDSPBCNTR;
>         u32 saveDSPARB;
> -       u32 savePIPEACONF;
> -       u32 savePIPEBCONF;
> -       u32 savePIPEASRC;
> -       u32 savePIPEBSRC;
> -       u32 saveFPA0;
> -       u32 saveFPA1;
> -       u32 saveDPLL_A;
> -       u32 saveDPLL_A_MD;
> -       u32 saveHTOTAL_A;
> -       u32 saveHBLANK_A;
> -       u32 saveHSYNC_A;
> -       u32 saveVTOTAL_A;
> -       u32 saveVBLANK_A;
> -       u32 saveVSYNC_A;
> -       u32 saveBCLRPAT_A;
> -       u32 saveTRANSACONF;
> -       u32 saveTRANS_HTOTAL_A;
> -       u32 saveTRANS_HBLANK_A;
> -       u32 saveTRANS_HSYNC_A;
> -       u32 saveTRANS_VTOTAL_A;
> -       u32 saveTRANS_VBLANK_A;
> -       u32 saveTRANS_VSYNC_A;
> -       u32 savePIPEASTAT;
> -       u32 saveDSPASTRIDE;
> -       u32 saveDSPASIZE;
> -       u32 saveDSPAPOS;
> -       u32 saveDSPAADDR;
> -       u32 saveDSPASURF;
> -       u32 saveDSPATILEOFF;
> -       u32 savePFIT_PGM_RATIOS;
> -       u32 saveBLC_HIST_CTL;
> -       u32 saveBLC_PWM_CTL;
> -       u32 saveBLC_PWM_CTL2;
> -       u32 saveBLC_CPU_PWM_CTL;
> -       u32 saveBLC_CPU_PWM_CTL2;
> -       u32 saveFPB0;
> -       u32 saveFPB1;
> -       u32 saveDPLL_B;
> -       u32 saveDPLL_B_MD;
> -       u32 saveHTOTAL_B;
> -       u32 saveHBLANK_B;
> -       u32 saveHSYNC_B;
> -       u32 saveVTOTAL_B;
> -       u32 saveVBLANK_B;
> -       u32 saveVSYNC_B;
> -       u32 saveBCLRPAT_B;
> -       u32 saveTRANSBCONF;
> -       u32 saveTRANS_HTOTAL_B;
> -       u32 saveTRANS_HBLANK_B;
> -       u32 saveTRANS_HSYNC_B;
> -       u32 saveTRANS_VTOTAL_B;
> -       u32 saveTRANS_VBLANK_B;
> -       u32 saveTRANS_VSYNC_B;
> -       u32 savePIPEBSTAT;
> -       u32 saveDSPBSTRIDE;
> -       u32 saveDSPBSIZE;
> -       u32 saveDSPBPOS;
> -       u32 saveDSPBADDR;
> -       u32 saveDSPBSURF;
> -       u32 saveDSPBTILEOFF;
> -       u32 saveVGA0;
> -       u32 saveVGA1;
> -       u32 saveVGA_PD;
> -       u32 saveVGACNTRL;
> -       u32 saveADPA;
>         u32 saveLVDS;
>         u32 savePP_ON_DELAYS;
>         u32 savePP_OFF_DELAYS;
> -       u32 saveDVOA;
> -       u32 saveDVOB;
> -       u32 saveDVOC;
>         u32 savePP_ON;
>         u32 savePP_OFF;
>         u32 savePP_CONTROL;
>         u32 savePP_DIVISOR;
> -       u32 savePFIT_CONTROL;
> -       u32 save_palette_a[256];
> -       u32 save_palette_b[256];
>         u32 saveFBC_CONTROL;
> -       u32 saveIER;
> -       u32 saveIIR;
> -       u32 saveIMR;
> -       u32 saveDEIER;
> -       u32 saveDEIMR;
> -       u32 saveGTIER;
> -       u32 saveGTIMR;
> -       u32 saveFDI_RXA_IMR;
> -       u32 saveFDI_RXB_IMR;
>         u32 saveCACHE_MODE_0;
>         u32 saveMI_ARB_STATE;
>         u32 saveSWF0[16];
>         u32 saveSWF1[16];
>         u32 saveSWF2[3];
> -       u8 saveMSR;
> -       u8 saveSR[8];
> -       u8 saveGR[25];
> -       u8 saveAR_INDEX;
> -       u8 saveAR[21];
> -       u8 saveDACMASK;
> -       u8 saveCR[37];
>         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
> -       u32 saveCURACNTR;
> -       u32 saveCURAPOS;
> -       u32 saveCURABASE;
> -       u32 saveCURBCNTR;
> -       u32 saveCURBPOS;
> -       u32 saveCURBBASE;
> -       u32 saveCURSIZE;
> -       u32 saveDP_B;
> -       u32 saveDP_C;
> -       u32 saveDP_D;
> -       u32 savePIPEA_GMCH_DATA_M;
> -       u32 savePIPEB_GMCH_DATA_M;
> -       u32 savePIPEA_GMCH_DATA_N;
> -       u32 savePIPEB_GMCH_DATA_N;
> -       u32 savePIPEA_DP_LINK_M;
> -       u32 savePIPEB_DP_LINK_M;
> -       u32 savePIPEA_DP_LINK_N;
> -       u32 savePIPEB_DP_LINK_N;
> -       u32 saveFDI_RXA_CTL;
> -       u32 saveFDI_TXA_CTL;
> -       u32 saveFDI_RXB_CTL;
> -       u32 saveFDI_TXB_CTL;
> -       u32 savePFA_CTL_1;
> -       u32 savePFB_CTL_1;
> -       u32 savePFA_WIN_SZ;
> -       u32 savePFB_WIN_SZ;
> -       u32 savePFA_WIN_POS;
> -       u32 savePFB_WIN_POS;
> -       u32 savePCH_DREF_CONTROL;
> -       u32 saveDISP_ARB_CTL;
> -       u32 savePIPEA_DATA_M1;
> -       u32 savePIPEA_DATA_N1;
> -       u32 savePIPEA_LINK_M1;
> -       u32 savePIPEA_LINK_N1;
> -       u32 savePIPEB_DATA_M1;
> -       u32 savePIPEB_DATA_N1;
> -       u32 savePIPEB_LINK_M1;
> -       u32 savePIPEB_LINK_N1;
> -       u32 saveMCHBAR_RENDER_STANDBY;
>         u32 savePCH_PORT_HOTPLUG;
>         u16 saveGCDGMBUS;
>  };

I didn't check reg by reg, but I believe on your gcc ;)

so Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> @@ -3124,10 +2995,6 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
>  extern int i915_save_state(struct drm_device *dev);
>  extern int i915_restore_state(struct drm_device *dev);
>
> -/* i915_ums.c */
> -void i915_save_display_reg(struct drm_device *dev);
> -void i915_restore_display_reg(struct drm_device *dev);
> -
>  /* i915_sysfs.c */
>  void i915_setup_sysfs(struct drm_device *dev_priv);
>  void i915_teardown_sysfs(struct drm_device *dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 9f19ed38cdc3..cf67f82f7b7f 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -29,166 +29,6 @@
>  #include "intel_drv.h"
>  #include "i915_reg.h"
>
> -static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
> -{
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -
> -       I915_WRITE8(index_port, reg);
> -       return I915_READ8(data_port);
> -}
> -
> -static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
> -{
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -
> -       I915_READ8(st01);
> -       I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
> -       return I915_READ8(VGA_AR_DATA_READ);
> -}
> -
> -static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
> -{
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -
> -       I915_READ8(st01);
> -       I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
> -       I915_WRITE8(VGA_AR_DATA_WRITE, val);
> -}
> -
> -static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
> -{
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -
> -       I915_WRITE8(index_port, reg);
> -       I915_WRITE8(data_port, val);
> -}
> -
> -static void i915_save_vga(struct drm_device *dev)
> -{
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -       int i;
> -       u16 cr_index, cr_data, st01;
> -
> -       /* VGA state */
> -       dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
> -       dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
> -       dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
> -       dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
> -
> -       /* VGA color palette registers */
> -       dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
> -
> -       /* MSR bits */
> -       dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
> -       if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
> -               cr_index = VGA_CR_INDEX_CGA;
> -               cr_data = VGA_CR_DATA_CGA;
> -               st01 = VGA_ST01_CGA;
> -       } else {
> -               cr_index = VGA_CR_INDEX_MDA;
> -               cr_data = VGA_CR_DATA_MDA;
> -               st01 = VGA_ST01_MDA;
> -       }
> -
> -       /* CRT controller regs */
> -       i915_write_indexed(dev, cr_index, cr_data, 0x11,
> -                          i915_read_indexed(dev, cr_index, cr_data, 0x11) &
> -                          (~0x80));
> -       for (i = 0; i <= 0x24; i++)
> -               dev_priv->regfile.saveCR[i] =
> -                       i915_read_indexed(dev, cr_index, cr_data, i);
> -       /* Make sure we don't turn off CR group 0 writes */
> -       dev_priv->regfile.saveCR[0x11] &= ~0x80;
> -
> -       /* Attribute controller registers */
> -       I915_READ8(st01);
> -       dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
> -       for (i = 0; i <= 0x14; i++)
> -               dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
> -       I915_READ8(st01);
> -       I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
> -       I915_READ8(st01);
> -
> -       /* Graphics controller registers */
> -       for (i = 0; i < 9; i++)
> -               dev_priv->regfile.saveGR[i] =
> -                       i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
> -
> -       dev_priv->regfile.saveGR[0x10] =
> -               i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
> -       dev_priv->regfile.saveGR[0x11] =
> -               i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
> -       dev_priv->regfile.saveGR[0x18] =
> -               i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
> -
> -       /* Sequencer registers */
> -       for (i = 0; i < 8; i++)
> -               dev_priv->regfile.saveSR[i] =
> -                       i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
> -}
> -
> -static void i915_restore_vga(struct drm_device *dev)
> -{
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -       int i;
> -       u16 cr_index, cr_data, st01;
> -
> -       /* VGA state */
> -       I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
> -
> -       I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
> -       I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
> -       I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
> -       POSTING_READ(VGA_PD);
> -       udelay(150);
> -
> -       /* MSR bits */
> -       I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
> -       if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
> -               cr_index = VGA_CR_INDEX_CGA;
> -               cr_data = VGA_CR_DATA_CGA;
> -               st01 = VGA_ST01_CGA;
> -       } else {
> -               cr_index = VGA_CR_INDEX_MDA;
> -               cr_data = VGA_CR_DATA_MDA;
> -               st01 = VGA_ST01_MDA;
> -       }
> -
> -       /* Sequencer registers, don't write SR07 */
> -       for (i = 0; i < 7; i++)
> -               i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
> -                                  dev_priv->regfile.saveSR[i]);
> -
> -       /* CRT controller regs */
> -       /* Enable CR group 0 writes */
> -       i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
> -       for (i = 0; i <= 0x24; i++)
> -               i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
> -
> -       /* Graphics controller regs */
> -       for (i = 0; i < 9; i++)
> -               i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
> -                                  dev_priv->regfile.saveGR[i]);
> -
> -       i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
> -                          dev_priv->regfile.saveGR[0x10]);
> -       i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
> -                          dev_priv->regfile.saveGR[0x11]);
> -       i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
> -                          dev_priv->regfile.saveGR[0x18]);
> -
> -       /* Attribute controller registers */
> -       I915_READ8(st01); /* switch back to index mode */
> -       for (i = 0; i <= 0x14; i++)
> -               i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
> -       I915_READ8(st01); /* switch back to index mode */
> -       I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
> -       I915_READ8(st01);
> -
> -       /* VGA color palette registers */
> -       I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
> -}
> -
>  static void i915_save_display(struct drm_device *dev)
>  {
>         struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -197,11 +37,6 @@ static void i915_save_display(struct drm_device *dev)
>         if (INTEL_INFO(dev)->gen <= 4)
>                 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
>
> -       /* This is only meaningful in non-KMS mode */
> -       /* Don't regfile.save them in KMS mode */
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET))
> -               i915_save_display_reg(dev);
> -
>         /* LVDS state */
>         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
>                 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
> @@ -224,9 +59,6 @@ static void i915_save_display(struct drm_device *dev)
>         /* save FBC interval */
>         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
>                 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
> -
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET))
> -               i915_save_vga(dev);
>  }
>
>  static void i915_restore_display(struct drm_device *dev)
> @@ -238,11 +70,7 @@ static void i915_restore_display(struct drm_device *dev)
>         if (INTEL_INFO(dev)->gen <= 4)
>                 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
>
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET))
> -               i915_restore_display_reg(dev);
> -
> -       if (drm_core_check_feature(dev, DRIVER_MODESET))
> -               mask = ~LVDS_PORT_EN;
> +       mask = ~LVDS_PORT_EN;
>
>         /* LVDS state */
>         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> @@ -270,10 +98,7 @@ static void i915_restore_display(struct drm_device *dev)
>         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
>                 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
>
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET))
> -               i915_restore_vga(dev);
> -       else
> -               i915_redisable_vga(dev);
> +       i915_redisable_vga(dev);
>  }
>
>  int i915_save_state(struct drm_device *dev)
> @@ -285,24 +110,6 @@ int i915_save_state(struct drm_device *dev)
>
>         i915_save_display(dev);
>
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
> -               /* Interrupt state */
> -               if (HAS_PCH_SPLIT(dev)) {
> -                       dev_priv->regfile.saveDEIER = I915_READ(DEIER);
> -                       dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
> -                       dev_priv->regfile.saveGTIER = I915_READ(GTIER);
> -                       dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
> -                       dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
> -                       dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
> -                       dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
> -                               I915_READ(RSTDBYCTL);
> -                       dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
> -               } else {
> -                       dev_priv->regfile.saveIER = I915_READ(IER);
> -                       dev_priv->regfile.saveIMR = I915_READ(IMR);
> -               }
> -       }
> -
>         if (IS_GEN4(dev))
>                 pci_read_config_word(dev->pdev, GCDGMBUS,
>                                      &dev_priv->regfile.saveGCDGMBUS);
> @@ -341,24 +148,6 @@ int i915_restore_state(struct drm_device *dev)
>                                       dev_priv->regfile.saveGCDGMBUS);
>         i915_restore_display(dev);
>
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
> -               /* Interrupt state */
> -               if (HAS_PCH_SPLIT(dev)) {
> -                       I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
> -                       I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
> -                       I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
> -                       I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
> -                       I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
> -                       I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
> -                       I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
> -                       I915_WRITE(RSTDBYCTL,
> -                                  dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
> -               } else {
> -                       I915_WRITE(IER, dev_priv->regfile.saveIER);
> -                       I915_WRITE(IMR, dev_priv->regfile.saveIMR);
> -               }
> -       }
> -
>         /* Cache mode state */
>         if (INTEL_INFO(dev)->gen < 7)
>                 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
> diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
> deleted file mode 100644
> index d10fe3e9c49f..000000000000
> --- a/drivers/gpu/drm/i915/i915_ums.c
> +++ /dev/null
> @@ -1,552 +0,0 @@
> -/*
> - *
> - * Copyright 2008 (c) Intel Corporation
> - *   Jesse Barnes <jbarnes@virtuousgeek.org>
> - * Copyright 2013 (c) Intel Corporation
> - *   Daniel Vetter <daniel.vetter@ffwll.ch>
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the
> - * "Software"), to deal in the Software without restriction, including
> - * without limitation the rights to use, copy, modify, merge, publish,
> - * distribute, sub license, and/or sell copies of the Software, and to
> - * permit persons to whom the Software is furnished to do so, subject to
> - * the following conditions:
> - *
> - * The above copyright notice and this permission notice (including the
> - * next paragraph) shall be included in all copies or substantial portions
> - * of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
> - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
> - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
> - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
> - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> - */
> -
> -#include <drm/drmP.h>
> -#include <drm/i915_drm.h>
> -#include "intel_drv.h"
> -#include "i915_reg.h"
> -
> -static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
> -{
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -       u32     dpll_reg;
> -
> -       /* On IVB, 3rd pipe shares PLL with another one */
> -       if (pipe > 1)
> -               return false;
> -
> -       if (HAS_PCH_SPLIT(dev))
> -               dpll_reg = PCH_DPLL(pipe);
> -       else
> -               dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
> -
> -       return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
> -}
> -
> -static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
> -{
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -       unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
> -       u32 *array;
> -       int i;
> -
> -       if (!i915_pipe_enabled(dev, pipe))
> -               return;
> -
> -       if (HAS_PCH_SPLIT(dev))
> -               reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
> -
> -       if (pipe == PIPE_A)
> -               array = dev_priv->regfile.save_palette_a;
> -       else
> -               array = dev_priv->regfile.save_palette_b;
> -
> -       for (i = 0; i < 256; i++)
> -               array[i] = I915_READ(reg + (i << 2));
> -}
> -
> -static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
> -{
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -       unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
> -       u32 *array;
> -       int i;
> -
> -       if (!i915_pipe_enabled(dev, pipe))
> -               return;
> -
> -       if (HAS_PCH_SPLIT(dev))
> -               reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
> -
> -       if (pipe == PIPE_A)
> -               array = dev_priv->regfile.save_palette_a;
> -       else
> -               array = dev_priv->regfile.save_palette_b;
> -
> -       for (i = 0; i < 256; i++)
> -               I915_WRITE(reg + (i << 2), array[i]);
> -}
> -
> -void i915_save_display_reg(struct drm_device *dev)
> -{
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -       int i;
> -
> -       /* Cursor state */
> -       dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
> -       dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
> -       dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
> -       dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
> -       dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
> -       dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
> -       if (IS_GEN2(dev))
> -               dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
> -
> -       if (HAS_PCH_SPLIT(dev)) {
> -               dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
> -               dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
> -       }
> -
> -       /* Pipe & plane A info */
> -       dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
> -       dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
> -       if (HAS_PCH_SPLIT(dev)) {
> -               dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
> -               dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
> -               dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
> -       } else {
> -               dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
> -               dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
> -               dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
> -       }
> -       if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
> -               dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
> -       dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
> -       dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
> -       dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
> -       dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
> -       dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
> -       dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
> -       if (!HAS_PCH_SPLIT(dev))
> -               dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
> -
> -       if (HAS_PCH_SPLIT(dev)) {
> -               dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
> -               dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
> -               dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
> -               dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
> -
> -               dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
> -               dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
> -
> -               dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
> -               dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
> -               dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
> -
> -               dev_priv->regfile.saveTRANSACONF = I915_READ(_PCH_TRANSACONF);
> -               dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_PCH_TRANS_HTOTAL_A);
> -               dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_PCH_TRANS_HBLANK_A);
> -               dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_PCH_TRANS_HSYNC_A);
> -               dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_PCH_TRANS_VTOTAL_A);
> -               dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_PCH_TRANS_VBLANK_A);
> -               dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_PCH_TRANS_VSYNC_A);
> -       }
> -
> -       dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
> -       dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
> -       dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
> -       dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
> -       dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
> -       if (INTEL_INFO(dev)->gen >= 4) {
> -               dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
> -               dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
> -       }
> -       i915_save_palette(dev, PIPE_A);
> -       dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
> -
> -       /* Pipe & plane B info */
> -       dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
> -       dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
> -       if (HAS_PCH_SPLIT(dev)) {
> -               dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
> -               dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
> -               dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
> -       } else {
> -               dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
> -               dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
> -               dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
> -       }
> -       if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
> -               dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
> -       dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
> -       dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
> -       dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
> -       dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
> -       dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
> -       dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
> -       if (!HAS_PCH_SPLIT(dev))
> -               dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
> -
> -       if (HAS_PCH_SPLIT(dev)) {
> -               dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
> -               dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
> -               dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
> -               dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
> -
> -               dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
> -               dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
> -
> -               dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
> -               dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
> -               dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
> -
> -               dev_priv->regfile.saveTRANSBCONF = I915_READ(_PCH_TRANSBCONF);
> -               dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_PCH_TRANS_HTOTAL_B);
> -               dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_PCH_TRANS_HBLANK_B);
> -               dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_PCH_TRANS_HSYNC_B);
> -               dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_PCH_TRANS_VTOTAL_B);
> -               dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_PCH_TRANS_VBLANK_B);
> -               dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_PCH_TRANS_VSYNC_B);
> -       }
> -
> -       dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
> -       dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
> -       dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
> -       dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
> -       dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
> -       if (INTEL_INFO(dev)->gen >= 4) {
> -               dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
> -               dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
> -       }
> -       i915_save_palette(dev, PIPE_B);
> -       dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
> -
> -       /* Fences */
> -       switch (INTEL_INFO(dev)->gen) {
> -       case 7:
> -       case 6:
> -               for (i = 0; i < 16; i++)
> -                       dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
> -               break;
> -       case 5:
> -       case 4:
> -               for (i = 0; i < 16; i++)
> -                       dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
> -               break;
> -       case 3:
> -               if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> -                       for (i = 0; i < 8; i++)
> -                               dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
> -       case 2:
> -               for (i = 0; i < 8; i++)
> -                       dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
> -               break;
> -       }
> -
> -       /* CRT state */
> -       if (HAS_PCH_SPLIT(dev))
> -               dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
> -       else
> -               dev_priv->regfile.saveADPA = I915_READ(ADPA);
> -
> -       /* Display Port state */
> -       if (SUPPORTS_INTEGRATED_DP(dev)) {
> -               dev_priv->regfile.saveDP_B = I915_READ(DP_B);
> -               dev_priv->regfile.saveDP_C = I915_READ(DP_C);
> -               dev_priv->regfile.saveDP_D = I915_READ(DP_D);
> -               dev_priv->regfile.savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_DATA_M_G4X);
> -               dev_priv->regfile.savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_DATA_M_G4X);
> -               dev_priv->regfile.savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_DATA_N_G4X);
> -               dev_priv->regfile.savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_DATA_N_G4X);
> -               dev_priv->regfile.savePIPEA_DP_LINK_M = I915_READ(_PIPEA_LINK_M_G4X);
> -               dev_priv->regfile.savePIPEB_DP_LINK_M = I915_READ(_PIPEB_LINK_M_G4X);
> -               dev_priv->regfile.savePIPEA_DP_LINK_N = I915_READ(_PIPEA_LINK_N_G4X);
> -               dev_priv->regfile.savePIPEB_DP_LINK_N = I915_READ(_PIPEB_LINK_N_G4X);
> -       }
> -       /* FIXME: regfile.save TV & SDVO state */
> -
> -       /* Panel fitter */
> -       if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) {
> -               dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
> -               dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
> -       }
> -
> -       /* Backlight */
> -       if (INTEL_INFO(dev)->gen <= 4)
> -               pci_read_config_byte(dev->pdev, PCI_LBPC,
> -                                    &dev_priv->regfile.saveLBB);
> -
> -       if (HAS_PCH_SPLIT(dev)) {
> -               dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
> -               dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
> -               dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
> -               dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
> -       } else {
> -               dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
> -               if (INTEL_INFO(dev)->gen >= 4)
> -                       dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
> -               dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
> -       }
> -
> -       return;
> -}
> -
> -void i915_restore_display_reg(struct drm_device *dev)
> -{
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -       int dpll_a_reg, fpa0_reg, fpa1_reg;
> -       int dpll_b_reg, fpb0_reg, fpb1_reg;
> -       int i;
> -
> -       /* Backlight */
> -       if (INTEL_INFO(dev)->gen <= 4)
> -               pci_write_config_byte(dev->pdev, PCI_LBPC,
> -                                     dev_priv->regfile.saveLBB);
> -
> -       if (HAS_PCH_SPLIT(dev)) {
> -               I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
> -               I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
> -               /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
> -                * otherwise we get blank eDP screen after S3 on some machines
> -                */
> -               I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
> -               I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
> -       } else {
> -               if (INTEL_INFO(dev)->gen >= 4)
> -                       I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
> -               I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
> -               I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
> -       }
> -
> -       /* Panel fitter */
> -       if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) {
> -               I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
> -               I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
> -       }
> -
> -       /* Display port ratios (must be done before clock is set) */
> -       if (SUPPORTS_INTEGRATED_DP(dev)) {
> -               I915_WRITE(_PIPEA_DATA_M_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
> -               I915_WRITE(_PIPEB_DATA_M_G4X, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
> -               I915_WRITE(_PIPEA_DATA_N_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
> -               I915_WRITE(_PIPEB_DATA_N_G4X, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
> -               I915_WRITE(_PIPEA_LINK_M_G4X, dev_priv->regfile.savePIPEA_DP_LINK_M);
> -               I915_WRITE(_PIPEB_LINK_M_G4X, dev_priv->regfile.savePIPEB_DP_LINK_M);
> -               I915_WRITE(_PIPEA_LINK_N_G4X, dev_priv->regfile.savePIPEA_DP_LINK_N);
> -               I915_WRITE(_PIPEB_LINK_N_G4X, dev_priv->regfile.savePIPEB_DP_LINK_N);
> -       }
> -
> -       /* Fences */
> -       switch (INTEL_INFO(dev)->gen) {
> -       case 7:
> -       case 6:
> -               for (i = 0; i < 16; i++)
> -                       I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
> -               break;
> -       case 5:
> -       case 4:
> -               for (i = 0; i < 16; i++)
> -                       I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
> -               break;
> -       case 3:
> -       case 2:
> -               if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> -                       for (i = 0; i < 8; i++)
> -                               I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
> -               for (i = 0; i < 8; i++)
> -                       I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
> -               break;
> -       }
> -
> -
> -       if (HAS_PCH_SPLIT(dev)) {
> -               dpll_a_reg = _PCH_DPLL_A;
> -               dpll_b_reg = _PCH_DPLL_B;
> -               fpa0_reg = _PCH_FPA0;
> -               fpb0_reg = _PCH_FPB0;
> -               fpa1_reg = _PCH_FPA1;
> -               fpb1_reg = _PCH_FPB1;
> -       } else {
> -               dpll_a_reg = _DPLL_A;
> -               dpll_b_reg = _DPLL_B;
> -               fpa0_reg = _FPA0;
> -               fpb0_reg = _FPB0;
> -               fpa1_reg = _FPA1;
> -               fpb1_reg = _FPB1;
> -       }
> -
> -       if (HAS_PCH_SPLIT(dev)) {
> -               I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
> -               I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
> -       }
> -
> -       /* Pipe & plane A info */
> -       /* Prime the clock */
> -       if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
> -               I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
> -                          ~DPLL_VCO_ENABLE);
> -               POSTING_READ(dpll_a_reg);
> -               udelay(150);
> -       }
> -       I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
> -       I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
> -       /* Actually enable it */
> -       I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
> -       POSTING_READ(dpll_a_reg);
> -       udelay(150);
> -       if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
> -               I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
> -               POSTING_READ(_DPLL_A_MD);
> -       }
> -       udelay(150);
> -
> -       /* Restore mode */
> -       I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
> -       I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
> -       I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
> -       I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
> -       I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
> -       I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
> -       if (!HAS_PCH_SPLIT(dev))
> -               I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
> -
> -       if (HAS_PCH_SPLIT(dev)) {
> -               I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
> -               I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
> -               I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
> -               I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
> -
> -               I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
> -               I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
> -
> -               I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
> -               I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
> -               I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
> -
> -               I915_WRITE(_PCH_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
> -               I915_WRITE(_PCH_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
> -               I915_WRITE(_PCH_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
> -               I915_WRITE(_PCH_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
> -               I915_WRITE(_PCH_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
> -               I915_WRITE(_PCH_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
> -               I915_WRITE(_PCH_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
> -       }
> -
> -       /* Restore plane info */
> -       I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
> -       I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
> -       I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
> -       I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
> -       I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
> -       if (INTEL_INFO(dev)->gen >= 4) {
> -               I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
> -               I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
> -       }
> -
> -       I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
> -
> -       i915_restore_palette(dev, PIPE_A);
> -       /* Enable the plane */
> -       I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
> -       I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
> -
> -       /* Pipe & plane B info */
> -       if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
> -               I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
> -                          ~DPLL_VCO_ENABLE);
> -               POSTING_READ(dpll_b_reg);
> -               udelay(150);
> -       }
> -       I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
> -       I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
> -       /* Actually enable it */
> -       I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
> -       POSTING_READ(dpll_b_reg);
> -       udelay(150);
> -       if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
> -               I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
> -               POSTING_READ(_DPLL_B_MD);
> -       }
> -       udelay(150);
> -
> -       /* Restore mode */
> -       I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
> -       I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
> -       I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
> -       I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
> -       I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
> -       I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
> -       if (!HAS_PCH_SPLIT(dev))
> -               I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
> -
> -       if (HAS_PCH_SPLIT(dev)) {
> -               I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
> -               I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
> -               I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
> -               I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
> -
> -               I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
> -               I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
> -
> -               I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
> -               I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
> -               I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
> -
> -               I915_WRITE(_PCH_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
> -               I915_WRITE(_PCH_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
> -               I915_WRITE(_PCH_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
> -               I915_WRITE(_PCH_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
> -               I915_WRITE(_PCH_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
> -               I915_WRITE(_PCH_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
> -               I915_WRITE(_PCH_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
> -       }
> -
> -       /* Restore plane info */
> -       I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
> -       I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
> -       I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
> -       I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
> -       I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
> -       if (INTEL_INFO(dev)->gen >= 4) {
> -               I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
> -               I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
> -       }
> -
> -       I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
> -
> -       i915_restore_palette(dev, PIPE_B);
> -       /* Enable the plane */
> -       I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
> -       I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
> -
> -       /* Cursor state */
> -       I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
> -       I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
> -       I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
> -       I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
> -       I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
> -       I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
> -       if (IS_GEN2(dev))
> -               I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
> -
> -       /* CRT state */
> -       if (HAS_PCH_SPLIT(dev))
> -               I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
> -       else
> -               I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
> -
> -       /* Display Port state */
> -       if (SUPPORTS_INTEGRATED_DP(dev)) {
> -               I915_WRITE(DP_B, dev_priv->regfile.saveDP_B);
> -               I915_WRITE(DP_C, dev_priv->regfile.saveDP_C);
> -               I915_WRITE(DP_D, dev_priv->regfile.saveDP_D);
> -       }
> -       /* FIXME: restore TV & SDVO state */
> -
> -       return;
> -}
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 7/7] drm/i915: Remove DRIVER_MODESET checks from modeset code
  2015-02-23 11:03 ` [PATCH 7/7] drm/i915: Remove DRIVER_MODESET checks from modeset code Daniel Vetter
  2015-02-23 17:13   ` shuang.he
@ 2015-02-27  1:17   ` Rodrigo Vivi
  2015-02-27 14:07     ` Daniel Vetter
  1 sibling, 1 reply; 19+ messages in thread
From: Rodrigo Vivi @ 2015-02-27  1:17 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Daniel Vetter, Intel Graphics Development

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Mon, Feb 23, 2015 at 3:03 AM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Mostly just checks in i915-private modeset ioctls.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c  | 3 ---
>  drivers/gpu/drm/i915/intel_opregion.c | 6 ++----
>  drivers/gpu/drm/i915/intel_overlay.c  | 2 --
>  drivers/gpu/drm/i915/intel_sprite.c   | 6 ------
>  4 files changed, 2 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3b0fe9f1f3c9..253a201e20dd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12372,9 +12372,6 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
>         struct drm_crtc *drmmode_crtc;
>         struct intel_crtc *crtc;
>
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET))
> -               return -ENODEV;
> -
>         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
>
>         if (!drmmode_crtc) {
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
> index d8de1d5140a7..71e87abdcae7 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -744,10 +744,8 @@ void intel_opregion_init(struct drm_device *dev)
>                 return;
>
>         if (opregion->acpi) {
> -               if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> -                       intel_didl_outputs(dev);
> -                       intel_setup_cadls(dev);
> -               }
> +               intel_didl_outputs(dev);
> +               intel_setup_cadls(dev);
>
>                 /* Notify BIOS we are ready to handle ACPI video ext notifs.
>                  * Right now, all the events are handled by the ACPI video module.
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index f93dfc174495..823d1d97a000 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -1065,7 +1065,6 @@ int intel_overlay_put_image(struct drm_device *dev, void *data,
>         struct put_image_params *params;
>         int ret;
>
> -       /* No need to check for DRIVER_MODESET - we don't set it up then. */
>         overlay = dev_priv->overlay;
>         if (!overlay) {
>                 DRM_DEBUG("userspace bug: no overlay\n");
> @@ -1261,7 +1260,6 @@ int intel_overlay_attrs(struct drm_device *dev, void *data,
>         struct overlay_registers __iomem *regs;
>         int ret;
>
> -       /* No need to check for DRIVER_MODESET - we don't set it up then. */
>         overlay = dev_priv->overlay;
>         if (!overlay) {
>                 DRM_DEBUG("userspace bug: no overlay\n");
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index f2d408dd7c15..4f8fa0534954 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1301,9 +1301,6 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
>         struct intel_plane *intel_plane;
>         int ret = 0;
>
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET))
> -               return -ENODEV;
> -
>         /* Make sure we don't try to enable both src & dest simultaneously */
>         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
>                 return -EINVAL;
> @@ -1332,9 +1329,6 @@ int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
>         struct intel_plane *intel_plane;
>         int ret = 0;
>
> -       if (!drm_core_check_feature(dev, DRIVER_MODESET))
> -               return -ENODEV;
> -
>         drm_modeset_lock_all(dev);
>
>         plane = drm_plane_find(dev, get->plane_id);
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 4/7] drm/i915: Remove irq-related FIXME in reset code
  2015-02-27  1:11   ` Rodrigo Vivi
@ 2015-02-27 14:04     ` Daniel Vetter
  2015-02-27 21:54       ` Rodrigo Vivi
  0 siblings, 1 reply; 19+ messages in thread
From: Daniel Vetter @ 2015-02-27 14:04 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: Daniel Vetter, Intel Graphics Development, Daniel Vetter

On Thu, Feb 26, 2015 at 05:11:16PM -0800, Rodrigo Vivi wrote:
> I believe this patch is on the wrong series, right?

It's in here since I've spotted the FIXME while removing ums crap.

> I'm afraid I don't know what was this race neither the two-step reset
> to be able to review this comment remove.
> Please give me some pointers to check that.

Let me explain the history a bit. git blame on the various parts and this
fixme should be able to dig out the details (it's a fun story):

Originally we've had an unconditional drm_irq_install/unistall in the
reset code. Which is not cool since it meant we'd kill all the interrutps
that have been going on, so pageflips, vblank waits, crc checksums, gem
waits all stopped working. This is the bug the FIXME is about.

With fixed most of these issues by no longer disabling/enabling interrupts
driver-wide, but only restoring the interrupt bits on the gt (they get
lost in the reset). That takes care of all the modeset interrupts.

The gem waits have been fixed differently and much earlier with the
2-stage reset code:

- before reset we set a flag RESET_IN_PROGRESS and wake up all waiters.

- after reset we clear that flag by incrementing the reset counter and
  again wake all waiters

Waiters always check this flag and the reset counter every time they are
woken and bail out with -EINTR (to restart the entire ioctl) if that's the
case. That means they'll never miss a reset and so won't be affected by
interrupts suddenly being cleared.

I've simply forgotten to remove the FIXME ;-)

Cheers, Daniel
> 
> 
> On Mon, Feb 23, 2015 at 3:03 AM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > With the two-step reset counter increments which braket the actual
> > reset code and the subsequent wake-up we're guaranteeing that all the
> > lockless waiters _will_ be woken up. And since we unconditionally bail
> > out of waits with -EAGAIN (or -EIO) in that case there is not risk of
> > lost interrupt enabling bits when the lockless wait code races against
> > a gpu reset.
> >
> > Let's remove this FIXME as resolved then.
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c | 6 ------
> >  1 file changed, 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index cc6c51107047..89741e6e2d08 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -878,12 +878,6 @@ int i915_reset(struct drm_device *dev)
> >         }
> >
> >         /*
> > -        * FIXME: This races pretty badly against concurrent holders of
> > -        * ring interrupts. This is possible since we've started to drop
> > -        * dev->struct_mutex in select places when waiting for the gpu.
> > -        */
> > -
> > -       /*
> >          * rps/rc6 re-init is necessary to restore state lost after the
> >          * reset and the re-install of gt irqs. Skip for ironlake per
> >          * previous concerns that it doesn't respond well to some forms
> > --
> > 2.1.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 7/7] drm/i915: Remove DRIVER_MODESET checks from modeset code
  2015-02-27  1:17   ` Rodrigo Vivi
@ 2015-02-27 14:07     ` Daniel Vetter
  0 siblings, 0 replies; 19+ messages in thread
From: Daniel Vetter @ 2015-02-27 14:07 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: Daniel Vetter, Intel Graphics Development, Daniel Vetter

On Thu, Feb 26, 2015 at 05:17:36PM -0800, Rodrigo Vivi wrote:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

All merged to dinq, thanks for your review.
-Daniel

> 
> On Mon, Feb 23, 2015 at 3:03 AM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > Mostly just checks in i915-private modeset ioctls.
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c  | 3 ---
> >  drivers/gpu/drm/i915/intel_opregion.c | 6 ++----
> >  drivers/gpu/drm/i915/intel_overlay.c  | 2 --
> >  drivers/gpu/drm/i915/intel_sprite.c   | 6 ------
> >  4 files changed, 2 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 3b0fe9f1f3c9..253a201e20dd 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -12372,9 +12372,6 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
> >         struct drm_crtc *drmmode_crtc;
> >         struct intel_crtc *crtc;
> >
> > -       if (!drm_core_check_feature(dev, DRIVER_MODESET))
> > -               return -ENODEV;
> > -
> >         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
> >
> >         if (!drmmode_crtc) {
> > diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
> > index d8de1d5140a7..71e87abdcae7 100644
> > --- a/drivers/gpu/drm/i915/intel_opregion.c
> > +++ b/drivers/gpu/drm/i915/intel_opregion.c
> > @@ -744,10 +744,8 @@ void intel_opregion_init(struct drm_device *dev)
> >                 return;
> >
> >         if (opregion->acpi) {
> > -               if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> > -                       intel_didl_outputs(dev);
> > -                       intel_setup_cadls(dev);
> > -               }
> > +               intel_didl_outputs(dev);
> > +               intel_setup_cadls(dev);
> >
> >                 /* Notify BIOS we are ready to handle ACPI video ext notifs.
> >                  * Right now, all the events are handled by the ACPI video module.
> > diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> > index f93dfc174495..823d1d97a000 100644
> > --- a/drivers/gpu/drm/i915/intel_overlay.c
> > +++ b/drivers/gpu/drm/i915/intel_overlay.c
> > @@ -1065,7 +1065,6 @@ int intel_overlay_put_image(struct drm_device *dev, void *data,
> >         struct put_image_params *params;
> >         int ret;
> >
> > -       /* No need to check for DRIVER_MODESET - we don't set it up then. */
> >         overlay = dev_priv->overlay;
> >         if (!overlay) {
> >                 DRM_DEBUG("userspace bug: no overlay\n");
> > @@ -1261,7 +1260,6 @@ int intel_overlay_attrs(struct drm_device *dev, void *data,
> >         struct overlay_registers __iomem *regs;
> >         int ret;
> >
> > -       /* No need to check for DRIVER_MODESET - we don't set it up then. */
> >         overlay = dev_priv->overlay;
> >         if (!overlay) {
> >                 DRM_DEBUG("userspace bug: no overlay\n");
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index f2d408dd7c15..4f8fa0534954 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1301,9 +1301,6 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
> >         struct intel_plane *intel_plane;
> >         int ret = 0;
> >
> > -       if (!drm_core_check_feature(dev, DRIVER_MODESET))
> > -               return -ENODEV;
> > -
> >         /* Make sure we don't try to enable both src & dest simultaneously */
> >         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
> >                 return -EINVAL;
> > @@ -1332,9 +1329,6 @@ int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
> >         struct intel_plane *intel_plane;
> >         int ret = 0;
> >
> > -       if (!drm_core_check_feature(dev, DRIVER_MODESET))
> > -               return -ENODEV;
> > -
> >         drm_modeset_lock_all(dev);
> >
> >         plane = drm_plane_find(dev, get->plane_id);
> > --
> > 2.1.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 4/7] drm/i915: Remove irq-related FIXME in reset code
  2015-02-27 14:04     ` Daniel Vetter
@ 2015-02-27 21:54       ` Rodrigo Vivi
  2015-03-02 15:23         ` Daniel Vetter
  0 siblings, 1 reply; 19+ messages in thread
From: Rodrigo Vivi @ 2015-02-27 21:54 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Daniel Vetter, Intel Graphics Development, Daniel Vetter

cool, thanks for the detailed explanation.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Fri, Feb 27, 2015 at 6:04 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Feb 26, 2015 at 05:11:16PM -0800, Rodrigo Vivi wrote:
>> I believe this patch is on the wrong series, right?
>
> It's in here since I've spotted the FIXME while removing ums crap.
>
>> I'm afraid I don't know what was this race neither the two-step reset
>> to be able to review this comment remove.
>> Please give me some pointers to check that.
>
> Let me explain the history a bit. git blame on the various parts and this
> fixme should be able to dig out the details (it's a fun story):
>
> Originally we've had an unconditional drm_irq_install/unistall in the
> reset code. Which is not cool since it meant we'd kill all the interrutps
> that have been going on, so pageflips, vblank waits, crc checksums, gem
> waits all stopped working. This is the bug the FIXME is about.
>
> With fixed most of these issues by no longer disabling/enabling interrupts
> driver-wide, but only restoring the interrupt bits on the gt (they get
> lost in the reset). That takes care of all the modeset interrupts.
>
> The gem waits have been fixed differently and much earlier with the
> 2-stage reset code:
>
> - before reset we set a flag RESET_IN_PROGRESS and wake up all waiters.
>
> - after reset we clear that flag by incrementing the reset counter and
>   again wake all waiters
>
> Waiters always check this flag and the reset counter every time they are
> woken and bail out with -EINTR (to restart the entire ioctl) if that's the
> case. That means they'll never miss a reset and so won't be affected by
> interrupts suddenly being cleared.
>
> I've simply forgotten to remove the FIXME ;-)
>
> Cheers, Daniel
>>
>>
>> On Mon, Feb 23, 2015 at 3:03 AM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
>> > With the two-step reset counter increments which braket the actual
>> > reset code and the subsequent wake-up we're guaranteeing that all the
>> > lockless waiters _will_ be woken up. And since we unconditionally bail
>> > out of waits with -EAGAIN (or -EIO) in that case there is not risk of
>> > lost interrupt enabling bits when the lockless wait code races against
>> > a gpu reset.
>> >
>> > Let's remove this FIXME as resolved then.
>> >
>> > Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/i915_drv.c | 6 ------
>> >  1 file changed, 6 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> > index cc6c51107047..89741e6e2d08 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.c
>> > +++ b/drivers/gpu/drm/i915/i915_drv.c
>> > @@ -878,12 +878,6 @@ int i915_reset(struct drm_device *dev)
>> >         }
>> >
>> >         /*
>> > -        * FIXME: This races pretty badly against concurrent holders of
>> > -        * ring interrupts. This is possible since we've started to drop
>> > -        * dev->struct_mutex in select places when waiting for the gpu.
>> > -        */
>> > -
>> > -       /*
>> >          * rps/rc6 re-init is necessary to restore state lost after the
>> >          * reset and the re-install of gt irqs. Skip for ironlake per
>> >          * previous concerns that it doesn't respond well to some forms
>> > --
>> > 2.1.4
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>> --
>> Rodrigo Vivi
>> Blog: http://blog.vivi.eng.br
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 4/7] drm/i915: Remove irq-related FIXME in reset code
  2015-02-27 21:54       ` Rodrigo Vivi
@ 2015-03-02 15:23         ` Daniel Vetter
  0 siblings, 0 replies; 19+ messages in thread
From: Daniel Vetter @ 2015-03-02 15:23 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: Daniel Vetter, Intel Graphics Development, Daniel Vetter

On Fri, Feb 27, 2015 at 01:54:02PM -0800, Rodrigo Vivi wrote:
> cool, thanks for the detailed explanation.
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Queued for -next, thanks for the patch.
-Daniel

> 
> On Fri, Feb 27, 2015 at 6:04 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Thu, Feb 26, 2015 at 05:11:16PM -0800, Rodrigo Vivi wrote:
> >> I believe this patch is on the wrong series, right?
> >
> > It's in here since I've spotted the FIXME while removing ums crap.
> >
> >> I'm afraid I don't know what was this race neither the two-step reset
> >> to be able to review this comment remove.
> >> Please give me some pointers to check that.
> >
> > Let me explain the history a bit. git blame on the various parts and this
> > fixme should be able to dig out the details (it's a fun story):
> >
> > Originally we've had an unconditional drm_irq_install/unistall in the
> > reset code. Which is not cool since it meant we'd kill all the interrutps
> > that have been going on, so pageflips, vblank waits, crc checksums, gem
> > waits all stopped working. This is the bug the FIXME is about.
> >
> > With fixed most of these issues by no longer disabling/enabling interrupts
> > driver-wide, but only restoring the interrupt bits on the gt (they get
> > lost in the reset). That takes care of all the modeset interrupts.
> >
> > The gem waits have been fixed differently and much earlier with the
> > 2-stage reset code:
> >
> > - before reset we set a flag RESET_IN_PROGRESS and wake up all waiters.
> >
> > - after reset we clear that flag by incrementing the reset counter and
> >   again wake all waiters
> >
> > Waiters always check this flag and the reset counter every time they are
> > woken and bail out with -EINTR (to restart the entire ioctl) if that's the
> > case. That means they'll never miss a reset and so won't be affected by
> > interrupts suddenly being cleared.
> >
> > I've simply forgotten to remove the FIXME ;-)
> >
> > Cheers, Daniel
> >>
> >>
> >> On Mon, Feb 23, 2015 at 3:03 AM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> >> > With the two-step reset counter increments which braket the actual
> >> > reset code and the subsequent wake-up we're guaranteeing that all the
> >> > lockless waiters _will_ be woken up. And since we unconditionally bail
> >> > out of waits with -EAGAIN (or -EIO) in that case there is not risk of
> >> > lost interrupt enabling bits when the lockless wait code races against
> >> > a gpu reset.
> >> >
> >> > Let's remove this FIXME as resolved then.
> >> >
> >> > Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/i915_drv.c | 6 ------
> >> >  1 file changed, 6 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> >> > index cc6c51107047..89741e6e2d08 100644
> >> > --- a/drivers/gpu/drm/i915/i915_drv.c
> >> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> >> > @@ -878,12 +878,6 @@ int i915_reset(struct drm_device *dev)
> >> >         }
> >> >
> >> >         /*
> >> > -        * FIXME: This races pretty badly against concurrent holders of
> >> > -        * ring interrupts. This is possible since we've started to drop
> >> > -        * dev->struct_mutex in select places when waiting for the gpu.
> >> > -        */
> >> > -
> >> > -       /*
> >> >          * rps/rc6 re-init is necessary to restore state lost after the
> >> >          * reset and the re-install of gt irqs. Skip for ironlake per
> >> >          * previous concerns that it doesn't respond well to some forms
> >> > --
> >> > 2.1.4
> >> >
> >> > _______________________________________________
> >> > Intel-gfx mailing list
> >> > Intel-gfx@lists.freedesktop.org
> >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >>
> >>
> >>
> >> --
> >> Rodrigo Vivi
> >> Blog: http://blog.vivi.eng.br
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 19+ messages in thread

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2015-02-23 11:03 [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code Daniel Vetter
2015-02-23 11:03 ` [PATCH 2/7] drm/i915: Remove DRIVER_MODESET checks from suspend/resume code Daniel Vetter
2015-02-27  1:06   ` Rodrigo Vivi
2015-02-23 11:03 ` [PATCH 3/7] drm/i915: Remove DRIVER_MODESET checks in the gpu reset code Daniel Vetter
2015-02-27  1:06   ` Rodrigo Vivi
2015-02-23 11:03 ` [PATCH 4/7] drm/i915: Remove irq-related FIXME in " Daniel Vetter
2015-02-27  1:11   ` Rodrigo Vivi
2015-02-27 14:04     ` Daniel Vetter
2015-02-27 21:54       ` Rodrigo Vivi
2015-03-02 15:23         ` Daniel Vetter
2015-02-23 11:03 ` [PATCH 5/7] drm/i915: Remove DRIVER_MODESET checks from gem code Daniel Vetter
2015-02-27  1:12   ` Rodrigo Vivi
2015-02-23 11:03 ` [PATCH 6/7] drm/i915: Remove regfile code&data for UMS suspend/resume Daniel Vetter
2015-02-27  1:16   ` Rodrigo Vivi
2015-02-23 11:03 ` [PATCH 7/7] drm/i915: Remove DRIVER_MODESET checks from modeset code Daniel Vetter
2015-02-23 17:13   ` shuang.he
2015-02-27  1:17   ` Rodrigo Vivi
2015-02-27 14:07     ` Daniel Vetter
2015-02-27  1:06 ` [PATCH 1/7] drm/i915: Remove DRIVER_MODESET checks in load/unload/close code Rodrigo Vivi

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