[PATCH 0/2] SSEU detection for CHV

[PATCH 0/2] SSEU detection for CHV

[jeff.mcgee]

From: Jeff McGee <jeff.mcgee@intel.com>

These two patches add detection of available and enabled
slice/subslice/EU on CHV following the implementation recently
merged for SKL. They have been requested to help CHV users
determine their configuration through the debugfs interface.

Jeff McGee (2):
  drm/i915/chv: Determine CHV slice/subslice/EU info
  drm/i915/chv: Add CHV HW status to SSEU status

 drivers/gpu/drm/i915/i915_debugfs.c | 31 ++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_dma.c     | 40 +++++++++++++++++++++++++++++++------
 drivers/gpu/drm/i915/i915_reg.h     | 13 ++++++++++++
 3 files changed, 76 insertions(+), 8 deletions(-)

-- 
2.3.0

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[PATCH 1/2] drm/i915/chv: Determine CHV slice/subslice/EU info

[jeff.mcgee]

From: Jeff McGee <jeff.mcgee@intel.com>

Total EU was already being detected on CHV, so we just add the
additional info parameters. The detection method is changed to
be more robust in the case of subslice fusing - we don't want
to trust the EU fuse bits corresponding to subslices which are
fused-off.

Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 40 ++++++++++++++++++++++++++++++++++------
 drivers/gpu/drm/i915/i915_reg.h |  2 ++
 2 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 053e178..04e5b55e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -608,14 +608,42 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 
 	/* Initialize slice/subslice/EU info */
 	if (IS_CHERRYVIEW(dev)) {
-		u32 fuse, mask_eu;
+		u32 fuse, eu_dis;
 
 		fuse = I915_READ(CHV_FUSE_GT);
-		mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
-				  CHV_FGT_EU_DIS_SS0_R1_MASK |
-				  CHV_FGT_EU_DIS_SS1_R0_MASK |
-				  CHV_FGT_EU_DIS_SS1_R1_MASK);
-		info->eu_total = 16 - hweight32(mask_eu);
+
+		info->slice_total = 1;
+
+		if (!(fuse & CHV_FGT_DISABLE_SS0)) {
+			info->subslice_per_slice++;
+			eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
+					 CHV_FGT_EU_DIS_SS0_R1_MASK);
+			info->eu_total += 8 - hweight32(eu_dis);
+		}
+
+		if (!(fuse & CHV_FGT_DISABLE_SS1)) {
+			info->subslice_per_slice++;
+			eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
+					CHV_FGT_EU_DIS_SS1_R1_MASK);
+			info->eu_total += 8 - hweight32(eu_dis);
+		}
+
+		info->subslice_total = info->subslice_per_slice;
+		/*
+		 * CHV expected to always have a uniform distribution of EU
+		 * across subslices.
+		*/
+		info->eu_per_subslice = info->subslice_total ?
+					info->eu_total / info->subslice_total :
+					0;
+		/*
+		 * CHV supports subslice power gating on devices with more than
+		 * one subslice, and supports EU power gating on devices with
+		 * more than one EU pair per subslice.
+		*/
+		info->has_slice_pg = 0;
+		info->has_subslice_pg = (info->subslice_total > 1) ? 1 : 0;
+		info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0;
 	} else if (IS_SKYLAKE(dev)) {
 		const int s_max = 3, ss_max = 4, eu_max = 8;
 		int s, ss;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..a8b205d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1522,6 +1522,8 @@ enum skl_disp_power_wells {
 
 /* Fuse readout registers for GT */
 #define CHV_FUSE_GT			(VLV_DISPLAY_BASE + 0x2168)
+#define   CHV_FGT_DISABLE_SS0		10
+#define   CHV_FGT_DISABLE_SS1		11
 #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
 #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
 #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
-- 
2.3.0

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[PATCH 2/2] drm/i915/chv: Add CHV HW status to SSEU status

[jeff.mcgee]

From: Jeff McGee <jeff.mcgee@intel.com>

Collect the currently enabled counts of slice, subslice, and
execution units using the power gate control ack message
registers specific to Cherryview.

Slice/subslice/EU info and hardware status can now be
determined for CHV, so allow the debugfs SSEU status dump
to proceed for CHV devices.

Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 31 +++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h     | 11 +++++++++++
 2 files changed, 40 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 94b3984..e42e79a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4362,7 +4362,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
 
-	if (INTEL_INFO(dev)->gen < 9)
+	if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
 		return -ENODEV;
 
 	seq_puts(m, "SSEU Device Info\n");
@@ -4384,7 +4384,34 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
 		   yesno(INTEL_INFO(dev)->has_eu_pg));
 
 	seq_puts(m, "SSEU Device Status\n");
-	if (IS_SKYLAKE(dev)) {
+	if (IS_CHERRYVIEW(dev)) {
+		const int ss_max = 2;
+		int ss;
+		u32 sig1[ss_max], sig2[ss_max];
+
+		sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
+		sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
+		sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
+		sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
+
+		for (ss = 0; ss < ss_max; ss++) {
+			unsigned int eu_cnt;
+
+			if (sig1[ss] & CHV_SS_PG_ENABLE)
+				/* skip disabled subslice */
+				continue;
+
+			s_tot = 1;
+			ss_per++;
+			eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
+				 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
+				 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
+				 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
+			eu_tot += eu_cnt;
+			eu_per = max(eu_per, eu_cnt);
+		}
+		ss_tot = ss_per;
+	} else if (IS_SKYLAKE(dev)) {
 		const int s_max = 3, ss_max = 4;
 		int s, ss;
 		u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a8b205d..659aefc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6227,6 +6227,17 @@ enum skl_disp_power_wells {
 #define   GEN6_RC6			3
 #define   GEN6_RC7			4
 
+#define CHV_POWER_SS0_SIG1		0xa720
+#define CHV_POWER_SS1_SIG1		0xa728
+#define   CHV_SS_PG_ENABLE		(1<<1)
+#define   CHV_EU08_PG_ENABLE		(1<<9)
+#define   CHV_EU19_PG_ENABLE		(1<<17)
+#define   CHV_EU210_PG_ENABLE		(1<<25)
+
+#define CHV_POWER_SS0_SIG2		0xa724
+#define CHV_POWER_SS1_SIG2		0xa72c
+#define   CHV_EU311_PG_ENABLE		(1<<1)
+
 #define GEN9_SLICE0_PGCTL_ACK		0x804c
 #define GEN9_SLICE1_PGCTL_ACK		0x8050
 #define GEN9_SLICE2_PGCTL_ACK		0x8054
-- 
2.3.0

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Re: [PATCH 1/2] drm/i915/chv: Determine CHV slice/subslice/EU info

[Ville Syrjälä]

On Fri, Feb 27, 2015 at 10:22:31AM -0800, jeff.mcgee@intel.com wrote:
> From: Jeff McGee <jeff.mcgee@intel.com>
> 
> Total EU was already being detected on CHV, so we just add the
> additional info parameters. The detection method is changed to
> be more robust in the case of subslice fusing - we don't want
> to trust the EU fuse bits corresponding to subslices which are
> fused-off.
> 
> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 40 ++++++++++++++++++++++++++++++++++------
>  drivers/gpu/drm/i915/i915_reg.h |  2 ++
>  2 files changed, 36 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 053e178..04e5b55e 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -608,14 +608,42 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  
>  	/* Initialize slice/subslice/EU info */
>  	if (IS_CHERRYVIEW(dev)) {
> -		u32 fuse, mask_eu;
> +		u32 fuse, eu_dis;
>  
>  		fuse = I915_READ(CHV_FUSE_GT);
> -		mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
> -				  CHV_FGT_EU_DIS_SS0_R1_MASK |
> -				  CHV_FGT_EU_DIS_SS1_R0_MASK |
> -				  CHV_FGT_EU_DIS_SS1_R1_MASK);
> -		info->eu_total = 16 - hweight32(mask_eu);
> +
> +		info->slice_total = 1;
> +
> +		if (!(fuse & CHV_FGT_DISABLE_SS0)) {
                             ^^^^^^^^^^^^^^^^^^^

That's your shift value. Masking with it probably won't work :P


> +			info->subslice_per_slice++;
> +			eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
> +					 CHV_FGT_EU_DIS_SS0_R1_MASK);
> +			info->eu_total += 8 - hweight32(eu_dis);
> +		}
> +
> +		if (!(fuse & CHV_FGT_DISABLE_SS1)) {

ditto

> +			info->subslice_per_slice++;
> +			eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
> +					CHV_FGT_EU_DIS_SS1_R1_MASK);
> +			info->eu_total += 8 - hweight32(eu_dis);
> +		}
> +
> +		info->subslice_total = info->subslice_per_slice;
> +		/*
> +		 * CHV expected to always have a uniform distribution of EU
> +		 * across subslices.
> +		*/
> +		info->eu_per_subslice = info->subslice_total ?
> +					info->eu_total / info->subslice_total :
> +					0;
> +		/*
> +		 * CHV supports subslice power gating on devices with more than
> +		 * one subslice, and supports EU power gating on devices with
> +		 * more than one EU pair per subslice.
> +		*/
> +		info->has_slice_pg = 0;
> +		info->has_subslice_pg = (info->subslice_total > 1) ? 1 : 0;
> +		info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0;

Nit: use of ?: seems pointless in these.

>  	} else if (IS_SKYLAKE(dev)) {
>  		const int s_max = 3, ss_max = 4, eu_max = 8;
>  		int s, ss;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 55143cb..a8b205d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1522,6 +1522,8 @@ enum skl_disp_power_wells {
>  
>  /* Fuse readout registers for GT */
>  #define CHV_FUSE_GT			(VLV_DISPLAY_BASE + 0x2168)
> +#define   CHV_FGT_DISABLE_SS0		10
> +#define   CHV_FGT_DISABLE_SS1		11
>  #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
>  #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
>  #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
> -- 
> 2.3.0

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 2/2] drm/i915/chv: Add CHV HW status to SSEU status

[Ville Syrjälä]

On Fri, Feb 27, 2015 at 10:22:32AM -0800, jeff.mcgee@intel.com wrote:
> From: Jeff McGee <jeff.mcgee@intel.com>
> 
> Collect the currently enabled counts of slice, subslice, and
> execution units using the power gate control ack message
> registers specific to Cherryview.
> 
> Slice/subslice/EU info and hardware status can now be
> determined for CHV, so allow the debugfs SSEU status dump
> to proceed for CHV devices.
> 
> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 31 +++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h     | 11 +++++++++++
>  2 files changed, 40 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 94b3984..e42e79a 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4362,7 +4362,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
>  
> -	if (INTEL_INFO(dev)->gen < 9)
> +	if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
>  		return -ENODEV;
>  
>  	seq_puts(m, "SSEU Device Info\n");
> @@ -4384,7 +4384,34 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>  		   yesno(INTEL_INFO(dev)->has_eu_pg));
>  
>  	seq_puts(m, "SSEU Device Status\n");
> -	if (IS_SKYLAKE(dev)) {
> +	if (IS_CHERRYVIEW(dev)) {
> +		const int ss_max = 2;
> +		int ss;
> +		u32 sig1[ss_max], sig2[ss_max];
> +
> +		sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
> +		sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
> +		sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
> +		sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
> +
> +		for (ss = 0; ss < ss_max; ss++) {
> +			unsigned int eu_cnt;
> +
> +			if (sig1[ss] & CHV_SS_PG_ENABLE)
> +				/* skip disabled subslice */
> +				continue;
> +
> +			s_tot = 1;
> +			ss_per++;
> +			eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
> +				 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
> +				 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
> +				 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
> +			eu_tot += eu_cnt;
> +			eu_per = max(eu_per, eu_cnt);
> +		}
> +		ss_tot = ss_per;
> +	} else if (IS_SKYLAKE(dev)) {
>  		const int s_max = 3, ss_max = 4;
>  		int s, ss;
>  		u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a8b205d..659aefc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6227,6 +6227,17 @@ enum skl_disp_power_wells {
>  #define   GEN6_RC6			3
>  #define   GEN6_RC7			4
>  
> +#define CHV_POWER_SS0_SIG1		0xa720
> +#define CHV_POWER_SS1_SIG1		0xa728
> +#define   CHV_SS_PG_ENABLE		(1<<1)
> +#define   CHV_EU08_PG_ENABLE		(1<<9)
> +#define   CHV_EU19_PG_ENABLE		(1<<17)
> +#define   CHV_EU210_PG_ENABLE		(1<<25)
> +
> +#define CHV_POWER_SS0_SIG2		0xa724
> +#define CHV_POWER_SS1_SIG2		0xa72c
> +#define   CHV_EU311_PG_ENABLE		(1<<1)
> +
>  #define GEN9_SLICE0_PGCTL_ACK		0x804c
>  #define GEN9_SLICE1_PGCTL_ACK		0x8050
>  #define GEN9_SLICE2_PGCTL_ACK		0x8054
> -- 
> 2.3.0

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v2 1/2] drm/i915/chv: Determine CHV slice/subslice/EU info

[Ville Syrjälä]

On Fri, Feb 27, 2015 at 12:12:28PM -0800, jeff.mcgee@intel.com wrote:
> From: Jeff McGee <jeff.mcgee@intel.com>
> 
> Total EU was already being detected on CHV, so we just add the
> additional info parameters. The detection method is changed to
> be more robust in the case of subslice fusing - we don't want
> to trust the EU fuse bits corresponding to subslices which are
> fused-off.
> 
> v2: Fixed subslice disable bitmasks and removed unnecessary ?
>     operation (Ville)
> 
> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_dma.c | 40 ++++++++++++++++++++++++++++++++++------
>  drivers/gpu/drm/i915/i915_reg.h |  2 ++
>  2 files changed, 36 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 9cbe3f5..4c33068 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -619,14 +619,42 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  
>  	/* Initialize slice/subslice/EU info */
>  	if (IS_CHERRYVIEW(dev)) {
> -		u32 fuse, mask_eu;
> +		u32 fuse, eu_dis;
>  
>  		fuse = I915_READ(CHV_FUSE_GT);
> -		mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
> -				  CHV_FGT_EU_DIS_SS0_R1_MASK |
> -				  CHV_FGT_EU_DIS_SS1_R0_MASK |
> -				  CHV_FGT_EU_DIS_SS1_R1_MASK);
> -		info->eu_total = 16 - hweight32(mask_eu);
> +
> +		info->slice_total = 1;
> +
> +		if (!(fuse & CHV_FGT_DISABLE_SS0)) {
> +			info->subslice_per_slice++;
> +			eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
> +					 CHV_FGT_EU_DIS_SS0_R1_MASK);
> +			info->eu_total += 8 - hweight32(eu_dis);
> +		}
> +
> +		if (!(fuse & CHV_FGT_DISABLE_SS1)) {
> +			info->subslice_per_slice++;
> +			eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
> +					CHV_FGT_EU_DIS_SS1_R1_MASK);
> +			info->eu_total += 8 - hweight32(eu_dis);
> +		}
> +
> +		info->subslice_total = info->subslice_per_slice;
> +		/*
> +		 * CHV expected to always have a uniform distribution of EU
> +		 * across subslices.
> +		*/
> +		info->eu_per_subslice = info->subslice_total ?
> +					info->eu_total / info->subslice_total :
> +					0;
> +		/*
> +		 * CHV supports subslice power gating on devices with more than
> +		 * one subslice, and supports EU power gating on devices with
> +		 * more than one EU pair per subslice.
> +		*/
> +		info->has_slice_pg = 0;
> +		info->has_subslice_pg = (info->subslice_total > 1);
> +		info->has_eu_pg = (info->eu_per_subslice > 2);
>  	} else if (IS_SKYLAKE(dev)) {
>  		const int s_max = 3, ss_max = 4, eu_max = 8;
>  		int s, ss;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e0a525c..ed84603 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1510,6 +1510,8 @@ enum skl_disp_power_wells {
>  
>  /* Fuse readout registers for GT */
>  #define CHV_FUSE_GT			(VLV_DISPLAY_BASE + 0x2168)
> +#define   CHV_FGT_DISABLE_SS0		(1 << 10)
> +#define   CHV_FGT_DISABLE_SS1		(1 << 11)
>  #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
>  #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
>  #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
> -- 
> 2.3.0

-- 
Ville Syrjälä
Intel OTC
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[PATCH v2 1/2] drm/i915/chv: Determine CHV slice/subslice/EU info

[jeff.mcgee]

From: Jeff McGee <jeff.mcgee@intel.com>

Total EU was already being detected on CHV, so we just add the
additional info parameters. The detection method is changed to
be more robust in the case of subslice fusing - we don't want
to trust the EU fuse bits corresponding to subslices which are
fused-off.

v2: Fixed subslice disable bitmasks and removed unnecessary ?
    operation (Ville)

Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 40 ++++++++++++++++++++++++++++++++++------
 drivers/gpu/drm/i915/i915_reg.h |  2 ++
 2 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 9cbe3f5..4c33068 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -619,14 +619,42 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 
 	/* Initialize slice/subslice/EU info */
 	if (IS_CHERRYVIEW(dev)) {
-		u32 fuse, mask_eu;
+		u32 fuse, eu_dis;
 
 		fuse = I915_READ(CHV_FUSE_GT);
-		mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
-				  CHV_FGT_EU_DIS_SS0_R1_MASK |
-				  CHV_FGT_EU_DIS_SS1_R0_MASK |
-				  CHV_FGT_EU_DIS_SS1_R1_MASK);
-		info->eu_total = 16 - hweight32(mask_eu);
+
+		info->slice_total = 1;
+
+		if (!(fuse & CHV_FGT_DISABLE_SS0)) {
+			info->subslice_per_slice++;
+			eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
+					 CHV_FGT_EU_DIS_SS0_R1_MASK);
+			info->eu_total += 8 - hweight32(eu_dis);
+		}
+
+		if (!(fuse & CHV_FGT_DISABLE_SS1)) {
+			info->subslice_per_slice++;
+			eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
+					CHV_FGT_EU_DIS_SS1_R1_MASK);
+			info->eu_total += 8 - hweight32(eu_dis);
+		}
+
+		info->subslice_total = info->subslice_per_slice;
+		/*
+		 * CHV expected to always have a uniform distribution of EU
+		 * across subslices.
+		*/
+		info->eu_per_subslice = info->subslice_total ?
+					info->eu_total / info->subslice_total :
+					0;
+		/*
+		 * CHV supports subslice power gating on devices with more than
+		 * one subslice, and supports EU power gating on devices with
+		 * more than one EU pair per subslice.
+		*/
+		info->has_slice_pg = 0;
+		info->has_subslice_pg = (info->subslice_total > 1);
+		info->has_eu_pg = (info->eu_per_subslice > 2);
 	} else if (IS_SKYLAKE(dev)) {
 		const int s_max = 3, ss_max = 4, eu_max = 8;
 		int s, ss;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e0a525c..ed84603 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1510,6 +1510,8 @@ enum skl_disp_power_wells {
 
 /* Fuse readout registers for GT */
 #define CHV_FUSE_GT			(VLV_DISPLAY_BASE + 0x2168)
+#define   CHV_FGT_DISABLE_SS0		(1 << 10)
+#define   CHV_FGT_DISABLE_SS1		(1 << 11)
 #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
 #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
 #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
-- 
2.3.0

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Re: [PATCH v2 1/2] drm/i915/chv: Determine CHV slice/subslice/EU info

[Jeff McGee]

On Fri, Feb 27, 2015 at 10:12:14PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 27, 2015 at 12:12:28PM -0800, jeff.mcgee@intel.com wrote:
> > From: Jeff McGee <jeff.mcgee@intel.com>
> > 
> > Total EU was already being detected on CHV, so we just add the
> > additional info parameters. The detection method is changed to
> > be more robust in the case of subslice fusing - we don't want
> > to trust the EU fuse bits corresponding to subslices which are
> > fused-off.
> > 
> > v2: Fixed subslice disable bitmasks and removed unnecessary ?
> >     operation (Ville)
> > 
> > Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 

This patch now also needed to support the export of CHV subslice count
to userspace (beignet).

http://lists.freedesktop.org/archives/intel-gfx/2015-March/061100.html

> > ---
> >  drivers/gpu/drm/i915/i915_dma.c | 40 ++++++++++++++++++++++++++++++++++------
> >  drivers/gpu/drm/i915/i915_reg.h |  2 ++
> >  2 files changed, 36 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> > index 9cbe3f5..4c33068 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -619,14 +619,42 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> >  
> >  	/* Initialize slice/subslice/EU info */
> >  	if (IS_CHERRYVIEW(dev)) {
> > -		u32 fuse, mask_eu;
> > +		u32 fuse, eu_dis;
> >  
> >  		fuse = I915_READ(CHV_FUSE_GT);
> > -		mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
> > -				  CHV_FGT_EU_DIS_SS0_R1_MASK |
> > -				  CHV_FGT_EU_DIS_SS1_R0_MASK |
> > -				  CHV_FGT_EU_DIS_SS1_R1_MASK);
> > -		info->eu_total = 16 - hweight32(mask_eu);
> > +
> > +		info->slice_total = 1;
> > +
> > +		if (!(fuse & CHV_FGT_DISABLE_SS0)) {
> > +			info->subslice_per_slice++;
> > +			eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
> > +					 CHV_FGT_EU_DIS_SS0_R1_MASK);
> > +			info->eu_total += 8 - hweight32(eu_dis);
> > +		}
> > +
> > +		if (!(fuse & CHV_FGT_DISABLE_SS1)) {
> > +			info->subslice_per_slice++;
> > +			eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
> > +					CHV_FGT_EU_DIS_SS1_R1_MASK);
> > +			info->eu_total += 8 - hweight32(eu_dis);
> > +		}
> > +
> > +		info->subslice_total = info->subslice_per_slice;
> > +		/*
> > +		 * CHV expected to always have a uniform distribution of EU
> > +		 * across subslices.
> > +		*/
> > +		info->eu_per_subslice = info->subslice_total ?
> > +					info->eu_total / info->subslice_total :
> > +					0;
> > +		/*
> > +		 * CHV supports subslice power gating on devices with more than
> > +		 * one subslice, and supports EU power gating on devices with
> > +		 * more than one EU pair per subslice.
> > +		*/
> > +		info->has_slice_pg = 0;
> > +		info->has_subslice_pg = (info->subslice_total > 1);
> > +		info->has_eu_pg = (info->eu_per_subslice > 2);
> >  	} else if (IS_SKYLAKE(dev)) {
> >  		const int s_max = 3, ss_max = 4, eu_max = 8;
> >  		int s, ss;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e0a525c..ed84603 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1510,6 +1510,8 @@ enum skl_disp_power_wells {
> >  
> >  /* Fuse readout registers for GT */
> >  #define CHV_FUSE_GT			(VLV_DISPLAY_BASE + 0x2168)
> > +#define   CHV_FGT_DISABLE_SS0		(1 << 10)
> > +#define   CHV_FGT_DISABLE_SS1		(1 << 11)
> >  #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
> >  #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
> >  #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
> > -- 
> > 2.3.0
> 
> -- 
> Ville Syrjälä
> Intel OTC
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Re: [PATCH 2/2] drm/i915/chv: Add CHV HW status to SSEU status

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5863
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -7              278/278              271/278
ILK                                  308/308              308/308
SNB                 -1              284/284              283/284
IVB                                  380/380              380/380
BYT                                  294/294              294/294
HSW                 -2              387/387              385/387
BDW                 -1              316/316              315/316
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt_gem_userptr_blits_coherency-sync      CRASH(2)PASS(6)      CRASH(2)
 PNV  igt_gem_userptr_blits_coherency-unsync      CRASH(2)PASS(5)      CRASH(1)PASS(1)
*PNV  igt_gem_userptr_blits_create-destroy-sync      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_userptr_blits_minor-sync-interruptible      PASS(2)      DMESG_WARN(1)PASS(1)
 PNV  igt_gen3_render_linear_blits      FAIL(3)PASS(5)      FAIL(2)
 PNV  igt_gen3_render_mixed_blits      FAIL(2)PASS(7)      FAIL(2)
 PNV  igt_gem_fence_thrash_bo-write-verify-threaded-none      FAIL(1)CRASH(1)PASS(3)      CRASH(1)PASS(1)
*SNB  igt_gem_fence_thrash_bo-write-verify-y      PASS(3)      DMESG_WARN(1)PASS(1)
*HSW  igt_gem_bad_length      PASS(2)      DMESG_WARN(1)PASS(1)
*HSW  igt_gem_storedw_loop_blt      PASS(3)      DMESG_WARN(1)PASS(1)
*BDW  igt_gem_gtt_hog      PASS(10)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 0/2] SSEU detection for CHV

[Jeff McGee]

On Fri, Feb 27, 2015 at 10:22:30AM -0800, jeff.mcgee@intel.com wrote:
> From: Jeff McGee <jeff.mcgee@intel.com>
> 
> These two patches add detection of available and enabled
> slice/subslice/EU on CHV following the implementation recently
> merged for SKL. They have been requested to help CHV users
> determine their configuration through the debugfs interface.
> 
> Jeff McGee (2):
>   drm/i915/chv: Determine CHV slice/subslice/EU info
>   drm/i915/chv: Add CHV HW status to SSEU status
> 
>  drivers/gpu/drm/i915/i915_debugfs.c | 31 ++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_dma.c     | 40 +++++++++++++++++++++++++++++++------
>  drivers/gpu/drm/i915/i915_reg.h     | 13 ++++++++++++
>  3 files changed, 76 insertions(+), 8 deletions(-)
> 

This appears reviewed and ready for merge. Can we merge?
-Jeff

> -- 
> 2.3.0
> 
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Re: [PATCH 0/2] SSEU detection for CHV

[Daniel Vetter]

On Fri, Mar 06, 2015 at 05:38:33PM -0800, Jeff McGee wrote:
> On Fri, Feb 27, 2015 at 10:22:30AM -0800, jeff.mcgee@intel.com wrote:
> > From: Jeff McGee <jeff.mcgee@intel.com>
> > 
> > These two patches add detection of available and enabled
> > slice/subslice/EU on CHV following the implementation recently
> > merged for SKL. They have been requested to help CHV users
> > determine their configuration through the debugfs interface.
> > 
> > Jeff McGee (2):
> >   drm/i915/chv: Determine CHV slice/subslice/EU info
> >   drm/i915/chv: Add CHV HW status to SSEU status
> > 
> >  drivers/gpu/drm/i915/i915_debugfs.c | 31 ++++++++++++++++++++++++++--
> >  drivers/gpu/drm/i915/i915_dma.c     | 40 +++++++++++++++++++++++++++++++------
> >  drivers/gpu/drm/i915/i915_reg.h     | 13 ++++++++++++
> >  3 files changed, 76 insertions(+), 8 deletions(-)
> > 
> 
> This appears reviewed and ready for merge. Can we merge?

I didn't realize that you've resent patch 1 since it wasn't in-reply-to v1
of patch 1/2 but as a reply to the cover letter. Reply-to cover letter is
usually used for additional follow-up patches. Hence I didn't realize that
your patches are ready for merging.

Applied now, thanks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 0/2] SSEU detection for CHV

[Jeff McGee]

On Mon, Mar 09, 2015 at 09:40:50AM +0100, Daniel Vetter wrote:
> On Fri, Mar 06, 2015 at 05:38:33PM -0800, Jeff McGee wrote:
> > On Fri, Feb 27, 2015 at 10:22:30AM -0800, jeff.mcgee@intel.com wrote:
> > > From: Jeff McGee <jeff.mcgee@intel.com>
> > > 
> > > These two patches add detection of available and enabled
> > > slice/subslice/EU on CHV following the implementation recently
> > > merged for SKL. They have been requested to help CHV users
> > > determine their configuration through the debugfs interface.
> > > 
> > > Jeff McGee (2):
> > >   drm/i915/chv: Determine CHV slice/subslice/EU info
> > >   drm/i915/chv: Add CHV HW status to SSEU status
> > > 
> > >  drivers/gpu/drm/i915/i915_debugfs.c | 31 ++++++++++++++++++++++++++--
> > >  drivers/gpu/drm/i915/i915_dma.c     | 40 +++++++++++++++++++++++++++++++------
> > >  drivers/gpu/drm/i915/i915_reg.h     | 13 ++++++++++++
> > >  3 files changed, 76 insertions(+), 8 deletions(-)
> > > 
> > 
> > This appears reviewed and ready for merge. Can we merge?
> 
> I didn't realize that you've resent patch 1 since it wasn't in-reply-to v1
> of patch 1/2 but as a reply to the cover letter. Reply-to cover letter is
> usually used for additional follow-up patches. Hence I didn't realize that
> your patches are ready for merging.
> 
> Applied now, thanks.
> -Daniel
> -- 

Yeah, I meant to send that v2 in reply to the v1 but confused the message ids.
Will get that right next time. Thanks for the merge.
-Jeff
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