[U-Boot] [PATCH V2 0/8] peach_pi: Add support for FIMD and DP

[U-Boot] [PATCH V2 0/8] peach_pi: Add support for FIMD and DP

[Ajay Kumar]

Add support for the eDP panel supported on peach_pi.

Changes since V1:
	-- Address comments for clock changes
	-- Remove the use of GPIO enums, and use DT to specify GPIOs.

Ajay Kumar (8):
  [PATCH V2 1/8] arm: exynos: add display clocks for Exynos5800
  [PATCH V2 2/8] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels
  [PATCH V2 3/8] video: exynos_fb: configure backlight GPIOs if specified in DT
  [PATCH V2 4/8] video: parade: configure SLP and RST GPIOs if specified in DT
  [PATCH V2 5/8] dts: exynos54xx: Add samsung,pwm-out-gpio property to FIMD node
  [PATCH V2 6/8] dts: peach_pit: Add SLP and RST GPIO properties in parade DT node
  [PATCH V2 7/8] dts: peach_pi: Add DT properties needed for display
  [PATCH V2 8/8] smdk5420: Remove GPIO enums

 arch/arm/cpu/armv7/exynos/clock.c              |   66 ++++++++++++++++++++++--
 arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |    4 +-
 arch/arm/dts/exynos5420-peach-pit.dts          |    2 +
 arch/arm/dts/exynos54xx.dtsi                   |    1 +
 arch/arm/dts/exynos5800-peach-pi.dts           |    3 ++
 arch/arm/include/asm/arch-exynos/clk.h         |    3 ++
 board/samsung/smdk5420/smdk5420.c              |   15 ------
 doc/device-tree-bindings/video/exynos-fb.txt   |    2 +
 drivers/video/exynos_fb.c                      |   23 +++++++++
 drivers/video/parade.c                         |   15 ++++++
 10 files changed, 114 insertions(+), 20 deletions(-)

-- 
1.7.9.5

[U-Boot] [PATCH V2 1/8] arm: exynos: add display clocks for Exynos5800

[Ajay Kumar]

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
exynos video driver.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
---
 arch/arm/cpu/armv7/exynos/clock.c      |   66 ++++++++++++++++++++++++++++++--
 arch/arm/include/asm/arch-exynos/clk.h |    3 ++
 2 files changed, 66 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index c6455c2..23f8ff7 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -14,7 +14,7 @@
 #define PLL_DIV_1024	1024
 #define PLL_DIV_65535	65535
 #define PLL_DIV_65536	65536
-
+#define FIN_HZ		24000000
 /* *
  * This structure is to store the src bit, div bit and prediv bit
  * positions of the peripheral clocks of the src and div registers
@@ -1028,6 +1028,40 @@ static unsigned long exynos5420_get_lcd_clk(void)
 	return pclk;
 }
 
+static unsigned long exynos5800_get_lcd_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_DISP10
+	 * CLKMUX_FIMD1 [6:4]
+	 */
+	sel = (readl(&clk->src_disp10) >> 4) & 0x7;
+
+	if (sel) {
+		/*
+		 * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
+		 * PLLs. The first element is a placeholder to bypass the
+		 * default settig.
+		 */
+		const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,
+									RPLL};
+		sclk = get_pll_clk(reg_map[sel]);
+	} else
+		sclk = FIN_HZ;
+	/*
+	 * CLK_DIV_DISP10
+	 * FIMD1_RATIO [3:0]
+	 */
+	ratio = readl(&clk->div_disp10) & 0xf;
+
+	return sclk / (ratio + 1);
+}
+
 void exynos4_set_lcd_clk(void)
 {
 	struct exynos4_clock *clk =
@@ -1159,6 +1193,28 @@ void exynos5420_set_lcd_clk(void)
 	writel(cfg, &clk->div_disp10);
 }
 
+void exynos5800_set_lcd_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned int cfg;
+
+	/*
+	 * Use RPLL for pixel clock
+	 * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
+	 * ==================
+	 * 111: SCLK_RPLL
+	 */
+	cfg = readl(&clk->src_disp10) | (0x7 << 4);
+	writel(cfg, &clk->src_disp10);
+
+	/*
+	 * CLK_DIV_DISP10
+	 * FIMD1_RATIO		[3:0]
+	 */
+	clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);
+}
+
 void exynos4_set_mipi_clk(void)
 {
 	struct exynos4_clock *clk =
@@ -1646,8 +1702,10 @@ unsigned long get_lcd_clk(void)
 	if (cpu_is_exynos4())
 		return exynos4_get_lcd_clk();
 	else {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420())
 			return exynos5420_get_lcd_clk();
+		else if (proid_is_exynos5800())
+			return exynos5800_get_lcd_clk();
 		else
 			return exynos5_get_lcd_clk();
 	}
@@ -1660,8 +1718,10 @@ void set_lcd_clk(void)
 	else {
 		if (proid_is_exynos5250())
 			exynos5_set_lcd_clk();
-		else if (proid_is_exynos5420() || proid_is_exynos5800())
+		else if (proid_is_exynos5420())
 			exynos5420_set_lcd_clk();
+		else
+			exynos5800_set_lcd_clk();
 	}
 }
 
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index 2a17dfc..d20b7d2 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -16,6 +16,9 @@
 #define BPLL	5
 #define RPLL	6
 #define SPLL	7
+#define CPLL	8
+#define DPLL	9
+#define IPLL	10
 
 #define MASK_PRE_RATIO(x)	(0xff << ((x << 4) + 8))
 #define MASK_RATIO(x)		(0xf << (x << 4))
-- 
1.7.9.5

[U-Boot] [PATCH 2/8] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels

[Ajay Kumar]

The existing setting for rpll_sdiv generates 70.5Mhz RPLL
video clock to drive 1366x768 panel on peach_pit.

This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
which can drive peach-pi LCD.

This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
divider at IP level will get set to 1(the required divider setting
will be calculated and set by exynos_fimd_set_clock()) and hence
peach-pit LCD still works fine.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
---
 arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index 0aff3d0..0200fd1 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = {
 		.spll_mdiv = 0xc8,
 		.spll_pdiv = 0x3,
 		.spll_sdiv = 0x2,
-		/* RPLL @70.5Mhz */
+		/* RPLL @141Mhz */
 		.rpll_mdiv = 0x5E,
 		.rpll_pdiv = 0x2,
-		.rpll_sdiv = 0x4,
+		.rpll_sdiv = 0x3,
 
 		.direct_cmd_msr = {
 			0x00020018, 0x00030000, 0x00010046, 0x00000d70,
-- 
1.7.9.5

[U-Boot] [PATCH V2 3/8] video: exynos_fb: configure backlight GPIOs if specified in DT

[Ajay Kumar]

Add support to configure PWM_OUT(PWM output) GPIO and
BL_EN(backlight enable) GPIO, if provided in FIMD DT node.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
---
 doc/device-tree-bindings/video/exynos-fb.txt |    2 ++
 drivers/video/exynos_fb.c                    |   23 +++++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt
index dc4e44f..b022f61 100644
--- a/doc/device-tree-bindings/video/exynos-fb.txt
+++ b/doc/device-tree-bindings/video/exynos-fb.txt
@@ -61,6 +61,8 @@ Board(panel specific):
 				disabled with compatible string
 				"samsung,sysmmu-v3.3", with a "reg" property
 				holding the register address of FIMD sysmmu.
+	samsung,pwm-out-gpio: PWM output GPIO.
+	samsung,bl-en-gpio: backlight enable GPIO.
 
 Example:
 SOC specific part:
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index c5d7330..be85ed8 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -19,6 +19,7 @@
 #include <asm/arch/mipi_dsim.h>
 #include <asm/arch/dp_info.h>
 #include <asm/arch/system.h>
+#include <asm/gpio.h>
 #include <asm-generic/errno.h>
 
 #include "exynos_fb.h"
@@ -102,6 +103,10 @@ __weak int exynos_lcd_misc_init(vidinfo_t *vid)
 
 static void lcd_panel_on(vidinfo_t *vid)
 {
+	struct gpio_desc pwm_out_gpio;
+	struct gpio_desc bl_en_gpio;
+	unsigned int node;
+
 	udelay(vid->init_delay);
 
 	exynos_backlight_reset();
@@ -121,6 +126,24 @@ static void lcd_panel_on(vidinfo_t *vid)
 
 	exynos_backlight_on(1);
 
+#ifdef CONFIG_OF_CONTROL
+	node = fdtdec_next_compatible(gd->fdt_blob, 0,
+						COMPAT_SAMSUNG_EXYNOS_FIMD);
+	if (node <= 0) {
+		debug("FIMD: Can't get device node for FIMD\n");
+		return;
+	}
+	gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio",
+				   0, &pwm_out_gpio, GPIOD_IS_OUT);
+	if (dm_gpio_is_valid(&pwm_out_gpio))
+		dm_gpio_set_value(&pwm_out_gpio, 1);
+
+	gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0,
+				   &bl_en_gpio, GPIOD_IS_OUT);
+	if (dm_gpio_is_valid(&bl_en_gpio))
+		dm_gpio_set_value(&bl_en_gpio, 1);
+
+#endif
 	exynos_cfg_ldo();
 
 	exynos_enable_ldo(1);
-- 
1.7.9.5

[U-Boot] [PATCH V2 4/8] video: parade: configure SLP and RST GPIOs if specified in DT

[Ajay Kumar]

Add support to configure EDP_RST GPIO and EDP_SLP GPIO,
if provided in parade DT node.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
---
 drivers/video/parade.c |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/video/parade.c b/drivers/video/parade.c
index 0f543f6..525ef07 100644
--- a/drivers/video/parade.c
+++ b/drivers/video/parade.c
@@ -12,6 +12,7 @@
 #include <common.h>
 #include <i2c.h>
 #include <fdtdec.h>
+#include <asm/gpio.h>
 
 /*
  * Initialization of the chip is a process of writing certaing values into
@@ -180,6 +181,8 @@ static int parade_write_regs(int base_addr, const struct reg_data *table)
 
 int parade_init(const void *blob)
 {
+	struct gpio_desc rst_gpio;
+	struct gpio_desc slp_gpio;
 	int bus, old_bus;
 	int parent;
 	int node;
@@ -201,6 +204,18 @@ int parade_init(const void *blob)
 		return -1;
 	}
 
+	gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio,
+				   GPIOD_IS_OUT);
+	if (dm_gpio_is_valid(&slp_gpio))
+		dm_gpio_set_value(&slp_gpio, 1);
+
+	mdelay(10);
+
+	gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio,
+				   GPIOD_IS_OUT);
+	if (dm_gpio_is_valid(&rst_gpio))
+		dm_gpio_set_value(&rst_gpio, 1);
+
 	bus = i2c_get_bus_num_fdt(parent);
 	old_bus = i2c_get_bus_num();
 
-- 
1.7.9.5

[U-Boot] [PATCH V2 5/8] dts: exynos54xx: Add samsung, pwm-out-gpio property to FIMD node

[Ajay Kumar]

Now that the exynos_fb driver supports handling backlight GPIO
via DT, specify pwm output property via FIMD DT node.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
---
 arch/arm/dts/exynos54xx.dtsi |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index 916cf3a..31fabb1 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -168,6 +168,7 @@
 	fimd at 14400000 {
 		/* sysmmu is not used in U-Boot */
 		samsung,disable-sysmmu;
+		samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>;
 	};
 
 	dp at 145b0000 {
-- 
1.7.9.5

[U-Boot] [PATCH V2 6/8] dts: peach_pit: Add SLP and RST GPIO properties in parade DT node

[Ajay Kumar]

Now that parade driver supports reading SLP and RST GPIO
from DT, specify the same in parade DT node.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
---
 arch/arm/dts/exynos5420-peach-pit.dts |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts
index b801de9..3ad4728 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -67,6 +67,8 @@
 	        edp-lvds-bridge at 48 {
 	                compatible = "parade,ps8625";
 	                reg = <0x48>;
+			sleep-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>;
+			reset-gpio = <&gpy7 7 GPIO_ACTIVE_HIGH>;
 	        };
 	};
 
-- 
1.7.9.5

[U-Boot] [PATCH V2 7/8] dts: peach_pi: Add DT properties needed for display

[Ajay Kumar]

Add backlight enable GPIO, and delay needed for panel powerup
via FIMD DT node.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
---
 arch/arm/dts/exynos5800-peach-pi.dts |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts
index e4bc100..494f764 100644
--- a/arch/arm/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/dts/exynos5800-peach-pi.dts
@@ -144,10 +144,13 @@
 		samsung,vl-vfpd = <10>;
 		samsung,vl-cmd-allow-len = <0xf>;
 
+		samsung,power-on-delay = <30000>;
 		samsung,winid = <3>;
 		samsung,interface-mode = <1>;
 		samsung,dp-enabled = <1>;
 		samsung,dual-lcd-enabled = <0>;
+
+		samsung,bl-en-gpio = <&gpx2 2 GPIO_ACTIVE_HIGH>;
 	};
 };
 
-- 
1.7.9.5

[U-Boot] [PATCH V2 8/8] smdk5420: Remove GPIO enums

[Ajay Kumar]

Remove GPIOs from smdk5420 board file and because the same
is already specified via DT.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
---
 board/samsung/smdk5420/smdk5420.c |   15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c
index 1aca9fa..82f607b 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -58,16 +58,6 @@ void exynos_lcd_power_on(void)
 
 	mdelay(5);
 
-	/* TODO(ajaykumar.rs at samsung.com): Use device tree */
-	gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
-	gpio_direction_output(EXYNOS5420_GPIO_X35, 1);	/* EDP_SLP# */
-	mdelay(10);
-	gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
-	gpio_direction_output(EXYNOS5420_GPIO_Y77, 1);	/* EDP_RST# */
-	gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
-	gpio_direction_input(EXYNOS5420_GPIO_X26);	/* EDP_HPD */
-	gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
-
 	if (has_edp_bridge())
 		if (parade_init(gd->fdt_blob))
 			printf("%s: ps8625_init() failed\n", __func__);
@@ -75,11 +65,6 @@ void exynos_lcd_power_on(void)
 
 void exynos_backlight_on(unsigned int onoff)
 {
-	/* For PWM */
-	gpio_request(EXYNOS5420_GPIO_B20, "backlight_on");
-	gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1));
-	gpio_set_value(EXYNOS5420_GPIO_B20, 1);
-
 #ifdef CONFIG_POWER_TPS65090
 	tps65090_fet_enable(1);
 #endif
-- 
1.7.9.5

[U-Boot] [PATCH V2 0/8] peach_pi: Add support for FIMD and DP

[Ajay kumar]

On Tue, Mar 3, 2015 at 7:33 PM, Ajay Kumar <ajaykumar.rs@samsung.com> wrote:
> Add support for the eDP panel supported on peach_pi.
>
> Changes since V1:
>         -- Address comments for clock changes
>         -- Remove the use of GPIO enums, and use DT to specify GPIOs.
>
> Ajay Kumar (8):
>   [PATCH V2 1/8] arm: exynos: add display clocks for Exynos5800
>   [PATCH V2 2/8] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels
>   [PATCH V2 3/8] video: exynos_fb: configure backlight GPIOs if specified in DT
>   [PATCH V2 4/8] video: parade: configure SLP and RST GPIOs if specified in DT
>   [PATCH V2 5/8] dts: exynos54xx: Add samsung,pwm-out-gpio property to FIMD node
>   [PATCH V2 6/8] dts: peach_pit: Add SLP and RST GPIO properties in parade DT node
>   [PATCH V2 7/8] dts: peach_pi: Add DT properties needed for display
>   [PATCH V2 8/8] smdk5420: Remove GPIO enums
>
>  arch/arm/cpu/armv7/exynos/clock.c              |   66 ++++++++++++++++++++++--
>  arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |    4 +-
>  arch/arm/dts/exynos5420-peach-pit.dts          |    2 +
>  arch/arm/dts/exynos54xx.dtsi                   |    1 +
>  arch/arm/dts/exynos5800-peach-pi.dts           |    3 ++
>  arch/arm/include/asm/arch-exynos/clk.h         |    3 ++
>  board/samsung/smdk5420/smdk5420.c              |   15 ------
>  doc/device-tree-bindings/video/exynos-fb.txt   |    2 +
>  drivers/video/exynos_fb.c                      |   23 +++++++++
>  drivers/video/parade.c                         |   15 ++++++
>  10 files changed, 114 insertions(+), 20 deletions(-)
>
> --
> 1.7.9.5
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH V2 1/8] arm: exynos: add display clocks for Exynos5800

[Simon Glass]

Hi Ajay,

On 3 March 2015 at 07:03, Ajay Kumar <ajaykumar.rs@samsung.com> wrote:
> Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
> exynos video driver.
>
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
> ---
>  arch/arm/cpu/armv7/exynos/clock.c      |   66 ++++++++++++++++++++++++++++++--
>  arch/arm/include/asm/arch-exynos/clk.h |    3 ++
>  2 files changed, 66 insertions(+), 3 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
(one question below)

Tested on Pi.

Tested-by: Simon Glass <sjg@chromium.org>

>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index c6455c2..23f8ff7 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -14,7 +14,7 @@
>  #define PLL_DIV_1024   1024
>  #define PLL_DIV_65535  65535
>  #define PLL_DIV_65536  65536
> -
> +#define FIN_HZ         24000000

Is this different from CONFIG_SYS_CLK_FREQ?

>  /* *
>   * This structure is to store the src bit, div bit and prediv bit
>   * positions of the peripheral clocks of the src and div registers
> @@ -1028,6 +1028,40 @@ static unsigned long exynos5420_get_lcd_clk(void)
>         return pclk;
>  }
>
> +static unsigned long exynos5800_get_lcd_clk(void)
> +{
> +       struct exynos5420_clock *clk =
> +               (struct exynos5420_clock *)samsung_get_base_clock();
> +       unsigned long sclk;
> +       unsigned int sel;
> +       unsigned int ratio;
> +
> +       /*
> +        * CLK_SRC_DISP10
> +        * CLKMUX_FIMD1 [6:4]
> +        */
> +       sel = (readl(&clk->src_disp10) >> 4) & 0x7;
> +
> +       if (sel) {
> +               /*
> +                * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
> +                * PLLs. The first element is a placeholder to bypass the
> +                * default settig.
> +                */
> +               const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,
> +                                                                       RPLL};
> +               sclk = get_pll_clk(reg_map[sel]);
> +       } else
> +               sclk = FIN_HZ;
> +       /*
> +        * CLK_DIV_DISP10
> +        * FIMD1_RATIO [3:0]
> +        */
> +       ratio = readl(&clk->div_disp10) & 0xf;
> +
> +       return sclk / (ratio + 1);
> +}
> +
>  void exynos4_set_lcd_clk(void)
>  {
>         struct exynos4_clock *clk =
> @@ -1159,6 +1193,28 @@ void exynos5420_set_lcd_clk(void)
>         writel(cfg, &clk->div_disp10);
>  }
>
> +void exynos5800_set_lcd_clk(void)
> +{
> +       struct exynos5420_clock *clk =
> +               (struct exynos5420_clock *)samsung_get_base_clock();
> +       unsigned int cfg;
> +
> +       /*
> +        * Use RPLL for pixel clock
> +        * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
> +        * ==================
> +        * 111: SCLK_RPLL
> +        */
> +       cfg = readl(&clk->src_disp10) | (0x7 << 4);
> +       writel(cfg, &clk->src_disp10);
> +
> +       /*
> +        * CLK_DIV_DISP10
> +        * FIMD1_RATIO          [3:0]
> +        */
> +       clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);
> +}
> +
>  void exynos4_set_mipi_clk(void)
>  {
>         struct exynos4_clock *clk =
> @@ -1646,8 +1702,10 @@ unsigned long get_lcd_clk(void)
>         if (cpu_is_exynos4())
>                 return exynos4_get_lcd_clk();
>         else {
> -               if (proid_is_exynos5420() || proid_is_exynos5800())
> +               if (proid_is_exynos5420())
>                         return exynos5420_get_lcd_clk();
> +               else if (proid_is_exynos5800())
> +                       return exynos5800_get_lcd_clk();
>                 else
>                         return exynos5_get_lcd_clk();
>         }
> @@ -1660,8 +1718,10 @@ void set_lcd_clk(void)
>         else {
>                 if (proid_is_exynos5250())
>                         exynos5_set_lcd_clk();
> -               else if (proid_is_exynos5420() || proid_is_exynos5800())
> +               else if (proid_is_exynos5420())
>                         exynos5420_set_lcd_clk();
> +               else
> +                       exynos5800_set_lcd_clk();
>         }
>  }
>
> diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
> index 2a17dfc..d20b7d2 100644
> --- a/arch/arm/include/asm/arch-exynos/clk.h
> +++ b/arch/arm/include/asm/arch-exynos/clk.h
> @@ -16,6 +16,9 @@
>  #define BPLL   5
>  #define RPLL   6
>  #define SPLL   7
> +#define CPLL   8
> +#define DPLL   9
> +#define IPLL   10
>
>  #define MASK_PRE_RATIO(x)      (0xff << ((x << 4) + 8))
>  #define MASK_RATIO(x)          (0xf << (x << 4))
> --
> 1.7.9.5
>

Regards,
Simon

[U-Boot] [PATCH 2/8] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels

[Simon Glass]

On 3 March 2015 at 07:03, Ajay Kumar <ajaykumar.rs@samsung.com> wrote:
> The existing setting for rpll_sdiv generates 70.5Mhz RPLL
> video clock to drive 1366x768 panel on peach_pit.
>
> This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
> So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
> which can drive peach-pi LCD.
>
> This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
> divider at IP level will get set to 1(the required divider setting
> will be calculated and set by exynos_fimd_set_clock()) and hence
> peach-pit LCD still works fine.
>
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>

Reviewed-by: Simon Glass <sjg@chromium.org>

Tested on Pi.

Tested-by: Simon Glass <sjg@chromium.org>

> ---
>  arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
> index 0aff3d0..0200fd1 100644
> --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
> +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
> @@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = {
>                 .spll_mdiv = 0xc8,
>                 .spll_pdiv = 0x3,
>                 .spll_sdiv = 0x2,
> -               /* RPLL @70.5Mhz */
> +               /* RPLL @141Mhz */
>                 .rpll_mdiv = 0x5E,
>                 .rpll_pdiv = 0x2,
> -               .rpll_sdiv = 0x4,
> +               .rpll_sdiv = 0x3,
>
>                 .direct_cmd_msr = {
>                         0x00020018, 0x00030000, 0x00010046, 0x00000d70,
> --
> 1.7.9.5
>

[U-Boot] [PATCH V2 3/8] video: exynos_fb: configure backlight GPIOs if specified in DT

[Simon Glass]

Hi Ajay,

On 3 March 2015 at 07:03, Ajay Kumar <ajaykumar.rs@samsung.com> wrote:
> Add support to configure PWM_OUT(PWM output) GPIO and
> BL_EN(backlight enable) GPIO, if provided in FIMD DT node.
>
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
> ---
>  doc/device-tree-bindings/video/exynos-fb.txt |    2 ++
>  drivers/video/exynos_fb.c                    |   23 +++++++++++++++++++++++
>  2 files changed, 25 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>
(with one suggested change below)

Tested on Pi.

Tested-by: Simon Glass <sjg@chromium.org>


> diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt
> index dc4e44f..b022f61 100644
> --- a/doc/device-tree-bindings/video/exynos-fb.txt
> +++ b/doc/device-tree-bindings/video/exynos-fb.txt
> @@ -61,6 +61,8 @@ Board(panel specific):
>                                 disabled with compatible string
>                                 "samsung,sysmmu-v3.3", with a "reg" property
>                                 holding the register address of FIMD sysmmu.
> +       samsung,pwm-out-gpio: PWM output GPIO.
> +       samsung,bl-en-gpio: backlight enable GPIO.
>
>  Example:
>  SOC specific part:
> diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
> index c5d7330..be85ed8 100644
> --- a/drivers/video/exynos_fb.c
> +++ b/drivers/video/exynos_fb.c
> @@ -19,6 +19,7 @@
>  #include <asm/arch/mipi_dsim.h>
>  #include <asm/arch/dp_info.h>
>  #include <asm/arch/system.h>
> +#include <asm/gpio.h>
>  #include <asm-generic/errno.h>
>
>  #include "exynos_fb.h"
> @@ -102,6 +103,10 @@ __weak int exynos_lcd_misc_init(vidinfo_t *vid)
>
>  static void lcd_panel_on(vidinfo_t *vid)
>  {
> +       struct gpio_desc pwm_out_gpio;
> +       struct gpio_desc bl_en_gpio;
> +       unsigned int node;
> +
>         udelay(vid->init_delay);
>
>         exynos_backlight_reset();
> @@ -121,6 +126,24 @@ static void lcd_panel_on(vidinfo_t *vid)
>
>         exynos_backlight_on(1);
>
> +#ifdef CONFIG_OF_CONTROL
> +       node = fdtdec_next_compatible(gd->fdt_blob, 0,
> +                                               COMPAT_SAMSUNG_EXYNOS_FIMD);
> +       if (node <= 0) {
> +               debug("FIMD: Can't get device node for FIMD\n");
> +               return;
> +       }
> +       gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio",
> +                                  0, &pwm_out_gpio, GPIOD_IS_OUT);
> +       if (dm_gpio_is_valid(&pwm_out_gpio))
> +               dm_gpio_set_value(&pwm_out_gpio, 1);

Instead of these two lines you can use GPIOD_IS_OUT |
GPIOD_IS_OUT_ACTIVE in the call above. That will make the GPIO an
output and set it high.

> +
> +       gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0,
> +                                  &bl_en_gpio, GPIOD_IS_OUT);
> +       if (dm_gpio_is_valid(&bl_en_gpio))
> +               dm_gpio_set_value(&bl_en_gpio, 1);

Here also.

> +
> +#endif
>         exynos_cfg_ldo();
>
>         exynos_enable_ldo(1);
> --
> 1.7.9.5
>

Regards,
SIimon

[U-Boot] [PATCH V2 4/8] video: parade: configure SLP and RST GPIOs if specified in DT

[Simon Glass]

Hi,

On 3 March 2015 at 07:03, Ajay Kumar <ajaykumar.rs@samsung.com> wrote:
> Add support to configure EDP_RST GPIO and EDP_SLP GPIO,
> if provided in parade DT node.
>
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
> ---
>  drivers/video/parade.c |   15 +++++++++++++++
>  1 file changed, 15 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>
(but see below)

Tested on Pi.

Tested-by: Simon Glass <sjg@chromium.org>

>
> diff --git a/drivers/video/parade.c b/drivers/video/parade.c
> index 0f543f6..525ef07 100644
> --- a/drivers/video/parade.c
> +++ b/drivers/video/parade.c
> @@ -12,6 +12,7 @@
>  #include <common.h>
>  #include <i2c.h>
>  #include <fdtdec.h>
> +#include <asm/gpio.h>
>
>  /*
>   * Initialization of the chip is a process of writing certaing values into
> @@ -180,6 +181,8 @@ static int parade_write_regs(int base_addr, const struct reg_data *table)
>
>  int parade_init(const void *blob)
>  {
> +       struct gpio_desc rst_gpio;
> +       struct gpio_desc slp_gpio;
>         int bus, old_bus;
>         int parent;
>         int node;
> @@ -201,6 +204,18 @@ int parade_init(const void *blob)
>                 return -1;
>         }
>
> +       gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio,
> +                                  GPIOD_IS_OUT);
> +       if (dm_gpio_is_valid(&slp_gpio))
> +               dm_gpio_set_value(&slp_gpio, 1);

Again you can use GPIOD_IS_OUT_ACTIVE here.

> +
> +       mdelay(10);
> +
> +       gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio,
> +                                  GPIOD_IS_OUT);
> +       if (dm_gpio_is_valid(&rst_gpio))
> +               dm_gpio_set_value(&rst_gpio, 1);
> +
>         bus = i2c_get_bus_num_fdt(parent);
>         old_bus = i2c_get_bus_num();
>
> --
> 1.7.9.5
>

Regards,
Simon

[U-Boot] [PATCH V2 5/8] dts: exynos54xx: Add samsung, pwm-out-gpio property to FIMD node

[Simon Glass]

On 3 March 2015 at 07:03, Ajay Kumar <ajaykumar.rs@samsung.com> wrote:
> Now that the exynos_fb driver supports handling backlight GPIO
> via DT, specify pwm output property via FIMD DT node.
>
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
> ---
>  arch/arm/dts/exynos54xx.dtsi |    1 +
>  1 file changed, 1 insertion(+)
>
Reviewed-by: Simon Glass <sjg@chromium.org>

Tested on Pi.

Tested-by: Simon Glass <sjg@chromium.org>

> diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
> index 916cf3a..31fabb1 100644
> --- a/arch/arm/dts/exynos54xx.dtsi
> +++ b/arch/arm/dts/exynos54xx.dtsi
> @@ -168,6 +168,7 @@
>         fimd at 14400000 {
>                 /* sysmmu is not used in U-Boot */
>                 samsung,disable-sysmmu;
> +               samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>;
>         };
>
>         dp at 145b0000 {
> --
> 1.7.9.5
>

[U-Boot] [PATCH V2 6/8] dts: peach_pit: Add SLP and RST GPIO properties in parade DT node

[Simon Glass]

On 3 March 2015 at 07:03, Ajay Kumar <ajaykumar.rs@samsung.com> wrote:
> Now that parade driver supports reading SLP and RST GPIO
> from DT, specify the same in parade DT node.
>
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
> ---
>  arch/arm/dts/exynos5420-peach-pit.dts |    2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

Tested on Pi.

Tested-by: Simon Glass <sjg@chromium.org>

>
> diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts
> index b801de9..3ad4728 100644
> --- a/arch/arm/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/dts/exynos5420-peach-pit.dts
> @@ -67,6 +67,8 @@
>                 edp-lvds-bridge at 48 {
>                         compatible = "parade,ps8625";
>                         reg = <0x48>;
> +                       sleep-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>;
> +                       reset-gpio = <&gpy7 7 GPIO_ACTIVE_HIGH>;
>                 };
>         };
>
> --
> 1.7.9.5
>

[U-Boot] [PATCH V2 7/8] dts: peach_pi: Add DT properties needed for display

[Simon Glass]

On 3 March 2015 at 07:03, Ajay Kumar <ajaykumar.rs@samsung.com> wrote:
> Add backlight enable GPIO, and delay needed for panel powerup
> via FIMD DT node.
>
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
> ---
>  arch/arm/dts/exynos5800-peach-pi.dts |    3 +++
>  1 file changed, 3 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

Tested on Pi.

Tested-by: Simon Glass <sjg@chromium.org>

>
> diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts
> index e4bc100..494f764 100644
> --- a/arch/arm/dts/exynos5800-peach-pi.dts
> +++ b/arch/arm/dts/exynos5800-peach-pi.dts
> @@ -144,10 +144,13 @@
>                 samsung,vl-vfpd = <10>;
>                 samsung,vl-cmd-allow-len = <0xf>;
>
> +               samsung,power-on-delay = <30000>;
>                 samsung,winid = <3>;
>                 samsung,interface-mode = <1>;
>                 samsung,dp-enabled = <1>;
>                 samsung,dual-lcd-enabled = <0>;
> +
> +               samsung,bl-en-gpio = <&gpx2 2 GPIO_ACTIVE_HIGH>;
>         };
>  };
>
> --
> 1.7.9.5
>

[U-Boot] [PATCH V2 8/8] smdk5420: Remove GPIO enums

[Simon Glass]

On 3 March 2015 at 07:03, Ajay Kumar <ajaykumar.rs@samsung.com> wrote:
> Remove GPIOs from smdk5420 board file and because the same
> is already specified via DT.
>
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
> ---
>  board/samsung/smdk5420/smdk5420.c |   15 ---------------
>  1 file changed, 15 deletions(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

Tested on Pi.

Tested-by: Simon Glass <sjg@chromium.org>

> diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c
> index 1aca9fa..82f607b 100644
> --- a/board/samsung/smdk5420/smdk5420.c
> +++ b/board/samsung/smdk5420/smdk5420.c
> @@ -58,16 +58,6 @@ void exynos_lcd_power_on(void)
>
>         mdelay(5);
>
> -       /* TODO(ajaykumar.rs at samsung.com): Use device tree */
> -       gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
> -       gpio_direction_output(EXYNOS5420_GPIO_X35, 1);  /* EDP_SLP# */
> -       mdelay(10);
> -       gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
> -       gpio_direction_output(EXYNOS5420_GPIO_Y77, 1);  /* EDP_RST# */
> -       gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
> -       gpio_direction_input(EXYNOS5420_GPIO_X26);      /* EDP_HPD */
> -       gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
> -
>         if (has_edp_bridge())
>                 if (parade_init(gd->fdt_blob))
>                         printf("%s: ps8625_init() failed\n", __func__);
> @@ -75,11 +65,6 @@ void exynos_lcd_power_on(void)
>
>  void exynos_backlight_on(unsigned int onoff)
>  {
> -       /* For PWM */
> -       gpio_request(EXYNOS5420_GPIO_B20, "backlight_on");
> -       gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1));
> -       gpio_set_value(EXYNOS5420_GPIO_B20, 1);
> -
>  #ifdef CONFIG_POWER_TPS65090
>         tps65090_fet_enable(1);
>  #endif
> --
> 1.7.9.5
>