[PATCH 1/2] dma: Add Freescale qDMA engine driver support

[PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Yuan Yao]

Add Freescale Queue Direct Memory Access (qDMA) controller support.
The qDMA supports channel virtualization by allowing DMA jobs to be
enqueued into different command queues. Core can initiate a DMA
transaction by preparing a command descriptor (CD) for each DMA job
and enqueuing this job to a command queue.

This module can be found on LS-1021 LS1043 and LS2085 SoCs.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
---
 Documentation/devicetree/bindings/dma/fsl-qdma.txt |  51 ++
 drivers/dma/Kconfig                                |  11 +
 drivers/dma/Makefile                               |   1 +
 drivers/dma/fsl-qdma.c                             | 929 +++++++++++++++++++++
 4 files changed, 992 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
 create mode 100644 drivers/dma/fsl-qdma.c

diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
new file mode 100644
index 0000000..676ae3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
@@ -0,0 +1,50 @@
+* Freescale queue Direct Memory Access Controller(qDMA) Controller
+
+  The qDMA controller transfers blocks of data between one source and one or more
+destinations. The blocks of data transferred can be represented in memory as contiguous
+or non-contiguous using scatter/gather table(s). Channel virtualization is supported
+through enqueuing of DMA jobs to, or dequeuing DMA jobs from, different work
+queues.
+
+* qDMA Controller
+Required properties:
+- compatible :
+	- "fsl,ls1021a-qdma" for qDMA used similar to that on LS1021a SoC
+- reg : Specifies base physical address(s) and size of the qDMA registers.
+	The region is qDMA control register's address and size.
+- interrupts : A list of interrupt-specifiers, one for each entry in
+	interrupt-names.
+- interrupt-names : Should contain:
+	"qdma-controller" - the controller interrupt
+	"qdma-queue" - the queue interrupt
+- status-sizes : Number of circular status descriptor queue size
+- channels : Number of channels supported by the controller
+- queues : Number of queues supported by the controller
+- queue-sizes : Number of circular descriptor queue size for each queue
+- queue-group : The group for each queue belong to
+- queue-weight : The weight for each queue belog to
+- default-queue : The default queue for request a new channel
+
+Optional properties:
+- big-endian: If present registers and hardware scatter/gather descriptors
+	of the qDMA are implemented in big endian mode, otherwise in little
+	mode.
+
+
+Examples:
+
+	qdma: qdma@8390000 {
+		compatible = "fsl,ls1021a-qdma";
+		reg = <0x0 0x8390000 0x0 0x10000>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "qdma-controller", "qdma-queue";
+		status-sizes = <64>;
+		channels = <8>;
+		queues = <2>;
+		queue-sizes = <256 256>;
+		queue-group = <0 1>;
+		queue-weight = <0 0>;
+		default-queue = <0>;
+		big-endian;
+	};
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 074ffad..fa52c9e 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -388,6 +388,17 @@ config FSL_EDMA
 	  multiplexing capability for DMA request sources(slot).
 	  This module can be found on Freescale Vybrid and LS-1 SoCs.
 
+config FSL_QDMA
+	tristate "Freescale qDMA engine support"
+	depends on OF
+	select DMA_ENGINE
+	select DMA_VIRTUAL_CHANNELS
+	help
+	  Support the Freescale qDMA engine with command queue and legacy mode.
+	  Channel virtualization is supported through enqueuing of DMA jobs to,
+	  or dequeuing DMA jobs from, different work queues.
+	  This module can be found on Freescale LS SoCs.
+
 config XILINX_VDMA
 	tristate "Xilinx AXI VDMA Engine"
 	depends on (ARCH_ZYNQ || MICROBLAZE)
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index bf44858..5f2b95e 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_TI_CPPI41) += cppi41.o
 obj-$(CONFIG_K3_DMA) += k3dma.o
 obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
 obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o
 obj-y += xilinx/
 obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
new file mode 100644
index 0000000..00f3c33
--- /dev/null
+++ b/drivers/dma/fsl-qdma.c
@@ -0,0 +1,929 @@
+/*
+ * drivers/dma/fsl-qdma.c
+ *
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Driver for the Freescale qDMA engine with command queue and legacy mode.
+ * Channel virtualization is supported through enqueuing of DMA jobs to,
+ * or dequeuing DMA jobs from, different work queues.
+ * This module can be found on Freescale LS SoCs.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <asm/cacheflush.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "virt-dma.h"
+
+#define FSL_QDMA_DMR			0x8000
+#define FSL_QDMA_DSR			0x8004
+#define FSL_QDMA_DEIER			0x9e00
+#define FSL_QDMA_DEDR			0x9e04
+#define FSL_QDMA_DECFDW0R		0x9e10
+#define FSL_QDMA_DECFDW1R		0x9e14
+#define FSL_QDMA_DECFDW2R		0x9e18
+#define FSL_QDMA_DECFDW3R		0x9e1c
+#define FSL_QDMA_DECFQIDR		0x9e30
+#define FSL_QDMA_DECBR			0x9e34
+
+#define FSL_QDMA_BCQMR(x)		(0xa0c0 + 0x100 * (x))
+#define FSL_QDMA_BCQSR(x)		(0xa0c4 + 0x100 * (x))
+#define FSL_QDMA_SQDPAR			0xa80c
+#define FSL_QDMA_SQEPAR			0xa814
+#define FSL_QDMA_BSQMR			0xa800
+#define FSL_QDMA_BSQSR			0xa804
+#define FSL_QDMA_BCQIER			0xa0e0
+#define FSL_QDMA_BSQICR			0xa828
+#define FSL_QDMA_CQIER			0xaa10
+#define FSL_QDMA_SQCCMR			0xaa20
+#define FSL_QDMA_BCQIDR			0xa0e4
+#define FSL_QDMA_CQDPA_SADDR(x)		(0xa0cc + 0x100 * (x))
+#define FSL_QDMA_CQEPA_SADDR(x)		(0xa0d4 + 0x100 * (x))
+
+#define FSL_QDMA_SQICR_ICEN
+
+#define FSL_QDMA_CQIDR_CQT		0xff000000
+#define FSL_QDMA_CQIDR_SQPE		0x800000
+#define FSL_QDMA_CQIDR_SQT		0x8000
+
+#define FSL_QDMA_BCQIER_CQTIE		0x8000
+#define FSL_QDMA_BCQIER_CQPEIE		0x800000
+#define FSL_QDMA_BSQICR_ICEN		0x80000000
+#define FSL_QDMA_BSQICR_ICST(x)		((x) << 16)
+#define FSL_QDMA_BSQICR_ICTT(x)		((x) & 0xffff)
+#define FSL_QDMA_CQIER_MEIE		0x80000000
+#define FSL_QDMA_CQIER_TEIE		0x1
+
+#define FSL_QDMA_QUEUE_MAX		8
+
+#define FSL_QDMA_BCQMR_EN		0x80000000
+#define FSL_QDMA_BCQMR_EI		0x40000000
+#define FSL_QDMA_BCQMR_CD_THLD(x)	((x) << 20)
+#define FSL_QDMA_BCQMR_CQ_SIZE(x)	((x) << 16)
+
+#define FSL_QDMA_BCQSR_QF		0x10000
+
+#define FSL_QDMA_BSQMR_EN		0x80000000
+#define FSL_QDMA_BSQMR_DI		0x40000000
+#define FSL_QDMA_BSQMR_CQ_SIZE(x)	((x) << 16)
+
+#define FSL_QDMA_BSQSR_QE		0x20000
+
+#define FSL_QDMA_DMR_DQD		0x40000000
+#define FSL_QDMA_DSR_DB			0x80000000
+
+#define FSL_QDMA_BASE_BUFFER_SIZE	96
+#define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN	64
+#define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX	16384
+#define FSL_QDMA_QUEUE_NUM_MAX		8
+
+#define FSL_QDMA_CMD_DWTTYPE_OFFSET	28
+#define FSL_QDMA_CMD_NS_OFFSET		27
+#define FSL_QDMA_CMD_DQOS_OFFSET	24
+#define FSL_QDMA_CMD_WTHROTL_OFFSET	20
+#define FSL_QDMA_CMD_DSEN_OFFSET	19
+#define FSL_QDMA_CMD_LWC_OFFSET		16
+
+struct fsl_qdma_ccdf {
+	u8 status;
+	u32 resv0:22;
+	u32 ser:1;
+	u32 resv1:1;
+	u32 resv2:20;
+	u32 offset:9;
+	u32 format:3;
+	union {
+		struct {
+			u32 addr_lo;	/* low 32-bits of 40-bit address */
+			u32 addr_hi:8;	/* high 8-bits of 40-bit address */
+			u32 resv3:16;
+			u32 queue:3;
+			u32 resv4:3;
+			u32 dd:2;	/* dynamic debug */
+		};
+		struct {
+			u64 addr:40;
+			/* More efficient address accessor */
+			u64 __notaddress:24;
+		};
+	};
+} __packed;
+
+struct fsl_qdma_csgf {
+	u32 offset:13;
+	u32 resv0:19;
+	u32 length:30;
+	u32 f:1;
+	u32 e:1;
+	union {
+		struct {
+			u32 addr_lo;	/* low 32-bits of 40-bit address */
+			u32 addr_hi:8;	/* high 8-bits of 40-bit address */
+			u32 resv1:24;
+		};
+		struct {
+			u64 addr:40;
+			/* More efficient address accessor */
+			u64 __notaddress:24;
+		};
+	};
+} __packed;
+
+struct fsl_qdma_sdf {
+	u32 resv0:32;
+	u32 ssd:12;	/* souce stride distance */
+	u32 sss:12;	/* souce stride size */
+	u32 resv1:8;
+	u32 resv2:32;
+	u32 cmd;
+} __packed;
+
+struct fsl_qdma_ddf {
+	u32 resv0:32;
+	u32 dsd:12;	/* Destination stride distance */
+	u32 dss:12;	/* Destination stride size */
+	u32 resv1:8;
+	u32 resv2:32;
+	u32 cmd;
+} __packed;
+
+struct fsl_qdma_tcd {
+	u16	saddr_high;
+	u32	saddr;
+	u32	nbytes;
+	u16	daddr_high;
+	u32	daddr;
+};
+
+struct fsl_qdma_sw_tcd {
+	dma_addr_t			ptcd;
+	struct fsl_qdma_tcd		*tcd;
+};
+
+struct fsl_qdma_chan_config {
+	enum dma_transfer_direction	dir;
+	enum dma_slave_buswidth		addr_width;
+	u32				burst;
+	u32				attr;
+};
+
+struct fsl_qdma_chan {
+	struct virt_dma_chan		vchan;
+	struct virt_dma_desc		vdesc;
+	enum dma_status			status;
+	u32				slave_id;
+	struct fsl_qdma_engine		*qdma;
+	struct fsl_qdma_queue		*queue;
+	struct list_head		qcomp;
+};
+
+struct fsl_qdma_queue {
+	struct fsl_qdma_ccdf	*virt_head;
+	struct fsl_qdma_ccdf	*virt_tail;
+	struct list_head	comp_used;
+	struct list_head	comp_free;
+	struct dma_pool		*comp_pool;
+	spinlock_t		queue_lock;
+	dma_addr_t		bus_addr;
+	u32                     n_cq;
+	u32			id;
+	struct fsl_qdma_ccdf	*cq;
+};
+
+struct fsl_qdma_comp {
+	dma_addr_t              bus_addr;
+	void			*virt_addr;
+	struct fsl_qdma_chan	*qchan;
+	struct virt_dma_desc    vdesc;
+	struct list_head	list;
+};
+
+struct fsl_qdma_engine {
+	struct dma_device	dma_dev;
+	void __iomem		*membase;
+	u32			n_chans;
+	u32			n_queues;
+	struct mutex            fsl_qdma_mutex;
+	int			controller_irq;
+	int			queue_irq;
+	bool			big_endian;
+	struct fsl_qdma_queue	*queue;
+	struct fsl_qdma_queue	*status;
+	struct fsl_qdma_chan	chans[];
+
+};
+
+static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr)
+{
+	if (qdma->big_endian)
+		return ioread32be(addr);
+	else
+		return ioread32(addr);
+}
+
+static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
+						void __iomem *addr)
+{
+	if (qdma->big_endian)
+		iowrite32be(val, addr);
+	else
+		iowrite32(val, addr);
+}
+
+static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct fsl_qdma_chan, vchan.chan);
+}
+
+static struct fsl_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
+{
+	return container_of(vd, struct fsl_qdma_comp, vdesc);
+}
+
+static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
+{
+	/*
+	 * In QDMA mode, We don't need to do anything.
+	 */
+	return 0;
+}
+
+static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	unsigned long flags;
+	LIST_HEAD(head);
+
+	spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+	vchan_get_all_descriptors(&fsl_chan->vchan, &head);
+	spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
+
+	vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
+}
+
+static void fsl_qdma_comp_fill(struct fsl_qdma_comp *fsl_comp,
+					u32 dst, u32 src, u32 len)
+{
+	struct fsl_qdma_ccdf *ccdf;
+	struct fsl_qdma_csgf *csgf_desc, *csgf_src, *csgf_dest;
+	struct fsl_qdma_sdf *sdf;
+	struct fsl_qdma_ddf *ddf;
+
+	ccdf = (struct fsl_qdma_ccdf *)fsl_comp->virt_addr;
+	csgf_desc = (struct fsl_qdma_csgf *)fsl_comp->virt_addr + 1;
+	csgf_src = (struct fsl_qdma_csgf *)fsl_comp->virt_addr + 2;
+	csgf_dest = (struct fsl_qdma_csgf *)fsl_comp->virt_addr + 3;
+	sdf = (struct fsl_qdma_sdf *)fsl_comp->virt_addr + 4;
+	ddf = (struct fsl_qdma_ddf *)fsl_comp->virt_addr + 5;
+
+	memset(fsl_comp->virt_addr, 0, FSL_QDMA_BASE_BUFFER_SIZE);
+	/* Head Command Descriptor(Frame Descriptor) */
+	ccdf->addr = fsl_comp->bus_addr + 16;
+	ccdf->format = 1; /* Compound S/G format */
+	ccdf->ser = 1; /* Status notification is enqueued to status queue. */
+	/* Compound Command Descriptor(Frame List Table) */
+	csgf_desc->addr = fsl_comp->bus_addr + 64;
+	csgf_desc->length = 32; /* It must be 32 as Compound S/G Descriptor */
+	csgf_src->addr = src;
+	csgf_src->length = len;
+	csgf_dest->addr = dst;
+	csgf_dest->length = len;
+	csgf_dest->f = 1; /* This entry is the last entry. */
+	/* Descriptor Buffer */
+	sdf->cmd = 0x4 << FSL_QDMA_CMD_DWTTYPE_OFFSET;
+	ddf->cmd = 0x4 << FSL_QDMA_CMD_DWTTYPE_OFFSET;
+}
+
+/*
+ * Request a command descriptor for enqueue.
+ */
+static struct fsl_qdma_comp *fsl_qdma_request_enqueue_desc(
+					struct fsl_qdma_chan *fsl_chan)
+{
+	struct fsl_qdma_comp *comp_temp;
+	struct fsl_qdma_queue *queue = fsl_chan->queue;
+	unsigned long flags;
+
+	spin_lock_irqsave(&queue->queue_lock, flags);
+	if (list_empty(&queue->comp_free)) {
+		spin_unlock_irqrestore(&queue->queue_lock, flags);
+		comp_temp = kzalloc(sizeof(*comp_temp), GFP_KERNEL);
+		if (!comp_temp)
+			return NULL;
+		comp_temp->virt_addr = dma_pool_alloc(queue->comp_pool,
+							GFP_NOWAIT,
+							&comp_temp->bus_addr);
+		if (!comp_temp->virt_addr)
+			return NULL;
+		comp_temp->qchan = fsl_chan;
+		return comp_temp;
+	}
+	comp_temp = list_first_entry(&queue->comp_free, struct fsl_qdma_comp,
+									list);
+	comp_temp->qchan = fsl_chan;
+	list_del(&comp_temp->list);
+	spin_unlock_irqrestore(&queue->queue_lock, flags);
+	return comp_temp;
+}
+
+static struct fsl_qdma_queue *fsl_qdma_alloc_queue_resources(
+					struct platform_device *pdev,
+					unsigned int queue_num)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_queue *queue_head, *queue_temp;
+	int ret, len, i;
+	unsigned int queue_size[FSL_QDMA_QUEUE_MAX];
+
+	if (queue_num > FSL_QDMA_QUEUE_MAX)
+		queue_num = FSL_QDMA_QUEUE_MAX;
+	len = sizeof(*queue_head) * queue_num;
+	queue_head = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
+	if (!queue_head)
+		return NULL;
+
+	ret = of_property_read_u32_array(np, "queue-sizes", queue_size,
+								queue_num);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't get queue-sizes.\n");
+		return NULL;
+	}
+
+	for (i = 0; i < queue_num; i++) {
+		if (queue_size[i] > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX
+			|| queue_size[i] < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
+			dev_err(&pdev->dev, "Get wrong queue-sizes.\n");
+			return NULL;
+		}
+		queue_temp = queue_head + i;
+		queue_temp->cq = dma_alloc_coherent(&pdev->dev,
+						sizeof(struct fsl_qdma_ccdf) *
+						queue_size[i],
+						&queue_temp->bus_addr,
+						GFP_KERNEL);
+		if (!queue_temp->cq)
+			return NULL;
+		queue_temp->n_cq = queue_size[i];
+		queue_temp->id = i;
+		queue_temp->virt_head = queue_temp->cq;
+		queue_temp->virt_tail = queue_temp->cq;
+		/*
+		 * The dma pool for queue command buffer
+		 */
+		queue_temp->comp_pool = dma_pool_create("comp_pool",
+						&pdev->dev,
+						FSL_QDMA_BASE_BUFFER_SIZE,
+						16, 0);
+		if (!queue_temp->comp_pool) {
+			dma_free_coherent(&pdev->dev,
+						sizeof(struct fsl_qdma_ccdf) *
+						queue_size[i],
+						queue_temp->cq,
+						queue_temp->bus_addr);
+			return NULL;
+		}
+		/*
+		 * List for queue command buffer
+		 */
+		INIT_LIST_HEAD(&queue_temp->comp_used);
+		INIT_LIST_HEAD(&queue_temp->comp_free);
+		spin_lock_init(&queue_temp->queue_lock);
+	}
+
+	return queue_head;
+}
+
+static struct fsl_qdma_queue *fsl_qdma_prep_status_queue(
+						struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_queue *status_head;
+	unsigned int status_size;
+	int ret;
+
+	ret = of_property_read_u32(np, "status-sizes", &status_size);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't get status-sizes.\n");
+		return NULL;
+	}
+	if (status_size > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX
+			|| status_size < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
+		dev_err(&pdev->dev, "Get wrong status_size.\n");
+		return NULL;
+	}
+	status_head = devm_kzalloc(&pdev->dev, sizeof(*status_head),
+								GFP_KERNEL);
+	if (!status_head)
+		return NULL;
+
+	/*
+	 * Buffer for queue command
+	 */
+	status_head->cq = dma_alloc_coherent(&pdev->dev,
+						sizeof(struct fsl_qdma_ccdf) *
+						status_size,
+						&status_head->bus_addr,
+						GFP_KERNEL);
+	if (!status_head->cq)
+		return NULL;
+	status_head->n_cq = status_size;
+	status_head->virt_head = status_head->cq;
+	status_head->virt_tail = status_head->cq;
+	status_head->comp_pool = NULL;
+
+	return status_head;
+}
+
+static int fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)
+{
+	void __iomem *addr = fsl_qdma->membase;
+	int i, count = 5;
+	u32 reg;
+
+	/* Disable the command queue and wait for idle state. */
+	reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DMR);
+	reg |= FSL_QDMA_DMR_DQD;
+	qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DMR);
+	for (i = 0; i < FSL_QDMA_QUEUE_NUM_MAX; i++)
+		qdma_writel(fsl_qdma, 0, addr + FSL_QDMA_BCQMR(i));
+
+	while (1) {
+		reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DSR);
+		if (!(reg & FSL_QDMA_DSR_DB))
+			break;
+		if (count-- < 0)
+			return -EBUSY;
+		udelay(100);
+	}
+
+	/* Disable status queue. */
+	qdma_writel(fsl_qdma, 0, addr + FSL_QDMA_BSQMR);
+
+	/*
+	 * Clear the command queue interrupt detect register for all queues.
+	 */
+	qdma_writel(fsl_qdma, 0xffffffff, addr + FSL_QDMA_BCQIDR);
+
+	return 0;
+}
+
+static void fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma)
+{
+	struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
+	struct fsl_qdma_queue *fsl_status = fsl_qdma->status;
+	struct fsl_qdma_queue *temp_queue;
+	struct fsl_qdma_comp *fsl_comp;
+	void __iomem *addr = fsl_qdma->membase;
+	u32 reg, i;
+	u32 *status_addr;
+
+	while (1) {
+		status_addr = (u32 *)fsl_status->virt_head++;
+		if (fsl_status->virt_head == fsl_status->cq + fsl_status->n_cq)
+			fsl_status->virt_head = fsl_status->cq;
+		/*
+		 * Sacn all the queues.
+		 * Match which queue completed this transfer.
+		 */
+		for (i = 0; i < fsl_qdma->n_queues; i++) {
+			temp_queue = fsl_queue + i;
+			if (list_empty(&temp_queue->comp_used))
+				continue;
+			fsl_comp = list_first_entry(&temp_queue->comp_used,
+							struct fsl_qdma_comp,
+							list);
+			if (fsl_comp->bus_addr + 16 != *(u32 *)(status_addr+2))
+				continue;
+			spin_lock(&temp_queue->queue_lock);
+			list_del(&fsl_comp->list);
+			spin_unlock(&temp_queue->queue_lock);
+
+			reg = qdma_readl(fsl_qdma, addr + FSL_QDMA_BSQMR);
+			reg |= FSL_QDMA_BSQMR_DI;
+			qdma_writel(fsl_qdma, reg, addr + FSL_QDMA_BSQMR);
+
+			spin_lock(&fsl_comp->qchan->vchan.lock);
+			vchan_cookie_complete(&fsl_comp->vdesc);
+			fsl_comp->qchan->status = DMA_COMPLETE;
+			spin_unlock(&fsl_comp->qchan->vchan.lock);
+			break;
+		}
+		reg = qdma_readl(fsl_qdma, addr + FSL_QDMA_BSQSR);
+		if (reg & FSL_QDMA_BSQSR_QE)
+			break;
+	}
+}
+
+static irqreturn_t fsl_qdma_controller_handler(int irq, void *dev_id)
+{
+	struct fsl_qdma_engine *fsl_qdma = dev_id;
+	unsigned int intr;
+	void __iomem *base_addr;
+
+	base_addr = fsl_qdma->membase;
+	intr = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DEDR);
+
+	if (intr)
+		dev_err(fsl_qdma->dma_dev.dev,
+				"Programming Errors! Code:0x%x\n", intr);
+	qdma_writel(fsl_qdma, 0xffffffff, fsl_qdma->membase + FSL_QDMA_DEDR);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t fsl_qdma_queue_handler(int irq, void *dev_id)
+{
+	struct fsl_qdma_engine *fsl_qdma = dev_id;
+	unsigned int intr;
+	void __iomem *base_addr;
+
+	base_addr = fsl_qdma->membase;
+	intr = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_BCQIDR);
+
+	if ((intr & FSL_QDMA_CQIDR_SQT) != 0)
+		fsl_qdma_queue_transfer_complete(fsl_qdma);
+
+	qdma_writel(fsl_qdma, 0xffffffff, fsl_qdma->membase + FSL_QDMA_BCQIDR);
+	return IRQ_HANDLED;
+}
+
+static int fsl_qdma_irq_init(struct platform_device *pdev,
+					struct fsl_qdma_engine *fsl_qdma)
+{
+	int ret;
+
+	fsl_qdma->controller_irq = platform_get_irq_byname(pdev,
+							"qdma-controller");
+	if (fsl_qdma->controller_irq < 0) {
+		dev_err(&pdev->dev, "Can't get qdma controller irq.\n");
+		return fsl_qdma->controller_irq;
+	}
+
+	fsl_qdma->queue_irq = platform_get_irq_byname(pdev, "qdma-queue");
+	if (fsl_qdma->queue_irq < 0) {
+		dev_err(&pdev->dev, "Can't get qdma queue irq.\n");
+		return fsl_qdma->queue_irq;
+	}
+
+	ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
+			fsl_qdma_controller_handler, 0, "qDMA controller",
+								fsl_qdma);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't register qDMA controller IRQ.\n");
+		return  ret;
+	}
+	ret = devm_request_irq(&pdev->dev, fsl_qdma->queue_irq,
+			fsl_qdma_queue_handler, 0, "qDMA queue", fsl_qdma);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't register qDMA queue IRQ.\n");
+		return  ret;
+	}
+
+	return 0;
+}
+
+static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
+{
+	struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
+	struct fsl_qdma_queue *temp;
+	void __iomem *addr = fsl_qdma->membase;
+	int i, ret;
+	u32 reg;
+
+	/* Try to halt the qDMA engine first. */
+	ret = fsl_qdma_halt(fsl_qdma);
+	if (ret) {
+		dev_err(fsl_qdma->dma_dev.dev, "DMA halt failed!");
+		return ret;
+	}
+
+	/*
+	 * Clear the command queue interrupt detect register for all queues.
+	 */
+	qdma_writel(fsl_qdma, 0xffffffff, addr + FSL_QDMA_BCQIDR);
+
+	for (i = 0; i < fsl_qdma->n_queues; i++) {
+		temp = fsl_queue + i;
+		/*
+		 * Initialize Command Queue registers to point to the first
+		 * command descriptor in memory.
+		 * Dequeue Pointer Address Registers
+		 * Enqueue Pointer Address Registers
+		 */
+		qdma_writel(fsl_qdma, temp->bus_addr,
+				addr + FSL_QDMA_CQDPA_SADDR(i));
+		qdma_writel(fsl_qdma, temp->bus_addr,
+				addr + FSL_QDMA_CQEPA_SADDR(i));
+
+		/* Initialize the queue mode. */
+		reg = FSL_QDMA_BCQMR_EN;
+		reg |= FSL_QDMA_BCQMR_CD_THLD(ilog2(temp->n_cq)-4);
+		reg |= FSL_QDMA_BCQMR_CQ_SIZE(ilog2(temp->n_cq)-6);
+		qdma_writel(fsl_qdma, reg, addr + FSL_QDMA_BCQMR(i));
+	}
+
+	/*
+	 * Initialize status queue registers to point to the first
+	 * command descriptor in memory.
+	 * Dequeue Pointer Address Registers
+	 * Enqueue Pointer Address Registers
+	 */
+	qdma_writel(fsl_qdma, fsl_qdma->status->bus_addr,
+					addr + FSL_QDMA_SQEPAR);
+	qdma_writel(fsl_qdma, fsl_qdma->status->bus_addr,
+					addr + FSL_QDMA_SQDPAR);
+	/* Initialize status queue interrupt. */
+	qdma_writel(fsl_qdma, FSL_QDMA_BCQIER_CQTIE, addr + FSL_QDMA_BCQIER);
+	qdma_writel(fsl_qdma, FSL_QDMA_BSQICR_ICEN |
+					FSL_QDMA_BSQICR_ICST(ilog2(16) + 1) |
+					FSL_QDMA_BSQICR_ICTT(0xffff),
+						addr + FSL_QDMA_BSQICR);
+	qdma_writel(fsl_qdma, FSL_QDMA_CQIER_MEIE | FSL_QDMA_CQIER_TEIE,
+							addr + FSL_QDMA_CQIER);
+	/* Initialize controller interrupt register. */
+	qdma_writel(fsl_qdma, 0xffffffff, addr + FSL_QDMA_DEDR);
+	qdma_writel(fsl_qdma, 0xffffffff, addr + FSL_QDMA_DEIER);
+
+	/* Set the statue queue critical watermark level. */
+	qdma_writel(fsl_qdma, 0x300000, addr + FSL_QDMA_SQCCMR);
+
+	/* Initialize the status queue mode. */
+	reg = FSL_QDMA_BSQMR_EN;
+	reg |= FSL_QDMA_BSQMR_CQ_SIZE(ilog2(fsl_qdma->status->n_cq)-6);
+	qdma_writel(fsl_qdma, reg, addr + FSL_QDMA_BSQMR);
+
+	reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DMR);
+	reg &= ~FSL_QDMA_DMR_DQD;
+	qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DMR);
+
+	return 0;
+}
+
+static struct dma_async_tx_descriptor *fsl_qdma_prep_dma_sg(
+		struct dma_chan *chan,
+		struct scatterlist *dst_sg, unsigned int dst_nents,
+		struct scatterlist *src_sg, unsigned int src_nents,
+		unsigned long flags)
+{
+	return NULL;
+}
+
+static struct dma_async_tx_descriptor *
+fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
+		dma_addr_t src, size_t len, unsigned long flags)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	struct fsl_qdma_comp *fsl_comp;
+
+	fsl_comp = fsl_qdma_request_enqueue_desc(fsl_chan);
+	fsl_qdma_comp_fill(fsl_comp, dst, src, len);
+
+	return vchan_tx_prep(&fsl_chan->vchan, &fsl_comp->vdesc, flags);
+}
+
+static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
+{
+	void __iomem *addr = fsl_chan->qdma->membase;
+	struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
+	struct fsl_qdma_comp *fsl_comp;
+	struct virt_dma_desc *vdesc;
+	u32 reg;
+
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_BCQSR(fsl_queue->id));
+	if (reg & FSL_QDMA_BCQSR_QF) {
+		dev_err(fsl_chan->qdma->dma_dev.dev, "Enqueue rejection!\n");
+		return;
+	}
+
+	vdesc = vchan_next_desc(&fsl_chan->vchan);
+	if (!vdesc)
+		return;
+	list_del(&vdesc->node);
+	fsl_comp = to_fsl_qdma_comp(vdesc);
+
+	memcpy(fsl_queue->virt_head++, fsl_comp->virt_addr, 16);
+	if (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq)
+		fsl_queue->virt_head = fsl_queue->cq;
+
+	list_add_tail(&fsl_comp->list, &fsl_queue->comp_used);
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_BCQMR(fsl_queue->id));
+	reg |= FSL_QDMA_BCQMR_EI;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_BCQMR(fsl_queue->id));
+	fsl_chan->status = DMA_IN_PROGRESS;
+}
+
+static enum dma_status fsl_qdma_tx_status(struct dma_chan *chan,
+		dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
+	return dma_cookie_status(chan, cookie, txstate);
+}
+
+static void fsl_qdma_free_desc(struct virt_dma_desc *vdesc)
+{
+	struct fsl_qdma_comp *fsl_comp;
+	struct fsl_qdma_queue *fsl_queue;
+	unsigned long flags;
+
+	fsl_comp = to_fsl_qdma_comp(vdesc);
+	fsl_queue = fsl_comp->qchan->queue;
+
+	spin_lock_irqsave(&fsl_queue->queue_lock, flags);
+	list_add_tail(&fsl_comp->list, &fsl_queue->comp_free);
+	spin_unlock_irqrestore(&fsl_queue->queue_lock, flags);
+}
+
+static void fsl_qdma_issue_pending(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsl_queue->queue_lock, flags);
+	spin_lock(&fsl_chan->vchan.lock);
+	if (vchan_issue_pending(&fsl_chan->vchan))
+		fsl_qdma_enqueue_desc(fsl_chan);
+	spin_unlock(&fsl_chan->vchan.lock);
+	spin_unlock_irqrestore(&fsl_queue->queue_lock, flags);
+}
+
+static int fsl_qdma_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_engine *fsl_qdma;
+	struct fsl_qdma_chan *fsl_chan;
+	struct resource *res;
+	unsigned int len, chans, queues;
+	int ret, i;
+
+	ret = of_property_read_u32(np, "channels", &chans);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't get channels.\n");
+		return ret;
+	}
+
+	len = sizeof(*fsl_qdma) + sizeof(*fsl_chan) * chans;
+	fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
+	if (!fsl_qdma)
+		return -ENOMEM;
+
+	ret = of_property_read_u32(np, "queues", &queues);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't get queues.\n");
+		return ret;
+	}
+
+	fsl_qdma->queue = fsl_qdma_alloc_queue_resources(pdev, queues);
+	if (!fsl_qdma->queue)
+		return -ENOMEM;
+
+	fsl_qdma->status = fsl_qdma_prep_status_queue(pdev);
+	if (!fsl_qdma->status)
+		return -ENOMEM;
+
+	fsl_qdma->n_chans = chans;
+	fsl_qdma->n_queues = queues;
+	mutex_init(&fsl_qdma->fsl_qdma_mutex);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	fsl_qdma->membase = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(fsl_qdma->membase))
+		return PTR_ERR(fsl_qdma->membase);
+
+	ret = fsl_qdma_irq_init(pdev, fsl_qdma);
+	if (ret)
+		return ret;
+
+	fsl_qdma->big_endian = of_property_read_bool(np, "big-endian");
+	INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
+	for (i = 0; i < fsl_qdma->n_chans; i++) {
+		struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
+
+		fsl_chan->qdma = fsl_qdma;
+		fsl_chan->queue = fsl_qdma->queue + i%fsl_qdma->n_queues;
+		fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
+		INIT_LIST_HEAD(&fsl_chan->qcomp);
+		vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
+	}
+
+	dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
+	dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
+	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
+
+	fsl_qdma->dma_dev.dev = &pdev->dev;
+	fsl_qdma->dma_dev.device_alloc_chan_resources
+		= fsl_qdma_alloc_chan_resources;
+	fsl_qdma->dma_dev.device_free_chan_resources
+		= fsl_qdma_free_chan_resources;
+	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
+	fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
+	fsl_qdma->dma_dev.device_prep_dma_sg = fsl_qdma_prep_dma_sg;
+	fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
+
+	platform_set_drvdata(pdev, fsl_qdma);
+
+	ret = dma_async_device_register(&fsl_qdma->dma_dev);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't register Freescale qDMA engine.\n");
+		return ret;
+	}
+
+	ret = fsl_qdma_reg_init(fsl_qdma);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n");
+		return ret;
+	}
+
+
+	return 0;
+}
+
+static int fsl_qdma_remove(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
+	struct fsl_qdma_queue *queue_temp;
+	struct fsl_qdma_queue *status = fsl_qdma->status;
+	struct fsl_qdma_comp *comp_temp, *_comp_temp;
+	int i;
+
+	of_dma_controller_free(np);
+	dma_async_device_unregister(&fsl_qdma->dma_dev);
+
+	/* Free descriptor areas */
+	for (i = 0; i < fsl_qdma->n_queues; i++) {
+		queue_temp = fsl_qdma->queue + i;
+		list_for_each_entry_safe(comp_temp, _comp_temp,
+					&queue_temp->comp_used,	list) {
+			dma_pool_free(queue_temp->comp_pool,
+					comp_temp->virt_addr,
+					comp_temp->bus_addr);
+			list_del(&comp_temp->list);
+			kfree(comp_temp);
+		}
+		list_for_each_entry_safe(comp_temp, _comp_temp,
+					&queue_temp->comp_free, list) {
+			dma_pool_free(queue_temp->comp_pool,
+					comp_temp->virt_addr,
+					comp_temp->bus_addr);
+			list_del(&comp_temp->list);
+			kfree(comp_temp);
+		}
+		dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_ccdf) *
+					queue_temp->n_cq, queue_temp->cq,
+					queue_temp->bus_addr);
+		dma_pool_destroy(queue_temp->comp_pool);
+	}
+
+	dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_ccdf) *
+				status->n_cq, status->cq, status->bus_addr);
+	return 0;
+}
+
+static const struct of_device_id fsl_qdma_dt_ids[] = {
+	{ .compatible = "fsl,ls1021a-qdma", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fsl_qdma_dt_ids);
+
+static struct platform_driver fsl_qdma_driver = {
+	.driver		= {
+		.name	= "fsl-qdma",
+		.owner  = THIS_MODULE,
+		.of_match_table = fsl_qdma_dt_ids,
+	},
+	.probe          = fsl_qdma_probe,
+	.remove		= fsl_qdma_remove,
+};
+
+static int __init fsl_qdma_init(void)
+{
+	return platform_driver_register(&fsl_qdma_driver);
+}
+subsys_initcall(fsl_qdma_init);
+
+static void __exit fsl_qdma_exit(void)
+{
+	platform_driver_unregister(&fsl_qdma_driver);
+}
+module_exit(fsl_qdma_exit);
+
+MODULE_ALIAS("platform:fsl-qdma");
+MODULE_DESCRIPTION("Freescale qDMA engine driver");
+MODULE_LICENSE("GPL v2");
-- 
2.1.0.27.g96db324

[PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Yuan Yao]

Add Freescale Queue Direct Memory Access (qDMA) controller support.
The qDMA supports channel virtualization by allowing DMA jobs to be
enqueued into different command queues. Core can initiate a DMA
transaction by preparing a command descriptor (CD) for each DMA job
and enqueuing this job to a command queue.

This module can be found on LS-1021 LS1043 and LS2085 SoCs.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
---
 Documentation/devicetree/bindings/dma/fsl-qdma.txt |  51 ++
 drivers/dma/Kconfig                                |  11 +
 drivers/dma/Makefile                               |   1 +
 drivers/dma/fsl-qdma.c                             | 929 +++++++++++++++++++++
 4 files changed, 992 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
 create mode 100644 drivers/dma/fsl-qdma.c

diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
new file mode 100644
index 0000000..676ae3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
@@ -0,0 +1,50 @@
+* Freescale queue Direct Memory Access Controller(qDMA) Controller
+
+  The qDMA controller transfers blocks of data between one source and one or more
+destinations. The blocks of data transferred can be represented in memory as contiguous
+or non-contiguous using scatter/gather table(s). Channel virtualization is supported
+through enqueuing of DMA jobs to, or dequeuing DMA jobs from, different work
+queues.
+
+* qDMA Controller
+Required properties:
+- compatible :
+	- "fsl,ls1021a-qdma" for qDMA used similar to that on LS1021a SoC
+- reg : Specifies base physical address(s) and size of the qDMA registers.
+	The region is qDMA control register's address and size.
+- interrupts : A list of interrupt-specifiers, one for each entry in
+	interrupt-names.
+- interrupt-names : Should contain:
+	"qdma-controller" - the controller interrupt
+	"qdma-queue" - the queue interrupt
+- status-sizes : Number of circular status descriptor queue size
+- channels : Number of channels supported by the controller
+- queues : Number of queues supported by the controller
+- queue-sizes : Number of circular descriptor queue size for each queue
+- queue-group : The group for each queue belong to
+- queue-weight : The weight for each queue belog to
+- default-queue : The default queue for request a new channel
+
+Optional properties:
+- big-endian: If present registers and hardware scatter/gather descriptors
+	of the qDMA are implemented in big endian mode, otherwise in little
+	mode.
+
+
+Examples:
+
+	qdma: qdma at 8390000 {
+		compatible = "fsl,ls1021a-qdma";
+		reg = <0x0 0x8390000 0x0 0x10000>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "qdma-controller", "qdma-queue";
+		status-sizes = <64>;
+		channels = <8>;
+		queues = <2>;
+		queue-sizes = <256 256>;
+		queue-group = <0 1>;
+		queue-weight = <0 0>;
+		default-queue = <0>;
+		big-endian;
+	};
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 074ffad..fa52c9e 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -388,6 +388,17 @@ config FSL_EDMA
 	  multiplexing capability for DMA request sources(slot).
 	  This module can be found on Freescale Vybrid and LS-1 SoCs.
 
+config FSL_QDMA
+	tristate "Freescale qDMA engine support"
+	depends on OF
+	select DMA_ENGINE
+	select DMA_VIRTUAL_CHANNELS
+	help
+	  Support the Freescale qDMA engine with command queue and legacy mode.
+	  Channel virtualization is supported through enqueuing of DMA jobs to,
+	  or dequeuing DMA jobs from, different work queues.
+	  This module can be found on Freescale LS SoCs.
+
 config XILINX_VDMA
 	tristate "Xilinx AXI VDMA Engine"
 	depends on (ARCH_ZYNQ || MICROBLAZE)
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index bf44858..5f2b95e 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_TI_CPPI41) += cppi41.o
 obj-$(CONFIG_K3_DMA) += k3dma.o
 obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
 obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o
 obj-y += xilinx/
 obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
new file mode 100644
index 0000000..00f3c33
--- /dev/null
+++ b/drivers/dma/fsl-qdma.c
@@ -0,0 +1,929 @@
+/*
+ * drivers/dma/fsl-qdma.c
+ *
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Driver for the Freescale qDMA engine with command queue and legacy mode.
+ * Channel virtualization is supported through enqueuing of DMA jobs to,
+ * or dequeuing DMA jobs from, different work queues.
+ * This module can be found on Freescale LS SoCs.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <asm/cacheflush.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "virt-dma.h"
+
+#define FSL_QDMA_DMR			0x8000
+#define FSL_QDMA_DSR			0x8004
+#define FSL_QDMA_DEIER			0x9e00
+#define FSL_QDMA_DEDR			0x9e04
+#define FSL_QDMA_DECFDW0R		0x9e10
+#define FSL_QDMA_DECFDW1R		0x9e14
+#define FSL_QDMA_DECFDW2R		0x9e18
+#define FSL_QDMA_DECFDW3R		0x9e1c
+#define FSL_QDMA_DECFQIDR		0x9e30
+#define FSL_QDMA_DECBR			0x9e34
+
+#define FSL_QDMA_BCQMR(x)		(0xa0c0 + 0x100 * (x))
+#define FSL_QDMA_BCQSR(x)		(0xa0c4 + 0x100 * (x))
+#define FSL_QDMA_SQDPAR			0xa80c
+#define FSL_QDMA_SQEPAR			0xa814
+#define FSL_QDMA_BSQMR			0xa800
+#define FSL_QDMA_BSQSR			0xa804
+#define FSL_QDMA_BCQIER			0xa0e0
+#define FSL_QDMA_BSQICR			0xa828
+#define FSL_QDMA_CQIER			0xaa10
+#define FSL_QDMA_SQCCMR			0xaa20
+#define FSL_QDMA_BCQIDR			0xa0e4
+#define FSL_QDMA_CQDPA_SADDR(x)		(0xa0cc + 0x100 * (x))
+#define FSL_QDMA_CQEPA_SADDR(x)		(0xa0d4 + 0x100 * (x))
+
+#define FSL_QDMA_SQICR_ICEN
+
+#define FSL_QDMA_CQIDR_CQT		0xff000000
+#define FSL_QDMA_CQIDR_SQPE		0x800000
+#define FSL_QDMA_CQIDR_SQT		0x8000
+
+#define FSL_QDMA_BCQIER_CQTIE		0x8000
+#define FSL_QDMA_BCQIER_CQPEIE		0x800000
+#define FSL_QDMA_BSQICR_ICEN		0x80000000
+#define FSL_QDMA_BSQICR_ICST(x)		((x) << 16)
+#define FSL_QDMA_BSQICR_ICTT(x)		((x) & 0xffff)
+#define FSL_QDMA_CQIER_MEIE		0x80000000
+#define FSL_QDMA_CQIER_TEIE		0x1
+
+#define FSL_QDMA_QUEUE_MAX		8
+
+#define FSL_QDMA_BCQMR_EN		0x80000000
+#define FSL_QDMA_BCQMR_EI		0x40000000
+#define FSL_QDMA_BCQMR_CD_THLD(x)	((x) << 20)
+#define FSL_QDMA_BCQMR_CQ_SIZE(x)	((x) << 16)
+
+#define FSL_QDMA_BCQSR_QF		0x10000
+
+#define FSL_QDMA_BSQMR_EN		0x80000000
+#define FSL_QDMA_BSQMR_DI		0x40000000
+#define FSL_QDMA_BSQMR_CQ_SIZE(x)	((x) << 16)
+
+#define FSL_QDMA_BSQSR_QE		0x20000
+
+#define FSL_QDMA_DMR_DQD		0x40000000
+#define FSL_QDMA_DSR_DB			0x80000000
+
+#define FSL_QDMA_BASE_BUFFER_SIZE	96
+#define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN	64
+#define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX	16384
+#define FSL_QDMA_QUEUE_NUM_MAX		8
+
+#define FSL_QDMA_CMD_DWTTYPE_OFFSET	28
+#define FSL_QDMA_CMD_NS_OFFSET		27
+#define FSL_QDMA_CMD_DQOS_OFFSET	24
+#define FSL_QDMA_CMD_WTHROTL_OFFSET	20
+#define FSL_QDMA_CMD_DSEN_OFFSET	19
+#define FSL_QDMA_CMD_LWC_OFFSET		16
+
+struct fsl_qdma_ccdf {
+	u8 status;
+	u32 resv0:22;
+	u32 ser:1;
+	u32 resv1:1;
+	u32 resv2:20;
+	u32 offset:9;
+	u32 format:3;
+	union {
+		struct {
+			u32 addr_lo;	/* low 32-bits of 40-bit address */
+			u32 addr_hi:8;	/* high 8-bits of 40-bit address */
+			u32 resv3:16;
+			u32 queue:3;
+			u32 resv4:3;
+			u32 dd:2;	/* dynamic debug */
+		};
+		struct {
+			u64 addr:40;
+			/* More efficient address accessor */
+			u64 __notaddress:24;
+		};
+	};
+} __packed;
+
+struct fsl_qdma_csgf {
+	u32 offset:13;
+	u32 resv0:19;
+	u32 length:30;
+	u32 f:1;
+	u32 e:1;
+	union {
+		struct {
+			u32 addr_lo;	/* low 32-bits of 40-bit address */
+			u32 addr_hi:8;	/* high 8-bits of 40-bit address */
+			u32 resv1:24;
+		};
+		struct {
+			u64 addr:40;
+			/* More efficient address accessor */
+			u64 __notaddress:24;
+		};
+	};
+} __packed;
+
+struct fsl_qdma_sdf {
+	u32 resv0:32;
+	u32 ssd:12;	/* souce stride distance */
+	u32 sss:12;	/* souce stride size */
+	u32 resv1:8;
+	u32 resv2:32;
+	u32 cmd;
+} __packed;
+
+struct fsl_qdma_ddf {
+	u32 resv0:32;
+	u32 dsd:12;	/* Destination stride distance */
+	u32 dss:12;	/* Destination stride size */
+	u32 resv1:8;
+	u32 resv2:32;
+	u32 cmd;
+} __packed;
+
+struct fsl_qdma_tcd {
+	u16	saddr_high;
+	u32	saddr;
+	u32	nbytes;
+	u16	daddr_high;
+	u32	daddr;
+};
+
+struct fsl_qdma_sw_tcd {
+	dma_addr_t			ptcd;
+	struct fsl_qdma_tcd		*tcd;
+};
+
+struct fsl_qdma_chan_config {
+	enum dma_transfer_direction	dir;
+	enum dma_slave_buswidth		addr_width;
+	u32				burst;
+	u32				attr;
+};
+
+struct fsl_qdma_chan {
+	struct virt_dma_chan		vchan;
+	struct virt_dma_desc		vdesc;
+	enum dma_status			status;
+	u32				slave_id;
+	struct fsl_qdma_engine		*qdma;
+	struct fsl_qdma_queue		*queue;
+	struct list_head		qcomp;
+};
+
+struct fsl_qdma_queue {
+	struct fsl_qdma_ccdf	*virt_head;
+	struct fsl_qdma_ccdf	*virt_tail;
+	struct list_head	comp_used;
+	struct list_head	comp_free;
+	struct dma_pool		*comp_pool;
+	spinlock_t		queue_lock;
+	dma_addr_t		bus_addr;
+	u32                     n_cq;
+	u32			id;
+	struct fsl_qdma_ccdf	*cq;
+};
+
+struct fsl_qdma_comp {
+	dma_addr_t              bus_addr;
+	void			*virt_addr;
+	struct fsl_qdma_chan	*qchan;
+	struct virt_dma_desc    vdesc;
+	struct list_head	list;
+};
+
+struct fsl_qdma_engine {
+	struct dma_device	dma_dev;
+	void __iomem		*membase;
+	u32			n_chans;
+	u32			n_queues;
+	struct mutex            fsl_qdma_mutex;
+	int			controller_irq;
+	int			queue_irq;
+	bool			big_endian;
+	struct fsl_qdma_queue	*queue;
+	struct fsl_qdma_queue	*status;
+	struct fsl_qdma_chan	chans[];
+
+};
+
+static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr)
+{
+	if (qdma->big_endian)
+		return ioread32be(addr);
+	else
+		return ioread32(addr);
+}
+
+static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
+						void __iomem *addr)
+{
+	if (qdma->big_endian)
+		iowrite32be(val, addr);
+	else
+		iowrite32(val, addr);
+}
+
+static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct fsl_qdma_chan, vchan.chan);
+}
+
+static struct fsl_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
+{
+	return container_of(vd, struct fsl_qdma_comp, vdesc);
+}
+
+static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
+{
+	/*
+	 * In QDMA mode, We don't need to do anything.
+	 */
+	return 0;
+}
+
+static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	unsigned long flags;
+	LIST_HEAD(head);
+
+	spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+	vchan_get_all_descriptors(&fsl_chan->vchan, &head);
+	spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
+
+	vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
+}
+
+static void fsl_qdma_comp_fill(struct fsl_qdma_comp *fsl_comp,
+					u32 dst, u32 src, u32 len)
+{
+	struct fsl_qdma_ccdf *ccdf;
+	struct fsl_qdma_csgf *csgf_desc, *csgf_src, *csgf_dest;
+	struct fsl_qdma_sdf *sdf;
+	struct fsl_qdma_ddf *ddf;
+
+	ccdf = (struct fsl_qdma_ccdf *)fsl_comp->virt_addr;
+	csgf_desc = (struct fsl_qdma_csgf *)fsl_comp->virt_addr + 1;
+	csgf_src = (struct fsl_qdma_csgf *)fsl_comp->virt_addr + 2;
+	csgf_dest = (struct fsl_qdma_csgf *)fsl_comp->virt_addr + 3;
+	sdf = (struct fsl_qdma_sdf *)fsl_comp->virt_addr + 4;
+	ddf = (struct fsl_qdma_ddf *)fsl_comp->virt_addr + 5;
+
+	memset(fsl_comp->virt_addr, 0, FSL_QDMA_BASE_BUFFER_SIZE);
+	/* Head Command Descriptor(Frame Descriptor) */
+	ccdf->addr = fsl_comp->bus_addr + 16;
+	ccdf->format = 1; /* Compound S/G format */
+	ccdf->ser = 1; /* Status notification is enqueued to status queue. */
+	/* Compound Command Descriptor(Frame List Table) */
+	csgf_desc->addr = fsl_comp->bus_addr + 64;
+	csgf_desc->length = 32; /* It must be 32 as Compound S/G Descriptor */
+	csgf_src->addr = src;
+	csgf_src->length = len;
+	csgf_dest->addr = dst;
+	csgf_dest->length = len;
+	csgf_dest->f = 1; /* This entry is the last entry. */
+	/* Descriptor Buffer */
+	sdf->cmd = 0x4 << FSL_QDMA_CMD_DWTTYPE_OFFSET;
+	ddf->cmd = 0x4 << FSL_QDMA_CMD_DWTTYPE_OFFSET;
+}
+
+/*
+ * Request a command descriptor for enqueue.
+ */
+static struct fsl_qdma_comp *fsl_qdma_request_enqueue_desc(
+					struct fsl_qdma_chan *fsl_chan)
+{
+	struct fsl_qdma_comp *comp_temp;
+	struct fsl_qdma_queue *queue = fsl_chan->queue;
+	unsigned long flags;
+
+	spin_lock_irqsave(&queue->queue_lock, flags);
+	if (list_empty(&queue->comp_free)) {
+		spin_unlock_irqrestore(&queue->queue_lock, flags);
+		comp_temp = kzalloc(sizeof(*comp_temp), GFP_KERNEL);
+		if (!comp_temp)
+			return NULL;
+		comp_temp->virt_addr = dma_pool_alloc(queue->comp_pool,
+							GFP_NOWAIT,
+							&comp_temp->bus_addr);
+		if (!comp_temp->virt_addr)
+			return NULL;
+		comp_temp->qchan = fsl_chan;
+		return comp_temp;
+	}
+	comp_temp = list_first_entry(&queue->comp_free, struct fsl_qdma_comp,
+									list);
+	comp_temp->qchan = fsl_chan;
+	list_del(&comp_temp->list);
+	spin_unlock_irqrestore(&queue->queue_lock, flags);
+	return comp_temp;
+}
+
+static struct fsl_qdma_queue *fsl_qdma_alloc_queue_resources(
+					struct platform_device *pdev,
+					unsigned int queue_num)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_queue *queue_head, *queue_temp;
+	int ret, len, i;
+	unsigned int queue_size[FSL_QDMA_QUEUE_MAX];
+
+	if (queue_num > FSL_QDMA_QUEUE_MAX)
+		queue_num = FSL_QDMA_QUEUE_MAX;
+	len = sizeof(*queue_head) * queue_num;
+	queue_head = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
+	if (!queue_head)
+		return NULL;
+
+	ret = of_property_read_u32_array(np, "queue-sizes", queue_size,
+								queue_num);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't get queue-sizes.\n");
+		return NULL;
+	}
+
+	for (i = 0; i < queue_num; i++) {
+		if (queue_size[i] > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX
+			|| queue_size[i] < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
+			dev_err(&pdev->dev, "Get wrong queue-sizes.\n");
+			return NULL;
+		}
+		queue_temp = queue_head + i;
+		queue_temp->cq = dma_alloc_coherent(&pdev->dev,
+						sizeof(struct fsl_qdma_ccdf) *
+						queue_size[i],
+						&queue_temp->bus_addr,
+						GFP_KERNEL);
+		if (!queue_temp->cq)
+			return NULL;
+		queue_temp->n_cq = queue_size[i];
+		queue_temp->id = i;
+		queue_temp->virt_head = queue_temp->cq;
+		queue_temp->virt_tail = queue_temp->cq;
+		/*
+		 * The dma pool for queue command buffer
+		 */
+		queue_temp->comp_pool = dma_pool_create("comp_pool",
+						&pdev->dev,
+						FSL_QDMA_BASE_BUFFER_SIZE,
+						16, 0);
+		if (!queue_temp->comp_pool) {
+			dma_free_coherent(&pdev->dev,
+						sizeof(struct fsl_qdma_ccdf) *
+						queue_size[i],
+						queue_temp->cq,
+						queue_temp->bus_addr);
+			return NULL;
+		}
+		/*
+		 * List for queue command buffer
+		 */
+		INIT_LIST_HEAD(&queue_temp->comp_used);
+		INIT_LIST_HEAD(&queue_temp->comp_free);
+		spin_lock_init(&queue_temp->queue_lock);
+	}
+
+	return queue_head;
+}
+
+static struct fsl_qdma_queue *fsl_qdma_prep_status_queue(
+						struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_queue *status_head;
+	unsigned int status_size;
+	int ret;
+
+	ret = of_property_read_u32(np, "status-sizes", &status_size);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't get status-sizes.\n");
+		return NULL;
+	}
+	if (status_size > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX
+			|| status_size < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
+		dev_err(&pdev->dev, "Get wrong status_size.\n");
+		return NULL;
+	}
+	status_head = devm_kzalloc(&pdev->dev, sizeof(*status_head),
+								GFP_KERNEL);
+	if (!status_head)
+		return NULL;
+
+	/*
+	 * Buffer for queue command
+	 */
+	status_head->cq = dma_alloc_coherent(&pdev->dev,
+						sizeof(struct fsl_qdma_ccdf) *
+						status_size,
+						&status_head->bus_addr,
+						GFP_KERNEL);
+	if (!status_head->cq)
+		return NULL;
+	status_head->n_cq = status_size;
+	status_head->virt_head = status_head->cq;
+	status_head->virt_tail = status_head->cq;
+	status_head->comp_pool = NULL;
+
+	return status_head;
+}
+
+static int fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)
+{
+	void __iomem *addr = fsl_qdma->membase;
+	int i, count = 5;
+	u32 reg;
+
+	/* Disable the command queue and wait for idle state. */
+	reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DMR);
+	reg |= FSL_QDMA_DMR_DQD;
+	qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DMR);
+	for (i = 0; i < FSL_QDMA_QUEUE_NUM_MAX; i++)
+		qdma_writel(fsl_qdma, 0, addr + FSL_QDMA_BCQMR(i));
+
+	while (1) {
+		reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DSR);
+		if (!(reg & FSL_QDMA_DSR_DB))
+			break;
+		if (count-- < 0)
+			return -EBUSY;
+		udelay(100);
+	}
+
+	/* Disable status queue. */
+	qdma_writel(fsl_qdma, 0, addr + FSL_QDMA_BSQMR);
+
+	/*
+	 * Clear the command queue interrupt detect register for all queues.
+	 */
+	qdma_writel(fsl_qdma, 0xffffffff, addr + FSL_QDMA_BCQIDR);
+
+	return 0;
+}
+
+static void fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma)
+{
+	struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
+	struct fsl_qdma_queue *fsl_status = fsl_qdma->status;
+	struct fsl_qdma_queue *temp_queue;
+	struct fsl_qdma_comp *fsl_comp;
+	void __iomem *addr = fsl_qdma->membase;
+	u32 reg, i;
+	u32 *status_addr;
+
+	while (1) {
+		status_addr = (u32 *)fsl_status->virt_head++;
+		if (fsl_status->virt_head == fsl_status->cq + fsl_status->n_cq)
+			fsl_status->virt_head = fsl_status->cq;
+		/*
+		 * Sacn all the queues.
+		 * Match which queue completed this transfer.
+		 */
+		for (i = 0; i < fsl_qdma->n_queues; i++) {
+			temp_queue = fsl_queue + i;
+			if (list_empty(&temp_queue->comp_used))
+				continue;
+			fsl_comp = list_first_entry(&temp_queue->comp_used,
+							struct fsl_qdma_comp,
+							list);
+			if (fsl_comp->bus_addr + 16 != *(u32 *)(status_addr+2))
+				continue;
+			spin_lock(&temp_queue->queue_lock);
+			list_del(&fsl_comp->list);
+			spin_unlock(&temp_queue->queue_lock);
+
+			reg = qdma_readl(fsl_qdma, addr + FSL_QDMA_BSQMR);
+			reg |= FSL_QDMA_BSQMR_DI;
+			qdma_writel(fsl_qdma, reg, addr + FSL_QDMA_BSQMR);
+
+			spin_lock(&fsl_comp->qchan->vchan.lock);
+			vchan_cookie_complete(&fsl_comp->vdesc);
+			fsl_comp->qchan->status = DMA_COMPLETE;
+			spin_unlock(&fsl_comp->qchan->vchan.lock);
+			break;
+		}
+		reg = qdma_readl(fsl_qdma, addr + FSL_QDMA_BSQSR);
+		if (reg & FSL_QDMA_BSQSR_QE)
+			break;
+	}
+}
+
+static irqreturn_t fsl_qdma_controller_handler(int irq, void *dev_id)
+{
+	struct fsl_qdma_engine *fsl_qdma = dev_id;
+	unsigned int intr;
+	void __iomem *base_addr;
+
+	base_addr = fsl_qdma->membase;
+	intr = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DEDR);
+
+	if (intr)
+		dev_err(fsl_qdma->dma_dev.dev,
+				"Programming Errors! Code:0x%x\n", intr);
+	qdma_writel(fsl_qdma, 0xffffffff, fsl_qdma->membase + FSL_QDMA_DEDR);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t fsl_qdma_queue_handler(int irq, void *dev_id)
+{
+	struct fsl_qdma_engine *fsl_qdma = dev_id;
+	unsigned int intr;
+	void __iomem *base_addr;
+
+	base_addr = fsl_qdma->membase;
+	intr = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_BCQIDR);
+
+	if ((intr & FSL_QDMA_CQIDR_SQT) != 0)
+		fsl_qdma_queue_transfer_complete(fsl_qdma);
+
+	qdma_writel(fsl_qdma, 0xffffffff, fsl_qdma->membase + FSL_QDMA_BCQIDR);
+	return IRQ_HANDLED;
+}
+
+static int fsl_qdma_irq_init(struct platform_device *pdev,
+					struct fsl_qdma_engine *fsl_qdma)
+{
+	int ret;
+
+	fsl_qdma->controller_irq = platform_get_irq_byname(pdev,
+							"qdma-controller");
+	if (fsl_qdma->controller_irq < 0) {
+		dev_err(&pdev->dev, "Can't get qdma controller irq.\n");
+		return fsl_qdma->controller_irq;
+	}
+
+	fsl_qdma->queue_irq = platform_get_irq_byname(pdev, "qdma-queue");
+	if (fsl_qdma->queue_irq < 0) {
+		dev_err(&pdev->dev, "Can't get qdma queue irq.\n");
+		return fsl_qdma->queue_irq;
+	}
+
+	ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
+			fsl_qdma_controller_handler, 0, "qDMA controller",
+								fsl_qdma);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't register qDMA controller IRQ.\n");
+		return  ret;
+	}
+	ret = devm_request_irq(&pdev->dev, fsl_qdma->queue_irq,
+			fsl_qdma_queue_handler, 0, "qDMA queue", fsl_qdma);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't register qDMA queue IRQ.\n");
+		return  ret;
+	}
+
+	return 0;
+}
+
+static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
+{
+	struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
+	struct fsl_qdma_queue *temp;
+	void __iomem *addr = fsl_qdma->membase;
+	int i, ret;
+	u32 reg;
+
+	/* Try to halt the qDMA engine first. */
+	ret = fsl_qdma_halt(fsl_qdma);
+	if (ret) {
+		dev_err(fsl_qdma->dma_dev.dev, "DMA halt failed!");
+		return ret;
+	}
+
+	/*
+	 * Clear the command queue interrupt detect register for all queues.
+	 */
+	qdma_writel(fsl_qdma, 0xffffffff, addr + FSL_QDMA_BCQIDR);
+
+	for (i = 0; i < fsl_qdma->n_queues; i++) {
+		temp = fsl_queue + i;
+		/*
+		 * Initialize Command Queue registers to point to the first
+		 * command descriptor in memory.
+		 * Dequeue Pointer Address Registers
+		 * Enqueue Pointer Address Registers
+		 */
+		qdma_writel(fsl_qdma, temp->bus_addr,
+				addr + FSL_QDMA_CQDPA_SADDR(i));
+		qdma_writel(fsl_qdma, temp->bus_addr,
+				addr + FSL_QDMA_CQEPA_SADDR(i));
+
+		/* Initialize the queue mode. */
+		reg = FSL_QDMA_BCQMR_EN;
+		reg |= FSL_QDMA_BCQMR_CD_THLD(ilog2(temp->n_cq)-4);
+		reg |= FSL_QDMA_BCQMR_CQ_SIZE(ilog2(temp->n_cq)-6);
+		qdma_writel(fsl_qdma, reg, addr + FSL_QDMA_BCQMR(i));
+	}
+
+	/*
+	 * Initialize status queue registers to point to the first
+	 * command descriptor in memory.
+	 * Dequeue Pointer Address Registers
+	 * Enqueue Pointer Address Registers
+	 */
+	qdma_writel(fsl_qdma, fsl_qdma->status->bus_addr,
+					addr + FSL_QDMA_SQEPAR);
+	qdma_writel(fsl_qdma, fsl_qdma->status->bus_addr,
+					addr + FSL_QDMA_SQDPAR);
+	/* Initialize status queue interrupt. */
+	qdma_writel(fsl_qdma, FSL_QDMA_BCQIER_CQTIE, addr + FSL_QDMA_BCQIER);
+	qdma_writel(fsl_qdma, FSL_QDMA_BSQICR_ICEN |
+					FSL_QDMA_BSQICR_ICST(ilog2(16) + 1) |
+					FSL_QDMA_BSQICR_ICTT(0xffff),
+						addr + FSL_QDMA_BSQICR);
+	qdma_writel(fsl_qdma, FSL_QDMA_CQIER_MEIE | FSL_QDMA_CQIER_TEIE,
+							addr + FSL_QDMA_CQIER);
+	/* Initialize controller interrupt register. */
+	qdma_writel(fsl_qdma, 0xffffffff, addr + FSL_QDMA_DEDR);
+	qdma_writel(fsl_qdma, 0xffffffff, addr + FSL_QDMA_DEIER);
+
+	/* Set the statue queue critical watermark level. */
+	qdma_writel(fsl_qdma, 0x300000, addr + FSL_QDMA_SQCCMR);
+
+	/* Initialize the status queue mode. */
+	reg = FSL_QDMA_BSQMR_EN;
+	reg |= FSL_QDMA_BSQMR_CQ_SIZE(ilog2(fsl_qdma->status->n_cq)-6);
+	qdma_writel(fsl_qdma, reg, addr + FSL_QDMA_BSQMR);
+
+	reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DMR);
+	reg &= ~FSL_QDMA_DMR_DQD;
+	qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DMR);
+
+	return 0;
+}
+
+static struct dma_async_tx_descriptor *fsl_qdma_prep_dma_sg(
+		struct dma_chan *chan,
+		struct scatterlist *dst_sg, unsigned int dst_nents,
+		struct scatterlist *src_sg, unsigned int src_nents,
+		unsigned long flags)
+{
+	return NULL;
+}
+
+static struct dma_async_tx_descriptor *
+fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
+		dma_addr_t src, size_t len, unsigned long flags)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	struct fsl_qdma_comp *fsl_comp;
+
+	fsl_comp = fsl_qdma_request_enqueue_desc(fsl_chan);
+	fsl_qdma_comp_fill(fsl_comp, dst, src, len);
+
+	return vchan_tx_prep(&fsl_chan->vchan, &fsl_comp->vdesc, flags);
+}
+
+static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
+{
+	void __iomem *addr = fsl_chan->qdma->membase;
+	struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
+	struct fsl_qdma_comp *fsl_comp;
+	struct virt_dma_desc *vdesc;
+	u32 reg;
+
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_BCQSR(fsl_queue->id));
+	if (reg & FSL_QDMA_BCQSR_QF) {
+		dev_err(fsl_chan->qdma->dma_dev.dev, "Enqueue rejection!\n");
+		return;
+	}
+
+	vdesc = vchan_next_desc(&fsl_chan->vchan);
+	if (!vdesc)
+		return;
+	list_del(&vdesc->node);
+	fsl_comp = to_fsl_qdma_comp(vdesc);
+
+	memcpy(fsl_queue->virt_head++, fsl_comp->virt_addr, 16);
+	if (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq)
+		fsl_queue->virt_head = fsl_queue->cq;
+
+	list_add_tail(&fsl_comp->list, &fsl_queue->comp_used);
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_BCQMR(fsl_queue->id));
+	reg |= FSL_QDMA_BCQMR_EI;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_BCQMR(fsl_queue->id));
+	fsl_chan->status = DMA_IN_PROGRESS;
+}
+
+static enum dma_status fsl_qdma_tx_status(struct dma_chan *chan,
+		dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
+	return dma_cookie_status(chan, cookie, txstate);
+}
+
+static void fsl_qdma_free_desc(struct virt_dma_desc *vdesc)
+{
+	struct fsl_qdma_comp *fsl_comp;
+	struct fsl_qdma_queue *fsl_queue;
+	unsigned long flags;
+
+	fsl_comp = to_fsl_qdma_comp(vdesc);
+	fsl_queue = fsl_comp->qchan->queue;
+
+	spin_lock_irqsave(&fsl_queue->queue_lock, flags);
+	list_add_tail(&fsl_comp->list, &fsl_queue->comp_free);
+	spin_unlock_irqrestore(&fsl_queue->queue_lock, flags);
+}
+
+static void fsl_qdma_issue_pending(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsl_queue->queue_lock, flags);
+	spin_lock(&fsl_chan->vchan.lock);
+	if (vchan_issue_pending(&fsl_chan->vchan))
+		fsl_qdma_enqueue_desc(fsl_chan);
+	spin_unlock(&fsl_chan->vchan.lock);
+	spin_unlock_irqrestore(&fsl_queue->queue_lock, flags);
+}
+
+static int fsl_qdma_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_engine *fsl_qdma;
+	struct fsl_qdma_chan *fsl_chan;
+	struct resource *res;
+	unsigned int len, chans, queues;
+	int ret, i;
+
+	ret = of_property_read_u32(np, "channels", &chans);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't get channels.\n");
+		return ret;
+	}
+
+	len = sizeof(*fsl_qdma) + sizeof(*fsl_chan) * chans;
+	fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
+	if (!fsl_qdma)
+		return -ENOMEM;
+
+	ret = of_property_read_u32(np, "queues", &queues);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't get queues.\n");
+		return ret;
+	}
+
+	fsl_qdma->queue = fsl_qdma_alloc_queue_resources(pdev, queues);
+	if (!fsl_qdma->queue)
+		return -ENOMEM;
+
+	fsl_qdma->status = fsl_qdma_prep_status_queue(pdev);
+	if (!fsl_qdma->status)
+		return -ENOMEM;
+
+	fsl_qdma->n_chans = chans;
+	fsl_qdma->n_queues = queues;
+	mutex_init(&fsl_qdma->fsl_qdma_mutex);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	fsl_qdma->membase = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(fsl_qdma->membase))
+		return PTR_ERR(fsl_qdma->membase);
+
+	ret = fsl_qdma_irq_init(pdev, fsl_qdma);
+	if (ret)
+		return ret;
+
+	fsl_qdma->big_endian = of_property_read_bool(np, "big-endian");
+	INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
+	for (i = 0; i < fsl_qdma->n_chans; i++) {
+		struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
+
+		fsl_chan->qdma = fsl_qdma;
+		fsl_chan->queue = fsl_qdma->queue + i%fsl_qdma->n_queues;
+		fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
+		INIT_LIST_HEAD(&fsl_chan->qcomp);
+		vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
+	}
+
+	dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
+	dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
+	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
+
+	fsl_qdma->dma_dev.dev = &pdev->dev;
+	fsl_qdma->dma_dev.device_alloc_chan_resources
+		= fsl_qdma_alloc_chan_resources;
+	fsl_qdma->dma_dev.device_free_chan_resources
+		= fsl_qdma_free_chan_resources;
+	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
+	fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
+	fsl_qdma->dma_dev.device_prep_dma_sg = fsl_qdma_prep_dma_sg;
+	fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
+
+	platform_set_drvdata(pdev, fsl_qdma);
+
+	ret = dma_async_device_register(&fsl_qdma->dma_dev);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't register Freescale qDMA engine.\n");
+		return ret;
+	}
+
+	ret = fsl_qdma_reg_init(fsl_qdma);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n");
+		return ret;
+	}
+
+
+	return 0;
+}
+
+static int fsl_qdma_remove(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
+	struct fsl_qdma_queue *queue_temp;
+	struct fsl_qdma_queue *status = fsl_qdma->status;
+	struct fsl_qdma_comp *comp_temp, *_comp_temp;
+	int i;
+
+	of_dma_controller_free(np);
+	dma_async_device_unregister(&fsl_qdma->dma_dev);
+
+	/* Free descriptor areas */
+	for (i = 0; i < fsl_qdma->n_queues; i++) {
+		queue_temp = fsl_qdma->queue + i;
+		list_for_each_entry_safe(comp_temp, _comp_temp,
+					&queue_temp->comp_used,	list) {
+			dma_pool_free(queue_temp->comp_pool,
+					comp_temp->virt_addr,
+					comp_temp->bus_addr);
+			list_del(&comp_temp->list);
+			kfree(comp_temp);
+		}
+		list_for_each_entry_safe(comp_temp, _comp_temp,
+					&queue_temp->comp_free, list) {
+			dma_pool_free(queue_temp->comp_pool,
+					comp_temp->virt_addr,
+					comp_temp->bus_addr);
+			list_del(&comp_temp->list);
+			kfree(comp_temp);
+		}
+		dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_ccdf) *
+					queue_temp->n_cq, queue_temp->cq,
+					queue_temp->bus_addr);
+		dma_pool_destroy(queue_temp->comp_pool);
+	}
+
+	dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_ccdf) *
+				status->n_cq, status->cq, status->bus_addr);
+	return 0;
+}
+
+static const struct of_device_id fsl_qdma_dt_ids[] = {
+	{ .compatible = "fsl,ls1021a-qdma", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fsl_qdma_dt_ids);
+
+static struct platform_driver fsl_qdma_driver = {
+	.driver		= {
+		.name	= "fsl-qdma",
+		.owner  = THIS_MODULE,
+		.of_match_table = fsl_qdma_dt_ids,
+	},
+	.probe          = fsl_qdma_probe,
+	.remove		= fsl_qdma_remove,
+};
+
+static int __init fsl_qdma_init(void)
+{
+	return platform_driver_register(&fsl_qdma_driver);
+}
+subsys_initcall(fsl_qdma_init);
+
+static void __exit fsl_qdma_exit(void)
+{
+	platform_driver_unregister(&fsl_qdma_driver);
+}
+module_exit(fsl_qdma_exit);
+
+MODULE_ALIAS("platform:fsl-qdma");
+MODULE_DESCRIPTION("Freescale qDMA engine driver");
+MODULE_LICENSE("GPL v2");
-- 
2.1.0.27.g96db324

[PATCH 2/2] ARM: dts: ls1021: Add qDMA node

[Yuan Yao]

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
---
 arch/arm/boot/dts/ls1021a.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 491480f..1a81b89 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -383,6 +383,22 @@
 				 <&platform_clk 1>;
 		};
 
+		qdma: qdma@8390000 {
+			compatible = "fsl,ls1021a-qdma";
+			reg = <0x0 0x8390000 0x0 0x10000>;
+			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "qdma-controller", "qdma-queue";
+			status-sizes = <64>;
+			channels = <8>;
+			queues = <2>;
+			queue-sizes = <256 256>;
+			queue-group = <0 1>;
+			queue-weight = <0 0>;
+			default-queue = <0>;
+			big-endian;
+		};
+
 		mdio0: mdio@2d24000 {
 			compatible = "gianfar";
 			device_type = "mdio";
-- 
2.1.0.27.g96db324

[PATCH 2/2] ARM: dts: ls1021: Add qDMA node

[Yuan Yao]

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
---
 arch/arm/boot/dts/ls1021a.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 491480f..1a81b89 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -383,6 +383,22 @@
 				 <&platform_clk 1>;
 		};
 
+		qdma: qdma at 8390000 {
+			compatible = "fsl,ls1021a-qdma";
+			reg = <0x0 0x8390000 0x0 0x10000>;
+			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "qdma-controller", "qdma-queue";
+			status-sizes = <64>;
+			channels = <8>;
+			queues = <2>;
+			queue-sizes = <256 256>;
+			queue-group = <0 1>;
+			queue-weight = <0 0>;
+			default-queue = <0>;
+			big-endian;
+		};
+
 		mdio0: mdio at 2d24000 {
 			compatible = "gianfar";
 			device_type = "mdio";
-- 
2.1.0.27.g96db324

Re: [PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Paul Bolle]

Just a license nit.

On Tue, 2015-03-17 at 13:28 +0800, Yuan Yao wrote:
> --- /dev/null
> +++ b/drivers/dma/fsl-qdma.c

> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.

This states the license is GPL v2 or later.

> +MODULE_LICENSE("GPL v2");

And
    MODULE_LICENSE("GPL");

would match that statement.


Paul Bolle

[PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Paul Bolle]

Just a license nit.

On Tue, 2015-03-17 at 13:28 +0800, Yuan Yao wrote:
> --- /dev/null
> +++ b/drivers/dma/fsl-qdma.c

> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.

This states the license is GPL v2 or later.

> +MODULE_LICENSE("GPL v2");

And
    MODULE_LICENSE("GPL");

would match that statement.


Paul Bolle

RE: [PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Yao Yuan]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 1189 bytes --]

Thanks for your review. I will fix it in the next version.

Best Regards,
Yuan Yao

> -----Original Message-----
> From: Paul Bolle [mailto:pebolle@tiscali.nl]
> Sent: Wednesday, March 18, 2015 2:57 AM
> To: Yuan Yao-B46683
> Cc: vinod.koul@intel.com; shawn.guo@linaro.org; dan.j.williams@intel.com;
> linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH 1/2] dma: Add Freescale qDMA engine driver support
> 
> Just a license nit.
> 
> On Tue, 2015-03-17 at 13:28 +0800, Yuan Yao wrote:
> > --- /dev/null
> > +++ b/drivers/dma/fsl-qdma.c
> 
> > + * This program is free software; you can redistribute  it and/or modify it
> > + * under  the terms of  the GNU General  Public License as published by the
> > + * Free Software Foundation;  either version 2 of the  License, or (at your
> > + * option) any later version.
> 
> This states the license is GPL v2 or later.
> 
> > +MODULE_LICENSE("GPL v2");
> 
> And
>     MODULE_LICENSE("GPL");
> 
> would match that statement.
> 
> 
> Paul Bolle

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[PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Yao Yuan]

Thanks for your review. I will fix it in the next version.

Best Regards,
Yuan Yao

> -----Original Message-----
> From: Paul Bolle [mailto:pebolle at tiscali.nl]
> Sent: Wednesday, March 18, 2015 2:57 AM
> To: Yuan Yao-B46683
> Cc: vinod.koul at intel.com; shawn.guo at linaro.org; dan.j.williams at intel.com;
> linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 1/2] dma: Add Freescale qDMA engine driver support
> 
> Just a license nit.
> 
> On Tue, 2015-03-17 at 13:28 +0800, Yuan Yao wrote:
> > --- /dev/null
> > +++ b/drivers/dma/fsl-qdma.c
> 
> > + * This program is free software; you can redistribute  it and/or modify it
> > + * under  the terms of  the GNU General  Public License as published by the
> > + * Free Software Foundation;  either version 2 of the  License, or (at your
> > + * option) any later version.
> 
> This states the license is GPL v2 or later.
> 
> > +MODULE_LICENSE("GPL v2");
> 
> And
>     MODULE_LICENSE("GPL");
> 
> would match that statement.
> 
> 
> Paul Bolle

Re: [PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Vinod Koul]

On Tue, Mar 17, 2015 at 01:28:38PM +0800, Yuan Yao wrote:
> +static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
> +{
> +	/*
> +	 * In QDMA mode, We don't need to do anything.
> +	 */
> +	return 0;
> +}
Pls remove this

> +static struct fsl_qdma_comp *fsl_qdma_request_enqueue_desc(
> +					struct fsl_qdma_chan *fsl_chan)
> +{
> +	struct fsl_qdma_comp *comp_temp;
> +	struct fsl_qdma_queue *queue = fsl_chan->queue;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&queue->queue_lock, flags);
> +	if (list_empty(&queue->comp_free)) {
> +		spin_unlock_irqrestore(&queue->queue_lock, flags);
> +		comp_temp = kzalloc(sizeof(*comp_temp), GFP_KERNEL);
this is called by prep_ APIs so should be atomic so GFP_KERNEL is wrong, you
should use GFP_NOWAIT like you did for below..

> +static int fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)
> +{
> +	void __iomem *addr = fsl_qdma->membase;
> +	int i, count = 5;
> +	u32 reg;
> +
> +	/* Disable the command queue and wait for idle state. */
no locks held while you do this ?

> +static struct dma_async_tx_descriptor *fsl_qdma_prep_dma_sg(
> +		struct dma_chan *chan,
> +		struct scatterlist *dst_sg, unsigned int dst_nents,
> +		struct scatterlist *src_sg, unsigned int src_nents,
> +		unsigned long flags)
> +{
> +	return NULL;
> +}
why is this empty?

> +	dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
> +	dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
> +	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
> +
> +	fsl_qdma->dma_dev.dev = &pdev->dev;
> +	fsl_qdma->dma_dev.device_alloc_chan_resources
> +		= fsl_qdma_alloc_chan_resources;
> +	fsl_qdma->dma_dev.device_free_chan_resources
> +		= fsl_qdma_free_chan_resources;
> +	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
> +	fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
> +	fsl_qdma->dma_dev.device_prep_dma_sg = fsl_qdma_prep_dma_sg;
> +	fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
pls set direction etc fields as well

> +
> +	/* Free descriptor areas */
> +	for (i = 0; i < fsl_qdma->n_queues; i++) {
> +		queue_temp = fsl_qdma->queue + i;
> +		list_for_each_entry_safe(comp_temp, _comp_temp,
> +					&queue_temp->comp_used,	list) {
> +			dma_pool_free(queue_temp->comp_pool,
> +					comp_temp->virt_addr,
> +					comp_temp->bus_addr);
> +			list_del(&comp_temp->list);
> +			kfree(comp_temp);
> +		}
> +		list_for_each_entry_safe(comp_temp, _comp_temp,
> +					&queue_temp->comp_free, list) {
> +			dma_pool_free(queue_temp->comp_pool,
> +					comp_temp->virt_addr,
> +					comp_temp->bus_addr);
> +			list_del(&comp_temp->list);
> +			kfree(comp_temp);
> +		}
> +		dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_ccdf) *
> +					queue_temp->n_cq, queue_temp->cq,
> +					queue_temp->bus_addr);
> +		dma_pool_destroy(queue_temp->comp_pool);
> +	}
> +
> +	dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_ccdf) *
> +				status->n_cq, status->cq, status->bus_addr);
and at this point you still have irq registered and enabled, so can be
invoked!

-- 
~Vinod

[PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Vinod Koul]

On Tue, Mar 17, 2015 at 01:28:38PM +0800, Yuan Yao wrote:
> +static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
> +{
> +	/*
> +	 * In QDMA mode, We don't need to do anything.
> +	 */
> +	return 0;
> +}
Pls remove this

> +static struct fsl_qdma_comp *fsl_qdma_request_enqueue_desc(
> +					struct fsl_qdma_chan *fsl_chan)
> +{
> +	struct fsl_qdma_comp *comp_temp;
> +	struct fsl_qdma_queue *queue = fsl_chan->queue;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&queue->queue_lock, flags);
> +	if (list_empty(&queue->comp_free)) {
> +		spin_unlock_irqrestore(&queue->queue_lock, flags);
> +		comp_temp = kzalloc(sizeof(*comp_temp), GFP_KERNEL);
this is called by prep_ APIs so should be atomic so GFP_KERNEL is wrong, you
should use GFP_NOWAIT like you did for below..

> +static int fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)
> +{
> +	void __iomem *addr = fsl_qdma->membase;
> +	int i, count = 5;
> +	u32 reg;
> +
> +	/* Disable the command queue and wait for idle state. */
no locks held while you do this ?

> +static struct dma_async_tx_descriptor *fsl_qdma_prep_dma_sg(
> +		struct dma_chan *chan,
> +		struct scatterlist *dst_sg, unsigned int dst_nents,
> +		struct scatterlist *src_sg, unsigned int src_nents,
> +		unsigned long flags)
> +{
> +	return NULL;
> +}
why is this empty?

> +	dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
> +	dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
> +	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
> +
> +	fsl_qdma->dma_dev.dev = &pdev->dev;
> +	fsl_qdma->dma_dev.device_alloc_chan_resources
> +		= fsl_qdma_alloc_chan_resources;
> +	fsl_qdma->dma_dev.device_free_chan_resources
> +		= fsl_qdma_free_chan_resources;
> +	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
> +	fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
> +	fsl_qdma->dma_dev.device_prep_dma_sg = fsl_qdma_prep_dma_sg;
> +	fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
pls set direction etc fields as well

> +
> +	/* Free descriptor areas */
> +	for (i = 0; i < fsl_qdma->n_queues; i++) {
> +		queue_temp = fsl_qdma->queue + i;
> +		list_for_each_entry_safe(comp_temp, _comp_temp,
> +					&queue_temp->comp_used,	list) {
> +			dma_pool_free(queue_temp->comp_pool,
> +					comp_temp->virt_addr,
> +					comp_temp->bus_addr);
> +			list_del(&comp_temp->list);
> +			kfree(comp_temp);
> +		}
> +		list_for_each_entry_safe(comp_temp, _comp_temp,
> +					&queue_temp->comp_free, list) {
> +			dma_pool_free(queue_temp->comp_pool,
> +					comp_temp->virt_addr,
> +					comp_temp->bus_addr);
> +			list_del(&comp_temp->list);
> +			kfree(comp_temp);
> +		}
> +		dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_ccdf) *
> +					queue_temp->n_cq, queue_temp->cq,
> +					queue_temp->bus_addr);
> +		dma_pool_destroy(queue_temp->comp_pool);
> +	}
> +
> +	dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_ccdf) *
> +				status->n_cq, status->cq, status->bus_addr);
and at this point you still have irq registered and enabled, so can be
invoked!

-- 
~Vinod

RE: [PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Yao Yuan]

Hi Vinod,

Thanks for your review, please see my comments inline.

Best Regards,
Yuan Yao

> -----Original Message-----
> From: Vinod Koul [mailto:vinod.koul@intel.com]
> Sent: Monday, October 05, 2015 10:37 PM
> To: Yuan Yao-B46683 <yao.yuan@freescale.com>
> Cc: shawn.guo@linaro.org; dan.j.williams@intel.com;
> dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH 1/2] dma: Add Freescale qDMA engine driver support
> 
> On Fri, Sep 11, 2015 at 01:53:52PM +0800, Yuan Yao wrote:
> 
> > +Examples:
> > +
> > +	qdma: qdma@8390000 {
> > +		compatible = "fsl,ls-qdma";
> > +		reg = <0x0 0x8380000 0x0 0x20000>;
> > +		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> > +				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
> > +		interrupt-names = "qdma-tx", "qdma-err";
> > +		big-endian;
> > +		channels = <1>;
> > +	};
> 
> Binding should be a separate patch
[Yuan Yao] 
Ok, Thanks.

> 
> > +FREESCALE qDMA DRIVER
> > +M:     Yuan Yao <yao.yuan@freescale.com>
> > +L:     linux-arm-kernel@lists.infradead.org
> 
> not dmaengine ML ?
[Yuan Yao] Ok, Thanks.

> 
> 
> > +config FSL_QDMA
> > +	tristate "Freescale qDMA engine support"
> > +	select DMA_ENGINE
> > +	select DMA_VIRTUAL_CHANNELS
> 
> No depends on arch, can it work on x86?
[Yuan Yao] Ok, Thanks.

> 
> > +static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan) {
> > +	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> > +
> > +	fsl_chan->desc = NULL;
> > +	return 0;
> > +}
> 
> why do you need this it seems to do nothing
[Yuan Yao] I will remove it.

> 
> > +static struct fsl_qdma_desc *fsl_qdma_alloc_desc(struct fsl_qdma_chan
> > +*fsl_chan) {
> > +	struct fsl_qdma_desc *fsl_desc;
> > +
> > +	fsl_desc = kzalloc(sizeof(*fsl_desc), GFP_NOWAIT);
> > +
> 
> empty line here is not required
> 
> > +	if (!fsl_desc)
> > +		return NULL;
> > +
> > +	fsl_desc->qchan = fsl_chan;
> > +
> > +	return fsl_desc;
> 
> why not return fsl_desc->qchan ;
> 
[Yuan Yao] 
I still need some data in fsl_desc. So I have to return fsl_desc  here.

> 
> > +	dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
> > +	dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
> > +	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
> > +
> > +	fsl_qdma->dma_dev.dev = &pdev->dev;
> > +	fsl_qdma->dma_dev.device_alloc_chan_resources
> > +		= fsl_qdma_alloc_chan_resources;
> > +	fsl_qdma->dma_dev.device_free_chan_resources
> > +		= fsl_qdma_free_chan_resources;
> > +	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
> > +	fsl_qdma->dma_dev.device_prep_dma_memcpy =
> fsl_qdma_prep_memcpy;
> > +	fsl_qdma->dma_dev.device_issue_pending =
> fsl_qdma_issue_pending;
> 
> You claim DMA_SLAVE but no prep_ for that?
> 
[Yuan Yao] It's a mistake. I will remove it.\

> > +
> > +static int __init fsl_qdma_init(void) {
> > +	return platform_driver_register(&fsl_qdma_driver);
> > +}
> > +subsys_initcall(fsl_qdma_init);
> why subsys_init?
> 
[Yuan Yao] For a preventive, some driver base on DMA, QDMA have to initialize earlier than them.
Even now there is no kernel driver base on QDMA, But I still think the subsys_init is better.

> --
> ~Vinod

RE: [PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Yao Yuan]

Hi Vinod,

Thanks for your review, please see my comments inline.

Best Regards,
Yuan Yao

> -----Original Message-----
> From: Vinod Koul [mailto:vinod.koul@intel.com]
> Sent: Monday, October 05, 2015 10:37 PM
> To: Yuan Yao-B46683 <yao.yuan@freescale.com>
> Cc: shawn.guo@linaro.org; dan.j.williams@intel.com;
> dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH 1/2] dma: Add Freescale qDMA engine driver support
> 
> On Fri, Sep 11, 2015 at 01:53:52PM +0800, Yuan Yao wrote:
> 
> > +Examples:
> > +
> > +	qdma: qdma@8390000 {
> > +		compatible = "fsl,ls-qdma";
> > +		reg = <0x0 0x8380000 0x0 0x20000>;
> > +		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> > +				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
> > +		interrupt-names = "qdma-tx", "qdma-err";
> > +		big-endian;
> > +		channels = <1>;
> > +	};
> 
> Binding should be a separate patch
[Yuan Yao] 
Ok, Thanks.

> 
> > +FREESCALE qDMA DRIVER
> > +M:     Yuan Yao <yao.yuan@freescale.com>
> > +L:     linux-arm-kernel@lists.infradead.org
> 
> not dmaengine ML ?
[Yuan Yao] Ok, Thanks.

> 
> 
> > +config FSL_QDMA
> > +	tristate "Freescale qDMA engine support"
> > +	select DMA_ENGINE
> > +	select DMA_VIRTUAL_CHANNELS
> 
> No depends on arch, can it work on x86?
[Yuan Yao] Ok, Thanks.

> 
> > +static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan) {
> > +	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> > +
> > +	fsl_chan->desc = NULL;
> > +	return 0;
> > +}
> 
> why do you need this it seems to do nothing
[Yuan Yao] I will remove it.

> 
> > +static struct fsl_qdma_desc *fsl_qdma_alloc_desc(struct fsl_qdma_chan
> > +*fsl_chan) {
> > +	struct fsl_qdma_desc *fsl_desc;
> > +
> > +	fsl_desc = kzalloc(sizeof(*fsl_desc), GFP_NOWAIT);
> > +
> 
> empty line here is not required
> 
> > +	if (!fsl_desc)
> > +		return NULL;
> > +
> > +	fsl_desc->qchan = fsl_chan;
> > +
> > +	return fsl_desc;
> 
> why not return fsl_desc->qchan ;
> 
[Yuan Yao] 
I still need some data in fsl_desc. So I have to return fsl_desc  here.

> 
> > +	dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
> > +	dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
> > +	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
> > +
> > +	fsl_qdma->dma_dev.dev = &pdev->dev;
> > +	fsl_qdma->dma_dev.device_alloc_chan_resources
> > +		= fsl_qdma_alloc_chan_resources;
> > +	fsl_qdma->dma_dev.device_free_chan_resources
> > +		= fsl_qdma_free_chan_resources;
> > +	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
> > +	fsl_qdma->dma_dev.device_prep_dma_memcpy =
> fsl_qdma_prep_memcpy;
> > +	fsl_qdma->dma_dev.device_issue_pending =
> fsl_qdma_issue_pending;
> 
> You claim DMA_SLAVE but no prep_ for that?
> 
[Yuan Yao] It's a mistake. I will remove it.\

> > +
> > +static int __init fsl_qdma_init(void) {
> > +	return platform_driver_register(&fsl_qdma_driver);
> > +}
> > +subsys_initcall(fsl_qdma_init);
> why subsys_init?
> 
[Yuan Yao] For a preventive, some driver base on DMA, QDMA have to initialize earlier than them.
Even now there is no kernel driver base on QDMA, But I still think the subsys_init is better.

> --
> ~Vinod

[PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Yao Yuan]

Hi Vinod,

Thanks for your review, please see my comments inline.

Best Regards,
Yuan Yao

> -----Original Message-----
> From: Vinod Koul [mailto:vinod.koul at intel.com]
> Sent: Monday, October 05, 2015 10:37 PM
> To: Yuan Yao-B46683 <yao.yuan@freescale.com>
> Cc: shawn.guo at linaro.org; dan.j.williams at intel.com;
> dmaengine at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; devicetree at vger.kernel.org
> Subject: Re: [PATCH 1/2] dma: Add Freescale qDMA engine driver support
> 
> On Fri, Sep 11, 2015 at 01:53:52PM +0800, Yuan Yao wrote:
> 
> > +Examples:
> > +
> > +	qdma: qdma at 8390000 {
> > +		compatible = "fsl,ls-qdma";
> > +		reg = <0x0 0x8380000 0x0 0x20000>;
> > +		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> > +				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
> > +		interrupt-names = "qdma-tx", "qdma-err";
> > +		big-endian;
> > +		channels = <1>;
> > +	};
> 
> Binding should be a separate patch
[Yuan Yao] 
Ok, Thanks.

> 
> > +FREESCALE qDMA DRIVER
> > +M:     Yuan Yao <yao.yuan@freescale.com>
> > +L:     linux-arm-kernel at lists.infradead.org
> 
> not dmaengine ML ?
[Yuan Yao] Ok, Thanks.

> 
> 
> > +config FSL_QDMA
> > +	tristate "Freescale qDMA engine support"
> > +	select DMA_ENGINE
> > +	select DMA_VIRTUAL_CHANNELS
> 
> No depends on arch, can it work on x86?
[Yuan Yao] Ok, Thanks.

> 
> > +static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan) {
> > +	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> > +
> > +	fsl_chan->desc = NULL;
> > +	return 0;
> > +}
> 
> why do you need this it seems to do nothing
[Yuan Yao] I will remove it.

> 
> > +static struct fsl_qdma_desc *fsl_qdma_alloc_desc(struct fsl_qdma_chan
> > +*fsl_chan) {
> > +	struct fsl_qdma_desc *fsl_desc;
> > +
> > +	fsl_desc = kzalloc(sizeof(*fsl_desc), GFP_NOWAIT);
> > +
> 
> empty line here is not required
> 
> > +	if (!fsl_desc)
> > +		return NULL;
> > +
> > +	fsl_desc->qchan = fsl_chan;
> > +
> > +	return fsl_desc;
> 
> why not return fsl_desc->qchan ;
> 
[Yuan Yao] 
I still need some data in fsl_desc. So I have to return fsl_desc  here.

> 
> > +	dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
> > +	dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
> > +	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
> > +
> > +	fsl_qdma->dma_dev.dev = &pdev->dev;
> > +	fsl_qdma->dma_dev.device_alloc_chan_resources
> > +		= fsl_qdma_alloc_chan_resources;
> > +	fsl_qdma->dma_dev.device_free_chan_resources
> > +		= fsl_qdma_free_chan_resources;
> > +	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
> > +	fsl_qdma->dma_dev.device_prep_dma_memcpy =
> fsl_qdma_prep_memcpy;
> > +	fsl_qdma->dma_dev.device_issue_pending =
> fsl_qdma_issue_pending;
> 
> You claim DMA_SLAVE but no prep_ for that?
> 
[Yuan Yao] It's a mistake. I will remove it.\

> > +
> > +static int __init fsl_qdma_init(void) {
> > +	return platform_driver_register(&fsl_qdma_driver);
> > +}
> > +subsys_initcall(fsl_qdma_init);
> why subsys_init?
> 
[Yuan Yao] For a preventive, some driver base on DMA, QDMA have to initialize earlier than them.
Even now there is no kernel driver base on QDMA, But I still think the subsys_init is better.

> --
> ~Vinod

Re: [PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Vinod Koul]

On Fri, Sep 11, 2015 at 01:53:52PM +0800, Yuan Yao wrote:

> +Examples:
> +
> +	qdma: qdma@8390000 {
> +		compatible = "fsl,ls-qdma";
> +		reg = <0x0 0x8380000 0x0 0x20000>;
> +		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "qdma-tx", "qdma-err";
> +		big-endian;
> +		channels = <1>;
> +	};

Binding should be a separate patch

> +FREESCALE qDMA DRIVER
> +M:     Yuan Yao <yao.yuan@freescale.com>
> +L:     linux-arm-kernel@lists.infradead.org

not dmaengine ML ?


> +config FSL_QDMA
> +	tristate "Freescale qDMA engine support"
> +	select DMA_ENGINE
> +	select DMA_VIRTUAL_CHANNELS

No depends on arch, can it work on x86?

> +static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
> +{
> +	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +
> +	fsl_chan->desc = NULL;
> +	return 0;
> +}

why do you need this it seems to do nothing

> +static struct fsl_qdma_desc *fsl_qdma_alloc_desc(struct fsl_qdma_chan *fsl_chan)
> +{
> +	struct fsl_qdma_desc *fsl_desc;
> +
> +	fsl_desc = kzalloc(sizeof(*fsl_desc), GFP_NOWAIT);
> +

empty line here is not required

> +	if (!fsl_desc)
> +		return NULL;
> +
> +	fsl_desc->qchan = fsl_chan;
> +
> +	return fsl_desc;

why not return fsl_desc->qchan ;


> +	dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
> +	dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
> +	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
> +
> +	fsl_qdma->dma_dev.dev = &pdev->dev;
> +	fsl_qdma->dma_dev.device_alloc_chan_resources
> +		= fsl_qdma_alloc_chan_resources;
> +	fsl_qdma->dma_dev.device_free_chan_resources
> +		= fsl_qdma_free_chan_resources;
> +	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
> +	fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
> +	fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;

You claim DMA_SLAVE but no prep_ for that?

> +
> +static int __init fsl_qdma_init(void)
> +{
> +	return platform_driver_register(&fsl_qdma_driver);
> +}
> +subsys_initcall(fsl_qdma_init);
why subsys_init?

-- 
~Vinod

[PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Vinod Koul]

On Fri, Sep 11, 2015 at 01:53:52PM +0800, Yuan Yao wrote:

> +Examples:
> +
> +	qdma: qdma at 8390000 {
> +		compatible = "fsl,ls-qdma";
> +		reg = <0x0 0x8380000 0x0 0x20000>;
> +		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "qdma-tx", "qdma-err";
> +		big-endian;
> +		channels = <1>;
> +	};

Binding should be a separate patch

> +FREESCALE qDMA DRIVER
> +M:     Yuan Yao <yao.yuan@freescale.com>
> +L:     linux-arm-kernel at lists.infradead.org

not dmaengine ML ?


> +config FSL_QDMA
> +	tristate "Freescale qDMA engine support"
> +	select DMA_ENGINE
> +	select DMA_VIRTUAL_CHANNELS

No depends on arch, can it work on x86?

> +static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
> +{
> +	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +
> +	fsl_chan->desc = NULL;
> +	return 0;
> +}

why do you need this it seems to do nothing

> +static struct fsl_qdma_desc *fsl_qdma_alloc_desc(struct fsl_qdma_chan *fsl_chan)
> +{
> +	struct fsl_qdma_desc *fsl_desc;
> +
> +	fsl_desc = kzalloc(sizeof(*fsl_desc), GFP_NOWAIT);
> +

empty line here is not required

> +	if (!fsl_desc)
> +		return NULL;
> +
> +	fsl_desc->qchan = fsl_chan;
> +
> +	return fsl_desc;

why not return fsl_desc->qchan ;


> +	dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
> +	dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
> +	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
> +
> +	fsl_qdma->dma_dev.dev = &pdev->dev;
> +	fsl_qdma->dma_dev.device_alloc_chan_resources
> +		= fsl_qdma_alloc_chan_resources;
> +	fsl_qdma->dma_dev.device_free_chan_resources
> +		= fsl_qdma_free_chan_resources;
> +	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
> +	fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
> +	fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;

You claim DMA_SLAVE but no prep_ for that?

> +
> +static int __init fsl_qdma_init(void)
> +{
> +	return platform_driver_register(&fsl_qdma_driver);
> +}
> +subsys_initcall(fsl_qdma_init);
why subsys_init?

-- 
~Vinod

Re: [PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Li Yang]

On Fri, Sep 11, 2015 at 12:53 AM, Yuan Yao <yao.yuan@freescale.com> wrote:
> Add Freescale Queue Direct Memory Access(qDMA) controller support.
> This module can be found on LS-1 and LS-2 SoCs.
>
> This add the legacy mode support for qDMA.
>
> Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
> ---
>  Documentation/devicetree/bindings/dma/fsl-qdma.txt |  43 ++
>  MAINTAINERS                                        |   7 +
>  drivers/dma/Kconfig                                |  10 +
>  drivers/dma/Makefile                               |   1 +
>  drivers/dma/fsl-qdma.c                             | 521 +++++++++++++++++++++
>  5 files changed, 582 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
>  create mode 100644 drivers/dma/fsl-qdma.c
>
> diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
> new file mode 100644
> index 0000000..cdae71c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
> @@ -0,0 +1,43 @@
> +* Freescale queue Direct Memory Access Controller(qDMA) Controller
> +
> +  The qDMA controller transfers blocks of data between one source and one or more
> +destinations. The blocks of data transferred can be represented in memory as contiguous
> +or non-contiguous using scatter/gather table(s). Channel virtualization is supported
> +through enqueuing of DMA jobs to, or dequeuing DMA jobs from, different work
> +queues.
> +  Legacy mode is primarily included for software requiring the earlier
> +QorIQ DMA programming model. This mode provides a simple programming
> +model not utilizing the datapath architecture. In legacy mode, DMA
> +operations are directly configured through a set of architectural
> +registers per channel.

Is this binding only covering the legacy mode?  The binding should
describe the whole IP block no matter if we have driver for all the
features.

> +
> +* qDMA Controller
> +Required properties:
> +- compatible :
> +       - "fsl,ls-qdma" for qDMA used similar to that on LS SoC

Compatible need to be specific like "fsl,ls1021a-qdma".  See
http://www.devicetree.org/Device_Tree_Usage.

> +- reg : Specifies base physical address(s) and size of the qDMA registers.
> +       The region is qDMA control register's address and size.
> +- interrupts : A list of interrupt-specifiers, one for each entry in
> +       interrupt-names.
> +- interrupt-names : Should contain:
> +       "qdma-tx" - the  interrupt
> +       "qdma-err" - the error interrupt
> +- channels : Number of channels supported by the controller
> +
> +Optional properties:
> +- big-endian: If present registers and hardware scatter/gather descriptors
> +       of the qDMA are implemented in big endian mode, otherwise in little

Endian
> +       mode.
> +
> +
> +Examples:
> +
> +       qdma: qdma@8390000 {
> +               compatible = "fsl,ls-qdma";
> +               reg = <0x0 0x8380000 0x0 0x20000>;
> +               interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
> +               interrupt-names = "qdma-tx", "qdma-err";
> +               big-endian;
> +               channels = <1>;
> +       };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5772ccf..a4d1b52 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -4357,6 +4357,13 @@ L:       linuxppc-dev@lists.ozlabs.org
>  S:     Maintained
>  F:     drivers/dma/fsldma.*
>
> +FREESCALE qDMA DRIVER
> +M:     Yuan Yao <yao.yuan@freescale.com>
> +L:     linux-arm-kernel@lists.infradead.org

Interestingly you listed arm mailing list instead of dmaengine mailing list.

> +S:     Maintained
> +F:     Documentation/devicetree/bindings/dma/fsl-qdma.txt
> +F:     drivers/dma/fsl-qdma.c
> +
>  FREESCALE I2C CPM DRIVER
>  M:     Jochen Friedrich <jochen@scram.de>
>  L:     linuxppc-dev@lists.ozlabs.org
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index b458475..e29e985 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -193,6 +193,16 @@ config FSL_EDMA
>           multiplexing capability for DMA request sources(slot).
>           This module can be found on Freescale Vybrid and LS-1 SoCs.
>
> +config FSL_QDMA
> +       tristate "Freescale qDMA engine support"
> +       select DMA_ENGINE
> +       select DMA_VIRTUAL_CHANNELS
> +       help
> +         Support the Freescale qDMA engine with command queue and legacy mode.
> +         Channel virtualization is supported through enqueuing of DMA jobs to,
> +         or dequeuing DMA jobs from, different work queues.
> +         This module can be found on Freescale LS SoCs.

Better to spell out Layerscape

> +
>  config FSL_RAID
>          tristate "Freescale RAID engine Support"
>          depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> index 7711a71..8de7526 100644
> --- a/drivers/dma/Makefile
> +++ b/drivers/dma/Makefile
> @@ -29,6 +29,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
>  obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
>  obj-$(CONFIG_FSL_DMA) += fsldma.o
>  obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
> +obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
>  obj-$(CONFIG_FSL_RAID) += fsl_raid.o
>  obj-$(CONFIG_HSU_DMA) += hsu/
>  obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
> diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
> new file mode 100644
> index 0000000..846cdba
> --- /dev/null
> +++ b/drivers/dma/fsl-qdma.c
> @@ -0,0 +1,521 @@
> +/*
> + * drivers/dma/fsl-qdma.c
> + *
> + * Copyright 2014-2015 Freescale Semiconductor, Inc.
> + *
> + * Driver for the Freescale qDMA engine with legacy mode.

If this is only for legacy mode, name it fsl-qdma-legacy.c

> + * This module can be found on Freescale LS SoCs.
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/dmapool.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_dma.h>
> +#include <linux/of_irq.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#include "virt-dma.h"
> +
> +#define FSL_QDMA_DMR           0x0
> +#define FSL_QDMA_DSR_P         0x4
> +
> +#define FSL_QDMA_DSR_M         0x10004
> +#define FSL_QDMA_DLMR          0x10100
> +#define FSL_QDMA_DLSR          0x10104
> +#define FSL_QDMA_DLSATR                0x10110
> +#define FSL_QDMA_DLSAR         0x10114
> +#define FSL_QDMA_DLDATR                0x10118
> +#define FSL_QDMA_DLDAR         0x1011c
> +#define FSL_QDMA_DLBCR         0x10120
> +#define FSL_QDMA_DLESAD                0x10148
> +#define FSL_QDMA_DLEDAD                0x1014c
> +
> +#define FSL_QDMA_DLMR_CS       0x1
> +#define FSL_QDMA_DLMR_EOSIE    0x200
> +#define FSL_QDMA_DLMR_EIE      0x40
> +#define FSL_QDMA_DLSR_TE       0x80
> +#define FSL_QDMA_DLSR_CH       0x20
> +#define FSL_QDMA_DLSR_PE       0x10
> +#define FSL_QDMA_DLSR_CB       0x4
> +#define FSL_QDMA_DLSR_EOSI     0x2
> +
> +#define FSL_QDMA_SRTTYPE_R_N   0x40000
> +
> +struct fsl_qdma_tcd {
> +       u64     saddr;
> +       u32     nbytes;
> +       u64     daddr;
> +};
> +
> +struct fsl_qdma_chan_config {
> +       enum dma_transfer_direction     dir;
> +       enum dma_slave_buswidth         addr_width;
> +       u32                             burst;
> +       u32                             attr;
> +};
> +
> +struct fsl_qdma_desc {
> +       struct virt_dma_desc            vdesc;
> +       struct fsl_qdma_chan            *qchan;
> +       struct fsl_qdma_tcd             tcd;
> +};
> +
> +struct fsl_qdma_chan {
> +       struct virt_dma_chan            vchan;
> +       struct fsl_qdma_desc            *desc;
> +       enum dma_status                 status;
> +       u32                             slave_id;
> +       struct fsl_qdma_engine          *qdma;
> +};
> +
> +struct fsl_qdma_engine {
> +       struct dma_device       dma_dev;
> +       void __iomem            *membase;
> +       u32                     n_chans;
> +       struct mutex            fsl_qdma_mutex;
> +       int                     controller_irq;
> +       int                     err_irq;
> +       bool                    big_endian;
> +       struct fsl_qdma_chan    chans[];
> +
> +};
> +
> +static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr)
> +{
> +       if (qdma->big_endian)
> +               return ioread32be(addr);
> +       else
> +               return ioread32(addr);
> +}
> +
> +static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
> +                                               void __iomem *addr)
> +{
> +       if (qdma->big_endian)
> +               iowrite32be(val, addr);
> +       else
> +               iowrite32(val, addr);
> +}
> +
> +static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
> +{
> +       return container_of(chan, struct fsl_qdma_chan, vchan.chan);
> +}
> +
> +static struct fsl_qdma_desc *to_fsl_qdma_desc(struct virt_dma_desc *vd)
> +{
> +       return container_of(vd, struct fsl_qdma_desc, vdesc);
> +}
> +
> +static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
> +{
> +       struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +
> +       fsl_chan->desc = NULL;
> +       return 0;
> +}
> +
> +static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
> +{
> +       struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +       unsigned long flags;
> +       LIST_HEAD(head);
> +
> +       spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
> +       vchan_get_all_descriptors(&fsl_chan->vchan, &head);
> +       spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
> +
> +       vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
> +}
> +
> +static void fsl_qdma_set_tcd_params(struct fsl_qdma_chan *fsl_chan,
> +                                       u64 src, u64 dst, u32 nbytes)
> +{
> +       void __iomem *addr = fsl_chan->qdma->membase;
> +       u32 reg;
> +
> +       /*
> +        * Source address.
> +        * Represents address bits 31-0 of a 49-bit source address.
> +        */
> +       qdma_writel(fsl_chan->qdma, (u32)src, addr + FSL_QDMA_DLSAR);
> +       /*
> +        * Source address.
> +        * Represents address bits 47-32 of a 49-bit source address.
> +        */
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLSATR);
> +       reg |= (u16)(src >> 32) & 0xffff;
> +       reg |= FSL_QDMA_SRTTYPE_R_N;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLSATR);
> +       /*
> +        * Source address.
> +        * Represents address bits 48 of a 49-bit source address.
> +        */
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLESAD);
> +       reg |= (src >> 48) & 0x1;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLESAD);
> +
> +       /*
> +        * Destination address.
> +        * Represents address bits 31-0 of a 49-bit destination address.
> +        */
> +       qdma_writel(fsl_chan->qdma, (u32)dst, addr + FSL_QDMA_DLDAR);
> +       /*
> +        * Destination address.
> +        * Represents address bits 47-32 of a 49-bit destination address.
> +        */
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLDATR);
> +       reg |= (u16)(dst >> 32) & 0xffff;
> +       reg |= FSL_QDMA_SRTTYPE_R_N;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLDATR);
> +       /*
> +        * Destination address.
> +        * Represents address bits 48 of a 49-bit destination address.
> +        */
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLEDAD);
> +       reg |= (dst >> 48) & 0x1;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLEDAD);
> +
> +       /*
> +        * Byte count.
> +        * Contains the number of bytes to transfer.
> +        */
> +       qdma_writel(fsl_chan->qdma, nbytes, addr + FSL_QDMA_DLBCR);
> +}
> +
> +static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
> +{
> +       u32 reg;
> +
> +       reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DLMR);
> +       reg |= FSL_QDMA_DLMR_EOSIE;
> +       reg |= FSL_QDMA_DLMR_EIE;
> +       qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DLMR);
> +       return 0;
> +}
> +
> +static void fsl_qdma_enable_request(struct fsl_qdma_chan *fsl_chan)
> +{
> +       void __iomem *addr = fsl_chan->qdma->membase;
> +       u32 reg;
> +
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLMR);
> +
> +       reg &= ~FSL_QDMA_DLMR_CS;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLMR);
> +
> +       reg |= FSL_QDMA_DLMR_CS;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLMR);
> +}
> +
> +static struct fsl_qdma_desc *fsl_qdma_alloc_desc(struct fsl_qdma_chan *fsl_chan)
> +{
> +       struct fsl_qdma_desc *fsl_desc;
> +
> +       fsl_desc = kzalloc(sizeof(*fsl_desc), GFP_NOWAIT);
> +
> +       if (!fsl_desc)
> +               return NULL;
> +
> +       fsl_desc->qchan = fsl_chan;
> +
> +       return fsl_desc;
> +}
> +
> +static void fsl_qdma_free_desc(struct virt_dma_desc *vdesc)
> +{
> +       struct fsl_qdma_desc *fsl_desc;
> +
> +       fsl_desc = to_fsl_qdma_desc(vdesc);
> +       kfree(fsl_desc);
> +}
> +
> +static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
> +{
> +       struct fsl_qdma_tcd *tcd;
> +       struct virt_dma_desc *vdesc;
> +
> +       vdesc = vchan_next_desc(&fsl_chan->vchan);
> +       if (!vdesc)
> +               return;
> +
> +       fsl_chan->desc = to_fsl_qdma_desc(vdesc);
> +       tcd = &fsl_chan->desc->tcd;
> +       fsl_qdma_set_tcd_params(fsl_chan, tcd->saddr, tcd->daddr, tcd->nbytes);
> +       fsl_qdma_enable_request(fsl_chan);
> +       fsl_chan->status = DMA_IN_PROGRESS;
> +}
> +
> +static void fsl_qdma_issue_pending(struct dma_chan *chan)
> +{
> +       struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +       unsigned long flags;
> +
> +       spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
> +
> +       if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->desc)
> +               fsl_qdma_enqueue_desc(fsl_chan);
> +
> +       spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
> +}
> +
> +static struct dma_async_tx_descriptor *
> +fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
> +               dma_addr_t src, size_t len, unsigned long flags)
> +{
> +       struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +       struct fsl_qdma_desc *fsl_desc;
> +       struct fsl_qdma_tcd *tcd;
> +
> +       fsl_desc = fsl_qdma_alloc_desc(fsl_chan);
> +       if (!fsl_desc)
> +               return NULL;
> +
> +       tcd = &fsl_desc->tcd;
> +       tcd->saddr = (u64)src;
> +       tcd->nbytes = (u32)len;
> +       tcd->daddr = (u64)dst;
> +
> +       return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
> +}
> +
> +static enum dma_status fsl_qdma_tx_status(struct dma_chan *chan,
> +               dma_cookie_t cookie, struct dma_tx_state *txstate)
> +{
> +       return dma_cookie_status(chan, cookie, txstate);
> +}
> +
> +static irqreturn_t fsl_qdma_controller_handler(int irq, void *dev_id)
> +{
> +       struct fsl_qdma_engine *fsl_qdma = dev_id;
> +       struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[0];
> +       void __iomem *addr = fsl_qdma->membase;
> +       u32 reg;
> +
> +       reg = qdma_readl(fsl_qdma, addr + FSL_QDMA_DLSR);
> +       if (!(reg & FSL_QDMA_DLSR_EOSI))
> +               return IRQ_NONE;
> +
> +       /* Don't clean TE and PE bit if they are set. */
> +       reg &= ~FSL_QDMA_DLSR_TE & ~FSL_QDMA_DLSR_PE;
> +       qdma_writel(fsl_qdma, reg, addr + FSL_QDMA_DLSR);
> +
> +       spin_lock(&fsl_chan->vchan.lock);
> +       list_del(&fsl_chan->desc->vdesc.node);
> +       vchan_cookie_complete(&fsl_chan->desc->vdesc);
> +       fsl_chan->desc = NULL;
> +       fsl_chan->status = DMA_COMPLETE;
> +       fsl_qdma_enqueue_desc(fsl_chan);
> +       spin_unlock(&fsl_chan->vchan.lock);
> +
> +       return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t fsl_qdma_controller_handler_err(int irq, void *dev_id)
> +{
> +       struct fsl_qdma_engine *fsl_qdma = dev_id;
> +       u32 reg;
> +
> +       reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DLSR);
> +
> +       if (reg & FSL_QDMA_DLSR_TE) {
> +               dev_err(fsl_qdma->dma_dev.dev,
> +                       "Transfer error. Check your address please!\n");
> +       }
> +
> +       if (reg & FSL_QDMA_DLSR_PE) {
> +               dev_err(fsl_qdma->dma_dev.dev,
> +                       "Programming error. Check your setting please!\n");
> +       }
> +
> +       /* Don't clean EOSI bit if it's set. */
> +       reg &= ~FSL_QDMA_DLSR_EOSI;
> +       qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DLSR);
> +
> +       return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t fsl_qdma_irq_handler(int irq, void *dev_id)
> +{
> +       if (fsl_qdma_controller_handler(irq, dev_id) == IRQ_HANDLED)
> +               return IRQ_HANDLED;
> +
> +       return fsl_qdma_controller_handler_err(irq, dev_id);
> +}
> +
> +static int fsl_qdma_irq_init(struct platform_device *pdev,
> +                                       struct fsl_qdma_engine *fsl_qdma)
> +{
> +       int ret;
> +
> +       fsl_qdma->controller_irq = platform_get_irq_byname(pdev,
> +                                                       "qdma-tx");
> +       if (fsl_qdma->controller_irq < 0) {
> +               dev_err(&pdev->dev, "Can't get qdma controller irq.\n");
> +               return fsl_qdma->controller_irq;
> +       }
> +
> +       fsl_qdma->err_irq = platform_get_irq_byname(pdev,
> +                                                       "qdma-err");
> +       if (fsl_qdma->err_irq < 0) {
> +               dev_err(&pdev->dev, "Can't get qdma err irq.\n");
> +               return fsl_qdma->err_irq;
> +       }
> +
> +       if (fsl_qdma->controller_irq == fsl_qdma->err_irq) {
> +               ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
> +                                       fsl_qdma_irq_handler, 0,
> +                                       "qDMA controller", fsl_qdma);
> +
> +               if (ret) {
> +                       dev_err(&pdev->dev, "Can't register qDMA IRQ.\n");
> +                       return  ret;
> +               }
> +       } else {
> +               ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
> +                               fsl_qdma_controller_handler, 0,
> +                               "qDMA controller", fsl_qdma);
> +               if (ret) {
> +                       dev_err(&pdev->dev,
> +                               "Can't register qDMA controller IRQ.\n");
> +                       return  ret;
> +               }
> +
> +               ret = devm_request_irq(&pdev->dev, fsl_qdma->err_irq,
> +                               fsl_qdma_controller_handler_err, 0,
> +                               "qDMA err", fsl_qdma);
> +               if (ret) {
> +                       dev_err(&pdev->dev, "Can't register qDMA err IRQ.\n");
> +                       return  ret;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static int fsl_qdma_probe(struct platform_device *pdev)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       struct fsl_qdma_engine *fsl_qdma;
> +       struct fsl_qdma_chan *fsl_chan;
> +       struct resource *res;
> +       unsigned int len, chans;
> +       int ret, i;
> +
> +       ret = of_property_read_u32(np, "channels", &chans);
> +       if (ret) {
> +               dev_err(&pdev->dev, "Can't get channels.\n");
> +               return ret;
> +       }
> +
> +       len = sizeof(*fsl_qdma) + sizeof(*fsl_chan) * chans;
> +       fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
> +       if (!fsl_qdma)
> +               return -ENOMEM;
> +
> +       fsl_qdma->n_chans = chans;
> +       mutex_init(&fsl_qdma->fsl_qdma_mutex);
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       fsl_qdma->membase = devm_ioremap_resource(&pdev->dev, res);
> +       if (IS_ERR(fsl_qdma->membase))
> +               return PTR_ERR(fsl_qdma->membase);
> +
> +       ret = fsl_qdma_irq_init(pdev, fsl_qdma);
> +       if (ret)
> +               return ret;
> +
> +       fsl_qdma->big_endian = of_property_read_bool(np, "big-endian");
> +       INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
> +       for (i = 0; i < fsl_qdma->n_chans; i++) {
> +               struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
> +
> +               fsl_chan->qdma = fsl_qdma;
> +               fsl_chan->desc = NULL;
> +               fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
> +               vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
> +       }
> +
> +       dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
> +       dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
> +       dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
> +
> +       fsl_qdma->dma_dev.dev = &pdev->dev;
> +       fsl_qdma->dma_dev.device_alloc_chan_resources
> +               = fsl_qdma_alloc_chan_resources;
> +       fsl_qdma->dma_dev.device_free_chan_resources
> +               = fsl_qdma_free_chan_resources;
> +       fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
> +       fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
> +       fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
> +
> +       platform_set_drvdata(pdev, fsl_qdma);
> +
> +       ret = dma_async_device_register(&fsl_qdma->dma_dev);
> +       if (ret) {
> +               dev_err(&pdev->dev, "Can't register Freescale qDMA engine.\n");
> +               return ret;
> +       }
> +
> +       ret = fsl_qdma_reg_init(fsl_qdma);
> +       if (ret) {
> +               dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n");
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static int fsl_qdma_remove(struct platform_device *pdev)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
> +
> +       of_dma_controller_free(np);
> +       dma_async_device_unregister(&fsl_qdma->dma_dev);
> +       return 0;
> +}
> +
> +static const struct of_device_id fsl_qdma_dt_ids[] = {
> +       { .compatible = "fsl,ls-qdma", },
> +       { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, fsl_qdma_dt_ids);
> +
> +static struct platform_driver fsl_qdma_driver = {
> +       .driver         = {
> +               .name   = "fsl-qdma",
> +               .owner  = THIS_MODULE,
> +               .of_match_table = fsl_qdma_dt_ids,
> +       },
> +       .probe          = fsl_qdma_probe,
> +       .remove         = fsl_qdma_remove,
> +};
> +
> +static int __init fsl_qdma_init(void)
> +{
> +       return platform_driver_register(&fsl_qdma_driver);
> +}
> +subsys_initcall(fsl_qdma_init);
> +
> +static void __exit fsl_qdma_exit(void)
> +{
> +       platform_driver_unregister(&fsl_qdma_driver);
> +}
> +module_exit(fsl_qdma_exit);
> +
> +MODULE_ALIAS("platform:fsl-qdma");
> +MODULE_DESCRIPTION("Freescale qDMA engine driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.1.0.27.g96db324
>
> --
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> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Li Yang]

On Fri, Sep 11, 2015 at 12:53 AM, Yuan Yao <yao.yuan@freescale.com> wrote:
> Add Freescale Queue Direct Memory Access(qDMA) controller support.
> This module can be found on LS-1 and LS-2 SoCs.
>
> This add the legacy mode support for qDMA.
>
> Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
> ---
>  Documentation/devicetree/bindings/dma/fsl-qdma.txt |  43 ++
>  MAINTAINERS                                        |   7 +
>  drivers/dma/Kconfig                                |  10 +
>  drivers/dma/Makefile                               |   1 +
>  drivers/dma/fsl-qdma.c                             | 521 +++++++++++++++++++++
>  5 files changed, 582 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
>  create mode 100644 drivers/dma/fsl-qdma.c
>
> diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
> new file mode 100644
> index 0000000..cdae71c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
> @@ -0,0 +1,43 @@
> +* Freescale queue Direct Memory Access Controller(qDMA) Controller
> +
> +  The qDMA controller transfers blocks of data between one source and one or more
> +destinations. The blocks of data transferred can be represented in memory as contiguous
> +or non-contiguous using scatter/gather table(s). Channel virtualization is supported
> +through enqueuing of DMA jobs to, or dequeuing DMA jobs from, different work
> +queues.
> +  Legacy mode is primarily included for software requiring the earlier
> +QorIQ DMA programming model. This mode provides a simple programming
> +model not utilizing the datapath architecture. In legacy mode, DMA
> +operations are directly configured through a set of architectural
> +registers per channel.

Is this binding only covering the legacy mode?  The binding should
describe the whole IP block no matter if we have driver for all the
features.

> +
> +* qDMA Controller
> +Required properties:
> +- compatible :
> +       - "fsl,ls-qdma" for qDMA used similar to that on LS SoC

Compatible need to be specific like "fsl,ls1021a-qdma".  See
http://www.devicetree.org/Device_Tree_Usage.

> +- reg : Specifies base physical address(s) and size of the qDMA registers.
> +       The region is qDMA control register's address and size.
> +- interrupts : A list of interrupt-specifiers, one for each entry in
> +       interrupt-names.
> +- interrupt-names : Should contain:
> +       "qdma-tx" - the  interrupt
> +       "qdma-err" - the error interrupt
> +- channels : Number of channels supported by the controller
> +
> +Optional properties:
> +- big-endian: If present registers and hardware scatter/gather descriptors
> +       of the qDMA are implemented in big endian mode, otherwise in little

Endian
> +       mode.
> +
> +
> +Examples:
> +
> +       qdma: qdma@8390000 {
> +               compatible = "fsl,ls-qdma";
> +               reg = <0x0 0x8380000 0x0 0x20000>;
> +               interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
> +               interrupt-names = "qdma-tx", "qdma-err";
> +               big-endian;
> +               channels = <1>;
> +       };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5772ccf..a4d1b52 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -4357,6 +4357,13 @@ L:       linuxppc-dev@lists.ozlabs.org
>  S:     Maintained
>  F:     drivers/dma/fsldma.*
>
> +FREESCALE qDMA DRIVER
> +M:     Yuan Yao <yao.yuan@freescale.com>
> +L:     linux-arm-kernel@lists.infradead.org

Interestingly you listed arm mailing list instead of dmaengine mailing list.

> +S:     Maintained
> +F:     Documentation/devicetree/bindings/dma/fsl-qdma.txt
> +F:     drivers/dma/fsl-qdma.c
> +
>  FREESCALE I2C CPM DRIVER
>  M:     Jochen Friedrich <jochen@scram.de>
>  L:     linuxppc-dev@lists.ozlabs.org
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index b458475..e29e985 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -193,6 +193,16 @@ config FSL_EDMA
>           multiplexing capability for DMA request sources(slot).
>           This module can be found on Freescale Vybrid and LS-1 SoCs.
>
> +config FSL_QDMA
> +       tristate "Freescale qDMA engine support"
> +       select DMA_ENGINE
> +       select DMA_VIRTUAL_CHANNELS
> +       help
> +         Support the Freescale qDMA engine with command queue and legacy mode.
> +         Channel virtualization is supported through enqueuing of DMA jobs to,
> +         or dequeuing DMA jobs from, different work queues.
> +         This module can be found on Freescale LS SoCs.

Better to spell out Layerscape

> +
>  config FSL_RAID
>          tristate "Freescale RAID engine Support"
>          depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> index 7711a71..8de7526 100644
> --- a/drivers/dma/Makefile
> +++ b/drivers/dma/Makefile
> @@ -29,6 +29,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
>  obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
>  obj-$(CONFIG_FSL_DMA) += fsldma.o
>  obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
> +obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
>  obj-$(CONFIG_FSL_RAID) += fsl_raid.o
>  obj-$(CONFIG_HSU_DMA) += hsu/
>  obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
> diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
> new file mode 100644
> index 0000000..846cdba
> --- /dev/null
> +++ b/drivers/dma/fsl-qdma.c
> @@ -0,0 +1,521 @@
> +/*
> + * drivers/dma/fsl-qdma.c
> + *
> + * Copyright 2014-2015 Freescale Semiconductor, Inc.
> + *
> + * Driver for the Freescale qDMA engine with legacy mode.

If this is only for legacy mode, name it fsl-qdma-legacy.c

> + * This module can be found on Freescale LS SoCs.
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/dmapool.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_dma.h>
> +#include <linux/of_irq.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#include "virt-dma.h"
> +
> +#define FSL_QDMA_DMR           0x0
> +#define FSL_QDMA_DSR_P         0x4
> +
> +#define FSL_QDMA_DSR_M         0x10004
> +#define FSL_QDMA_DLMR          0x10100
> +#define FSL_QDMA_DLSR          0x10104
> +#define FSL_QDMA_DLSATR                0x10110
> +#define FSL_QDMA_DLSAR         0x10114
> +#define FSL_QDMA_DLDATR                0x10118
> +#define FSL_QDMA_DLDAR         0x1011c
> +#define FSL_QDMA_DLBCR         0x10120
> +#define FSL_QDMA_DLESAD                0x10148
> +#define FSL_QDMA_DLEDAD                0x1014c
> +
> +#define FSL_QDMA_DLMR_CS       0x1
> +#define FSL_QDMA_DLMR_EOSIE    0x200
> +#define FSL_QDMA_DLMR_EIE      0x40
> +#define FSL_QDMA_DLSR_TE       0x80
> +#define FSL_QDMA_DLSR_CH       0x20
> +#define FSL_QDMA_DLSR_PE       0x10
> +#define FSL_QDMA_DLSR_CB       0x4
> +#define FSL_QDMA_DLSR_EOSI     0x2
> +
> +#define FSL_QDMA_SRTTYPE_R_N   0x40000
> +
> +struct fsl_qdma_tcd {
> +       u64     saddr;
> +       u32     nbytes;
> +       u64     daddr;
> +};
> +
> +struct fsl_qdma_chan_config {
> +       enum dma_transfer_direction     dir;
> +       enum dma_slave_buswidth         addr_width;
> +       u32                             burst;
> +       u32                             attr;
> +};
> +
> +struct fsl_qdma_desc {
> +       struct virt_dma_desc            vdesc;
> +       struct fsl_qdma_chan            *qchan;
> +       struct fsl_qdma_tcd             tcd;
> +};
> +
> +struct fsl_qdma_chan {
> +       struct virt_dma_chan            vchan;
> +       struct fsl_qdma_desc            *desc;
> +       enum dma_status                 status;
> +       u32                             slave_id;
> +       struct fsl_qdma_engine          *qdma;
> +};
> +
> +struct fsl_qdma_engine {
> +       struct dma_device       dma_dev;
> +       void __iomem            *membase;
> +       u32                     n_chans;
> +       struct mutex            fsl_qdma_mutex;
> +       int                     controller_irq;
> +       int                     err_irq;
> +       bool                    big_endian;
> +       struct fsl_qdma_chan    chans[];
> +
> +};
> +
> +static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr)
> +{
> +       if (qdma->big_endian)
> +               return ioread32be(addr);
> +       else
> +               return ioread32(addr);
> +}
> +
> +static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
> +                                               void __iomem *addr)
> +{
> +       if (qdma->big_endian)
> +               iowrite32be(val, addr);
> +       else
> +               iowrite32(val, addr);
> +}
> +
> +static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
> +{
> +       return container_of(chan, struct fsl_qdma_chan, vchan.chan);
> +}
> +
> +static struct fsl_qdma_desc *to_fsl_qdma_desc(struct virt_dma_desc *vd)
> +{
> +       return container_of(vd, struct fsl_qdma_desc, vdesc);
> +}
> +
> +static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
> +{
> +       struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +
> +       fsl_chan->desc = NULL;
> +       return 0;
> +}
> +
> +static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
> +{
> +       struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +       unsigned long flags;
> +       LIST_HEAD(head);
> +
> +       spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
> +       vchan_get_all_descriptors(&fsl_chan->vchan, &head);
> +       spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
> +
> +       vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
> +}
> +
> +static void fsl_qdma_set_tcd_params(struct fsl_qdma_chan *fsl_chan,
> +                                       u64 src, u64 dst, u32 nbytes)
> +{
> +       void __iomem *addr = fsl_chan->qdma->membase;
> +       u32 reg;
> +
> +       /*
> +        * Source address.
> +        * Represents address bits 31-0 of a 49-bit source address.
> +        */
> +       qdma_writel(fsl_chan->qdma, (u32)src, addr + FSL_QDMA_DLSAR);
> +       /*
> +        * Source address.
> +        * Represents address bits 47-32 of a 49-bit source address.
> +        */
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLSATR);
> +       reg |= (u16)(src >> 32) & 0xffff;
> +       reg |= FSL_QDMA_SRTTYPE_R_N;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLSATR);
> +       /*
> +        * Source address.
> +        * Represents address bits 48 of a 49-bit source address.
> +        */
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLESAD);
> +       reg |= (src >> 48) & 0x1;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLESAD);
> +
> +       /*
> +        * Destination address.
> +        * Represents address bits 31-0 of a 49-bit destination address.
> +        */
> +       qdma_writel(fsl_chan->qdma, (u32)dst, addr + FSL_QDMA_DLDAR);
> +       /*
> +        * Destination address.
> +        * Represents address bits 47-32 of a 49-bit destination address.
> +        */
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLDATR);
> +       reg |= (u16)(dst >> 32) & 0xffff;
> +       reg |= FSL_QDMA_SRTTYPE_R_N;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLDATR);
> +       /*
> +        * Destination address.
> +        * Represents address bits 48 of a 49-bit destination address.
> +        */
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLEDAD);
> +       reg |= (dst >> 48) & 0x1;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLEDAD);
> +
> +       /*
> +        * Byte count.
> +        * Contains the number of bytes to transfer.
> +        */
> +       qdma_writel(fsl_chan->qdma, nbytes, addr + FSL_QDMA_DLBCR);
> +}
> +
> +static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
> +{
> +       u32 reg;
> +
> +       reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DLMR);
> +       reg |= FSL_QDMA_DLMR_EOSIE;
> +       reg |= FSL_QDMA_DLMR_EIE;
> +       qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DLMR);
> +       return 0;
> +}
> +
> +static void fsl_qdma_enable_request(struct fsl_qdma_chan *fsl_chan)
> +{
> +       void __iomem *addr = fsl_chan->qdma->membase;
> +       u32 reg;
> +
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLMR);
> +
> +       reg &= ~FSL_QDMA_DLMR_CS;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLMR);
> +
> +       reg |= FSL_QDMA_DLMR_CS;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLMR);
> +}
> +
> +static struct fsl_qdma_desc *fsl_qdma_alloc_desc(struct fsl_qdma_chan *fsl_chan)
> +{
> +       struct fsl_qdma_desc *fsl_desc;
> +
> +       fsl_desc = kzalloc(sizeof(*fsl_desc), GFP_NOWAIT);
> +
> +       if (!fsl_desc)
> +               return NULL;
> +
> +       fsl_desc->qchan = fsl_chan;
> +
> +       return fsl_desc;
> +}
> +
> +static void fsl_qdma_free_desc(struct virt_dma_desc *vdesc)
> +{
> +       struct fsl_qdma_desc *fsl_desc;
> +
> +       fsl_desc = to_fsl_qdma_desc(vdesc);
> +       kfree(fsl_desc);
> +}
> +
> +static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
> +{
> +       struct fsl_qdma_tcd *tcd;
> +       struct virt_dma_desc *vdesc;
> +
> +       vdesc = vchan_next_desc(&fsl_chan->vchan);
> +       if (!vdesc)
> +               return;
> +
> +       fsl_chan->desc = to_fsl_qdma_desc(vdesc);
> +       tcd = &fsl_chan->desc->tcd;
> +       fsl_qdma_set_tcd_params(fsl_chan, tcd->saddr, tcd->daddr, tcd->nbytes);
> +       fsl_qdma_enable_request(fsl_chan);
> +       fsl_chan->status = DMA_IN_PROGRESS;
> +}
> +
> +static void fsl_qdma_issue_pending(struct dma_chan *chan)
> +{
> +       struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +       unsigned long flags;
> +
> +       spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
> +
> +       if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->desc)
> +               fsl_qdma_enqueue_desc(fsl_chan);
> +
> +       spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
> +}
> +
> +static struct dma_async_tx_descriptor *
> +fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
> +               dma_addr_t src, size_t len, unsigned long flags)
> +{
> +       struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +       struct fsl_qdma_desc *fsl_desc;
> +       struct fsl_qdma_tcd *tcd;
> +
> +       fsl_desc = fsl_qdma_alloc_desc(fsl_chan);
> +       if (!fsl_desc)
> +               return NULL;
> +
> +       tcd = &fsl_desc->tcd;
> +       tcd->saddr = (u64)src;
> +       tcd->nbytes = (u32)len;
> +       tcd->daddr = (u64)dst;
> +
> +       return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
> +}
> +
> +static enum dma_status fsl_qdma_tx_status(struct dma_chan *chan,
> +               dma_cookie_t cookie, struct dma_tx_state *txstate)
> +{
> +       return dma_cookie_status(chan, cookie, txstate);
> +}
> +
> +static irqreturn_t fsl_qdma_controller_handler(int irq, void *dev_id)
> +{
> +       struct fsl_qdma_engine *fsl_qdma = dev_id;
> +       struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[0];
> +       void __iomem *addr = fsl_qdma->membase;
> +       u32 reg;
> +
> +       reg = qdma_readl(fsl_qdma, addr + FSL_QDMA_DLSR);
> +       if (!(reg & FSL_QDMA_DLSR_EOSI))
> +               return IRQ_NONE;
> +
> +       /* Don't clean TE and PE bit if they are set. */
> +       reg &= ~FSL_QDMA_DLSR_TE & ~FSL_QDMA_DLSR_PE;
> +       qdma_writel(fsl_qdma, reg, addr + FSL_QDMA_DLSR);
> +
> +       spin_lock(&fsl_chan->vchan.lock);
> +       list_del(&fsl_chan->desc->vdesc.node);
> +       vchan_cookie_complete(&fsl_chan->desc->vdesc);
> +       fsl_chan->desc = NULL;
> +       fsl_chan->status = DMA_COMPLETE;
> +       fsl_qdma_enqueue_desc(fsl_chan);
> +       spin_unlock(&fsl_chan->vchan.lock);
> +
> +       return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t fsl_qdma_controller_handler_err(int irq, void *dev_id)
> +{
> +       struct fsl_qdma_engine *fsl_qdma = dev_id;
> +       u32 reg;
> +
> +       reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DLSR);
> +
> +       if (reg & FSL_QDMA_DLSR_TE) {
> +               dev_err(fsl_qdma->dma_dev.dev,
> +                       "Transfer error. Check your address please!\n");
> +       }
> +
> +       if (reg & FSL_QDMA_DLSR_PE) {
> +               dev_err(fsl_qdma->dma_dev.dev,
> +                       "Programming error. Check your setting please!\n");
> +       }
> +
> +       /* Don't clean EOSI bit if it's set. */
> +       reg &= ~FSL_QDMA_DLSR_EOSI;
> +       qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DLSR);
> +
> +       return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t fsl_qdma_irq_handler(int irq, void *dev_id)
> +{
> +       if (fsl_qdma_controller_handler(irq, dev_id) == IRQ_HANDLED)
> +               return IRQ_HANDLED;
> +
> +       return fsl_qdma_controller_handler_err(irq, dev_id);
> +}
> +
> +static int fsl_qdma_irq_init(struct platform_device *pdev,
> +                                       struct fsl_qdma_engine *fsl_qdma)
> +{
> +       int ret;
> +
> +       fsl_qdma->controller_irq = platform_get_irq_byname(pdev,
> +                                                       "qdma-tx");
> +       if (fsl_qdma->controller_irq < 0) {
> +               dev_err(&pdev->dev, "Can't get qdma controller irq.\n");
> +               return fsl_qdma->controller_irq;
> +       }
> +
> +       fsl_qdma->err_irq = platform_get_irq_byname(pdev,
> +                                                       "qdma-err");
> +       if (fsl_qdma->err_irq < 0) {
> +               dev_err(&pdev->dev, "Can't get qdma err irq.\n");
> +               return fsl_qdma->err_irq;
> +       }
> +
> +       if (fsl_qdma->controller_irq == fsl_qdma->err_irq) {
> +               ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
> +                                       fsl_qdma_irq_handler, 0,
> +                                       "qDMA controller", fsl_qdma);
> +
> +               if (ret) {
> +                       dev_err(&pdev->dev, "Can't register qDMA IRQ.\n");
> +                       return  ret;
> +               }
> +       } else {
> +               ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
> +                               fsl_qdma_controller_handler, 0,
> +                               "qDMA controller", fsl_qdma);
> +               if (ret) {
> +                       dev_err(&pdev->dev,
> +                               "Can't register qDMA controller IRQ.\n");
> +                       return  ret;
> +               }
> +
> +               ret = devm_request_irq(&pdev->dev, fsl_qdma->err_irq,
> +                               fsl_qdma_controller_handler_err, 0,
> +                               "qDMA err", fsl_qdma);
> +               if (ret) {
> +                       dev_err(&pdev->dev, "Can't register qDMA err IRQ.\n");
> +                       return  ret;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static int fsl_qdma_probe(struct platform_device *pdev)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       struct fsl_qdma_engine *fsl_qdma;
> +       struct fsl_qdma_chan *fsl_chan;
> +       struct resource *res;
> +       unsigned int len, chans;
> +       int ret, i;
> +
> +       ret = of_property_read_u32(np, "channels", &chans);
> +       if (ret) {
> +               dev_err(&pdev->dev, "Can't get channels.\n");
> +               return ret;
> +       }
> +
> +       len = sizeof(*fsl_qdma) + sizeof(*fsl_chan) * chans;
> +       fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
> +       if (!fsl_qdma)
> +               return -ENOMEM;
> +
> +       fsl_qdma->n_chans = chans;
> +       mutex_init(&fsl_qdma->fsl_qdma_mutex);
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       fsl_qdma->membase = devm_ioremap_resource(&pdev->dev, res);
> +       if (IS_ERR(fsl_qdma->membase))
> +               return PTR_ERR(fsl_qdma->membase);
> +
> +       ret = fsl_qdma_irq_init(pdev, fsl_qdma);
> +       if (ret)
> +               return ret;
> +
> +       fsl_qdma->big_endian = of_property_read_bool(np, "big-endian");
> +       INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
> +       for (i = 0; i < fsl_qdma->n_chans; i++) {
> +               struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
> +
> +               fsl_chan->qdma = fsl_qdma;
> +               fsl_chan->desc = NULL;
> +               fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
> +               vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
> +       }
> +
> +       dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
> +       dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
> +       dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
> +
> +       fsl_qdma->dma_dev.dev = &pdev->dev;
> +       fsl_qdma->dma_dev.device_alloc_chan_resources
> +               = fsl_qdma_alloc_chan_resources;
> +       fsl_qdma->dma_dev.device_free_chan_resources
> +               = fsl_qdma_free_chan_resources;
> +       fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
> +       fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
> +       fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
> +
> +       platform_set_drvdata(pdev, fsl_qdma);
> +
> +       ret = dma_async_device_register(&fsl_qdma->dma_dev);
> +       if (ret) {
> +               dev_err(&pdev->dev, "Can't register Freescale qDMA engine.\n");
> +               return ret;
> +       }
> +
> +       ret = fsl_qdma_reg_init(fsl_qdma);
> +       if (ret) {
> +               dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n");
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static int fsl_qdma_remove(struct platform_device *pdev)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
> +
> +       of_dma_controller_free(np);
> +       dma_async_device_unregister(&fsl_qdma->dma_dev);
> +       return 0;
> +}
> +
> +static const struct of_device_id fsl_qdma_dt_ids[] = {
> +       { .compatible = "fsl,ls-qdma", },
> +       { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, fsl_qdma_dt_ids);
> +
> +static struct platform_driver fsl_qdma_driver = {
> +       .driver         = {
> +               .name   = "fsl-qdma",
> +               .owner  = THIS_MODULE,
> +               .of_match_table = fsl_qdma_dt_ids,
> +       },
> +       .probe          = fsl_qdma_probe,
> +       .remove         = fsl_qdma_remove,
> +};
> +
> +static int __init fsl_qdma_init(void)
> +{
> +       return platform_driver_register(&fsl_qdma_driver);
> +}
> +subsys_initcall(fsl_qdma_init);
> +
> +static void __exit fsl_qdma_exit(void)
> +{
> +       platform_driver_unregister(&fsl_qdma_driver);
> +}
> +module_exit(fsl_qdma_exit);
> +
> +MODULE_ALIAS("platform:fsl-qdma");
> +MODULE_DESCRIPTION("Freescale qDMA engine driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.1.0.27.g96db324
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Li Yang]

On Fri, Sep 11, 2015 at 12:53 AM, Yuan Yao <yao.yuan@freescale.com> wrote:
> Add Freescale Queue Direct Memory Access(qDMA) controller support.
> This module can be found on LS-1 and LS-2 SoCs.
>
> This add the legacy mode support for qDMA.
>
> Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
> ---
>  Documentation/devicetree/bindings/dma/fsl-qdma.txt |  43 ++
>  MAINTAINERS                                        |   7 +
>  drivers/dma/Kconfig                                |  10 +
>  drivers/dma/Makefile                               |   1 +
>  drivers/dma/fsl-qdma.c                             | 521 +++++++++++++++++++++
>  5 files changed, 582 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
>  create mode 100644 drivers/dma/fsl-qdma.c
>
> diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
> new file mode 100644
> index 0000000..cdae71c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
> @@ -0,0 +1,43 @@
> +* Freescale queue Direct Memory Access Controller(qDMA) Controller
> +
> +  The qDMA controller transfers blocks of data between one source and one or more
> +destinations. The blocks of data transferred can be represented in memory as contiguous
> +or non-contiguous using scatter/gather table(s). Channel virtualization is supported
> +through enqueuing of DMA jobs to, or dequeuing DMA jobs from, different work
> +queues.
> +  Legacy mode is primarily included for software requiring the earlier
> +QorIQ DMA programming model. This mode provides a simple programming
> +model not utilizing the datapath architecture. In legacy mode, DMA
> +operations are directly configured through a set of architectural
> +registers per channel.

Is this binding only covering the legacy mode?  The binding should
describe the whole IP block no matter if we have driver for all the
features.

> +
> +* qDMA Controller
> +Required properties:
> +- compatible :
> +       - "fsl,ls-qdma" for qDMA used similar to that on LS SoC

Compatible need to be specific like "fsl,ls1021a-qdma".  See
http://www.devicetree.org/Device_Tree_Usage.

> +- reg : Specifies base physical address(s) and size of the qDMA registers.
> +       The region is qDMA control register's address and size.
> +- interrupts : A list of interrupt-specifiers, one for each entry in
> +       interrupt-names.
> +- interrupt-names : Should contain:
> +       "qdma-tx" - the  interrupt
> +       "qdma-err" - the error interrupt
> +- channels : Number of channels supported by the controller
> +
> +Optional properties:
> +- big-endian: If present registers and hardware scatter/gather descriptors
> +       of the qDMA are implemented in big endian mode, otherwise in little

Endian
> +       mode.
> +
> +
> +Examples:
> +
> +       qdma: qdma at 8390000 {
> +               compatible = "fsl,ls-qdma";
> +               reg = <0x0 0x8380000 0x0 0x20000>;
> +               interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
> +               interrupt-names = "qdma-tx", "qdma-err";
> +               big-endian;
> +               channels = <1>;
> +       };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5772ccf..a4d1b52 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -4357,6 +4357,13 @@ L:       linuxppc-dev at lists.ozlabs.org
>  S:     Maintained
>  F:     drivers/dma/fsldma.*
>
> +FREESCALE qDMA DRIVER
> +M:     Yuan Yao <yao.yuan@freescale.com>
> +L:     linux-arm-kernel at lists.infradead.org

Interestingly you listed arm mailing list instead of dmaengine mailing list.

> +S:     Maintained
> +F:     Documentation/devicetree/bindings/dma/fsl-qdma.txt
> +F:     drivers/dma/fsl-qdma.c
> +
>  FREESCALE I2C CPM DRIVER
>  M:     Jochen Friedrich <jochen@scram.de>
>  L:     linuxppc-dev at lists.ozlabs.org
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index b458475..e29e985 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -193,6 +193,16 @@ config FSL_EDMA
>           multiplexing capability for DMA request sources(slot).
>           This module can be found on Freescale Vybrid and LS-1 SoCs.
>
> +config FSL_QDMA
> +       tristate "Freescale qDMA engine support"
> +       select DMA_ENGINE
> +       select DMA_VIRTUAL_CHANNELS
> +       help
> +         Support the Freescale qDMA engine with command queue and legacy mode.
> +         Channel virtualization is supported through enqueuing of DMA jobs to,
> +         or dequeuing DMA jobs from, different work queues.
> +         This module can be found on Freescale LS SoCs.

Better to spell out Layerscape

> +
>  config FSL_RAID
>          tristate "Freescale RAID engine Support"
>          depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> index 7711a71..8de7526 100644
> --- a/drivers/dma/Makefile
> +++ b/drivers/dma/Makefile
> @@ -29,6 +29,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
>  obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
>  obj-$(CONFIG_FSL_DMA) += fsldma.o
>  obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
> +obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
>  obj-$(CONFIG_FSL_RAID) += fsl_raid.o
>  obj-$(CONFIG_HSU_DMA) += hsu/
>  obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
> diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
> new file mode 100644
> index 0000000..846cdba
> --- /dev/null
> +++ b/drivers/dma/fsl-qdma.c
> @@ -0,0 +1,521 @@
> +/*
> + * drivers/dma/fsl-qdma.c
> + *
> + * Copyright 2014-2015 Freescale Semiconductor, Inc.
> + *
> + * Driver for the Freescale qDMA engine with legacy mode.

If this is only for legacy mode, name it fsl-qdma-legacy.c

> + * This module can be found on Freescale LS SoCs.
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/dmapool.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_dma.h>
> +#include <linux/of_irq.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#include "virt-dma.h"
> +
> +#define FSL_QDMA_DMR           0x0
> +#define FSL_QDMA_DSR_P         0x4
> +
> +#define FSL_QDMA_DSR_M         0x10004
> +#define FSL_QDMA_DLMR          0x10100
> +#define FSL_QDMA_DLSR          0x10104
> +#define FSL_QDMA_DLSATR                0x10110
> +#define FSL_QDMA_DLSAR         0x10114
> +#define FSL_QDMA_DLDATR                0x10118
> +#define FSL_QDMA_DLDAR         0x1011c
> +#define FSL_QDMA_DLBCR         0x10120
> +#define FSL_QDMA_DLESAD                0x10148
> +#define FSL_QDMA_DLEDAD                0x1014c
> +
> +#define FSL_QDMA_DLMR_CS       0x1
> +#define FSL_QDMA_DLMR_EOSIE    0x200
> +#define FSL_QDMA_DLMR_EIE      0x40
> +#define FSL_QDMA_DLSR_TE       0x80
> +#define FSL_QDMA_DLSR_CH       0x20
> +#define FSL_QDMA_DLSR_PE       0x10
> +#define FSL_QDMA_DLSR_CB       0x4
> +#define FSL_QDMA_DLSR_EOSI     0x2
> +
> +#define FSL_QDMA_SRTTYPE_R_N   0x40000
> +
> +struct fsl_qdma_tcd {
> +       u64     saddr;
> +       u32     nbytes;
> +       u64     daddr;
> +};
> +
> +struct fsl_qdma_chan_config {
> +       enum dma_transfer_direction     dir;
> +       enum dma_slave_buswidth         addr_width;
> +       u32                             burst;
> +       u32                             attr;
> +};
> +
> +struct fsl_qdma_desc {
> +       struct virt_dma_desc            vdesc;
> +       struct fsl_qdma_chan            *qchan;
> +       struct fsl_qdma_tcd             tcd;
> +};
> +
> +struct fsl_qdma_chan {
> +       struct virt_dma_chan            vchan;
> +       struct fsl_qdma_desc            *desc;
> +       enum dma_status                 status;
> +       u32                             slave_id;
> +       struct fsl_qdma_engine          *qdma;
> +};
> +
> +struct fsl_qdma_engine {
> +       struct dma_device       dma_dev;
> +       void __iomem            *membase;
> +       u32                     n_chans;
> +       struct mutex            fsl_qdma_mutex;
> +       int                     controller_irq;
> +       int                     err_irq;
> +       bool                    big_endian;
> +       struct fsl_qdma_chan    chans[];
> +
> +};
> +
> +static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr)
> +{
> +       if (qdma->big_endian)
> +               return ioread32be(addr);
> +       else
> +               return ioread32(addr);
> +}
> +
> +static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
> +                                               void __iomem *addr)
> +{
> +       if (qdma->big_endian)
> +               iowrite32be(val, addr);
> +       else
> +               iowrite32(val, addr);
> +}
> +
> +static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
> +{
> +       return container_of(chan, struct fsl_qdma_chan, vchan.chan);
> +}
> +
> +static struct fsl_qdma_desc *to_fsl_qdma_desc(struct virt_dma_desc *vd)
> +{
> +       return container_of(vd, struct fsl_qdma_desc, vdesc);
> +}
> +
> +static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
> +{
> +       struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +
> +       fsl_chan->desc = NULL;
> +       return 0;
> +}
> +
> +static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
> +{
> +       struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +       unsigned long flags;
> +       LIST_HEAD(head);
> +
> +       spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
> +       vchan_get_all_descriptors(&fsl_chan->vchan, &head);
> +       spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
> +
> +       vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
> +}
> +
> +static void fsl_qdma_set_tcd_params(struct fsl_qdma_chan *fsl_chan,
> +                                       u64 src, u64 dst, u32 nbytes)
> +{
> +       void __iomem *addr = fsl_chan->qdma->membase;
> +       u32 reg;
> +
> +       /*
> +        * Source address.
> +        * Represents address bits 31-0 of a 49-bit source address.
> +        */
> +       qdma_writel(fsl_chan->qdma, (u32)src, addr + FSL_QDMA_DLSAR);
> +       /*
> +        * Source address.
> +        * Represents address bits 47-32 of a 49-bit source address.
> +        */
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLSATR);
> +       reg |= (u16)(src >> 32) & 0xffff;
> +       reg |= FSL_QDMA_SRTTYPE_R_N;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLSATR);
> +       /*
> +        * Source address.
> +        * Represents address bits 48 of a 49-bit source address.
> +        */
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLESAD);
> +       reg |= (src >> 48) & 0x1;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLESAD);
> +
> +       /*
> +        * Destination address.
> +        * Represents address bits 31-0 of a 49-bit destination address.
> +        */
> +       qdma_writel(fsl_chan->qdma, (u32)dst, addr + FSL_QDMA_DLDAR);
> +       /*
> +        * Destination address.
> +        * Represents address bits 47-32 of a 49-bit destination address.
> +        */
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLDATR);
> +       reg |= (u16)(dst >> 32) & 0xffff;
> +       reg |= FSL_QDMA_SRTTYPE_R_N;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLDATR);
> +       /*
> +        * Destination address.
> +        * Represents address bits 48 of a 49-bit destination address.
> +        */
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLEDAD);
> +       reg |= (dst >> 48) & 0x1;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLEDAD);
> +
> +       /*
> +        * Byte count.
> +        * Contains the number of bytes to transfer.
> +        */
> +       qdma_writel(fsl_chan->qdma, nbytes, addr + FSL_QDMA_DLBCR);
> +}
> +
> +static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
> +{
> +       u32 reg;
> +
> +       reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DLMR);
> +       reg |= FSL_QDMA_DLMR_EOSIE;
> +       reg |= FSL_QDMA_DLMR_EIE;
> +       qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DLMR);
> +       return 0;
> +}
> +
> +static void fsl_qdma_enable_request(struct fsl_qdma_chan *fsl_chan)
> +{
> +       void __iomem *addr = fsl_chan->qdma->membase;
> +       u32 reg;
> +
> +       reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLMR);
> +
> +       reg &= ~FSL_QDMA_DLMR_CS;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLMR);
> +
> +       reg |= FSL_QDMA_DLMR_CS;
> +       qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLMR);
> +}
> +
> +static struct fsl_qdma_desc *fsl_qdma_alloc_desc(struct fsl_qdma_chan *fsl_chan)
> +{
> +       struct fsl_qdma_desc *fsl_desc;
> +
> +       fsl_desc = kzalloc(sizeof(*fsl_desc), GFP_NOWAIT);
> +
> +       if (!fsl_desc)
> +               return NULL;
> +
> +       fsl_desc->qchan = fsl_chan;
> +
> +       return fsl_desc;
> +}
> +
> +static void fsl_qdma_free_desc(struct virt_dma_desc *vdesc)
> +{
> +       struct fsl_qdma_desc *fsl_desc;
> +
> +       fsl_desc = to_fsl_qdma_desc(vdesc);
> +       kfree(fsl_desc);
> +}
> +
> +static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
> +{
> +       struct fsl_qdma_tcd *tcd;
> +       struct virt_dma_desc *vdesc;
> +
> +       vdesc = vchan_next_desc(&fsl_chan->vchan);
> +       if (!vdesc)
> +               return;
> +
> +       fsl_chan->desc = to_fsl_qdma_desc(vdesc);
> +       tcd = &fsl_chan->desc->tcd;
> +       fsl_qdma_set_tcd_params(fsl_chan, tcd->saddr, tcd->daddr, tcd->nbytes);
> +       fsl_qdma_enable_request(fsl_chan);
> +       fsl_chan->status = DMA_IN_PROGRESS;
> +}
> +
> +static void fsl_qdma_issue_pending(struct dma_chan *chan)
> +{
> +       struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +       unsigned long flags;
> +
> +       spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
> +
> +       if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->desc)
> +               fsl_qdma_enqueue_desc(fsl_chan);
> +
> +       spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
> +}
> +
> +static struct dma_async_tx_descriptor *
> +fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
> +               dma_addr_t src, size_t len, unsigned long flags)
> +{
> +       struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
> +       struct fsl_qdma_desc *fsl_desc;
> +       struct fsl_qdma_tcd *tcd;
> +
> +       fsl_desc = fsl_qdma_alloc_desc(fsl_chan);
> +       if (!fsl_desc)
> +               return NULL;
> +
> +       tcd = &fsl_desc->tcd;
> +       tcd->saddr = (u64)src;
> +       tcd->nbytes = (u32)len;
> +       tcd->daddr = (u64)dst;
> +
> +       return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
> +}
> +
> +static enum dma_status fsl_qdma_tx_status(struct dma_chan *chan,
> +               dma_cookie_t cookie, struct dma_tx_state *txstate)
> +{
> +       return dma_cookie_status(chan, cookie, txstate);
> +}
> +
> +static irqreturn_t fsl_qdma_controller_handler(int irq, void *dev_id)
> +{
> +       struct fsl_qdma_engine *fsl_qdma = dev_id;
> +       struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[0];
> +       void __iomem *addr = fsl_qdma->membase;
> +       u32 reg;
> +
> +       reg = qdma_readl(fsl_qdma, addr + FSL_QDMA_DLSR);
> +       if (!(reg & FSL_QDMA_DLSR_EOSI))
> +               return IRQ_NONE;
> +
> +       /* Don't clean TE and PE bit if they are set. */
> +       reg &= ~FSL_QDMA_DLSR_TE & ~FSL_QDMA_DLSR_PE;
> +       qdma_writel(fsl_qdma, reg, addr + FSL_QDMA_DLSR);
> +
> +       spin_lock(&fsl_chan->vchan.lock);
> +       list_del(&fsl_chan->desc->vdesc.node);
> +       vchan_cookie_complete(&fsl_chan->desc->vdesc);
> +       fsl_chan->desc = NULL;
> +       fsl_chan->status = DMA_COMPLETE;
> +       fsl_qdma_enqueue_desc(fsl_chan);
> +       spin_unlock(&fsl_chan->vchan.lock);
> +
> +       return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t fsl_qdma_controller_handler_err(int irq, void *dev_id)
> +{
> +       struct fsl_qdma_engine *fsl_qdma = dev_id;
> +       u32 reg;
> +
> +       reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DLSR);
> +
> +       if (reg & FSL_QDMA_DLSR_TE) {
> +               dev_err(fsl_qdma->dma_dev.dev,
> +                       "Transfer error. Check your address please!\n");
> +       }
> +
> +       if (reg & FSL_QDMA_DLSR_PE) {
> +               dev_err(fsl_qdma->dma_dev.dev,
> +                       "Programming error. Check your setting please!\n");
> +       }
> +
> +       /* Don't clean EOSI bit if it's set. */
> +       reg &= ~FSL_QDMA_DLSR_EOSI;
> +       qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DLSR);
> +
> +       return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t fsl_qdma_irq_handler(int irq, void *dev_id)
> +{
> +       if (fsl_qdma_controller_handler(irq, dev_id) == IRQ_HANDLED)
> +               return IRQ_HANDLED;
> +
> +       return fsl_qdma_controller_handler_err(irq, dev_id);
> +}
> +
> +static int fsl_qdma_irq_init(struct platform_device *pdev,
> +                                       struct fsl_qdma_engine *fsl_qdma)
> +{
> +       int ret;
> +
> +       fsl_qdma->controller_irq = platform_get_irq_byname(pdev,
> +                                                       "qdma-tx");
> +       if (fsl_qdma->controller_irq < 0) {
> +               dev_err(&pdev->dev, "Can't get qdma controller irq.\n");
> +               return fsl_qdma->controller_irq;
> +       }
> +
> +       fsl_qdma->err_irq = platform_get_irq_byname(pdev,
> +                                                       "qdma-err");
> +       if (fsl_qdma->err_irq < 0) {
> +               dev_err(&pdev->dev, "Can't get qdma err irq.\n");
> +               return fsl_qdma->err_irq;
> +       }
> +
> +       if (fsl_qdma->controller_irq == fsl_qdma->err_irq) {
> +               ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
> +                                       fsl_qdma_irq_handler, 0,
> +                                       "qDMA controller", fsl_qdma);
> +
> +               if (ret) {
> +                       dev_err(&pdev->dev, "Can't register qDMA IRQ.\n");
> +                       return  ret;
> +               }
> +       } else {
> +               ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
> +                               fsl_qdma_controller_handler, 0,
> +                               "qDMA controller", fsl_qdma);
> +               if (ret) {
> +                       dev_err(&pdev->dev,
> +                               "Can't register qDMA controller IRQ.\n");
> +                       return  ret;
> +               }
> +
> +               ret = devm_request_irq(&pdev->dev, fsl_qdma->err_irq,
> +                               fsl_qdma_controller_handler_err, 0,
> +                               "qDMA err", fsl_qdma);
> +               if (ret) {
> +                       dev_err(&pdev->dev, "Can't register qDMA err IRQ.\n");
> +                       return  ret;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static int fsl_qdma_probe(struct platform_device *pdev)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       struct fsl_qdma_engine *fsl_qdma;
> +       struct fsl_qdma_chan *fsl_chan;
> +       struct resource *res;
> +       unsigned int len, chans;
> +       int ret, i;
> +
> +       ret = of_property_read_u32(np, "channels", &chans);
> +       if (ret) {
> +               dev_err(&pdev->dev, "Can't get channels.\n");
> +               return ret;
> +       }
> +
> +       len = sizeof(*fsl_qdma) + sizeof(*fsl_chan) * chans;
> +       fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
> +       if (!fsl_qdma)
> +               return -ENOMEM;
> +
> +       fsl_qdma->n_chans = chans;
> +       mutex_init(&fsl_qdma->fsl_qdma_mutex);
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       fsl_qdma->membase = devm_ioremap_resource(&pdev->dev, res);
> +       if (IS_ERR(fsl_qdma->membase))
> +               return PTR_ERR(fsl_qdma->membase);
> +
> +       ret = fsl_qdma_irq_init(pdev, fsl_qdma);
> +       if (ret)
> +               return ret;
> +
> +       fsl_qdma->big_endian = of_property_read_bool(np, "big-endian");
> +       INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
> +       for (i = 0; i < fsl_qdma->n_chans; i++) {
> +               struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
> +
> +               fsl_chan->qdma = fsl_qdma;
> +               fsl_chan->desc = NULL;
> +               fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
> +               vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
> +       }
> +
> +       dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
> +       dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
> +       dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
> +
> +       fsl_qdma->dma_dev.dev = &pdev->dev;
> +       fsl_qdma->dma_dev.device_alloc_chan_resources
> +               = fsl_qdma_alloc_chan_resources;
> +       fsl_qdma->dma_dev.device_free_chan_resources
> +               = fsl_qdma_free_chan_resources;
> +       fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
> +       fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
> +       fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
> +
> +       platform_set_drvdata(pdev, fsl_qdma);
> +
> +       ret = dma_async_device_register(&fsl_qdma->dma_dev);
> +       if (ret) {
> +               dev_err(&pdev->dev, "Can't register Freescale qDMA engine.\n");
> +               return ret;
> +       }
> +
> +       ret = fsl_qdma_reg_init(fsl_qdma);
> +       if (ret) {
> +               dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n");
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static int fsl_qdma_remove(struct platform_device *pdev)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
> +
> +       of_dma_controller_free(np);
> +       dma_async_device_unregister(&fsl_qdma->dma_dev);
> +       return 0;
> +}
> +
> +static const struct of_device_id fsl_qdma_dt_ids[] = {
> +       { .compatible = "fsl,ls-qdma", },
> +       { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, fsl_qdma_dt_ids);
> +
> +static struct platform_driver fsl_qdma_driver = {
> +       .driver         = {
> +               .name   = "fsl-qdma",
> +               .owner  = THIS_MODULE,
> +               .of_match_table = fsl_qdma_dt_ids,
> +       },
> +       .probe          = fsl_qdma_probe,
> +       .remove         = fsl_qdma_remove,
> +};
> +
> +static int __init fsl_qdma_init(void)
> +{
> +       return platform_driver_register(&fsl_qdma_driver);
> +}
> +subsys_initcall(fsl_qdma_init);
> +
> +static void __exit fsl_qdma_exit(void)
> +{
> +       platform_driver_unregister(&fsl_qdma_driver);
> +}
> +module_exit(fsl_qdma_exit);
> +
> +MODULE_ALIAS("platform:fsl-qdma");
> +MODULE_DESCRIPTION("Freescale qDMA engine driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.1.0.27.g96db324
>
> --
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[PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Yuan Yao]

Add Freescale Queue Direct Memory Access(qDMA) controller support.
This module can be found on LS-1 and LS-2 SoCs.

This add the legacy mode support for qDMA.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
---
 Documentation/devicetree/bindings/dma/fsl-qdma.txt |  43 ++
 MAINTAINERS                                        |   7 +
 drivers/dma/Kconfig                                |  10 +
 drivers/dma/Makefile                               |   1 +
 drivers/dma/fsl-qdma.c                             | 521 +++++++++++++++++++++
 5 files changed, 582 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
 create mode 100644 drivers/dma/fsl-qdma.c

diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
new file mode 100644
index 0000000..cdae71c
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
@@ -0,0 +1,43 @@
+* Freescale queue Direct Memory Access Controller(qDMA) Controller
+
+  The qDMA controller transfers blocks of data between one source and one or more
+destinations. The blocks of data transferred can be represented in memory as contiguous
+or non-contiguous using scatter/gather table(s). Channel virtualization is supported
+through enqueuing of DMA jobs to, or dequeuing DMA jobs from, different work
+queues.
+  Legacy mode is primarily included for software requiring the earlier
+QorIQ DMA programming model. This mode provides a simple programming
+model not utilizing the datapath architecture. In legacy mode, DMA
+operations are directly configured through a set of architectural
+registers per channel.
+
+* qDMA Controller
+Required properties:
+- compatible :
+	- "fsl,ls-qdma" for qDMA used similar to that on LS SoC
+- reg : Specifies base physical address(s) and size of the qDMA registers.
+	The region is qDMA control register's address and size.
+- interrupts : A list of interrupt-specifiers, one for each entry in
+	interrupt-names.
+- interrupt-names : Should contain:
+	"qdma-tx" - the  interrupt
+	"qdma-err" - the error interrupt
+- channels : Number of channels supported by the controller
+
+Optional properties:
+- big-endian: If present registers and hardware scatter/gather descriptors
+	of the qDMA are implemented in big endian mode, otherwise in little
+	mode.
+
+
+Examples:
+
+	qdma: qdma@8390000 {
+		compatible = "fsl,ls-qdma";
+		reg = <0x0 0x8380000 0x0 0x20000>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "qdma-tx", "qdma-err";
+		big-endian;
+		channels = <1>;
+	};
diff --git a/MAINTAINERS b/MAINTAINERS
index 5772ccf..a4d1b52 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4357,6 +4357,13 @@ L:	linuxppc-dev@lists.ozlabs.org
 S:	Maintained
 F:	drivers/dma/fsldma.*
 
+FREESCALE qDMA DRIVER
+M:     Yuan Yao <yao.yuan@freescale.com>
+L:     linux-arm-kernel@lists.infradead.org
+S:     Maintained
+F:     Documentation/devicetree/bindings/dma/fsl-qdma.txt
+F:     drivers/dma/fsl-qdma.c
+
 FREESCALE I2C CPM DRIVER
 M:	Jochen Friedrich <jochen@scram.de>
 L:	linuxppc-dev@lists.ozlabs.org
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index b458475..e29e985 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -193,6 +193,16 @@ config FSL_EDMA
 	  multiplexing capability for DMA request sources(slot).
 	  This module can be found on Freescale Vybrid and LS-1 SoCs.
 
+config FSL_QDMA
+	tristate "Freescale qDMA engine support"
+	select DMA_ENGINE
+	select DMA_VIRTUAL_CHANNELS
+	help
+	  Support the Freescale qDMA engine with command queue and legacy mode.
+	  Channel virtualization is supported through enqueuing of DMA jobs to,
+	  or dequeuing DMA jobs from, different work queues.
+	  This module can be found on Freescale LS SoCs.
+
 config FSL_RAID
         tristate "Freescale RAID engine Support"
         depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 7711a71..8de7526 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
 obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
 obj-$(CONFIG_FSL_DMA) += fsldma.o
 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
 obj-$(CONFIG_FSL_RAID) += fsl_raid.o
 obj-$(CONFIG_HSU_DMA) += hsu/
 obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
new file mode 100644
index 0000000..846cdba
--- /dev/null
+++ b/drivers/dma/fsl-qdma.c
@@ -0,0 +1,521 @@
+/*
+ * drivers/dma/fsl-qdma.c
+ *
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Driver for the Freescale qDMA engine with legacy mode.
+ * This module can be found on Freescale LS SoCs.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "virt-dma.h"
+
+#define FSL_QDMA_DMR		0x0
+#define FSL_QDMA_DSR_P		0x4
+
+#define FSL_QDMA_DSR_M		0x10004
+#define FSL_QDMA_DLMR		0x10100
+#define FSL_QDMA_DLSR		0x10104
+#define FSL_QDMA_DLSATR		0x10110
+#define FSL_QDMA_DLSAR		0x10114
+#define FSL_QDMA_DLDATR		0x10118
+#define FSL_QDMA_DLDAR		0x1011c
+#define FSL_QDMA_DLBCR		0x10120
+#define FSL_QDMA_DLESAD		0x10148
+#define FSL_QDMA_DLEDAD		0x1014c
+
+#define FSL_QDMA_DLMR_CS	0x1
+#define FSL_QDMA_DLMR_EOSIE	0x200
+#define FSL_QDMA_DLMR_EIE	0x40
+#define FSL_QDMA_DLSR_TE	0x80
+#define FSL_QDMA_DLSR_CH	0x20
+#define FSL_QDMA_DLSR_PE	0x10
+#define FSL_QDMA_DLSR_CB	0x4
+#define FSL_QDMA_DLSR_EOSI	0x2
+
+#define FSL_QDMA_SRTTYPE_R_N	0x40000
+
+struct fsl_qdma_tcd {
+	u64	saddr;
+	u32	nbytes;
+	u64	daddr;
+};
+
+struct fsl_qdma_chan_config {
+	enum dma_transfer_direction	dir;
+	enum dma_slave_buswidth		addr_width;
+	u32				burst;
+	u32				attr;
+};
+
+struct fsl_qdma_desc {
+	struct virt_dma_desc		vdesc;
+	struct fsl_qdma_chan		*qchan;
+	struct fsl_qdma_tcd		tcd;
+};
+
+struct fsl_qdma_chan {
+	struct virt_dma_chan		vchan;
+	struct fsl_qdma_desc		*desc;
+	enum dma_status			status;
+	u32				slave_id;
+	struct fsl_qdma_engine		*qdma;
+};
+
+struct fsl_qdma_engine {
+	struct dma_device	dma_dev;
+	void __iomem		*membase;
+	u32			n_chans;
+	struct mutex            fsl_qdma_mutex;
+	int			controller_irq;
+	int			err_irq;
+	bool			big_endian;
+	struct fsl_qdma_chan	chans[];
+
+};
+
+static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr)
+{
+	if (qdma->big_endian)
+		return ioread32be(addr);
+	else
+		return ioread32(addr);
+}
+
+static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
+						void __iomem *addr)
+{
+	if (qdma->big_endian)
+		iowrite32be(val, addr);
+	else
+		iowrite32(val, addr);
+}
+
+static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct fsl_qdma_chan, vchan.chan);
+}
+
+static struct fsl_qdma_desc *to_fsl_qdma_desc(struct virt_dma_desc *vd)
+{
+	return container_of(vd, struct fsl_qdma_desc, vdesc);
+}
+
+static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+
+	fsl_chan->desc = NULL;
+	return 0;
+}
+
+static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	unsigned long flags;
+	LIST_HEAD(head);
+
+	spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+	vchan_get_all_descriptors(&fsl_chan->vchan, &head);
+	spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
+
+	vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
+}
+
+static void fsl_qdma_set_tcd_params(struct fsl_qdma_chan *fsl_chan,
+					u64 src, u64 dst, u32 nbytes)
+{
+	void __iomem *addr = fsl_chan->qdma->membase;
+	u32 reg;
+
+	/*
+	 * Source address.
+	 * Represents address bits 31-0 of a 49-bit source address.
+	 */
+	qdma_writel(fsl_chan->qdma, (u32)src, addr + FSL_QDMA_DLSAR);
+	/*
+	 * Source address.
+	 * Represents address bits 47-32 of a 49-bit source address.
+	 */
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLSATR);
+	reg |= (u16)(src >> 32) & 0xffff;
+	reg |= FSL_QDMA_SRTTYPE_R_N;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLSATR);
+	/*
+	 * Source address.
+	 * Represents address bits 48 of a 49-bit source address.
+	 */
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLESAD);
+	reg |= (src >> 48) & 0x1;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLESAD);
+
+	/*
+	 * Destination address.
+	 * Represents address bits 31-0 of a 49-bit destination address.
+	 */
+	qdma_writel(fsl_chan->qdma, (u32)dst, addr + FSL_QDMA_DLDAR);
+	/*
+	 * Destination address.
+	 * Represents address bits 47-32 of a 49-bit destination address.
+	 */
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLDATR);
+	reg |= (u16)(dst >> 32) & 0xffff;
+	reg |= FSL_QDMA_SRTTYPE_R_N;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLDATR);
+	/*
+	 * Destination address.
+	 * Represents address bits 48 of a 49-bit destination address.
+	 */
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLEDAD);
+	reg |= (dst >> 48) & 0x1;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLEDAD);
+
+	/*
+	 * Byte count.
+	 * Contains the number of bytes to transfer.
+	 */
+	qdma_writel(fsl_chan->qdma, nbytes, addr + FSL_QDMA_DLBCR);
+}
+
+static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
+{
+	u32 reg;
+
+	reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DLMR);
+	reg |= FSL_QDMA_DLMR_EOSIE;
+	reg |= FSL_QDMA_DLMR_EIE;
+	qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DLMR);
+	return 0;
+}
+
+static void fsl_qdma_enable_request(struct fsl_qdma_chan *fsl_chan)
+{
+	void __iomem *addr = fsl_chan->qdma->membase;
+	u32 reg;
+
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLMR);
+
+	reg &= ~FSL_QDMA_DLMR_CS;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLMR);
+
+	reg |= FSL_QDMA_DLMR_CS;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLMR);
+}
+
+static struct fsl_qdma_desc *fsl_qdma_alloc_desc(struct fsl_qdma_chan *fsl_chan)
+{
+	struct fsl_qdma_desc *fsl_desc;
+
+	fsl_desc = kzalloc(sizeof(*fsl_desc), GFP_NOWAIT);
+
+	if (!fsl_desc)
+		return NULL;
+
+	fsl_desc->qchan = fsl_chan;
+
+	return fsl_desc;
+}
+
+static void fsl_qdma_free_desc(struct virt_dma_desc *vdesc)
+{
+	struct fsl_qdma_desc *fsl_desc;
+
+	fsl_desc = to_fsl_qdma_desc(vdesc);
+	kfree(fsl_desc);
+}
+
+static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
+{
+	struct fsl_qdma_tcd *tcd;
+	struct virt_dma_desc *vdesc;
+
+	vdesc = vchan_next_desc(&fsl_chan->vchan);
+	if (!vdesc)
+		return;
+
+	fsl_chan->desc = to_fsl_qdma_desc(vdesc);
+	tcd = &fsl_chan->desc->tcd;
+	fsl_qdma_set_tcd_params(fsl_chan, tcd->saddr, tcd->daddr, tcd->nbytes);
+	fsl_qdma_enable_request(fsl_chan);
+	fsl_chan->status = DMA_IN_PROGRESS;
+}
+
+static void fsl_qdma_issue_pending(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+
+	if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->desc)
+		fsl_qdma_enqueue_desc(fsl_chan);
+
+	spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
+}
+
+static struct dma_async_tx_descriptor *
+fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
+		dma_addr_t src, size_t len, unsigned long flags)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	struct fsl_qdma_desc *fsl_desc;
+	struct fsl_qdma_tcd *tcd;
+
+	fsl_desc = fsl_qdma_alloc_desc(fsl_chan);
+	if (!fsl_desc)
+		return NULL;
+
+	tcd = &fsl_desc->tcd;
+	tcd->saddr = (u64)src;
+	tcd->nbytes = (u32)len;
+	tcd->daddr = (u64)dst;
+
+	return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
+}
+
+static enum dma_status fsl_qdma_tx_status(struct dma_chan *chan,
+		dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
+	return dma_cookie_status(chan, cookie, txstate);
+}
+
+static irqreturn_t fsl_qdma_controller_handler(int irq, void *dev_id)
+{
+	struct fsl_qdma_engine *fsl_qdma = dev_id;
+	struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[0];
+	void __iomem *addr = fsl_qdma->membase;
+	u32 reg;
+
+	reg = qdma_readl(fsl_qdma, addr + FSL_QDMA_DLSR);
+	if (!(reg & FSL_QDMA_DLSR_EOSI))
+		return IRQ_NONE;
+
+	/* Don't clean TE and PE bit if they are set. */
+	reg &= ~FSL_QDMA_DLSR_TE & ~FSL_QDMA_DLSR_PE;
+	qdma_writel(fsl_qdma, reg, addr + FSL_QDMA_DLSR);
+
+	spin_lock(&fsl_chan->vchan.lock);
+	list_del(&fsl_chan->desc->vdesc.node);
+	vchan_cookie_complete(&fsl_chan->desc->vdesc);
+	fsl_chan->desc = NULL;
+	fsl_chan->status = DMA_COMPLETE;
+	fsl_qdma_enqueue_desc(fsl_chan);
+	spin_unlock(&fsl_chan->vchan.lock);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t fsl_qdma_controller_handler_err(int irq, void *dev_id)
+{
+	struct fsl_qdma_engine *fsl_qdma = dev_id;
+	u32 reg;
+
+	reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DLSR);
+
+	if (reg & FSL_QDMA_DLSR_TE) {
+		dev_err(fsl_qdma->dma_dev.dev,
+			"Transfer error. Check your address please!\n");
+	}
+
+	if (reg & FSL_QDMA_DLSR_PE) {
+		dev_err(fsl_qdma->dma_dev.dev,
+			"Programming error. Check your setting please!\n");
+	}
+
+	/* Don't clean EOSI bit if it's set. */
+	reg &= ~FSL_QDMA_DLSR_EOSI;
+	qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DLSR);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t fsl_qdma_irq_handler(int irq, void *dev_id)
+{
+	if (fsl_qdma_controller_handler(irq, dev_id) == IRQ_HANDLED)
+		return IRQ_HANDLED;
+
+	return fsl_qdma_controller_handler_err(irq, dev_id);
+}
+
+static int fsl_qdma_irq_init(struct platform_device *pdev,
+					struct fsl_qdma_engine *fsl_qdma)
+{
+	int ret;
+
+	fsl_qdma->controller_irq = platform_get_irq_byname(pdev,
+							"qdma-tx");
+	if (fsl_qdma->controller_irq < 0) {
+		dev_err(&pdev->dev, "Can't get qdma controller irq.\n");
+		return fsl_qdma->controller_irq;
+	}
+
+	fsl_qdma->err_irq = platform_get_irq_byname(pdev,
+							"qdma-err");
+	if (fsl_qdma->err_irq < 0) {
+		dev_err(&pdev->dev, "Can't get qdma err irq.\n");
+		return fsl_qdma->err_irq;
+	}
+
+	if (fsl_qdma->controller_irq == fsl_qdma->err_irq) {
+		ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
+					fsl_qdma_irq_handler, 0,
+					"qDMA controller", fsl_qdma);
+
+		if (ret) {
+			dev_err(&pdev->dev, "Can't register qDMA IRQ.\n");
+			return  ret;
+		}
+	} else {
+		ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
+				fsl_qdma_controller_handler, 0,
+				"qDMA controller", fsl_qdma);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"Can't register qDMA controller IRQ.\n");
+			return  ret;
+		}
+
+		ret = devm_request_irq(&pdev->dev, fsl_qdma->err_irq,
+				fsl_qdma_controller_handler_err, 0,
+				"qDMA err", fsl_qdma);
+		if (ret) {
+			dev_err(&pdev->dev, "Can't register qDMA err IRQ.\n");
+			return  ret;
+		}
+	}
+
+	return 0;
+}
+
+static int fsl_qdma_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_engine *fsl_qdma;
+	struct fsl_qdma_chan *fsl_chan;
+	struct resource *res;
+	unsigned int len, chans;
+	int ret, i;
+
+	ret = of_property_read_u32(np, "channels", &chans);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't get channels.\n");
+		return ret;
+	}
+
+	len = sizeof(*fsl_qdma) + sizeof(*fsl_chan) * chans;
+	fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
+	if (!fsl_qdma)
+		return -ENOMEM;
+
+	fsl_qdma->n_chans = chans;
+	mutex_init(&fsl_qdma->fsl_qdma_mutex);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	fsl_qdma->membase = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(fsl_qdma->membase))
+		return PTR_ERR(fsl_qdma->membase);
+
+	ret = fsl_qdma_irq_init(pdev, fsl_qdma);
+	if (ret)
+		return ret;
+
+	fsl_qdma->big_endian = of_property_read_bool(np, "big-endian");
+	INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
+	for (i = 0; i < fsl_qdma->n_chans; i++) {
+		struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
+
+		fsl_chan->qdma = fsl_qdma;
+		fsl_chan->desc = NULL;
+		fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
+		vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
+	}
+
+	dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
+	dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
+	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
+
+	fsl_qdma->dma_dev.dev = &pdev->dev;
+	fsl_qdma->dma_dev.device_alloc_chan_resources
+		= fsl_qdma_alloc_chan_resources;
+	fsl_qdma->dma_dev.device_free_chan_resources
+		= fsl_qdma_free_chan_resources;
+	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
+	fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
+	fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
+
+	platform_set_drvdata(pdev, fsl_qdma);
+
+	ret = dma_async_device_register(&fsl_qdma->dma_dev);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't register Freescale qDMA engine.\n");
+		return ret;
+	}
+
+	ret = fsl_qdma_reg_init(fsl_qdma);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int fsl_qdma_remove(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
+
+	of_dma_controller_free(np);
+	dma_async_device_unregister(&fsl_qdma->dma_dev);
+	return 0;
+}
+
+static const struct of_device_id fsl_qdma_dt_ids[] = {
+	{ .compatible = "fsl,ls-qdma", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fsl_qdma_dt_ids);
+
+static struct platform_driver fsl_qdma_driver = {
+	.driver		= {
+		.name	= "fsl-qdma",
+		.owner  = THIS_MODULE,
+		.of_match_table = fsl_qdma_dt_ids,
+	},
+	.probe          = fsl_qdma_probe,
+	.remove		= fsl_qdma_remove,
+};
+
+static int __init fsl_qdma_init(void)
+{
+	return platform_driver_register(&fsl_qdma_driver);
+}
+subsys_initcall(fsl_qdma_init);
+
+static void __exit fsl_qdma_exit(void)
+{
+	platform_driver_unregister(&fsl_qdma_driver);
+}
+module_exit(fsl_qdma_exit);
+
+MODULE_ALIAS("platform:fsl-qdma");
+MODULE_DESCRIPTION("Freescale qDMA engine driver");
+MODULE_LICENSE("GPL v2");
-- 
2.1.0.27.g96db324

[PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Yuan Yao]

Add Freescale Queue Direct Memory Access(qDMA) controller support.
This module can be found on LS-1 and LS-2 SoCs.

This add the legacy mode support for qDMA.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
---
 Documentation/devicetree/bindings/dma/fsl-qdma.txt |  43 ++
 MAINTAINERS                                        |   7 +
 drivers/dma/Kconfig                                |  10 +
 drivers/dma/Makefile                               |   1 +
 drivers/dma/fsl-qdma.c                             | 521 +++++++++++++++++++++
 5 files changed, 582 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
 create mode 100644 drivers/dma/fsl-qdma.c

diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
new file mode 100644
index 0000000..cdae71c
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
@@ -0,0 +1,43 @@
+* Freescale queue Direct Memory Access Controller(qDMA) Controller
+
+  The qDMA controller transfers blocks of data between one source and one or more
+destinations. The blocks of data transferred can be represented in memory as contiguous
+or non-contiguous using scatter/gather table(s). Channel virtualization is supported
+through enqueuing of DMA jobs to, or dequeuing DMA jobs from, different work
+queues.
+  Legacy mode is primarily included for software requiring the earlier
+QorIQ DMA programming model. This mode provides a simple programming
+model not utilizing the datapath architecture. In legacy mode, DMA
+operations are directly configured through a set of architectural
+registers per channel.
+
+* qDMA Controller
+Required properties:
+- compatible :
+	- "fsl,ls-qdma" for qDMA used similar to that on LS SoC
+- reg : Specifies base physical address(s) and size of the qDMA registers.
+	The region is qDMA control register's address and size.
+- interrupts : A list of interrupt-specifiers, one for each entry in
+	interrupt-names.
+- interrupt-names : Should contain:
+	"qdma-tx" - the  interrupt
+	"qdma-err" - the error interrupt
+- channels : Number of channels supported by the controller
+
+Optional properties:
+- big-endian: If present registers and hardware scatter/gather descriptors
+	of the qDMA are implemented in big endian mode, otherwise in little
+	mode.
+
+
+Examples:
+
+	qdma: qdma@8390000 {
+		compatible = "fsl,ls-qdma";
+		reg = <0x0 0x8380000 0x0 0x20000>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "qdma-tx", "qdma-err";
+		big-endian;
+		channels = <1>;
+	};
diff --git a/MAINTAINERS b/MAINTAINERS
index 5772ccf..a4d1b52 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4357,6 +4357,13 @@ L:	linuxppc-dev@lists.ozlabs.org
 S:	Maintained
 F:	drivers/dma/fsldma.*
 
+FREESCALE qDMA DRIVER
+M:     Yuan Yao <yao.yuan@freescale.com>
+L:     linux-arm-kernel@lists.infradead.org
+S:     Maintained
+F:     Documentation/devicetree/bindings/dma/fsl-qdma.txt
+F:     drivers/dma/fsl-qdma.c
+
 FREESCALE I2C CPM DRIVER
 M:	Jochen Friedrich <jochen@scram.de>
 L:	linuxppc-dev@lists.ozlabs.org
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index b458475..e29e985 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -193,6 +193,16 @@ config FSL_EDMA
 	  multiplexing capability for DMA request sources(slot).
 	  This module can be found on Freescale Vybrid and LS-1 SoCs.
 
+config FSL_QDMA
+	tristate "Freescale qDMA engine support"
+	select DMA_ENGINE
+	select DMA_VIRTUAL_CHANNELS
+	help
+	  Support the Freescale qDMA engine with command queue and legacy mode.
+	  Channel virtualization is supported through enqueuing of DMA jobs to,
+	  or dequeuing DMA jobs from, different work queues.
+	  This module can be found on Freescale LS SoCs.
+
 config FSL_RAID
         tristate "Freescale RAID engine Support"
         depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 7711a71..8de7526 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
 obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
 obj-$(CONFIG_FSL_DMA) += fsldma.o
 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
 obj-$(CONFIG_FSL_RAID) += fsl_raid.o
 obj-$(CONFIG_HSU_DMA) += hsu/
 obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
new file mode 100644
index 0000000..846cdba
--- /dev/null
+++ b/drivers/dma/fsl-qdma.c
@@ -0,0 +1,521 @@
+/*
+ * drivers/dma/fsl-qdma.c
+ *
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Driver for the Freescale qDMA engine with legacy mode.
+ * This module can be found on Freescale LS SoCs.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "virt-dma.h"
+
+#define FSL_QDMA_DMR		0x0
+#define FSL_QDMA_DSR_P		0x4
+
+#define FSL_QDMA_DSR_M		0x10004
+#define FSL_QDMA_DLMR		0x10100
+#define FSL_QDMA_DLSR		0x10104
+#define FSL_QDMA_DLSATR		0x10110
+#define FSL_QDMA_DLSAR		0x10114
+#define FSL_QDMA_DLDATR		0x10118
+#define FSL_QDMA_DLDAR		0x1011c
+#define FSL_QDMA_DLBCR		0x10120
+#define FSL_QDMA_DLESAD		0x10148
+#define FSL_QDMA_DLEDAD		0x1014c
+
+#define FSL_QDMA_DLMR_CS	0x1
+#define FSL_QDMA_DLMR_EOSIE	0x200
+#define FSL_QDMA_DLMR_EIE	0x40
+#define FSL_QDMA_DLSR_TE	0x80
+#define FSL_QDMA_DLSR_CH	0x20
+#define FSL_QDMA_DLSR_PE	0x10
+#define FSL_QDMA_DLSR_CB	0x4
+#define FSL_QDMA_DLSR_EOSI	0x2
+
+#define FSL_QDMA_SRTTYPE_R_N	0x40000
+
+struct fsl_qdma_tcd {
+	u64	saddr;
+	u32	nbytes;
+	u64	daddr;
+};
+
+struct fsl_qdma_chan_config {
+	enum dma_transfer_direction	dir;
+	enum dma_slave_buswidth		addr_width;
+	u32				burst;
+	u32				attr;
+};
+
+struct fsl_qdma_desc {
+	struct virt_dma_desc		vdesc;
+	struct fsl_qdma_chan		*qchan;
+	struct fsl_qdma_tcd		tcd;
+};
+
+struct fsl_qdma_chan {
+	struct virt_dma_chan		vchan;
+	struct fsl_qdma_desc		*desc;
+	enum dma_status			status;
+	u32				slave_id;
+	struct fsl_qdma_engine		*qdma;
+};
+
+struct fsl_qdma_engine {
+	struct dma_device	dma_dev;
+	void __iomem		*membase;
+	u32			n_chans;
+	struct mutex            fsl_qdma_mutex;
+	int			controller_irq;
+	int			err_irq;
+	bool			big_endian;
+	struct fsl_qdma_chan	chans[];
+
+};
+
+static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr)
+{
+	if (qdma->big_endian)
+		return ioread32be(addr);
+	else
+		return ioread32(addr);
+}
+
+static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
+						void __iomem *addr)
+{
+	if (qdma->big_endian)
+		iowrite32be(val, addr);
+	else
+		iowrite32(val, addr);
+}
+
+static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct fsl_qdma_chan, vchan.chan);
+}
+
+static struct fsl_qdma_desc *to_fsl_qdma_desc(struct virt_dma_desc *vd)
+{
+	return container_of(vd, struct fsl_qdma_desc, vdesc);
+}
+
+static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+
+	fsl_chan->desc = NULL;
+	return 0;
+}
+
+static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	unsigned long flags;
+	LIST_HEAD(head);
+
+	spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+	vchan_get_all_descriptors(&fsl_chan->vchan, &head);
+	spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
+
+	vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
+}
+
+static void fsl_qdma_set_tcd_params(struct fsl_qdma_chan *fsl_chan,
+					u64 src, u64 dst, u32 nbytes)
+{
+	void __iomem *addr = fsl_chan->qdma->membase;
+	u32 reg;
+
+	/*
+	 * Source address.
+	 * Represents address bits 31-0 of a 49-bit source address.
+	 */
+	qdma_writel(fsl_chan->qdma, (u32)src, addr + FSL_QDMA_DLSAR);
+	/*
+	 * Source address.
+	 * Represents address bits 47-32 of a 49-bit source address.
+	 */
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLSATR);
+	reg |= (u16)(src >> 32) & 0xffff;
+	reg |= FSL_QDMA_SRTTYPE_R_N;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLSATR);
+	/*
+	 * Source address.
+	 * Represents address bits 48 of a 49-bit source address.
+	 */
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLESAD);
+	reg |= (src >> 48) & 0x1;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLESAD);
+
+	/*
+	 * Destination address.
+	 * Represents address bits 31-0 of a 49-bit destination address.
+	 */
+	qdma_writel(fsl_chan->qdma, (u32)dst, addr + FSL_QDMA_DLDAR);
+	/*
+	 * Destination address.
+	 * Represents address bits 47-32 of a 49-bit destination address.
+	 */
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLDATR);
+	reg |= (u16)(dst >> 32) & 0xffff;
+	reg |= FSL_QDMA_SRTTYPE_R_N;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLDATR);
+	/*
+	 * Destination address.
+	 * Represents address bits 48 of a 49-bit destination address.
+	 */
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLEDAD);
+	reg |= (dst >> 48) & 0x1;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLEDAD);
+
+	/*
+	 * Byte count.
+	 * Contains the number of bytes to transfer.
+	 */
+	qdma_writel(fsl_chan->qdma, nbytes, addr + FSL_QDMA_DLBCR);
+}
+
+static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
+{
+	u32 reg;
+
+	reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DLMR);
+	reg |= FSL_QDMA_DLMR_EOSIE;
+	reg |= FSL_QDMA_DLMR_EIE;
+	qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DLMR);
+	return 0;
+}
+
+static void fsl_qdma_enable_request(struct fsl_qdma_chan *fsl_chan)
+{
+	void __iomem *addr = fsl_chan->qdma->membase;
+	u32 reg;
+
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLMR);
+
+	reg &= ~FSL_QDMA_DLMR_CS;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLMR);
+
+	reg |= FSL_QDMA_DLMR_CS;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLMR);
+}
+
+static struct fsl_qdma_desc *fsl_qdma_alloc_desc(struct fsl_qdma_chan *fsl_chan)
+{
+	struct fsl_qdma_desc *fsl_desc;
+
+	fsl_desc = kzalloc(sizeof(*fsl_desc), GFP_NOWAIT);
+
+	if (!fsl_desc)
+		return NULL;
+
+	fsl_desc->qchan = fsl_chan;
+
+	return fsl_desc;
+}
+
+static void fsl_qdma_free_desc(struct virt_dma_desc *vdesc)
+{
+	struct fsl_qdma_desc *fsl_desc;
+
+	fsl_desc = to_fsl_qdma_desc(vdesc);
+	kfree(fsl_desc);
+}
+
+static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
+{
+	struct fsl_qdma_tcd *tcd;
+	struct virt_dma_desc *vdesc;
+
+	vdesc = vchan_next_desc(&fsl_chan->vchan);
+	if (!vdesc)
+		return;
+
+	fsl_chan->desc = to_fsl_qdma_desc(vdesc);
+	tcd = &fsl_chan->desc->tcd;
+	fsl_qdma_set_tcd_params(fsl_chan, tcd->saddr, tcd->daddr, tcd->nbytes);
+	fsl_qdma_enable_request(fsl_chan);
+	fsl_chan->status = DMA_IN_PROGRESS;
+}
+
+static void fsl_qdma_issue_pending(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+
+	if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->desc)
+		fsl_qdma_enqueue_desc(fsl_chan);
+
+	spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
+}
+
+static struct dma_async_tx_descriptor *
+fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
+		dma_addr_t src, size_t len, unsigned long flags)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	struct fsl_qdma_desc *fsl_desc;
+	struct fsl_qdma_tcd *tcd;
+
+	fsl_desc = fsl_qdma_alloc_desc(fsl_chan);
+	if (!fsl_desc)
+		return NULL;
+
+	tcd = &fsl_desc->tcd;
+	tcd->saddr = (u64)src;
+	tcd->nbytes = (u32)len;
+	tcd->daddr = (u64)dst;
+
+	return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
+}
+
+static enum dma_status fsl_qdma_tx_status(struct dma_chan *chan,
+		dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
+	return dma_cookie_status(chan, cookie, txstate);
+}
+
+static irqreturn_t fsl_qdma_controller_handler(int irq, void *dev_id)
+{
+	struct fsl_qdma_engine *fsl_qdma = dev_id;
+	struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[0];
+	void __iomem *addr = fsl_qdma->membase;
+	u32 reg;
+
+	reg = qdma_readl(fsl_qdma, addr + FSL_QDMA_DLSR);
+	if (!(reg & FSL_QDMA_DLSR_EOSI))
+		return IRQ_NONE;
+
+	/* Don't clean TE and PE bit if they are set. */
+	reg &= ~FSL_QDMA_DLSR_TE & ~FSL_QDMA_DLSR_PE;
+	qdma_writel(fsl_qdma, reg, addr + FSL_QDMA_DLSR);
+
+	spin_lock(&fsl_chan->vchan.lock);
+	list_del(&fsl_chan->desc->vdesc.node);
+	vchan_cookie_complete(&fsl_chan->desc->vdesc);
+	fsl_chan->desc = NULL;
+	fsl_chan->status = DMA_COMPLETE;
+	fsl_qdma_enqueue_desc(fsl_chan);
+	spin_unlock(&fsl_chan->vchan.lock);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t fsl_qdma_controller_handler_err(int irq, void *dev_id)
+{
+	struct fsl_qdma_engine *fsl_qdma = dev_id;
+	u32 reg;
+
+	reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DLSR);
+
+	if (reg & FSL_QDMA_DLSR_TE) {
+		dev_err(fsl_qdma->dma_dev.dev,
+			"Transfer error. Check your address please!\n");
+	}
+
+	if (reg & FSL_QDMA_DLSR_PE) {
+		dev_err(fsl_qdma->dma_dev.dev,
+			"Programming error. Check your setting please!\n");
+	}
+
+	/* Don't clean EOSI bit if it's set. */
+	reg &= ~FSL_QDMA_DLSR_EOSI;
+	qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DLSR);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t fsl_qdma_irq_handler(int irq, void *dev_id)
+{
+	if (fsl_qdma_controller_handler(irq, dev_id) == IRQ_HANDLED)
+		return IRQ_HANDLED;
+
+	return fsl_qdma_controller_handler_err(irq, dev_id);
+}
+
+static int fsl_qdma_irq_init(struct platform_device *pdev,
+					struct fsl_qdma_engine *fsl_qdma)
+{
+	int ret;
+
+	fsl_qdma->controller_irq = platform_get_irq_byname(pdev,
+							"qdma-tx");
+	if (fsl_qdma->controller_irq < 0) {
+		dev_err(&pdev->dev, "Can't get qdma controller irq.\n");
+		return fsl_qdma->controller_irq;
+	}
+
+	fsl_qdma->err_irq = platform_get_irq_byname(pdev,
+							"qdma-err");
+	if (fsl_qdma->err_irq < 0) {
+		dev_err(&pdev->dev, "Can't get qdma err irq.\n");
+		return fsl_qdma->err_irq;
+	}
+
+	if (fsl_qdma->controller_irq == fsl_qdma->err_irq) {
+		ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
+					fsl_qdma_irq_handler, 0,
+					"qDMA controller", fsl_qdma);
+
+		if (ret) {
+			dev_err(&pdev->dev, "Can't register qDMA IRQ.\n");
+			return  ret;
+		}
+	} else {
+		ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
+				fsl_qdma_controller_handler, 0,
+				"qDMA controller", fsl_qdma);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"Can't register qDMA controller IRQ.\n");
+			return  ret;
+		}
+
+		ret = devm_request_irq(&pdev->dev, fsl_qdma->err_irq,
+				fsl_qdma_controller_handler_err, 0,
+				"qDMA err", fsl_qdma);
+		if (ret) {
+			dev_err(&pdev->dev, "Can't register qDMA err IRQ.\n");
+			return  ret;
+		}
+	}
+
+	return 0;
+}
+
+static int fsl_qdma_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_engine *fsl_qdma;
+	struct fsl_qdma_chan *fsl_chan;
+	struct resource *res;
+	unsigned int len, chans;
+	int ret, i;
+
+	ret = of_property_read_u32(np, "channels", &chans);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't get channels.\n");
+		return ret;
+	}
+
+	len = sizeof(*fsl_qdma) + sizeof(*fsl_chan) * chans;
+	fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
+	if (!fsl_qdma)
+		return -ENOMEM;
+
+	fsl_qdma->n_chans = chans;
+	mutex_init(&fsl_qdma->fsl_qdma_mutex);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	fsl_qdma->membase = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(fsl_qdma->membase))
+		return PTR_ERR(fsl_qdma->membase);
+
+	ret = fsl_qdma_irq_init(pdev, fsl_qdma);
+	if (ret)
+		return ret;
+
+	fsl_qdma->big_endian = of_property_read_bool(np, "big-endian");
+	INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
+	for (i = 0; i < fsl_qdma->n_chans; i++) {
+		struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
+
+		fsl_chan->qdma = fsl_qdma;
+		fsl_chan->desc = NULL;
+		fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
+		vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
+	}
+
+	dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
+	dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
+	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
+
+	fsl_qdma->dma_dev.dev = &pdev->dev;
+	fsl_qdma->dma_dev.device_alloc_chan_resources
+		= fsl_qdma_alloc_chan_resources;
+	fsl_qdma->dma_dev.device_free_chan_resources
+		= fsl_qdma_free_chan_resources;
+	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
+	fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
+	fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
+
+	platform_set_drvdata(pdev, fsl_qdma);
+
+	ret = dma_async_device_register(&fsl_qdma->dma_dev);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't register Freescale qDMA engine.\n");
+		return ret;
+	}
+
+	ret = fsl_qdma_reg_init(fsl_qdma);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int fsl_qdma_remove(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
+
+	of_dma_controller_free(np);
+	dma_async_device_unregister(&fsl_qdma->dma_dev);
+	return 0;
+}
+
+static const struct of_device_id fsl_qdma_dt_ids[] = {
+	{ .compatible = "fsl,ls-qdma", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fsl_qdma_dt_ids);
+
+static struct platform_driver fsl_qdma_driver = {
+	.driver		= {
+		.name	= "fsl-qdma",
+		.owner  = THIS_MODULE,
+		.of_match_table = fsl_qdma_dt_ids,
+	},
+	.probe          = fsl_qdma_probe,
+	.remove		= fsl_qdma_remove,
+};
+
+static int __init fsl_qdma_init(void)
+{
+	return platform_driver_register(&fsl_qdma_driver);
+}
+subsys_initcall(fsl_qdma_init);
+
+static void __exit fsl_qdma_exit(void)
+{
+	platform_driver_unregister(&fsl_qdma_driver);
+}
+module_exit(fsl_qdma_exit);
+
+MODULE_ALIAS("platform:fsl-qdma");
+MODULE_DESCRIPTION("Freescale qDMA engine driver");
+MODULE_LICENSE("GPL v2");
-- 
2.1.0.27.g96db324

[PATCH 1/2] dma: Add Freescale qDMA engine driver support

[Yuan Yao]

Add Freescale Queue Direct Memory Access(qDMA) controller support.
This module can be found on LS-1 and LS-2 SoCs.

This add the legacy mode support for qDMA.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
---
 Documentation/devicetree/bindings/dma/fsl-qdma.txt |  43 ++
 MAINTAINERS                                        |   7 +
 drivers/dma/Kconfig                                |  10 +
 drivers/dma/Makefile                               |   1 +
 drivers/dma/fsl-qdma.c                             | 521 +++++++++++++++++++++
 5 files changed, 582 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
 create mode 100644 drivers/dma/fsl-qdma.c

diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
new file mode 100644
index 0000000..cdae71c
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
@@ -0,0 +1,43 @@
+* Freescale queue Direct Memory Access Controller(qDMA) Controller
+
+  The qDMA controller transfers blocks of data between one source and one or more
+destinations. The blocks of data transferred can be represented in memory as contiguous
+or non-contiguous using scatter/gather table(s). Channel virtualization is supported
+through enqueuing of DMA jobs to, or dequeuing DMA jobs from, different work
+queues.
+  Legacy mode is primarily included for software requiring the earlier
+QorIQ DMA programming model. This mode provides a simple programming
+model not utilizing the datapath architecture. In legacy mode, DMA
+operations are directly configured through a set of architectural
+registers per channel.
+
+* qDMA Controller
+Required properties:
+- compatible :
+	- "fsl,ls-qdma" for qDMA used similar to that on LS SoC
+- reg : Specifies base physical address(s) and size of the qDMA registers.
+	The region is qDMA control register's address and size.
+- interrupts : A list of interrupt-specifiers, one for each entry in
+	interrupt-names.
+- interrupt-names : Should contain:
+	"qdma-tx" - the  interrupt
+	"qdma-err" - the error interrupt
+- channels : Number of channels supported by the controller
+
+Optional properties:
+- big-endian: If present registers and hardware scatter/gather descriptors
+	of the qDMA are implemented in big endian mode, otherwise in little
+	mode.
+
+
+Examples:
+
+	qdma: qdma at 8390000 {
+		compatible = "fsl,ls-qdma";
+		reg = <0x0 0x8380000 0x0 0x20000>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "qdma-tx", "qdma-err";
+		big-endian;
+		channels = <1>;
+	};
diff --git a/MAINTAINERS b/MAINTAINERS
index 5772ccf..a4d1b52 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4357,6 +4357,13 @@ L:	linuxppc-dev at lists.ozlabs.org
 S:	Maintained
 F:	drivers/dma/fsldma.*
 
+FREESCALE qDMA DRIVER
+M:     Yuan Yao <yao.yuan@freescale.com>
+L:     linux-arm-kernel at lists.infradead.org
+S:     Maintained
+F:     Documentation/devicetree/bindings/dma/fsl-qdma.txt
+F:     drivers/dma/fsl-qdma.c
+
 FREESCALE I2C CPM DRIVER
 M:	Jochen Friedrich <jochen@scram.de>
 L:	linuxppc-dev at lists.ozlabs.org
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index b458475..e29e985 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -193,6 +193,16 @@ config FSL_EDMA
 	  multiplexing capability for DMA request sources(slot).
 	  This module can be found on Freescale Vybrid and LS-1 SoCs.
 
+config FSL_QDMA
+	tristate "Freescale qDMA engine support"
+	select DMA_ENGINE
+	select DMA_VIRTUAL_CHANNELS
+	help
+	  Support the Freescale qDMA engine with command queue and legacy mode.
+	  Channel virtualization is supported through enqueuing of DMA jobs to,
+	  or dequeuing DMA jobs from, different work queues.
+	  This module can be found on Freescale LS SoCs.
+
 config FSL_RAID
         tristate "Freescale RAID engine Support"
         depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 7711a71..8de7526 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
 obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
 obj-$(CONFIG_FSL_DMA) += fsldma.o
 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
 obj-$(CONFIG_FSL_RAID) += fsl_raid.o
 obj-$(CONFIG_HSU_DMA) += hsu/
 obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
new file mode 100644
index 0000000..846cdba
--- /dev/null
+++ b/drivers/dma/fsl-qdma.c
@@ -0,0 +1,521 @@
+/*
+ * drivers/dma/fsl-qdma.c
+ *
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Driver for the Freescale qDMA engine with legacy mode.
+ * This module can be found on Freescale LS SoCs.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "virt-dma.h"
+
+#define FSL_QDMA_DMR		0x0
+#define FSL_QDMA_DSR_P		0x4
+
+#define FSL_QDMA_DSR_M		0x10004
+#define FSL_QDMA_DLMR		0x10100
+#define FSL_QDMA_DLSR		0x10104
+#define FSL_QDMA_DLSATR		0x10110
+#define FSL_QDMA_DLSAR		0x10114
+#define FSL_QDMA_DLDATR		0x10118
+#define FSL_QDMA_DLDAR		0x1011c
+#define FSL_QDMA_DLBCR		0x10120
+#define FSL_QDMA_DLESAD		0x10148
+#define FSL_QDMA_DLEDAD		0x1014c
+
+#define FSL_QDMA_DLMR_CS	0x1
+#define FSL_QDMA_DLMR_EOSIE	0x200
+#define FSL_QDMA_DLMR_EIE	0x40
+#define FSL_QDMA_DLSR_TE	0x80
+#define FSL_QDMA_DLSR_CH	0x20
+#define FSL_QDMA_DLSR_PE	0x10
+#define FSL_QDMA_DLSR_CB	0x4
+#define FSL_QDMA_DLSR_EOSI	0x2
+
+#define FSL_QDMA_SRTTYPE_R_N	0x40000
+
+struct fsl_qdma_tcd {
+	u64	saddr;
+	u32	nbytes;
+	u64	daddr;
+};
+
+struct fsl_qdma_chan_config {
+	enum dma_transfer_direction	dir;
+	enum dma_slave_buswidth		addr_width;
+	u32				burst;
+	u32				attr;
+};
+
+struct fsl_qdma_desc {
+	struct virt_dma_desc		vdesc;
+	struct fsl_qdma_chan		*qchan;
+	struct fsl_qdma_tcd		tcd;
+};
+
+struct fsl_qdma_chan {
+	struct virt_dma_chan		vchan;
+	struct fsl_qdma_desc		*desc;
+	enum dma_status			status;
+	u32				slave_id;
+	struct fsl_qdma_engine		*qdma;
+};
+
+struct fsl_qdma_engine {
+	struct dma_device	dma_dev;
+	void __iomem		*membase;
+	u32			n_chans;
+	struct mutex            fsl_qdma_mutex;
+	int			controller_irq;
+	int			err_irq;
+	bool			big_endian;
+	struct fsl_qdma_chan	chans[];
+
+};
+
+static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr)
+{
+	if (qdma->big_endian)
+		return ioread32be(addr);
+	else
+		return ioread32(addr);
+}
+
+static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
+						void __iomem *addr)
+{
+	if (qdma->big_endian)
+		iowrite32be(val, addr);
+	else
+		iowrite32(val, addr);
+}
+
+static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct fsl_qdma_chan, vchan.chan);
+}
+
+static struct fsl_qdma_desc *to_fsl_qdma_desc(struct virt_dma_desc *vd)
+{
+	return container_of(vd, struct fsl_qdma_desc, vdesc);
+}
+
+static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+
+	fsl_chan->desc = NULL;
+	return 0;
+}
+
+static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	unsigned long flags;
+	LIST_HEAD(head);
+
+	spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+	vchan_get_all_descriptors(&fsl_chan->vchan, &head);
+	spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
+
+	vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
+}
+
+static void fsl_qdma_set_tcd_params(struct fsl_qdma_chan *fsl_chan,
+					u64 src, u64 dst, u32 nbytes)
+{
+	void __iomem *addr = fsl_chan->qdma->membase;
+	u32 reg;
+
+	/*
+	 * Source address.
+	 * Represents address bits 31-0 of a 49-bit source address.
+	 */
+	qdma_writel(fsl_chan->qdma, (u32)src, addr + FSL_QDMA_DLSAR);
+	/*
+	 * Source address.
+	 * Represents address bits 47-32 of a 49-bit source address.
+	 */
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLSATR);
+	reg |= (u16)(src >> 32) & 0xffff;
+	reg |= FSL_QDMA_SRTTYPE_R_N;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLSATR);
+	/*
+	 * Source address.
+	 * Represents address bits 48 of a 49-bit source address.
+	 */
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLESAD);
+	reg |= (src >> 48) & 0x1;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLESAD);
+
+	/*
+	 * Destination address.
+	 * Represents address bits 31-0 of a 49-bit destination address.
+	 */
+	qdma_writel(fsl_chan->qdma, (u32)dst, addr + FSL_QDMA_DLDAR);
+	/*
+	 * Destination address.
+	 * Represents address bits 47-32 of a 49-bit destination address.
+	 */
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLDATR);
+	reg |= (u16)(dst >> 32) & 0xffff;
+	reg |= FSL_QDMA_SRTTYPE_R_N;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLDATR);
+	/*
+	 * Destination address.
+	 * Represents address bits 48 of a 49-bit destination address.
+	 */
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLEDAD);
+	reg |= (dst >> 48) & 0x1;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLEDAD);
+
+	/*
+	 * Byte count.
+	 * Contains the number of bytes to transfer.
+	 */
+	qdma_writel(fsl_chan->qdma, nbytes, addr + FSL_QDMA_DLBCR);
+}
+
+static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
+{
+	u32 reg;
+
+	reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DLMR);
+	reg |= FSL_QDMA_DLMR_EOSIE;
+	reg |= FSL_QDMA_DLMR_EIE;
+	qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DLMR);
+	return 0;
+}
+
+static void fsl_qdma_enable_request(struct fsl_qdma_chan *fsl_chan)
+{
+	void __iomem *addr = fsl_chan->qdma->membase;
+	u32 reg;
+
+	reg = qdma_readl(fsl_chan->qdma, addr + FSL_QDMA_DLMR);
+
+	reg &= ~FSL_QDMA_DLMR_CS;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLMR);
+
+	reg |= FSL_QDMA_DLMR_CS;
+	qdma_writel(fsl_chan->qdma, reg, addr + FSL_QDMA_DLMR);
+}
+
+static struct fsl_qdma_desc *fsl_qdma_alloc_desc(struct fsl_qdma_chan *fsl_chan)
+{
+	struct fsl_qdma_desc *fsl_desc;
+
+	fsl_desc = kzalloc(sizeof(*fsl_desc), GFP_NOWAIT);
+
+	if (!fsl_desc)
+		return NULL;
+
+	fsl_desc->qchan = fsl_chan;
+
+	return fsl_desc;
+}
+
+static void fsl_qdma_free_desc(struct virt_dma_desc *vdesc)
+{
+	struct fsl_qdma_desc *fsl_desc;
+
+	fsl_desc = to_fsl_qdma_desc(vdesc);
+	kfree(fsl_desc);
+}
+
+static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
+{
+	struct fsl_qdma_tcd *tcd;
+	struct virt_dma_desc *vdesc;
+
+	vdesc = vchan_next_desc(&fsl_chan->vchan);
+	if (!vdesc)
+		return;
+
+	fsl_chan->desc = to_fsl_qdma_desc(vdesc);
+	tcd = &fsl_chan->desc->tcd;
+	fsl_qdma_set_tcd_params(fsl_chan, tcd->saddr, tcd->daddr, tcd->nbytes);
+	fsl_qdma_enable_request(fsl_chan);
+	fsl_chan->status = DMA_IN_PROGRESS;
+}
+
+static void fsl_qdma_issue_pending(struct dma_chan *chan)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+
+	if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->desc)
+		fsl_qdma_enqueue_desc(fsl_chan);
+
+	spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
+}
+
+static struct dma_async_tx_descriptor *
+fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
+		dma_addr_t src, size_t len, unsigned long flags)
+{
+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+	struct fsl_qdma_desc *fsl_desc;
+	struct fsl_qdma_tcd *tcd;
+
+	fsl_desc = fsl_qdma_alloc_desc(fsl_chan);
+	if (!fsl_desc)
+		return NULL;
+
+	tcd = &fsl_desc->tcd;
+	tcd->saddr = (u64)src;
+	tcd->nbytes = (u32)len;
+	tcd->daddr = (u64)dst;
+
+	return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
+}
+
+static enum dma_status fsl_qdma_tx_status(struct dma_chan *chan,
+		dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
+	return dma_cookie_status(chan, cookie, txstate);
+}
+
+static irqreturn_t fsl_qdma_controller_handler(int irq, void *dev_id)
+{
+	struct fsl_qdma_engine *fsl_qdma = dev_id;
+	struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[0];
+	void __iomem *addr = fsl_qdma->membase;
+	u32 reg;
+
+	reg = qdma_readl(fsl_qdma, addr + FSL_QDMA_DLSR);
+	if (!(reg & FSL_QDMA_DLSR_EOSI))
+		return IRQ_NONE;
+
+	/* Don't clean TE and PE bit if they are set. */
+	reg &= ~FSL_QDMA_DLSR_TE & ~FSL_QDMA_DLSR_PE;
+	qdma_writel(fsl_qdma, reg, addr + FSL_QDMA_DLSR);
+
+	spin_lock(&fsl_chan->vchan.lock);
+	list_del(&fsl_chan->desc->vdesc.node);
+	vchan_cookie_complete(&fsl_chan->desc->vdesc);
+	fsl_chan->desc = NULL;
+	fsl_chan->status = DMA_COMPLETE;
+	fsl_qdma_enqueue_desc(fsl_chan);
+	spin_unlock(&fsl_chan->vchan.lock);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t fsl_qdma_controller_handler_err(int irq, void *dev_id)
+{
+	struct fsl_qdma_engine *fsl_qdma = dev_id;
+	u32 reg;
+
+	reg = qdma_readl(fsl_qdma, fsl_qdma->membase + FSL_QDMA_DLSR);
+
+	if (reg & FSL_QDMA_DLSR_TE) {
+		dev_err(fsl_qdma->dma_dev.dev,
+			"Transfer error. Check your address please!\n");
+	}
+
+	if (reg & FSL_QDMA_DLSR_PE) {
+		dev_err(fsl_qdma->dma_dev.dev,
+			"Programming error. Check your setting please!\n");
+	}
+
+	/* Don't clean EOSI bit if it's set. */
+	reg &= ~FSL_QDMA_DLSR_EOSI;
+	qdma_writel(fsl_qdma, reg, fsl_qdma->membase + FSL_QDMA_DLSR);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t fsl_qdma_irq_handler(int irq, void *dev_id)
+{
+	if (fsl_qdma_controller_handler(irq, dev_id) == IRQ_HANDLED)
+		return IRQ_HANDLED;
+
+	return fsl_qdma_controller_handler_err(irq, dev_id);
+}
+
+static int fsl_qdma_irq_init(struct platform_device *pdev,
+					struct fsl_qdma_engine *fsl_qdma)
+{
+	int ret;
+
+	fsl_qdma->controller_irq = platform_get_irq_byname(pdev,
+							"qdma-tx");
+	if (fsl_qdma->controller_irq < 0) {
+		dev_err(&pdev->dev, "Can't get qdma controller irq.\n");
+		return fsl_qdma->controller_irq;
+	}
+
+	fsl_qdma->err_irq = platform_get_irq_byname(pdev,
+							"qdma-err");
+	if (fsl_qdma->err_irq < 0) {
+		dev_err(&pdev->dev, "Can't get qdma err irq.\n");
+		return fsl_qdma->err_irq;
+	}
+
+	if (fsl_qdma->controller_irq == fsl_qdma->err_irq) {
+		ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
+					fsl_qdma_irq_handler, 0,
+					"qDMA controller", fsl_qdma);
+
+		if (ret) {
+			dev_err(&pdev->dev, "Can't register qDMA IRQ.\n");
+			return  ret;
+		}
+	} else {
+		ret = devm_request_irq(&pdev->dev, fsl_qdma->controller_irq,
+				fsl_qdma_controller_handler, 0,
+				"qDMA controller", fsl_qdma);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"Can't register qDMA controller IRQ.\n");
+			return  ret;
+		}
+
+		ret = devm_request_irq(&pdev->dev, fsl_qdma->err_irq,
+				fsl_qdma_controller_handler_err, 0,
+				"qDMA err", fsl_qdma);
+		if (ret) {
+			dev_err(&pdev->dev, "Can't register qDMA err IRQ.\n");
+			return  ret;
+		}
+	}
+
+	return 0;
+}
+
+static int fsl_qdma_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_engine *fsl_qdma;
+	struct fsl_qdma_chan *fsl_chan;
+	struct resource *res;
+	unsigned int len, chans;
+	int ret, i;
+
+	ret = of_property_read_u32(np, "channels", &chans);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't get channels.\n");
+		return ret;
+	}
+
+	len = sizeof(*fsl_qdma) + sizeof(*fsl_chan) * chans;
+	fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
+	if (!fsl_qdma)
+		return -ENOMEM;
+
+	fsl_qdma->n_chans = chans;
+	mutex_init(&fsl_qdma->fsl_qdma_mutex);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	fsl_qdma->membase = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(fsl_qdma->membase))
+		return PTR_ERR(fsl_qdma->membase);
+
+	ret = fsl_qdma_irq_init(pdev, fsl_qdma);
+	if (ret)
+		return ret;
+
+	fsl_qdma->big_endian = of_property_read_bool(np, "big-endian");
+	INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
+	for (i = 0; i < fsl_qdma->n_chans; i++) {
+		struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
+
+		fsl_chan->qdma = fsl_qdma;
+		fsl_chan->desc = NULL;
+		fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
+		vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
+	}
+
+	dma_cap_set(DMA_PRIVATE, fsl_qdma->dma_dev.cap_mask);
+	dma_cap_set(DMA_SLAVE, fsl_qdma->dma_dev.cap_mask);
+	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
+
+	fsl_qdma->dma_dev.dev = &pdev->dev;
+	fsl_qdma->dma_dev.device_alloc_chan_resources
+		= fsl_qdma_alloc_chan_resources;
+	fsl_qdma->dma_dev.device_free_chan_resources
+		= fsl_qdma_free_chan_resources;
+	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
+	fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
+	fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
+
+	platform_set_drvdata(pdev, fsl_qdma);
+
+	ret = dma_async_device_register(&fsl_qdma->dma_dev);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't register Freescale qDMA engine.\n");
+		return ret;
+	}
+
+	ret = fsl_qdma_reg_init(fsl_qdma);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int fsl_qdma_remove(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
+
+	of_dma_controller_free(np);
+	dma_async_device_unregister(&fsl_qdma->dma_dev);
+	return 0;
+}
+
+static const struct of_device_id fsl_qdma_dt_ids[] = {
+	{ .compatible = "fsl,ls-qdma", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fsl_qdma_dt_ids);
+
+static struct platform_driver fsl_qdma_driver = {
+	.driver		= {
+		.name	= "fsl-qdma",
+		.owner  = THIS_MODULE,
+		.of_match_table = fsl_qdma_dt_ids,
+	},
+	.probe          = fsl_qdma_probe,
+	.remove		= fsl_qdma_remove,
+};
+
+static int __init fsl_qdma_init(void)
+{
+	return platform_driver_register(&fsl_qdma_driver);
+}
+subsys_initcall(fsl_qdma_init);
+
+static void __exit fsl_qdma_exit(void)
+{
+	platform_driver_unregister(&fsl_qdma_driver);
+}
+module_exit(fsl_qdma_exit);
+
+MODULE_ALIAS("platform:fsl-qdma");
+MODULE_DESCRIPTION("Freescale qDMA engine driver");
+MODULE_LICENSE("GPL v2");
-- 
2.1.0.27.g96db324