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From: Thierry Reding <thierry.reding@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 5/6] armv8/gic: Fix GIC v2 initialization
Date: Fri, 20 Mar 2015 12:47:52 +0100	[thread overview]
Message-ID: <1426852073-10299-5-git-send-email-thierry.reding@gmail.com> (raw)
In-Reply-To: <1426852073-10299-1-git-send-email-thierry.reding@gmail.com>

From: Thierry Reding <treding@nvidia.com>

Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.

Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm/lib/gic_64.S | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S
index a3e18f7713e5..62d0022408bc 100644
--- a/arch/arm/lib/gic_64.S
+++ b/arch/arm/lib/gic_64.S
@@ -46,11 +46,19 @@ ENTRY(gic_init_secure)
 	ldr	w9, [x0, GICD_TYPER]
 	and	w10, w9, #0x1f		/* ITLinesNumber */
 	cbz	w10, 1f			/* No SPIs */
-	add	x11, x0, (GICD_IGROUPRn + 4)
+	add	x11, x0, GICD_IGROUPRn
 	mov	w9, #~0			/* Config SPIs as Grp1 */
+	str	w9, [x11], #0x4
 0:	str	w9, [x11], #0x4
 	sub	w10, w10, #0x1
 	cbnz	w10, 0b
+
+	ldr	x1, =GICC_BASE		/* GICC_CTLR */
+	mov	w0, #3			/* EnableGrp0 | EnableGrp1 */
+	str	w0, [x1]
+
+	mov	w0, #1 << 7		/* allow NS access to GICC_PMR */
+	str	w0, [x1, #4]		/* GICC_PMR */
 #endif
 1:
 	ret
-- 
2.3.2

  parent reply	other threads:[~2015-03-20 11:47 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-20 11:47 [U-Boot] [PATCH 1/6] armv8/cache: Fix page table creation Thierry Reding
2015-03-20 11:47 ` [U-Boot] [PATCH 2/6] armv8: Implement CONFIG_SYS_MALLOC_F_LEN support Thierry Reding
2015-03-24 14:47   ` FengHua
2015-03-20 11:47 ` [U-Boot] [PATCH 3/6] armv8/mmu: Clean up TCR programming Thierry Reding
2015-03-20 18:13   ` Marc Zyngier
2015-07-02 21:06     ` Albert ARIBAUD
2015-07-03  7:28       ` Marc Zyngier
2015-03-24 14:55   ` FengHua
2015-03-20 11:47 ` [U-Boot] [PATCH 4/6] armv8/mmu: Set bits marked RES1 in TCR Thierry Reding
2015-03-20 18:16   ` Marc Zyngier
2015-03-24 15:10   ` FengHua
2015-03-20 11:47 ` Thierry Reding [this message]
2015-03-20 18:03   ` [U-Boot] [PATCH 5/6] armv8/gic: Fix GIC v2 initialization Marc Zyngier
2015-03-20 11:47 ` [U-Boot] [PATCH 6/6] armv8: Allow SoCs to override the generic timer Thierry Reding
2015-03-20 18:18   ` Marc Zyngier
2015-03-24 14:59   ` FengHua
2015-03-20 18:06 ` [U-Boot] [PATCH 1/6] armv8/cache: Fix page table creation Marc Zyngier
2015-03-24 14:52 ` FengHua
2015-04-16 11:24 ` Albert ARIBAUD
2015-06-03 15:09   ` Albert ARIBAUD

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