[PATCH 15/21 v2] drm/i915: Update scaling ratio as part of crtc_compute_config

[Chandra Konduru <chandra.konduru@intel.com>]

Based on computed crtc config, stage any updates to scaling ratios.

Also call intel_atomic_setup_scalers() to stage scaler assignments
if crtc compute config staged any changes to its scaler needs.

Above actions should be moved to atomic crtc once it is available.

v2:
-moved gen comparision check to caller (Matt)

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dfd24ed..c393480 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5790,6 +5790,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	int ret;
 
 	/* FIXME should check pixel clock limits on all platforms */
 	if (INTEL_INFO(dev)->gen < 4) {
@@ -5844,7 +5845,17 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 	if (pipe_config->has_pch_encoder)
 		return ironlake_fdi_compute_config(crtc, pipe_config);
 
-	return 0;
+	if (INTEL_INFO(dev)->gen >= 9)
+		skl_update_scaling_ratio(dev, pipe_config);
+
+	/* FIXME: remove below call once atomic mode set is place and all crtc
+	 * related checks called from atomic_crtc_check function */
+	ret = 0;
+	DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
+		crtc, pipe_config->base.state);
+	ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
+
+	return ret;
 }
 
 static int valleyview_get_display_clock_speed(struct drm_device *dev)
-- 
1.7.9.5

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