[U-Boot] [PATCH v5 0/28] Adding LS2085AQDS and RDB

[U-Boot] [PATCH v5 0/28] Adding LS2085AQDS and RDB

[York Sun]

This set adds necessary support in common ls2085a support and board
support for QDS and RDB.

Changes in v5:
  Re-generate patches using patman default flags
  s/LayerScape/Layerscape/g
  Fix board README for inconsistent SoC name
  Fix comment in board header file
  s/LS2080/LS2085/g
  Fix Kconfig help for inconsistent SoC name
  Update LS2085AQDS README to include instructions to form NAND image
  Update LS2085ARDB README to include instructions to form NAND image

Changes in v4:
  Remove temporary variable cntfrq.
  Fix board README for inconsistent SoC name
  Fix comments in board header file
  Update MAINTAINERS file
  Update MAINTAINERS file

Changes in v3:
  Move secondary core fix to mp.c.
  Replace hard-coded value with COUNTER_FREQUENCY.

Changes in v2:
  Rebase after adding macros CONFIG_SYS_I2C_MXC_I2C3 in another patch set
  Fix CNTFRQ for secondary cores when COUNTER_FREQUENCY_REAL is defined.
  Add comment to I2C workaround

Bhupesh Sharma (1):
  armv8/fsl-ch3: Add support to print RCW configuration

J. German Rivera (2):
  drivers/fsl-mc: Changed MC firmware loading for new boot architecture
  drivers/fsl-mc: Autoload AOIP image from NOR flash

Jaiprakash Singh (1):
  driver/ifc: Add 64KB page support

Minghuan Lian (1):
  armv8: Add SerDes framework for Layerscape Architecture

Prabhakar Kushwaha (4):
  armv8/ls2085a: Update common header file
  driver/ldpaa_eth: Update ldpaa ethernet driver
  driver/ldpaa: Add support of WRIOP static data structure
  board/ls2085qds: Add support ethernet

Scott Wood (8):
  armv8/fsl-lsch3: Set nodes in DVM domain
  fsl-lsch3: Introduce place for common early SoC init
  armv8/ls2085a: Add workaround for USB erratum A-008751
  armv8/fsl-lsch3: Use correct compatible for serial clock fixup
  armv8/fsl-lsch3: Enable system error aborts
  armv8/ls2085aqds: NAND boot support
  freescale/qixis: Add support for booting from NAND
  armv8/ls2085ardb: Enable NAND SPL support

Shaohui Xie (1):
  net/memac_phy: reuse driver for little endian SoCs

Yangbo Lu (1):
  ls2085a: esdhc: Add esdhc support for ls2085a

York Sun (7):
  armv8/fsl-lsch3: Implement workaround for erratum A008585
  armv8/fsl-lsch3: Fix platform clock calculation
  armv8/ls2085a: Fix generic timer clock source
  armv8/fsl-lsch3: Update early MMU table
  armv8/ls2085aqds: Add support of LS2085AQDS platform
  armv8/ls2085ardb: Add support of LS2085ARDB platform
  armv8/fsl-lsch3: Implement workaround for I2C issue

pankaj chauhan (2):
  armv8/ls2085a: Add support for reset request
  net/phy/cortina: Fix compilation warning

 README                                            |    8 +
 arch/arm/Kconfig                                  |   24 +
 arch/arm/cpu/armv7/ls102xa/clock.c                |    4 +-
 arch/arm/cpu/armv8/fsl-lsch3/Makefile             |    2 +
 arch/arm/cpu/armv8/fsl-lsch3/README               |   78 +++-
 arch/arm/cpu/armv8/fsl-lsch3/cpu.c                |  123 ++++-
 arch/arm/cpu/armv8/fsl-lsch3/fdt.c                |    9 +-
 arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c   |  115 +++++
 arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S           |   15 +
 arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c     |  117 +++++
 arch/arm/cpu/armv8/fsl-lsch3/mp.c                 |    7 +
 arch/arm/cpu/armv8/fsl-lsch3/mp.h                 |    1 +
 arch/arm/cpu/armv8/fsl-lsch3/soc.c                |  107 +++++
 arch/arm/cpu/armv8/fsl-lsch3/speed.c              |   11 +-
 arch/arm/cpu/armv8/generic_timer.c                |   11 +
 arch/arm/cpu/armv8/u-boot-spl.lds                 |   77 ++++
 arch/arm/include/asm/arch-fsl-lsch3/config.h      |   42 ++
 arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h  |   67 +++
 arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h |   29 ++
 arch/arm/include/asm/arch-fsl-lsch3/soc.h         |    8 +
 arch/arm/lib/crt0_64.S                            |    7 +
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c         |    8 +-
 arch/powerpc/cpu/mpc85xx/speed.c                  |    4 +-
 board/freescale/bsc9132qds/bsc9132qds.c           |    4 +-
 board/freescale/c29xpcie/c29xpcie.c               |    4 +-
 board/freescale/common/qixis.c                    |   31 +-
 board/freescale/ls2085a/ls2085a.c                 |   29 +-
 board/freescale/ls2085aqds/Kconfig                |   16 +
 board/freescale/ls2085aqds/MAINTAINERS            |    8 +
 board/freescale/ls2085aqds/Makefile               |    9 +
 board/freescale/ls2085aqds/README                 |  148 ++++++
 board/freescale/ls2085aqds/ddr.c                  |  196 ++++++++
 board/freescale/ls2085aqds/ddr.h                  |   92 ++++
 board/freescale/ls2085aqds/eth.c                  |  380 +++++++++++++++
 board/freescale/ls2085aqds/ls2085aqds.c           |  274 +++++++++++
 board/freescale/ls2085aqds/ls2085aqds_qixis.h     |   30 ++
 board/freescale/ls2085ardb/Kconfig                |   16 +
 board/freescale/ls2085ardb/MAINTAINERS            |    8 +
 board/freescale/ls2085ardb/Makefile               |    8 +
 board/freescale/ls2085ardb/README                 |  128 ++++++
 board/freescale/ls2085ardb/ddr.c                  |  196 ++++++++
 board/freescale/ls2085ardb/ddr.h                  |   92 ++++
 board/freescale/ls2085ardb/ls2085ardb.c           |  249 ++++++++++
 board/freescale/ls2085ardb/ls2085ardb_qixis.h     |   20 +
 board/freescale/p1010rdb/p1010rdb.c               |    5 +-
 board/freescale/p1010rdb/spl.c                    |    4 +-
 common/board_r.c                                  |    6 +
 common/spl/spl.c                                  |    2 +-
 common/spl/spl_nand.c                             |    2 +-
 configs/ls2085aqds_defconfig                      |    3 +
 configs/ls2085aqds_nand_defconfig                 |    4 +
 configs/ls2085ardb_defconfig                      |    3 +
 configs/ls2085ardb_nand_defconfig                 |    4 +
 drivers/misc/fsl_ifc.c                            |   12 +
 drivers/mmc/fsl_esdhc.c                           |   36 +-
 drivers/mtd/nand/fsl_ifc_nand.c                   |   53 ++-
 drivers/mtd/nand/fsl_ifc_spl.c                    |   25 +-
 drivers/net/Makefile                              |    1 +
 drivers/net/fm/eth.c                              |    2 +-
 drivers/net/fm/memac.c                            |    2 +-
 drivers/net/fm/memac_phy.c                        |   62 ++-
 drivers/net/fsl-mc/mc.c                           |  512 ++++++++++++++++-----
 drivers/net/ldpaa_eth/Makefile                    |    3 +-
 drivers/net/ldpaa_eth/ldpaa_eth.c                 |   62 ++-
 drivers/net/ldpaa_eth/ldpaa_eth.h                 |    4 -
 drivers/net/ldpaa_eth/ldpaa_wriop.c               |  146 ++++++
 drivers/net/ldpaa_eth/ls2085a.c                   |   83 ++++
 drivers/net/phy/cortina.c                         |    4 +-
 drivers/net/vsc9953.c                             |    2 +-
 include/configs/ls2085a_common.h                  |  225 +++++----
 include/configs/ls2085a_emu.h                     |   65 +++
 include/configs/ls2085a_simu.h                    |  122 +++++
 include/configs/ls2085aqds.h                      |  362 +++++++++++++++
 include/configs/ls2085ardb.h                      |  308 +++++++++++++
 include/fsl-mc/ldpaa_wriop.h                      |   70 +++
 include/fsl_ddr_sdram.h                           |    1 +
 include/fsl_esdhc.h                               |    4 +
 include/fsl_ifc.h                                 |   84 ++--
 {arch/powerpc/include/asm => include}/fsl_memac.h |    0
 79 files changed, 4658 insertions(+), 437 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
 create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
 create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/soc.c
 create mode 100644 arch/arm/cpu/armv8/u-boot-spl.lds
 create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
 create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/soc.h
 create mode 100644 board/freescale/ls2085aqds/Kconfig
 create mode 100644 board/freescale/ls2085aqds/MAINTAINERS
 create mode 100644 board/freescale/ls2085aqds/Makefile
 create mode 100644 board/freescale/ls2085aqds/README
 create mode 100644 board/freescale/ls2085aqds/ddr.c
 create mode 100644 board/freescale/ls2085aqds/ddr.h
 create mode 100644 board/freescale/ls2085aqds/eth.c
 create mode 100644 board/freescale/ls2085aqds/ls2085aqds.c
 create mode 100644 board/freescale/ls2085aqds/ls2085aqds_qixis.h
 create mode 100644 board/freescale/ls2085ardb/Kconfig
 create mode 100644 board/freescale/ls2085ardb/MAINTAINERS
 create mode 100644 board/freescale/ls2085ardb/Makefile
 create mode 100644 board/freescale/ls2085ardb/README
 create mode 100644 board/freescale/ls2085ardb/ddr.c
 create mode 100644 board/freescale/ls2085ardb/ddr.h
 create mode 100644 board/freescale/ls2085ardb/ls2085ardb.c
 create mode 100644 board/freescale/ls2085ardb/ls2085ardb_qixis.h
 create mode 100644 configs/ls2085aqds_defconfig
 create mode 100644 configs/ls2085aqds_nand_defconfig
 create mode 100644 configs/ls2085ardb_defconfig
 create mode 100644 configs/ls2085ardb_nand_defconfig
 create mode 100644 drivers/net/ldpaa_eth/ldpaa_wriop.c
 create mode 100644 drivers/net/ldpaa_eth/ls2085a.c
 create mode 100644 include/configs/ls2085aqds.h
 create mode 100644 include/configs/ls2085ardb.h
 create mode 100644 include/fsl-mc/ldpaa_wriop.h
 rename {arch/powerpc/include/asm => include}/fsl_memac.h (100%)

-- 
1.7.9.5

[U-Boot] [PATCH v5 01/28] armv8/fsl-lsch3: Implement workaround for erratum A008585

[York Sun]

Generic Timer may contain an erroneous value. The workaround is to
read it twice until getting the same value.

Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/generic_timer.c           |   11 +++++++++++
 arch/arm/include/asm/arch-fsl-lsch3/config.h |    1 +
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c
index 223b95e..8e60bae 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -25,7 +25,18 @@ unsigned long get_tbclk(void)
 unsigned long timer_read_counter(void)
 {
 	unsigned long cntpct;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
+	/* This erratum number needs to be confirmed to match ARM document */
+	unsigned long temp;
+#endif
 	isb();
 	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
+	asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
+	while (temp != cntpct) {
+		asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+		asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
+	}
+#endif
 	return cntpct;
 }
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 1d2a7fa..2d461d9 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -120,6 +120,7 @@
 #ifdef CONFIG_LS2085A
 #define CONFIG_SYS_FSL_ERRATUM_A008336
 #define CONFIG_SYS_FSL_ERRATUM_A008514
+#define CONFIG_SYS_FSL_ERRATUM_A008585
 #endif
 
 #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
-- 
1.7.9.5

[U-Boot] [PATCH v5 02/28] armv8/ls2085a: Update common header file

[York Sun]

From: Prabhakar Kushwaha <prabhakar@freescale.com>

ls2085a_common.h contains hard-coded information for NOR/NAND flash,
I2C, DDR, etc. These are platform specific. Move them out of common
header file and placed into respective board header files.

Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector
size.

Enable command auto complete. Update prompt symbol. Set fdt_high to
0xa0000000 because Linux requires that the fdt  be 8-byte aligned
and below 512 MiB. Besides ensuring compliance with the 512 MiB
limit, this avoids problems with the dtb being misaligned within
the FIT image.

Change the MC FW, MC DPL and Debug server NOR addresses in compliance
with the NOR flash layouts for 128MB flash.

Add PCIe macros. Enable "loadb" command. Disable debug server.
Enable workaround for erratum A008511.
Stop reset on panic for postmortem debugging.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>

---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
  Rebase after adding macros CONFIG_SYS_I2C_MXC_I2C3 in another patch set

 arch/arm/include/asm/arch-fsl-lsch3/config.h |   11 ++
 include/configs/ls2085a_common.h             |  142 ++++++--------------------
 include/configs/ls2085a_emu.h                |   62 +++++++++++
 include/configs/ls2085a_simu.h               |  117 +++++++++++++++++++++
 4 files changed, 222 insertions(+), 110 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 2d461d9..518e59c 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -108,6 +108,16 @@
 /* IFC */
 #define CONFIG_SYS_FSL_IFC_LE
 
+/* PCIe */
+#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_PCIE4_ADDR			(CONFIG_SYS_IMMR + 0x2700000)
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x1000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
+
 #ifdef CONFIG_LS2085A
 #define CONFIG_MAX_CPUS				16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
@@ -119,6 +129,7 @@
 
 #ifdef CONFIG_LS2085A
 #define CONFIG_SYS_FSL_ERRATUM_A008336
+#define CONFIG_SYS_FSL_ERRATUM_A008511
 #define CONFIG_SYS_FSL_ERRATUM_A008514
 #define CONFIG_SYS_FSL_ERRATUM_A008585
 #endif
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 1f1eddb..5721b18 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -23,7 +23,7 @@
 #define CONFIG_ARCH_MISC_INIT
 
 /* Link Definitions */
-#define CONFIG_SYS_TEXT_BASE		0x30001000
+#define CONFIG_SYS_TEXT_BASE		0x30100000
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
@@ -47,8 +47,6 @@
 #define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
 #define CONFIG_SYS_DDR_RAW_TIMING
 #endif
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	4
 
 #define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
 
@@ -72,7 +70,6 @@
 #define CONFIG_SYS_DP_DDR_BASE_PHY	0
 #define CONFIG_DP_DDR_CTRL		2
 #define CONFIG_DP_DDR_NUM_CTRLS		1
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
 
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY		12000000	/* 12MHz */
@@ -86,8 +83,6 @@
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */
-#define CONFIG_SYS_MXC_I2C1_SPEED	40000000
-#define CONFIG_SYS_MXC_I2C2_SPEED	40000000
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX       2
@@ -101,8 +96,7 @@
 
 /* IFC */
 #define CONFIG_FSL_IFC
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
 /*
  * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
  * address 0. But this region is limited to 256MB. To accommodate bigger NOR
@@ -116,125 +110,55 @@
 #define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
 
-/*
- * NOR Flash Timing Params
- */
-#define CONFIG_SYS_NOR0_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
-	CSPR_PORT_SIZE_16					| \
-	CSPR_MSEL_NOR						| \
-	CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
-	CSPR_PORT_SIZE_16					| \
-	CSPR_MSEL_NOR						| \
-	CSPR_V)
-#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
-				FTIM0_NOR_TEADC(0x1) | \
-				FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
-				FTIM1_NOR_TRAD_NOR(0x1))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
-				FTIM2_NOR_TCH(0x0) | \
-				FTIM2_NOR_TWP(0x1))
-#define CONFIG_SYS_NOR_FTIM3	0x04000000
-#define CONFIG_SYS_IFC_CCR	0x01000000
-
 #ifndef CONFIG_SYS_NO_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 #endif
 
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS	256
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
 #define CONFIG_SYS_NAND_BASE		0x520000000
 #define CONFIG_SYS_NAND_BASE_PHYS	0x20000000
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
-				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
-				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
-
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
-				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
-				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
-				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
-				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
-				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
-				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
-					FTIM0_NAND_TWP(0x18)   | \
-					FTIM0_NAND_TWCHT(0x07) | \
-					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
-					FTIM1_NAND_TWBE(0x39)  | \
-					FTIM1_NAND_TRR(0x0e)   | \
-					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
-					FTIM2_NAND_TREH(0x0a) | \
-					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
-
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-
 /* Debug Server firmware */
-#define CONFIG_FSL_DEBUG_SERVER
 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR			0x580C00000ULL
 /* 2 sec timeout */
 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT			(2 * 1000 * 1000)
 
 /* MC firmware */
 #define CONFIG_FSL_MC_ENET
 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
-#define CONFIG_SYS_LS_MC_FW_IN_NOR
-#define CONFIG_SYS_LS_MC_FW_ADDR	0x580200000ULL
-#define CONFIG_SYS_LS_MC_DPL_IN_NOR
-#define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL
 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	(256 * 1024)
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0xe00000
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH		(256 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET	0xe00000
 
 /* Carve out a DDR region which will not be used by u-boot/Linux */
 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
 #define CONFIG_SYS_MEM_TOP_HIDE		get_dram_size_to_hide()
 #endif
 
+/* PCIe */
+#define CONFIG_PCIE1		/* PCIE controler 1 */
+#define CONFIG_PCIE2		/* PCIE controler 2 */
+#define CONFIG_PCIE3		/* PCIE controler 3 */
+#define CONFIG_PCIE4		/* PCIE controler 4 */
+#define FSL_PCIE_COMPAT "fsl,20851a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS		0x40000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x40000000
+#define CONFIG_SYS_PCIE_MEM_SIZE	0x40000000	/* 1G */
+
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_BDI
@@ -242,6 +166,7 @@
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
+#define CONFIG_CMD_LOADB
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
@@ -261,8 +186,6 @@
 /* Physical Memory Map */
 /* fixme: these need to be checked against the board */
 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
-#define CONFIG_SYS_CLK_FREQ	100000000
-#define CONFIG_DDR_CLK_FREQ	133333333
 
 #define CONFIG_NR_DRAM_BANKS		3
 
@@ -278,7 +201,7 @@
 	"kernel_addr=0x100000\0"		\
 	"ramdisk_addr=0x800000\0"		\
 	"ramdisk_size=0x2000000\0"		\
-	"fdt_high=0xffffffffffffffff\0"		\
+	"fdt_high=0xa0000000\0"			\
 	"initrd_high=0xffffffffffffffff\0"	\
 	"kernel_start=0x581200000\0"		\
 	"kernel_load=0xa0000000\0"		\
@@ -293,13 +216,9 @@
 					"$kernel_size && bootm $kernel_load"
 #define CONFIG_BOOTDELAY		1
 
-/* Store environment at top of flash */
-#define CONFIG_ENV_IS_NOWHERE		1
-#define CONFIG_ENV_SIZE			0x1000
-
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PROMPT		"> "
+#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_HUSH_PARSER
@@ -307,10 +226,13 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS		64	/* max command args */
 
 #ifndef __ASSEMBLY__
 unsigned long get_dram_size_to_hide(void);
 #endif
 
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
 #endif /* __LS2_COMMON_H */
diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h
index a02d694..961dc63 100644
--- a/include/configs/ls2085a_emu.h
+++ b/include/configs/ls2085a_emu.h
@@ -12,6 +12,12 @@
 #define CONFIG_IDENT_STRING		" LS2085A-EMU"
 #define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-EMU"
 
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	133333333
+
+#define CONFIG_SYS_MXC_I2C1_SPEED	40000000
+#define CONFIG_SYS_MXC_I2C2_SPEED	40000000
+
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR_EMU		/* Support emulator */
 #define SPD_EEPROM_ADDRESS1	0x51
@@ -19,6 +25,62 @@
 #define SPD_EEPROM_ADDRESS3	0x53
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
 #define CONFIG_SYS_SPD_BUS_NUM	1	/* SPD on I2C bus 1 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR		1
+#define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
 
 #define CONFIG_FSL_DDR_SYNC_REFRESH
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/*
+ * NOR Flash Timing Params
+ */
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
+				FTIM0_NOR_TEADC(0x1) | \
+				FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
+				FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
+				FTIM2_NOR_TCH(0x0) | \
+				FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580C00000ULL
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_FW_IN_NOR
+#define CONFIG_SYS_LS_MC_FW_ADDR	0x580200000ULL
+
+#define CONFIG_SYS_LS_MC_DPL_IN_NOR
+#define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_IS_NOWHERE		1
+#define CONFIG_ENV_SIZE			0x1000
+
 #endif /* __LS2_EMU_H */
diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h
index af34f3f..e669d8d 100644
--- a/include/configs/ls2085a_simu.h
+++ b/include/configs/ls2085a_simu.h
@@ -12,10 +12,112 @@
 #define CONFIG_IDENT_STRING		" LS2085A-SIMU"
 #define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-SIMU"
 
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	133333333
+
+#define CONFIG_SYS_MXC_I2C1_SPEED	40000000
+#define CONFIG_SYS_MXC_I2C2_SPEED	40000000
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR		1
+#define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+
 /* SMSC 91C111 ethernet configuration */
 #define CONFIG_SMC91111
 #define CONFIG_SMC91111_BASE	(0x2210000)
 
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
+/*
+ * NOR Flash Timing Params
+ */
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
+				FTIM0_NOR_TEADC(0x1) | \
+				FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
+				FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
+				FTIM2_NOR_TCH(0x0) | \
+				FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
@@ -25,4 +127,19 @@
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
 
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580C00000ULL
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_FW_IN_NOR
+#define CONFIG_SYS_LS_MC_FW_ADDR	0x580200000ULL
+
+#define CONFIG_SYS_LS_MC_DPL_IN_NOR
+#define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_IS_NOWHERE		1
+#define CONFIG_ENV_SIZE			0x1000
+
 #endif /* __LS2_SIMU_H */
-- 
1.7.9.5

[U-Boot] [PATCH v5 03/28] armv8/fsl-lsch3: Fix platform clock calculation

[York Sun]

Platform clock is half of platform PLL. There is an additional divisor
in place. Clean up code copied from powerpc.

Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/speed.c |    7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
index 72cd999..2b140cd 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
@@ -86,6 +86,8 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
+	/* Platform clock is half of platform PLL */
+	sys_info->freq_systembus /= 2;
 	sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
@@ -102,10 +104,7 @@ void get_sys_info(struct sys_info *sys_info)
 			 offsetof(struct ccsr_clk_cluster_group,
 				  pllngsr[i%3].gsr));
 		ratio[i] = (in_le32(offset) >> 1) & 0x3f;
-		if (ratio[i] > 4)
-			freq_c_pll[i] = sysclk * ratio[i];
-		else
-			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
+		freq_c_pll[i] = sysclk * ratio[i];
 	}
 
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
-- 
1.7.9.5

[U-Boot] [PATCH v5 04/28] armv8/ls2085a: Fix generic timer clock source

[York Sun]

The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Mark Rutland <mark.rutland@arm.com>

---

Changes in v5: None
Changes in v4:
  Remove temporary variable cntfrq.

Changes in v3:
  Move secondary core fix to mp.c.
  Replace hard-coded value with COUNTER_FREQUENCY.

Changes in v2:
  Fix CNTFRQ for secondary cores when COUNTER_FREQUENCY_REAL is defined.

 README                                  |    8 ++++++++
 arch/arm/cpu/armv8/fsl-lsch3/cpu.c      |   24 ++++++++++++++++++++++++
 arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S |    6 ++++++
 arch/arm/cpu/armv8/fsl-lsch3/mp.c       |    7 +++++++
 arch/arm/cpu/armv8/fsl-lsch3/mp.h       |    1 +
 board/freescale/ls2085a/ls2085a.c       |   18 ------------------
 include/configs/ls2085a_common.h        |    6 +++++-
 7 files changed, 51 insertions(+), 19 deletions(-)

diff --git a/README b/README
index e710226..f063a74 100644
--- a/README
+++ b/README
@@ -690,6 +690,14 @@ The following options need to be configured:
 		exists, unlike the similar options in the Linux kernel. Do not
 		set these options unless they apply!
 
+		COUNTER_FREQUENCY
+		Generic timer clock source frequency.
+
+		COUNTER_FREQUENCY_REAL
+		Generic timer clock source frequency if the real clock is
+		different from COUNTER_FREQUENCY, and can only be determined
+		at run time.
+
 		NOTE: The following can be machine specific errata. These
 		do have ability to provide rudimentary version and machine
 		specific checks, but expect no product checks.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 94fd147..e985181 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -395,3 +395,27 @@ int arch_early_init_r(void)
 
 	return 0;
 }
+
+int timer_init(void)
+{
+	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#ifdef COUNTER_FREQUENCY_REAL
+	unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
+
+	/* Update with accurate clock frequency */
+	asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+#endif
+
+	/* Enable timebase for all clusters.
+	 * It is safe to do so even some clusters are not enabled.
+	 */
+	out_le32(cltbenr, 0xf);
+
+	/* Enable clock for timer
+	 * This is a global setting.
+	 */
+	out_le32(cntcr, 0x1);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index 886576e..53bdb44 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -224,6 +224,9 @@ ENTRY(secondary_boot_func)
 	/* physical address of this cpus spin table element */
 	add	x11, x1, x0
 
+	ldr	x0, =__real_cntfrq
+	ldr	x0, [x0]
+	msr	cntfrq_el0, x0	/* set with real frequency */
 	str	x9, [x11, #16]	/* LPID */
 	mov	x4, #1
 	str	x4, [x11, #8]	/* STATUS */
@@ -275,6 +278,9 @@ ENDPROC(secondary_switch_to_el1)
 
 	/* 64 bit alignment for elements accessed as data */
 	.align 4
+	.global __real_cntfrq
+__real_cntfrq:
+	.quad COUNTER_FREQUENCY
 	.globl __secondary_boot_code_size
 	.type __secondary_boot_code_size, %object
 	/* Secondary Boot Code ends here */
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
index ce9c0c1..da7853a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
@@ -31,6 +31,13 @@ int fsl_lsch3_wake_seconday_cores(void)
 	int i, timeout = 10;
 	u64 *table = get_spin_tbl_addr();
 
+#ifdef COUNTER_FREQUENCY_REAL
+	/* update for secondary cores */
+	__real_cntfrq = COUNTER_FREQUENCY_REAL;
+	flush_dcache_range((unsigned long)&__real_cntfrq,
+			   (unsigned long)&__real_cntfrq + 8);
+#endif
+
 	cores = cpu_mask();
 	/* Clear spin table so that secondary processors
 	 * observe the correct value after waking up from wfe.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
index 66144d6..c985d6a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
@@ -26,6 +26,7 @@
 #define id_to_core(x)	((x & 3) | (x >> 6))
 #ifndef __ASSEMBLY__
 extern u64 __spin_table[];
+extern u64 __real_cntfrq;
 extern u64 *secondary_boot_code;
 extern size_t __secondary_boot_code_size;
 int fsl_lsch3_wake_seconday_cores(void);
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index e78c63a..bd016e9 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -55,24 +55,6 @@ int dram_init(void)
 	return 0;
 }
 
-int timer_init(void)
-{
-	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
-	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
-
-	/* Enable timebase for all clusters.
-	 * It is safe to do so even some clusters are not enabled.
-	 */
-	out_le32(cltbenr, 0xf);
-
-	/* Enable clock for timer
-	 * This is a global setting.
-	 */
-	out_le32(cntcr, 0x1);
-
-	return 0;
-}
-
 /*
  * Board specific reset that is system reset.
  */
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 5721b18..f6b3ed0 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -72,7 +72,11 @@
 #define CONFIG_DP_DDR_NUM_CTRLS		1
 
 /* Generic Timer Definitions */
-#define COUNTER_FREQUENCY		12000000	/* 12MHz */
+/*
+ * This is not an accurate number. It is used in start.S. The frequency
+ * will be udpated later when get_bus_freq(0) is available.
+ */
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
-- 
1.7.9.5

[U-Boot] [PATCH v5 05/28] armv8/ls2085a: Add support for reset request

[York Sun]

From: pankaj chauhan <pankaj.chauhan@freescale.com>

Add support for reset_cpu() by asserting RESET_REQ_B.

Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/cpu.c |   11 +++++++++++
 board/freescale/ls2085a/ls2085a.c  |    7 -------
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index e985181..0e5aa5c 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -419,3 +419,14 @@ int timer_init(void)
 
 	return 0;
 }
+
+void reset_cpu(ulong addr)
+{
+	u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
+	u32 val;
+
+	/* Raise RESET_REQ_B */
+	val = in_le32(rstcr);
+	val |= 0x02;
+	out_le32(rstcr, val);
+}
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index bd016e9..19f5a7b 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -55,13 +55,6 @@ int dram_init(void)
 	return 0;
 }
 
-/*
- * Board specific reset that is system reset.
- */
-void reset_cpu(ulong addr)
-{
-}
-
 #if defined(CONFIG_ARCH_MISC_INIT)
 int arch_misc_init(void)
 {
-- 
1.7.9.5

[U-Boot] [PATCH v5 06/28] armv8/fsl-lsch3: Set nodes in DVM domain

[York Sun]

From: Scott Wood <scottwood@freescale.com>

This is required for TLB invalidation broadcasts to work.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S      |    9 +++++++++
 arch/arm/include/asm/arch-fsl-lsch3/config.h |    6 ++++++
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index 53bdb44..018c617 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -15,6 +15,15 @@
 ENTRY(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
+	/* Add fully-coherent masters to DVM domain */
+	ldr	x1, =CCI_MN_BASE
+	ldr	x2, [x1, #CCI_MN_RNF_NODEID_LIST]
+	str	x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
+1:	ldr	x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
+	mvn	x0, x3
+	tst	x0, x3		/* Wait for domain addition to complete */
+	b.ne	1b
+
 	/* Set the SMMU page size in the sACR register */
 	ldr	x1, =SMMU_BASE
 	ldr	w0, [x1, #0x10]
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 518e59c..9121452 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -118,6 +118,12 @@
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
 #define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
 
+/* Cache Coherent Interconnect */
+#define CCI_MN_BASE		0x04000000
+#define CCI_MN_RNF_NODEID_LIST		0x180
+#define CCI_MN_DVM_DOMAIN_CTL		0x200
+#define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
+
 #ifdef CONFIG_LS2085A
 #define CONFIG_MAX_CPUS				16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
-- 
1.7.9.5

[U-Boot] [PATCH v5 07/28] armv8/fsl-lsch3: Update early MMU table

[York Sun]

During booting, IFC is mapped to low region. After booting up, IFC is
remapped to high region for larger space. The environmental variables are
also stored at high region. In order to read the variables during booting,
a virtual mapping is required.

Cache was enabled for entire IFC space before. Actually the first two
entries are big enough (4MB) to cover the boot code and environmental
variables. Remove extra entries. Move OCRAM entry out of ifdef.

Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/cpu.c |   56 +++++++++++++++++++++++++-----------
 common/board_r.c                   |    6 ++++
 2 files changed, 45 insertions(+), 17 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 0e5aa5c..595dbd1 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -25,8 +25,9 @@ DECLARE_GLOBAL_DATA_PTR;
  * levels of translation tables here to cover 40-bit address space.
  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
  * Level 0 IA[39], table address @0
- * Level 1 IA[31:30], table address @01000, 0x2000
- * Level 2 IA[29:21], table address @0x3000
+ * Level 1 IA[31:30], table address @0x1000, 0x2000
+ * Level 2 IA[29:21], table address @0x3000, 0x4000
+ * Address above 0x5000 is free for other purpose.
  */
 
 #define SECTION_SHIFT_L0	39UL
@@ -61,12 +62,12 @@ static inline void early_mmu_setup(void)
 {
 	int el;
 	u64 i;
-	u64 section_l1t0, section_l1t1, section_l2;
+	u64 section_l1t0, section_l1t1, section_l2t0, section_l2t1;
 	u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
 	u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
 	u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
-	u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
-
+	u64 *level2_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
+	u64 *level2_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
 
 	level0_table[0] =
 		(u64)level1_table_0 | PMD_TYPE_TABLE;
@@ -80,21 +81,25 @@ static inline void early_mmu_setup(void)
 	 */
 	section_l1t0 = 0;
 	section_l1t1 = BLOCK_SIZE_L0;
-	section_l2 = 0;
+	section_l2t0 = 0;
+	section_l2t1 = CONFIG_SYS_FLASH_BASE;
 	for (i = 0; i < 512; i++) {
 		set_pgtable_section(level1_table_0, i, section_l1t0,
 				    MT_DEVICE_NGNRNE);
 		set_pgtable_section(level1_table_1, i, section_l1t1,
 				    MT_NORMAL);
-		set_pgtable_section(level2_table, i, section_l2,
+		set_pgtable_section(level2_table_0, i, section_l2t0,
+				    MT_DEVICE_NGNRNE);
+		set_pgtable_section(level2_table_1, i, section_l2t1,
 				    MT_DEVICE_NGNRNE);
 		section_l1t0 += BLOCK_SIZE_L1;
 		section_l1t1 += BLOCK_SIZE_L1;
-		section_l2 += BLOCK_SIZE_L2;
+		section_l2t0 += BLOCK_SIZE_L2;
+		section_l2t1 += BLOCK_SIZE_L2;
 	}
 
 	level1_table_0[0] =
-		(u64)level2_table | PMD_TYPE_TABLE;
+		(u64)level2_table_0 | PMD_TYPE_TABLE;
 	level1_table_0[1] =
 		0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT |
 		PMD_ATTRINDX(MT_DEVICE_NGNRNE);
@@ -105,17 +110,34 @@ static inline void early_mmu_setup(void)
 		0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
 		PMD_ATTRINDX(MT_NORMAL);
 
-	/* Rewrite table to enable cache */
-	set_pgtable_section(level2_table,
+	/* Rewerite table to enable cache for OCRAM */
+	set_pgtable_section(level2_table_0,
 			    CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
 			    CONFIG_SYS_FSL_OCRAM_BASE,
 			    MT_NORMAL);
-	for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2;
-	     i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE)
-	     >> SECTION_SHIFT_L2; i++) {
-		section_l2 = i << SECTION_SHIFT_L2;
-		set_pgtable_section(level2_table, i,
-				    section_l2, MT_NORMAL);
+
+#if defined(CONFIG_SYS_NOR0_CSPR_EARLY) && defined(CONFIG_SYS_NOR_AMASK_EARLY)
+	/* Rewrite table to enable cache for two entries (4MB) */
+	section_l2t1 = CONFIG_SYS_IFC_BASE;
+	set_pgtable_section(level2_table_0,
+			    section_l2t1 >> SECTION_SHIFT_L2,
+			    section_l2t1,
+			    MT_NORMAL);
+	section_l2t1 += BLOCK_SIZE_L2;
+	set_pgtable_section(level2_table_0,
+			    section_l2t1 >> SECTION_SHIFT_L2,
+			    section_l2t1,
+			    MT_NORMAL);
+#endif
+
+	/* Create a mapping for 256MB IFC region to final flash location */
+	level1_table_0[CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1] =
+		(u64)level2_table_1 | PMD_TYPE_TABLE;
+	section_l2t1 = CONFIG_SYS_IFC_BASE;
+	for (i = 0; i < 0x10000000 >> SECTION_SHIFT_L2; i++) {
+		set_pgtable_section(level2_table_1, i,
+				    section_l2t1, MT_DEVICE_NGNRNE);
+		section_l2t1 += BLOCK_SIZE_L2;
 	}
 
 	el = current_el();
diff --git a/common/board_r.c b/common/board_r.c
index 0335f6b..d6dcc97 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -699,6 +699,12 @@ init_fnc_t init_sequence_r[] = {
 	/* TODO: could x86/PPC have this also perhaps? */
 #ifdef CONFIG_ARM
 	initr_caches,
+	/* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
+	 *	 A temporary mapping of IFC high region is since removed,
+	 *	 so environmental variables in NOR flash is not availble
+	 *	 until board_init() is called below to remap IFC to high
+	 *	 region.
+	 */
 #endif
 	initr_reloc_global_data,
 #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
-- 
1.7.9.5

[U-Boot] [PATCH v5 08/28] fsl-lsch3: Introduce place for common early SoC init

[York Sun]

From: Scott Wood <scottwood@freescale.com>

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/Makefile     |    1 +
 arch/arm/cpu/armv8/fsl-lsch3/soc.c        |   14 ++++++++++++++
 arch/arm/include/asm/arch-fsl-lsch3/soc.h |    8 ++++++++
 board/freescale/ls2085a/ls2085a.c         |    4 ++--
 4 files changed, 25 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/soc.c
 create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/soc.h

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
index f920eeb..6542590 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
@@ -6,6 +6,7 @@
 
 obj-y += cpu.o
 obj-y += lowlevel.o
+obj-y += soc.o
 obj-y += speed.o
 obj-$(CONFIG_MP) += mp.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
new file mode 100644
index 0000000..242a865
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ifc.h>
+#include <asm/arch-fsl-lsch3/soc.h>
+
+void fsl_lsch3_early_init_f(void)
+{
+	init_early_memctl_regs();	/* tighten IFC timing */
+}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
new file mode 100644
index 0000000..16b723d
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+void fsl_lsch3_early_init_f(void);
+
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index 19f5a7b..dd0acf2 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -15,6 +15,7 @@
 #include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
 #include <environment.h>
+#include <asm/arch-fsl-lsch3/soc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -31,8 +32,7 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
-	init_early_memctl_regs();	/* tighten IFC timing */
-
+	fsl_lsch3_early_init_f();
 	return 0;
 }
 
-- 
1.7.9.5

[U-Boot] [PATCH v5 09/28] armv8/ls2085a: Add workaround for USB erratum A-008751

[York Sun]

From: Scott Wood <scottwood@freescale.com>

Without this "USB may not work" according to the erratum text, though I
did not notice a problem without it.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/soc.c           |   11 +++++++++++
 arch/arm/include/asm/arch-fsl-lsch3/config.h |    5 +++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index 242a865..17700ef 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -7,8 +7,19 @@
 #include <common.h>
 #include <fsl_ifc.h>
 #include <asm/arch-fsl-lsch3/soc.h>
+#include <asm/io.h>
+
+static void erratum_a008751(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+	writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
+#endif
+}
 
 void fsl_lsch3_early_init_f(void)
 {
+	erratum_a008751();
 	init_early_memctl_regs();	/* tighten IFC timing */
 }
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 9121452..a81e3ed 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -124,6 +124,10 @@
 #define CCI_MN_DVM_DOMAIN_CTL		0x200
 #define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
 
+/* Supplemental Configuration */
+#define SCFG_BASE		0x01fc0000
+#define SCFG_USB3PRM1CR			0x000
+
 #ifdef CONFIG_LS2085A
 #define CONFIG_MAX_CPUS				16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
@@ -138,6 +142,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A008511
 #define CONFIG_SYS_FSL_ERRATUM_A008514
 #define CONFIG_SYS_FSL_ERRATUM_A008585
+#define CONFIG_SYS_FSL_ERRATUM_A008751
 #endif
 
 #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
-- 
1.7.9.5

[U-Boot] [PATCH v5 10/28] armv8/fsl-lsch3: Use correct compatible for serial clock fixup

[York Sun]

From: Scott Wood <scottwood@freescale.com>

The serial nodes in the fsl-lsch3 device trees have compatible =
"fsl,ns16550", "ns16550a" -- so don't look for "ns16550".

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/fdt.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
index 7eb9b6a..42c5b58 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
@@ -62,7 +62,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
 
 #ifdef CONFIG_SYS_NS16550
-	do_fixup_by_compat_u32(blob, "ns16550",
+	do_fixup_by_compat_u32(blob, "fsl,ns16550",
 			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
 }
-- 
1.7.9.5

[U-Boot] [PATCH v5 11/28] driver/ldpaa_eth: Update ldpaa ethernet driver

[York Sun]

From: Prabhakar Kushwaha <prabhakar@freescale.com>

Fix flush_dcache_range() input parameter to use start and end addresses.
Change ethernet interface name to DPNI. Update entry criteria for
ldpaa_eth_stop. Ethernet stack first stop the device before performing
next operation. At the time of Ethernet driver registration,
net_dev->state is set as ETH_STATE_INIT So take care net_dev->state as
ETH_STATE_INIT in ldpaa_eth_stop.

Undef CONFIG_PHYLIB temorarily because ldpaa_eth driver currently does
not support PHYLIB.

Instead of clearing pull descriptor one time, clear it before issuing any
volatile dequeue command.

Volatile command does not return frame immidiately, wait till a frame
is available in DQRR. This frame can be valid or expired.

Flush buffer before releasing to BMan ensure the core does not have any
cachelines that the WRIOP will DMA to.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/ldpaa_eth/ldpaa_eth.c |   62 +++++++++++++++++++++++--------------
 1 file changed, 38 insertions(+), 24 deletions(-)

diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c
index b79942f..9015e4f 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -15,6 +15,7 @@
 
 #include "ldpaa_eth.h"
 
+#undef CONFIG_PHYLIB
 static int init_phy(struct eth_device *dev)
 {
 	/*TODO for external PHY */
@@ -33,8 +34,6 @@ static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv,
 	struct qbman_release_desc releasedesc;
 	struct qbman_swp *swp = dflt_dpio->sw_portal;
 
-	invalidate_dcache_all();
-
 	fd_addr = ldpaa_fd_get_addr(fd);
 	fd_offset = ldpaa_fd_get_offset(fd);
 	fd_length = ldpaa_fd_get_len(fd);
@@ -62,6 +61,7 @@ static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv,
 	NetReceive((uint8_t *)(fd_addr)  + fd_offset, fd_length);
 
 error:
+	flush_dcache_range(fd_addr, fd_addr + LDPAA_ETH_RX_BUFFER_SIZE);
 	qbman_release_desc_clear(&releasedesc);
 	qbman_release_desc_set_bpid(&releasedesc, dflt_dpbp->dpbp_attr.bpid);
 	do {
@@ -76,22 +76,29 @@ static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
 	struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
 	const struct ldpaa_dq *dq;
 	const struct dpaa_fd *fd;
-	int i = 5, err = 0, status;
+	int i = 5, err = 0, status, loop = 20;
 	static struct qbman_pull_desc pulldesc;
 	struct qbman_swp *swp = dflt_dpio->sw_portal;
 
-	qbman_pull_desc_clear(&pulldesc);
-	qbman_pull_desc_set_numframes(&pulldesc, 1);
-	qbman_pull_desc_set_fq(&pulldesc, priv->rx_dflt_fqid);
-
 	while (--i) {
+		qbman_pull_desc_clear(&pulldesc);
+		qbman_pull_desc_set_numframes(&pulldesc, 1);
+		qbman_pull_desc_set_fq(&pulldesc, priv->rx_dflt_fqid);
+
 		err = qbman_swp_pull(swp, &pulldesc);
 		if (err < 0) {
 			printf("Dequeue frames error:0x%08x\n", err);
 			continue;
 		}
 
-		dq = qbman_swp_dqrr_next(swp);
+		do {
+			loop--;
+			dq = qbman_swp_dqrr_next(swp);
+
+			if (!loop)
+				break;
+		} while (!dq);
+
 		if (dq) {
 			/* Check for valid frame. If not sent a consume
 			 * confirmation to QBMAN otherwise give it to NADK
@@ -128,7 +135,6 @@ static void ldpaa_eth_tx_conf(struct ldpaa_eth_priv *priv,
 	struct qbman_release_desc releasedesc;
 	struct qbman_swp *swp = dflt_dpio->sw_portal;
 
-	invalidate_dcache_all();
 	fd_addr = ldpaa_fd_get_addr(fd);
 
 
@@ -159,22 +165,29 @@ static int ldpaa_eth_pull_dequeue_tx_conf(struct ldpaa_eth_priv *priv)
 	const struct ldpaa_dq *dq;
 	const struct dpaa_fd *fd;
 	int err = 0;
-	int i = 5, status;
+	int i = 5, status, loop = 20;
 	static struct qbman_pull_desc pulldesc;
 	struct qbman_swp *swp = dflt_dpio->sw_portal;
 
-	qbman_pull_desc_clear(&pulldesc);
-	qbman_pull_desc_set_numframes(&pulldesc, 1);
-	qbman_pull_desc_set_fq(&pulldesc, priv->tx_conf_fqid);
-
 	while (--i) {
+		qbman_pull_desc_clear(&pulldesc);
+		qbman_pull_desc_set_numframes(&pulldesc, 1);
+		qbman_pull_desc_set_fq(&pulldesc, priv->tx_conf_fqid);
+
 		err =  qbman_swp_pull(swp, &pulldesc);
 		if (err < 0) {
 			printf("Dequeue TX conf frames error:0x%08x\n", err);
 			continue;
 		}
 
-		dq = qbman_swp_dqrr_next(swp);
+		do {
+			loop--;
+			dq = qbman_swp_dqrr_next(swp);
+
+			if (!loop)
+				break;
+		} while (!dq);
+
 		if (dq) {
 			/* Check for valid frame. If not sent a consume
 			 * confirmation to QBMAN otherwise give it to NADK
@@ -229,7 +242,8 @@ static int ldpaa_eth_tx(struct eth_device *net_dev, void *buf, int len)
 
 	memcpy(((uint8_t *)(buffer_start) + data_offset), buf, len);
 
-	flush_dcache_range(buffer_start, LDPAA_ETH_RX_BUFFER_SIZE);
+	flush_dcache_range(buffer_start, buffer_start +
+					LDPAA_ETH_RX_BUFFER_SIZE);
 
 	ldpaa_fd_set_addr(&fd, (u64)buffer_start);
 	ldpaa_fd_set_offset(&fd, (uint16_t)(data_offset));
@@ -297,10 +311,10 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
 
 #ifdef CONFIG_PHYLIB
 	/* TODO Check this path */
-	ret = phy_startup(priv->phydev);
-	if (ret) {
+	err = phy_startup(priv->phydev);
+	if (err) {
 		printf("%s: Could not initialize\n", priv->phydev->dev->name);
-		return ret;
+		return err;
 	}
 #else
 	priv->phydev->speed = SPEED_1000;
@@ -361,7 +375,8 @@ static void ldpaa_eth_stop(struct eth_device *net_dev)
 	struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
 	int err = 0;
 
-	if (net_dev->state == ETH_STATE_PASSIVE)
+	if ((net_dev->state == ETH_STATE_PASSIVE) ||
+	    (net_dev->state == ETH_STATE_INIT))
 		return;
 	/* Stop Tx and Rx traffic */
 	err = dpni_disable(dflt_mc_io, priv->dpni_handle);
@@ -422,6 +437,8 @@ static int ldpaa_bp_add_7(uint16_t bpid)
 			goto err_alloc;
 		}
 		memset(addr, 0x00, LDPAA_ETH_RX_BUFFER_SIZE);
+		flush_dcache_range((u64)addr,
+				   (u64)(addr + LDPAA_ETH_RX_BUFFER_SIZE));
 
 		buf_array[i] = (uint64_t)addr;
 		debug("Release: buffer addr =0x%p\n", addr);
@@ -623,10 +640,7 @@ static int ldpaa_eth_netdev_init(struct eth_device *net_dev)
 	int err;
 	struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
 
-	if (priv->type == LDPAA_ETH_1G_E)
-		sprintf(net_dev->name, "DTSEC%d", priv->dpni_id);
-	else
-		sprintf(net_dev->name, "TGEC%d", priv->dpni_id);
+	sprintf(net_dev->name, "DPNI%d", priv->dpni_id);
 
 	net_dev->iobase = 0;
 	net_dev->init = ldpaa_eth_open;
-- 
1.7.9.5

[U-Boot] [PATCH v5 12/28] armv8: Add SerDes framework for Layerscape Architecture

[York Sun]

From: Minghuan Lian <Minghuan.Lian@freescale.com>

Add support of SerDes framework for Layerscape Architecture.
    - Add support of 2 SerDes block
    - Add SerDes protocol parsing and detection
    - Create table of SerDes protocol supported by LS2085A

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>

---

Changes in v5:
  s/LayerScape/Layerscape/g

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/Makefile             |    1 +
 arch/arm/cpu/armv8/fsl-lsch3/cpu.c                |    4 +
 arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c   |  110 +++++++++++++++++++
 arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c     |  117 +++++++++++++++++++++
 arch/arm/include/asm/arch-fsl-lsch3/config.h      |    4 +
 arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h  |   67 ++++++++++++
 arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h |    5 +
 include/configs/ls2085a_common.h                  |    5 +
 8 files changed, 313 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
 create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
 create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
index 6542590..9f7815b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
@@ -8,5 +8,6 @@ obj-y += cpu.o
 obj-y += lowlevel.o
 obj-y += soc.o
 obj-y += speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o
 obj-$(CONFIG_MP) += mp.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 595dbd1..caa48f2 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -12,6 +12,7 @@
 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
 #include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
+#include <asm/arch/fsl_serdes.h>
 #include "cpu.h"
 #include "mp.h"
 #include "speed.h"
@@ -415,6 +416,9 @@ int arch_early_init_r(void)
 	if (rv)
 		printf("Did not wake secondary cores\n");
 
+#ifdef CONFIG_SYS_HAS_SERDES
+	fsl_serdes_init();
+#endif
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
new file mode 100644
index 0000000..78b9210
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+	int ret = 0;
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	ret |= serdes1_prtcl_map[device];
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	ret |= serdes2_prtcl_map[device];
+#endif
+
+	return !!ret;
+}
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 cfg = in_le32(&gur->rcwsr[28]);
+	int i;
+
+	switch (sd) {
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	case FSL_SRDS_1:
+		cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+		cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+		break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	case FSL_SRDS_2:
+		cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+		cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+		break;
+#endif
+	default:
+		printf("invalid SerDes%d\n", sd);
+		break;
+	}
+	/* Is serdes enabled at all? */
+	if (cfg == 0)
+		return -ENODEV;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_get_prtcl(sd, cfg, i) == device)
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
+		u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 cfg;
+	int lane;
+
+	memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
+
+	cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask;
+	cfg >>= sd_prctl_shift;
+	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
+
+	if (!is_serdes_prtcl_valid(sd, cfg))
+		printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+
+	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
+		if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
+			debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
+		else
+			serdes_prtcl_map[lane_prtcl] = 1;
+	}
+}
+
+void fsl_serdes_init(void)
+{
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	serdes_init(FSL_SRDS_1,
+		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
+		    FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK,
+		    FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT,
+		    serdes1_prtcl_map);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	serdes_init(FSL_SRDS_2,
+		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
+		    FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK,
+		    FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT,
+		    serdes2_prtcl_map);
+#endif
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
new file mode 100644
index 0000000..098745b
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+
+struct serdes_config {
+	u8 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } },
+	{0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
+	{0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+		SGMII1 } },
+	{0x09, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+		SGMII1 } },
+	{0x0A, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+		SGMII1 } },
+	{0x0C, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+		SGMII1 } },
+	{0x0E, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+		SGMII1 } },
+	{0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
+	{0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
+	{0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
+	{0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1  } },
+	{0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1  } },
+	{0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B,
+		QSGMII_A} },
+	{0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+		{}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+	/* SerDes 2 */
+	{0x07, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+		SGMII16 } },
+	{0x09, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+		SGMII16 } },
+	{0x0A, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+		SGMII16 } },
+	{0x0C, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+		SGMII16 } },
+	{0x0E, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+		SGMII16 } },
+	{0x3D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
+	{0x3E, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
+	{0x3F, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
+	{0x40, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
+	{0x41, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
+	{0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
+	{0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
+	{0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
+	{0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
+		SGMII16 } },
+	{0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
+		PCIE4 } },
+	{0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
+		SATA2 } },
+	{0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
+		SATA2 } },
+	{}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+	serdes2_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index a81e3ed..98db1ef 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -38,6 +38,8 @@
 #define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
 						 0x18A0)
 
+#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR	(CONFIG_SYS_IMMR + 0xEA0000)
+
 /* SP (Cortex-A5) related */
 #define CONFIG_SYS_FSL_SP_ADDR			(CONFIG_SYS_IMMR + 0x00F00000)
 #define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR		(CONFIG_SYS_FSL_SP_ADDR)
@@ -133,6 +135,8 @@
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
 #define CONFIG_NUM_DDR_CONTROLLERS		3
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
 #else
 #error SoC not defined
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
new file mode 100644
index 0000000..2810f3f
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_SERDES_H
+#define __FSL_SERDES_H
+
+#include <config.h>
+
+#define	SRDS_MAX_LANES	8
+
+enum srds_prtcl {
+	NONE = 0,
+	PCIE1,
+	PCIE2,
+	PCIE3,
+	PCIE4,
+	SATA1,
+	SATA2,
+	XAUI1,
+	XAUI2,
+	XFI1,
+	XFI2,
+	XFI3,
+	XFI4,
+	XFI5,
+	XFI6,
+	XFI7,
+	XFI8,
+	SGMII1,
+	SGMII2,
+	SGMII3,
+	SGMII4,
+	SGMII5,
+	SGMII6,
+	SGMII7,
+	SGMII8,
+	SGMII9,
+	SGMII10,
+	SGMII11,
+	SGMII12,
+	SGMII13,
+	SGMII14,
+	SGMII15,
+	SGMII16,
+	QSGMII_A, /* A indicates MACs 1-4 */
+	QSGMII_B, /* B indicates MACs 5-8 */
+	QSGMII_C, /* C indicates MACs 9-12 */
+	QSGMII_D, /* D indicates MACs 12-16 */
+	SERDES_PRCTL_COUNT
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
+};
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+
+#endif /* __FSL_SERDES_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
index dd11ef7..91cf68b 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -63,6 +63,11 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK	0x3f
 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT	18
 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK	0x3f
+#define	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK	0x00FF0000
+#define	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT	16
+#define	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK	0xFF000000
+#define	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT	24
+
 	u8	res_180[0x200-0x180];
 	u32	scratchrw[32];	/* Scratch Read/Write */
 	u8	res_280[0x300-0x280];
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index f6b3ed0..5ce5e1c 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -19,6 +19,11 @@
 #define CONFIG_ARM_ERRATA_828024
 #define CONFIG_ARM_ERRATA_826974
 
+#include <asm/arch-fsl-lsch3/config.h>
+#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
+#define	CONFIG_SYS_HAS_SERDES
+#endif
+
 /* We need architecture specific misc initializations */
 #define CONFIG_ARCH_MISC_INIT
 
-- 
1.7.9.5

[U-Boot] [PATCH v5 13/28] net/phy/cortina: Fix compilation warning

[York Sun]

From: pankaj chauhan <pankaj.chauhan@freescale.com>

Fix comilation warning which is emitted when
firmware address is more than 32 bit.

Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/phy/cortina.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index 254f056..3a2b3bb 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -186,8 +186,8 @@ void cs4340_upload_firmware(struct phy_device *phydev)
 		while (*addr != 0x0a) {
 			line_temp[i++] = *addr++;
 			if (0x50 < i) {
-				printf("Not found Cortina PHY ucode at 0x%x\n",
-				       CONFIG_CORTINA_FW_ADDR);
+				printf("Not found Cortina PHY ucode@0x%p\n",
+				       (char *)CONFIG_CORTINA_FW_ADDR);
 				return;
 			}
 		}
-- 
1.7.9.5

[U-Boot] [PATCH v5 14/28] drivers/fsl-mc: Changed MC firmware loading for new boot architecture

[York Sun]

From: "J. German Rivera" <German.Rivera@freescale.com>

Changed MC firmware loading to comply with the new MC boot architecture.
Flush D-cache hierarchy after loading MC images. Add environment
variables "mcboottimeout" for MC boot timeout in milliseconds,
"mcmemsize" for MC DRAM block size. Check MC boot status before calling
flib functions.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/README |    8 +
 drivers/net/fsl-mc/mc.c             |  494 ++++++++++++++++++++++++++---------
 include/configs/ls2085a_common.h    |    6 +-
 include/configs/ls2085a_emu.h       |   13 +-
 include/configs/ls2085a_simu.h      |    5 +
 5 files changed, 395 insertions(+), 131 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README
index 99fc39a..f781620 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -33,3 +33,11 @@ is shown below considering a 32MB NOR flash device:
 	------------------------- ----> 0x0000_0000
 
 	32-MB NOR flash layout
+
+Environment Variables
+=====================
+mcboottimeout:	MC boot timeout in milliseconds. If this variable is not defined
+		the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+
+mcmemsize:	MC DRAM block size. If this variable is not defined, the value
+		CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 2a2b0af..c5c44bc 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -3,7 +3,6 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-
 #include <errno.h>
 #include <asm/io.h>
 #include <fsl-mc/fsl_mc.h>
@@ -15,14 +14,64 @@
 #include <fsl-mc/fsl_dpio.h>
 #include <fsl-mc/fsl_qbman_portal.h>
 
+#define MC_RAM_BASE_ADDR_ALIGNMENT  (512UL * 1024 * 1024)
+#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK	(~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
+#define MC_RAM_SIZE_ALIGNMENT	    (256UL * 1024 * 1024)
+
+#define MC_MEM_SIZE_ENV_VAR	"mcmemsize"
+#define MC_BOOT_TIMEOUT_ENV_VAR	"mcboottimeout"
+
 DECLARE_GLOBAL_DATA_PTR;
 static int mc_boot_status;
 struct fsl_mc_io *dflt_mc_io = NULL;
 uint16_t dflt_dprc_handle = 0;
 struct fsl_dpbp_obj *dflt_dpbp = NULL;
 struct fsl_dpio_obj *dflt_dpio = NULL;
-uint16_t dflt_dpio_handle = NULL;
+uint16_t dflt_dpio_handle = 0;
+
+#ifdef DEBUG
+void dump_ram_words(const char *title, void *addr)
+{
+	int i;
+	uint32_t *words = addr;
+
+	printf("Dumping beginning of %s (%p):\n", title, addr);
+	for (i = 0; i < 16; i++)
+		printf("%#x ", words[i]);
+
+	printf("\n");
+}
 
+void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs)
+{
+	printf("MC CCSR registers:\n"
+		"reg_gcr1 %#x\n"
+		"reg_gsr %#x\n"
+		"reg_sicbalr %#x\n"
+		"reg_sicbahr %#x\n"
+		"reg_sicapr %#x\n"
+		"reg_mcfbalr %#x\n"
+		"reg_mcfbahr %#x\n"
+		"reg_mcfapr %#x\n"
+		"reg_psr %#x\n",
+		mc_ccsr_regs->reg_gcr1,
+		mc_ccsr_regs->reg_gsr,
+		mc_ccsr_regs->reg_sicbalr,
+		mc_ccsr_regs->reg_sicbahr,
+		mc_ccsr_regs->reg_sicapr,
+		mc_ccsr_regs->reg_mcfbalr,
+		mc_ccsr_regs->reg_mcfbahr,
+		mc_ccsr_regs->reg_mcfapr,
+		mc_ccsr_regs->reg_psr);
+}
+#else
+
+#define dump_ram_words(title, addr)
+#define dump_mc_ccsr_regs(mc_ccsr_regs)
+
+#endif /* DEBUG */
+
+#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
 /**
  * Copying MC firmware or DPL image to DDR
  */
@@ -31,6 +80,7 @@ static int mc_copy_image(const char *title,
 {
 	debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
 	memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
+	flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size);
 	return 0;
 }
 
@@ -92,22 +142,254 @@ int parse_mc_firmware_fit_image(const void **raw_image_addr,
 
 	return 0;
 }
+#endif
+
+/*
+ * Calculates the values to be used to specify the address range
+ * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers.
+ * It returns the highest 512MB-aligned address within the given
+ * address range, in '*aligned_base_addr', and the number of 256 MiB
+ * blocks in it, in 'num_256mb_blocks'.
+ */
+static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr,
+					   size_t mc_ram_size,
+					   u64 *aligned_base_addr,
+					   u8 *num_256mb_blocks)
+{
+	u64 addr;
+	u16 num_blocks;
+
+	if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) {
+		printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
+		       mc_ram_size);
+		return -EINVAL;
+	}
+
+	num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
+	if (num_blocks < 1 || num_blocks > 0xff) {
+		printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
+		       mc_ram_size);
+		return -EINVAL;
+	}
+
+	addr = (mc_private_ram_start_addr + mc_ram_size - 1) &
+		MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
+
+	if (addr < mc_private_ram_start_addr) {
+		printf("fsl-mc: ERROR: bad start address %#llx\n",
+		       mc_private_ram_start_addr);
+		return -EFAULT;
+	}
+
+	*aligned_base_addr = addr;
+	*num_256mb_blocks = num_blocks;
+	return 0;
+}
+
+static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size)
+{
+	u64 mc_dpc_offset;
+#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
+	int error;
+	void *dpc_fdt_hdr;
+	int dpc_size;
+#endif
+
+#ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
+	BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
+		     CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
+
+	mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET;
+#else
+#error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
+#endif
+
+	/*
+	 * Load the MC DPC blob in the MC private DRAM block:
+	 */
+#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
+	printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset);
+#else
+	/*
+	 * Get address and size of the DPC blob stored in flash:
+	 */
+#ifdef CONFIG_SYS_LS_MC_DPC_IN_NOR
+	dpc_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPC_ADDR;
+#else
+#error "No CONFIG_SYS_LS_MC_DPC_IN_xxx defined"
+#endif
+
+	error = fdt_check_header(dpc_fdt_hdr);
+	if (error != 0) {
+		/*
+		 * Don't return with error here, since the MC firmware can
+		 * still boot without a DPC
+		 */
+		printf("fsl-mc: WARNING: No DPC image found\n");
+		return 0;
+	}
+
+	dpc_size = fdt_totalsize(dpc_fdt_hdr);
+	if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) {
+		printf("fsl-mc: ERROR: Bad DPC image (too large: %d)\n",
+		       dpc_size);
+		return -EINVAL;
+	}
+
+	mc_copy_image("MC DPC blob",
+		      (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset);
+#endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */
+
+	dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset));
+	return 0;
+}
+
+static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size)
+{
+	u64 mc_dpl_offset;
+#ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR
+	int error;
+	void *dpl_fdt_hdr;
+	int dpl_size;
+#endif
+
+#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
+	BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
+		     CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
+
+	mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
+#else
+#error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
+#endif
+
+	/*
+	 * Load the MC DPL blob in the MC private DRAM block:
+	 */
+#ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR
+	printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset);
+#else
+	/*
+	 * Get address and size of the DPL blob stored in flash:
+	 */
+#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
+	dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
+#else
+#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
+#endif
+
+	error = fdt_check_header(dpl_fdt_hdr);
+	if (error != 0) {
+		printf("fsl-mc: ERROR: Bad DPL image (bad header)\n");
+		return error;
+	}
+
+	dpl_size = fdt_totalsize(dpl_fdt_hdr);
+	if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
+		printf("fsl-mc: ERROR: Bad DPL image (too large: %d)\n",
+		       dpl_size);
+		return -EINVAL;
+	}
+
+	mc_copy_image("MC DPL blob",
+		      (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
+#endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */
+
+	dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset));
+	return 0;
+}
+
+/**
+ * Return the MC boot timeout value in milliseconds
+ */
+static unsigned long get_mc_boot_timeout_ms(void)
+{
+	unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
+
+	char *timeout_ms_env_var = getenv(MC_BOOT_TIMEOUT_ENV_VAR);
+
+	if (timeout_ms_env_var) {
+		timeout_ms = simple_strtoul(timeout_ms_env_var, NULL, 10);
+		if (timeout_ms == 0) {
+			printf("fsl-mc: WARNING: Invalid value for \'"
+			       MC_BOOT_TIMEOUT_ENV_VAR
+			       "\' environment variable: %lu\n",
+			       timeout_ms);
+
+			timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
+		}
+	}
+
+	return timeout_ms;
+}
+
+static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
+{
+	u32 reg_gsr;
+	u32 mc_fw_boot_status;
+	unsigned long timeout_ms = get_mc_boot_timeout_ms();
+	struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
+
+	dmb();
+	debug("Polling mc_ccsr_regs->reg_gsr ...\n");
+	assert(timeout_ms > 0);
+	for (;;) {
+		udelay(1000);	/* throttle polling */
+		reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
+		mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
+		if (mc_fw_boot_status & 0x1)
+			break;
+
+		timeout_ms--;
+		if (timeout_ms == 0)
+			break;
+	}
+
+	if (timeout_ms == 0) {
+		if (booting_mc)
+			printf("fsl-mc: timeout booting management complex firmware\n");
+		else
+			printf("fsl-mc: timeout deploying data path layout\n");
+
+		/* TODO: Get an error status from an MC CCSR register */
+		return -ETIMEDOUT;
+	}
+
+	if (mc_fw_boot_status != 0x1) {
+		/*
+		 * TODO: Identify critical errors from the GSR register's FS
+		 * field and for those errors, set error to -ENODEV or other
+		 * appropriate errno, so that the status property is set to
+		 * failure in the fsl,dprc device tree node.
+		 */
+		if (booting_mc) {
+			printf("fsl-mc: WARNING: Firmware booted with error (GSR: %#x)\n",
+			       reg_gsr);
+		} else {
+			printf("fsl-mc: WARNING: Data path layout deployed with error (GSR: %#x)\n",
+			       reg_gsr);
+		}
+	}
+
+	*final_reg_gsr = reg_gsr;
+	return 0;
+}
 
 int mc_init(void)
 {
 	int error = 0;
-	int timeout = 200000;
 	int portal_id = 0;
 	struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
 	u64 mc_ram_addr;
-	u64 mc_dpl_offset;
 	u32 reg_gsr;
-	u32 mc_fw_boot_status;
-	void *dpl_fdt_hdr;
-	int dpl_size;
+	u32 reg_mcfbalr;
+#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
 	const void *raw_image_addr;
 	size_t raw_image_size = 0;
+#endif
 	struct mc_version mc_ver_info;
+	u64 mc_ram_aligned_base_addr;
+	u8 mc_ram_num_256mb_blocks;
+	size_t mc_ram_size = mc_get_dram_block_size();
 
 	/*
 	 * The MC private DRAM block was already carved at the end of DRAM
@@ -122,8 +404,19 @@ int mc_init(void)
 	}
 
 #ifdef CONFIG_FSL_DEBUG_SERVER
+	/*
+	 * FIXME: I don't think this is right. See get_dram_size_to_hide()
+	 */
 		mc_ram_addr -= debug_server_get_dram_block_size();
 #endif
+
+	error = calculate_mc_private_ram_params(mc_ram_addr,
+						mc_ram_size,
+						&mc_ram_aligned_base_addr,
+						&mc_ram_num_256mb_blocks);
+	if (error != 0)
+		goto out;
+
 	/*
 	 * Management Complex cores should be held at reset out of POR.
 	 * U-boot should be the first software to touch MC. To be safe,
@@ -139,6 +432,9 @@ int mc_init(void)
 	out_le32(&mc_ccsr_regs->reg_gcr1, 0);
 	dmb();
 
+#ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
+	printf("MC firmware is preloaded to %#llx\n", mc_ram_addr);
+#else
 	error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size);
 	if (error != 0)
 		goto out;
@@ -147,83 +443,34 @@ int mc_init(void)
 	 */
 	mc_copy_image("MC Firmware",
 		      (u64)raw_image_addr, raw_image_size, mc_ram_addr);
-
-	/*
-	 * Get address and size of the DPL blob stored in flash:
-	 */
-#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
-	dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
-#else
-#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
 #endif
+	dump_ram_words("firmware", (void *)mc_ram_addr);
 
-	error = fdt_check_header(dpl_fdt_hdr);
-	if (error != 0) {
-		printf("fsl-mc: ERROR: Bad DPL image (bad header)\n");
-		goto out;
-	}
-
-	dpl_size = fdt_totalsize(dpl_fdt_hdr);
-	if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
-		printf("fsl-mc: ERROR: Bad DPL image (too large: %d)\n",
-		       dpl_size);
-		error = -EINVAL;
+	error = load_mc_dpc(mc_ram_addr, mc_ram_size);
+	if (error != 0)
 		goto out;
-	}
 
-	/*
-	 * Calculate offset in the MC private DRAM block at which the MC DPL
-	 * blob is to be placed:
-	 */
-#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
-	BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
-		     CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
-
-	mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
-#else
-	mc_dpl_offset = mc_get_dram_block_size() -
-			roundup(CONFIG_SYS_LS_MC_DPL_MAX_LENGTH, 4096);
-
-	if ((mc_dpl_offset & 0x3) != 0 || mc_dpl_offset > 0xffffffff) {
-		printf("%s: Invalid MC DPL offset: %llu\n",
-		       __func__, mc_dpl_offset);
-		error = -EINVAL;
+	error = load_mc_dpl(mc_ram_addr, mc_ram_size);
+	if (error != 0)
 		goto out;
-	}
-#endif
-
-	/*
-	 * Load the MC DPL blob at the far end of the MC private DRAM block:
-	 *
-	 * TODO: Should we place the DPL at a different location to match
-	 * assumptions of MC firmware about its memory layout?
-	 */
-	mc_copy_image("MC DPL blob",
-		      (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
 
 	debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
+	dump_mc_ccsr_regs(mc_ccsr_regs);
 
 	/*
-	 * Tell MC where the MC Firmware image was loaded in DDR:
+	 * Tell MC what is the address range of the DRAM block assigned to it:
 	 */
-	out_le32(&mc_ccsr_regs->reg_mcfbalr, (u32)mc_ram_addr);
-	out_le32(&mc_ccsr_regs->reg_mcfbahr, (u32)((u64)mc_ram_addr >> 32));
+	reg_mcfbalr = (u32)mc_ram_aligned_base_addr |
+		      (mc_ram_num_256mb_blocks - 1);
+	out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
+	out_le32(&mc_ccsr_regs->reg_mcfbahr,
+		 (u32)(mc_ram_aligned_base_addr >> 32));
 	out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK);
 
 	/*
-	 * Tell MC where the DPL blob was loaded in DDR, by indicating
-	 * its offset relative to the beginning of the DDR block
-	 * allocated to the MC firmware. The MC firmware is responsible
-	 * for checking that there is no overlap between the DPL blob
-	 * and the runtime heap and stack of the MC firmware itself.
-	 *
-	 * NOTE: bits [31:2] of this offset need to be stored in bits [29:0] of
-	 * the GSR MC CCSR register. So, this offset is assumed to be 4-byte
-	 * aligned.
-	 * Care must be taken not to write 1s into bits 31 and 30 of the GSR in
-	 * this case as the SoC COP or PIC will be signaled.
+	 * Tell the MC that we want delayed DPL deployment.
 	 */
-	out_le32(&mc_ccsr_regs->reg_gsr, (u32)(mc_dpl_offset >> 2));
+	out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00);
 
 	printf("\nfsl-mc: Booting Management Complex ...\n");
 
@@ -231,38 +478,9 @@ int mc_init(void)
 	 * Deassert reset and release MC core 0 to run
 	 */
 	out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
-	dmb();
-	debug("Polling mc_ccsr_regs->reg_gsr ...\n");
-
-	for (;;) {
-		reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
-		mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
-		if (mc_fw_boot_status & 0x1)
-			break;
-
-		udelay(1000);	/* throttle polling */
-		if (timeout-- <= 0)
-			break;
-	}
-
-	if (timeout <= 0) {
-		printf("fsl-mc: timeout booting management complex firmware\n");
-
-		/* TODO: Get an error status from an MC CCSR register */
-		error = -ETIMEDOUT;
+	error = wait_for_mc(true, &reg_gsr);
+	if (error != 0)
 		goto out;
-	}
-
-	if (mc_fw_boot_status != 0x1) {
-		/*
-		 * TODO: Identify critical errors from the GSR register's FS
-		 * field and for those errors, set error to -ENODEV or other
-		 * appropriate errno, so that the status property is set to
-		 * failure in the fsl,dprc device tree node.
-		 */
-		printf("fsl-mc: WARNING: Firmware booted with error (GSR: %#x)\n",
-		       reg_gsr);
-	}
 
 	/*
 	 * TODO: need to obtain the portal_id for the root container from the
@@ -301,7 +519,16 @@ int mc_init(void)
 
 	printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
 	       mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
-	       mc_fw_boot_status);
+	       reg_gsr & GSR_FS_MASK);
+
+	/*
+	 * Tell the MC to deploy the DPL:
+	 */
+	out_le32(&mc_ccsr_regs->reg_gsr, 0x0);
+	printf("\nfsl-mc: Deploying data path layout ...\n");
+	error = wait_for_mc(false, &reg_gsr);
+	if (error != 0)
+		goto out;
 out:
 	if (error != 0)
 		mc_boot_status = -error;
@@ -318,14 +545,28 @@ int get_mc_boot_status(void)
 
 /**
  * Return the actual size of the MC private DRAM block.
- *
- * NOTE: For now this function always returns the minimum required size,
- * However, in the future, the actual size may be obtained from an environment
- * variable.
  */
 unsigned long mc_get_dram_block_size(void)
 {
-	return CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+	unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+
+	char *dram_block_size_env_var = getenv(MC_MEM_SIZE_ENV_VAR);
+
+	if (dram_block_size_env_var) {
+		dram_block_size = simple_strtoul(dram_block_size_env_var, NULL,
+						 10);
+
+		if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
+			printf("fsl-mc: WARNING: Invalid value for \'"
+			       MC_MEM_SIZE_ENV_VAR
+			       "\' environment variable: %lu\n",
+			       dram_block_size);
+
+			dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+		}
+	}
+
+	return dram_block_size;
 }
 
 int dpio_init(struct dprc_obj_desc obj_desc)
@@ -464,6 +705,8 @@ int fsl_mc_ldpaa_init(bd_t *bis)
 	int num_child_objects = 0;
 
 	error = mc_init();
+	if (error < 0)
+		goto error;
 
 	error = dprc_get_container_id(dflt_mc_io, &container_id);
 	if (error < 0) {
@@ -517,24 +760,27 @@ void fsl_mc_ldpaa_exit(bd_t *bis)
 {
 	int err;
 
+	if (get_mc_boot_status() == 0) {
+		err = dpio_disable(dflt_mc_io, dflt_dpio_handle);
+		if (err < 0) {
+			printf("dpio_disable() failed: %d\n", err);
+			return;
+		}
+		err = dpio_reset(dflt_mc_io, dflt_dpio_handle);
+		if (err < 0) {
+			printf("dpio_reset() failed: %d\n", err);
+			return;
+		}
+		err = dpio_close(dflt_mc_io, dflt_dpio_handle);
+		if (err < 0) {
+			printf("dpio_close() failed: %d\n", err);
+			return;
+		}
 
-	err = dpio_disable(dflt_mc_io, dflt_dpio_handle);
-	if (err < 0) {
-		printf("dpio_disable() failed: %d\n", err);
-		return;
-	}
-	err = dpio_reset(dflt_mc_io, dflt_dpio_handle);
-	if (err < 0) {
-		printf("dpio_reset() failed: %d\n", err);
-		return;
-	}
-	err = dpio_close(dflt_mc_io, dflt_dpio_handle);
-	if (err < 0) {
-		printf("dpio_close() failed: %d\n", err);
-		return;
+		free(dflt_dpio);
+		free(dflt_dpbp);
 	}
 
-	free(dflt_dpio);
-	free(dflt_dpbp);
-	free(dflt_mc_io);
+	if (dflt_mc_io)
+		free(dflt_mc_io);
 }
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 5ce5e1c..4b68106 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -138,8 +138,10 @@
 #define CONFIG_FSL_MC_ENET
 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH		(256 * 1024)
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET	0xe00000
+#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
 
 /* Carve out a DDR region which will not be used by u-boot/Linux */
 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h
index 961dc63..2d68e1b 100644
--- a/include/configs/ls2085a_emu.h
+++ b/include/configs/ls2085a_emu.h
@@ -72,12 +72,15 @@
 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580C00000ULL
 
-/* MC firmware */
-#define CONFIG_SYS_LS_MC_FW_IN_NOR
-#define CONFIG_SYS_LS_MC_FW_ADDR	0x580200000ULL
+/*
+ * This trick allows users to load MC images into DDR directly without
+ * copying from NOR flash. It dramatically improves speed.
+ */
+#define CONFIG_SYS_LS_MC_FW_IN_DDR
+#define CONFIG_SYS_LS_MC_DPL_IN_DDR
+#define CONFIG_SYS_LS_MC_DPC_IN_DDR
 
-#define CONFIG_SYS_LS_MC_DPL_IN_NOR
-#define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
 
 /* Store environment at top of flash */
 #define CONFIG_ENV_IS_NOWHERE		1
diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h
index e669d8d..d0d2eed 100644
--- a/include/configs/ls2085a_simu.h
+++ b/include/configs/ls2085a_simu.h
@@ -138,6 +138,11 @@
 #define CONFIG_SYS_LS_MC_DPL_IN_NOR
 #define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL
 
+#define CONFIG_SYS_LS_MC_DPC_IN_NOR
+#define CONFIG_SYS_LS_MC_DPC_ADDR	0x5806F8000ULL
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
+
 /* Store environment@top of flash */
 #define CONFIG_ENV_IS_NOWHERE		1
 #define CONFIG_ENV_SIZE			0x1000
-- 
1.7.9.5

[U-Boot] [PATCH v5 15/28] net/memac_phy: reuse driver for little endian SoCs

[York Sun]

From: Shaohui Xie <Shaohui.Xie@freescale.com>

The memac for PHY management on little endian SoCs is similar on big
endian SoCs, so we modify the driver by using I/O accessor function to
handle the endianness, so the driver can be reused on little endian
SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian
SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access
is little endian, if not, the I/O access is big endian. Move fsl_memac.h
out of powerpc include.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/include/asm/arch-fsl-lsch3/config.h      |    1 +
 drivers/net/Makefile                              |    1 +
 drivers/net/fm/eth.c                              |    2 +-
 drivers/net/fm/memac.c                            |    2 +-
 drivers/net/fm/memac_phy.c                        |   62 ++++++++++++++-------
 drivers/net/vsc9953.c                             |    2 +-
 {arch/powerpc/include/asm => include}/fsl_memac.h |    0
 7 files changed, 46 insertions(+), 24 deletions(-)
 rename {arch/powerpc/include/asm => include}/fsl_memac.h (100%)

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 98db1ef..684c70f 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -109,6 +109,7 @@
 
 /* IFC */
 #define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 
 /* PCIe */
 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 5497934..d871093 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -66,4 +66,5 @@ obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
 obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
 obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
 obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
+obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
 obj-$(CONFIG_VSC9953) += vsc9953.o
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 1d1089d..a7a5c69 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -15,7 +15,7 @@
 #include <phy.h>
 #include <asm/fsl_dtsec.h>
 #include <asm/fsl_tgec.h>
-#include <asm/fsl_memac.h>
+#include <fsl_memac.h>
 
 #include "fm.h"
 
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 60e898c..81a64bf 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -12,7 +12,7 @@
 #include <phy.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_memac.h>
+#include <fsl_memac.h>
 
 #include "fm.h"
 
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index a155d89..4ab78e6 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -10,9 +10,28 @@
 #include <miiphy.h>
 #include <phy.h>
 #include <asm/io.h>
-#include <asm/fsl_memac.h>
+#include <fsl_memac.h>
 #include <fm_eth.h>
 
+#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+#define memac_out_32(a, v)	out_le32(a, v)
+#define memac_clrbits_32(a, v)	clrbits_le32(a, v)
+#define memac_setbits_32(a, v)	setbits_le32(a, v)
+#else
+#define memac_out_32(a, v)	out_be32(a, v)
+#define memac_clrbits_32(a, v)	clrbits_be32(a, v)
+#define memac_setbits_32(a, v)	setbits_be32(a, v)
+#endif
+
+static u32 memac_in_32(u32 *reg)
+{
+#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+	return in_le32(reg);
+#else
+	return in_be32(reg);
+#endif
+}
+
 /*
  * Write value to the PHY for this device to the register at regnum, waiting
  * until the write is done before it returns.  All PHY configuration has to be
@@ -28,31 +47,31 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
 	if (dev_addr == MDIO_DEVAD_NONE) {
 		c45 = 0; /* clause 22 */
 		dev_addr = regnum & 0x1f;
-		clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
+		memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
 	} else
-		setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
+		memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
 
 	/* Wait till the bus is free */
-	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
+	while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
 		;
 
 	/* Set the port and dev addr */
 	mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
-	out_be32(&regs->mdio_ctl, mdio_ctl);
+	memac_out_32(&regs->mdio_ctl, mdio_ctl);
 
 	/* Set the register address */
 	if (c45)
-		out_be32(&regs->mdio_addr, regnum & 0xffff);
+		memac_out_32(&regs->mdio_addr, regnum & 0xffff);
 
 	/* Wait till the bus is free */
-	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
+	while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
 		;
 
 	/* Write the value to the register */
-	out_be32(&regs->mdio_data, MDIO_DATA(value));
+	memac_out_32(&regs->mdio_data, MDIO_DATA(value));
 
 	/* Wait till the MDIO write is complete */
-	while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
+	while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
 		;
 
 	return 0;
@@ -75,39 +94,39 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
 			return 0xffff;
 		c45 = 0; /* clause 22 */
 		dev_addr = regnum & 0x1f;
-		clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
+		memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
 	} else
-		setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
+		memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
 
 	/* Wait till the bus is free */
-	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
+	while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
 		;
 
 	/* Set the Port and Device Addrs */
 	mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
-	out_be32(&regs->mdio_ctl, mdio_ctl);
+	memac_out_32(&regs->mdio_ctl, mdio_ctl);
 
 	/* Set the register address */
 	if (c45)
-		out_be32(&regs->mdio_addr, regnum & 0xffff);
+		memac_out_32(&regs->mdio_addr, regnum & 0xffff);
 
 	/* Wait till the bus is free */
-	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
+	while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
 		;
 
 	/* Initiate the read */
 	mdio_ctl |= MDIO_CTL_READ;
-	out_be32(&regs->mdio_ctl, mdio_ctl);
+	memac_out_32(&regs->mdio_ctl, mdio_ctl);
 
 	/* Wait till the MDIO write is complete */
-	while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
+	while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
 		;
 
 	/* Return all Fs if nothing was there */
-	if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
+	if (memac_in_32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
 		return 0xffff;
 
-	return in_be32(&regs->mdio_data) & 0xffff;
+	return memac_in_32(&regs->mdio_data) & 0xffff;
 }
 
 int memac_mdio_reset(struct mii_dev *bus)
@@ -143,8 +162,9 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
 	 * like T2080QDS, this bit default is '0', which leads to MDIO failure
 	 * on XAUI PHY, so set this bit definitely.
 	 */
-	setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
-		     MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
+	memac_setbits_32(
+		&((struct memac_mdio_controller *)info->regs)->mdio_stat,
+		MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
 
 	return mdio_register(bus);
 }
diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c
index 9fc3c18..fed7358 100644
--- a/drivers/net/vsc9953.c
+++ b/drivers/net/vsc9953.c
@@ -9,7 +9,7 @@
 #include <asm/io.h>
 #include <asm/fsl_serdes.h>
 #include <fm_eth.h>
-#include <asm/fsl_memac.h>
+#include <fsl_memac.h>
 #include <vsc9953.h>
 
 static struct vsc9953_info vsc9953_l2sw = {
diff --git a/arch/powerpc/include/asm/fsl_memac.h b/include/fsl_memac.h
similarity index 100%
rename from arch/powerpc/include/asm/fsl_memac.h
rename to include/fsl_memac.h
-- 
1.7.9.5

[U-Boot] [PATCH v5 16/28] armv8/fsl-ch3: Add support to print RCW configuration

[York Sun]

From: Bhupesh Sharma <bhupesh.sharma@freescale.com>

This patch adds support to print out the Reset Configuration Word
information.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/cpu.c |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index caa48f2..07064a3 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -371,6 +371,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	struct sys_info sysinfo;
 	char buf[32];
 	unsigned int i, core;
@@ -394,6 +395,19 @@ int print_cpuinfo(void)
 	printf("     DP-DDR:   %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2));
 	puts("\n");
 
+	/* Display the RCW, so that no one gets confused as to what RCW
+	 * we're actually using for this boot.
+	 */
+	puts("Reset Configuration Word (RCW):");
+	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+		u32 rcw = in_le32(&gur->rcwsr[i]);
+
+		if ((i % 4) == 0)
+			printf("\n       %02x:", i * 4);
+		printf(" %08x", rcw);
+	}
+	puts("\n");
+
 	return 0;
 }
 #endif
-- 
1.7.9.5

[U-Boot] [PATCH v5 17/28] armv8/fsl-lsch3: Enable system error aborts

[York Sun]

From: Scott Wood <scottwood@freescale.com>

This lets us see the problems (close to) when they happen,
rather than Linux hanging when it enables them prior to having a
working console.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/cpu.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 07064a3..22b5fb2 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -263,6 +263,10 @@ int arch_cpu_init(void)
 	__asm_invalidate_tlb_all();
 	early_mmu_setup();
 	set_sctlr(get_sctlr() | CR_C);
+
+	/* Enable system error aborts */
+	asm volatile("msr daifclr, #4" : : : "memory");
+
 	return 0;
 }
 
-- 
1.7.9.5

[U-Boot] [PATCH v5 18/28] driver/ldpaa: Add support of WRIOP static data structure

[York Sun]

From: Prabhakar Kushwaha <prabhakar@freescale.com>

Wire rate IO Processor (WRIOP) provide support of receive and transmit
ethernet frames from the ethernet MAC.  Here Each WRIOP block supports
upto 64 DPMACs.

Create a house keeping data structure to support upto 16 DPMACs and
store external phy related information.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c   |    7 +-
 arch/arm/include/asm/arch-fsl-lsch3/config.h      |    3 +
 arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h |   24 ++++
 drivers/net/ldpaa_eth/Makefile                    |    2 +-
 drivers/net/ldpaa_eth/ldpaa_eth.h                 |    4 -
 drivers/net/ldpaa_eth/ldpaa_wriop.c               |  146 +++++++++++++++++++++
 include/fsl-mc/ldpaa_wriop.h                      |   70 ++++++++++
 7 files changed, 250 insertions(+), 6 deletions(-)
 create mode 100644 drivers/net/ldpaa_eth/ldpaa_wriop.c
 create mode 100644 include/fsl-mc/ldpaa_wriop.h

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
index 78b9210..02ca126 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
@@ -9,6 +9,7 @@
 #include <asm/errno.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl-mc/ldpaa_wriop.h>
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
@@ -86,8 +87,12 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
 		if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
 			debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
-		else
+		else {
 			serdes_prtcl_map[lane_prtcl] = 1;
+#ifdef CONFIG_FSL_MC_ENET
+			wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl);
+#endif
+		}
 	}
 }
 
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 684c70f..403b2ef 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -38,6 +38,9 @@
 #define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
 						 0x18A0)
 
+#define CONFIG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO1	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO2	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR	(CONFIG_SYS_IMMR + 0xEA0000)
 
 /* SP (Cortex-A5) related */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
index 91cf68b..d6bee60 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -47,6 +47,30 @@ struct ccsr_gur {
 	u32	devdisr5;	/* Device disable control 5 */
 	u32	devdisr6;	/* Device disable control 6 */
 	u32	devdisr7;	/* Device disable control 7 */
+#define FSL_CHASSIS3_DEVDISR2_DPMAC1	0x00000001
+#define FSL_CHASSIS3_DEVDISR2_DPMAC2	0x00000002
+#define FSL_CHASSIS3_DEVDISR2_DPMAC3	0x00000004
+#define FSL_CHASSIS3_DEVDISR2_DPMAC4	0x00000008
+#define FSL_CHASSIS3_DEVDISR2_DPMAC5	0x00000010
+#define FSL_CHASSIS3_DEVDISR2_DPMAC6	0x00000020
+#define FSL_CHASSIS3_DEVDISR2_DPMAC7	0x00000040
+#define FSL_CHASSIS3_DEVDISR2_DPMAC8	0x00000080
+#define FSL_CHASSIS3_DEVDISR2_DPMAC9	0x00000100
+#define FSL_CHASSIS3_DEVDISR2_DPMAC10	0x00000200
+#define FSL_CHASSIS3_DEVDISR2_DPMAC11	0x00000400
+#define FSL_CHASSIS3_DEVDISR2_DPMAC12	0x00000800
+#define FSL_CHASSIS3_DEVDISR2_DPMAC13	0x00001000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC14	0x00002000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC15	0x00004000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC16	0x00008000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC17	0x00010000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC18	0x00020000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC19	0x00040000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC20	0x00080000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC21	0x00100000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC22	0x00200000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC23	0x00400000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC24	0x00800000
 	u8	res_08c[0x90-0x8c];
 	u32	coredisru;	/* uppper portion for support of 64 cores */
 	u32	coredisrl;	/* lower portion for support of 64 cores */
diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile
index 3b1a60b..d32d67e 100644
--- a/drivers/net/ldpaa_eth/Makefile
+++ b/drivers/net/ldpaa_eth/Makefile
@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-# Layerscape LDPAA driver
+obj-y += ldpaa_wriop.o
 obj-y += ldpaa_eth.o
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h
index c7760ef..3107ab6 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.h
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.h
@@ -132,11 +132,7 @@ struct ldpaa_eth_priv {
 	uint16_t tx_flow_id;
 
 	enum ldpaa_eth_type type;	/* 1G or 10G ethernet */
-	phy_interface_t enet_if;
-	struct mii_dev *bus;
 	struct phy_device *phydev;
-	int phyaddr;
-
 };
 
 extern struct fsl_mc_io *dflt_mc_io;
diff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c
new file mode 100644
index 0000000..926057a
--- /dev/null
+++ b/drivers/net/ldpaa_eth/ldpaa_wriop.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <malloc.h>
+#include <net.h>
+#include <linux/compat.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
+
+__weak phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtc)
+{
+	return PHY_INTERFACE_MODE_NONE;
+}
+
+void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
+{
+	phy_interface_t enet_if;
+	int index = dpmac_id + sd * 8;
+
+	dpmac_info[index].enabled = 0;
+	dpmac_info[index].id = 0;
+	dpmac_info[index].enet_if = PHY_INTERFACE_MODE_NONE;
+
+	enet_if = wriop_dpmac_enet_if(index, lane_prtcl);
+	if (enet_if != PHY_INTERFACE_MODE_NONE) {
+		dpmac_info[index].enabled = 1;
+		dpmac_info[index].id = index;
+		dpmac_info[index].enet_if = enet_if;
+	}
+}
+
+/*TODO what it do */
+static int wriop_dpmac_to_index(int dpmac_id)
+{
+	int i;
+
+	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+		if (dpmac_info[i].id == dpmac_id)
+			return i;
+	}
+
+	return -1;
+}
+
+void wriop_disable_dpmac(int dpmac_id)
+{
+	int i = wriop_dpmac_to_index(dpmac_id);
+
+	if (i == -1)
+		return;
+
+	dpmac_info[i].enabled = 0;
+	wriop_dpmac_disable(dpmac_id);
+}
+
+void wriop_enable_dpmac(int dpmac_id)
+{
+	int i = wriop_dpmac_to_index(dpmac_id);
+
+	if (i == -1)
+		return;
+
+	dpmac_info[i].enabled = 1;
+	wriop_dpmac_enable(dpmac_id);
+}
+
+void wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
+{
+	int i = wriop_dpmac_to_index(dpmac_id);
+
+	if (i == -1)
+		return;
+
+	dpmac_info[i].bus = bus;
+}
+
+struct mii_dev *wriop_get_mdio(int dpmac_id)
+{
+	int i = wriop_dpmac_to_index(dpmac_id);
+
+	if (i == -1)
+		return NULL;
+
+	return dpmac_info[i].bus;
+}
+
+void wriop_set_phy_address(int dpmac_id, int address)
+{
+	int i = wriop_dpmac_to_index(dpmac_id);
+
+	if (i == -1)
+		return;
+
+	dpmac_info[i].phy_addr = address;
+}
+
+int wriop_get_phy_address(int dpmac_id)
+{
+	int i = wriop_dpmac_to_index(dpmac_id);
+
+	if (i == -1)
+		return -1;
+
+	return dpmac_info[i].phy_addr;
+}
+
+void wriop_set_phy_dev(int dpmac_id, struct phy_device *phydev)
+{
+	int i = wriop_dpmac_to_index(dpmac_id);
+
+	if (i == -1)
+		return;
+
+	dpmac_info[i].phydev = phydev;
+}
+
+struct phy_device *wriop_get_phy_dev(int dpmac_id)
+{
+	int i = wriop_dpmac_to_index(dpmac_id);
+
+	if (i == -1)
+		return NULL;
+
+	return dpmac_info[i].phydev;
+}
+
+phy_interface_t wriop_get_enet_if(int dpmac_id)
+{
+	int i = wriop_dpmac_to_index(dpmac_id);
+
+	if (i == -1)
+		return PHY_INTERFACE_MODE_NONE;
+
+	if (dpmac_info[i].enabled)
+		return dpmac_info[i].enet_if;
+
+	return PHY_INTERFACE_MODE_NONE;
+}
diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h
new file mode 100644
index 0000000..ca8e440
--- /dev/null
+++ b/include/fsl-mc/ldpaa_wriop.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LDPAA_WRIOP_H
+#define __LDPAA_WRIOP_H
+
+ #include <phy.h>
+
+enum wriop_port {
+	WRIOP1_DPMAC1 = 1,
+	WRIOP1_DPMAC2,
+	WRIOP1_DPMAC3,
+	WRIOP1_DPMAC4,
+	WRIOP1_DPMAC5,
+	WRIOP1_DPMAC6,
+	WRIOP1_DPMAC7,
+	WRIOP1_DPMAC8,
+	WRIOP1_DPMAC9,
+	WRIOP1_DPMAC10,
+	WRIOP1_DPMAC11,
+	WRIOP1_DPMAC12,
+	WRIOP1_DPMAC13,
+	WRIOP1_DPMAC14,
+	WRIOP1_DPMAC15,
+	WRIOP1_DPMAC16,
+	WRIOP1_DPMAC17,
+	WRIOP1_DPMAC18,
+	WRIOP1_DPMAC19,
+	WRIOP1_DPMAC20,
+	WRIOP1_DPMAC21,
+	WRIOP1_DPMAC22,
+	WRIOP1_DPMAC23,
+	WRIOP1_DPMAC24,
+	NUM_WRIOP_PORTS,
+};
+
+struct wriop_dpmac_info {
+	u8 enabled;
+	u8 id;
+	u8 phy_addr;
+	u8 board_mux;
+	void *phy_regs;
+	phy_interface_t enet_if;
+	struct phy_device *phydev;
+	struct mii_dev *bus;
+};
+
+extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
+
+#define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0"
+#define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1"
+
+void wriop_init_dpmac(int, int, int);
+void wriop_disable_dpmac(int);
+void wriop_enable_dpmac(int);
+void wriop_set_mdio(int, struct mii_dev *);
+struct mii_dev *wriop_get_mdio(int);
+void wriop_set_phy_address(int, int);
+int wriop_get_phy_address(int);
+void wriop_set_phy_dev(int, struct phy_device *);
+struct phy_device *wriop_get_phy_dev(int);
+phy_interface_t wriop_get_enet_if(int);
+
+void wriop_dpmac_disable(int);
+void wriop_dpmac_enable(int);
+phy_interface_t wriop_dpmac_enet_if(int, int);
+#endif	/* __LDPAA_WRIOP_H */
-- 
1.7.9.5

[U-Boot] [PATCH v5 19/28] armv8/ls2085aqds: Add support of LS2085AQDS platform

[York Sun]

The LS2085AQDS is an evaluatoin platform that supports the LS2085A
family SoCs. This patch add basic support of the platform.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>

---

Changes in v5:
  Fix board README for inconsistent SoC name
  Fix comment in board header file
  s/LS2080/LS2085/g

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/Kconfig                              |   11 +
 arch/arm/cpu/armv8/fsl-lsch3/README           |   70 +++++-
 board/freescale/ls2085aqds/Kconfig            |   16 ++
 board/freescale/ls2085aqds/MAINTAINERS        |    7 +
 board/freescale/ls2085aqds/Makefile           |    8 +
 board/freescale/ls2085aqds/README             |  129 +++++++++++
 board/freescale/ls2085aqds/ddr.c              |  192 +++++++++++++++++
 board/freescale/ls2085aqds/ddr.h              |   92 ++++++++
 board/freescale/ls2085aqds/ls2085aqds.c       |  287 +++++++++++++++++++++++++
 board/freescale/ls2085aqds/ls2085aqds_qixis.h |   26 +++
 configs/ls2085aqds_defconfig                  |    3 +
 include/configs/ls2085a_common.h              |   38 +++-
 include/configs/ls2085aqds.h                  |  283 ++++++++++++++++++++++++
 include/fsl_ddr_sdram.h                       |    1 +
 14 files changed, 1148 insertions(+), 15 deletions(-)
 create mode 100644 board/freescale/ls2085aqds/Kconfig
 create mode 100644 board/freescale/ls2085aqds/MAINTAINERS
 create mode 100644 board/freescale/ls2085aqds/Makefile
 create mode 100644 board/freescale/ls2085aqds/README
 create mode 100644 board/freescale/ls2085aqds/ddr.c
 create mode 100644 board/freescale/ls2085aqds/ddr.h
 create mode 100644 board/freescale/ls2085aqds/ls2085aqds.c
 create mode 100644 board/freescale/ls2085aqds/ls2085aqds_qixis.h
 create mode 100644 configs/ls2085aqds_defconfig
 create mode 100644 include/configs/ls2085aqds.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b9ebee1..f4a7851 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -648,6 +648,16 @@ config TARGET_LS2085A_SIMU
 	select ARM64
 	select ARMV8_MULTIENTRY
 
+config TARGET_LS2085AQDS
+	bool "Support ls2085aqds"
+	select ARM64
+	select ARMV8_MULTIENTRY
+	help
+	  Support for Freescale LS2085AQDS platform
+	  The LS2085A Development System (QDS) is a high-performance
+	  development platform that supports the QorIQ LS2085A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
@@ -793,6 +803,7 @@ source "board/denx/m53evk/Kconfig"
 source "board/embest/mx6boards/Kconfig"
 source "board/esg/ima3-mx53/Kconfig"
 source "board/freescale/ls2085a/Kconfig"
+source "board/freescale/ls2085aqds/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README
index f781620..817ea1b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -11,28 +11,82 @@ for example LS2085A.
 
 Flash Layout
 ============
-A typical layout of various images (including Linux and other firmware images)
-is shown below considering a 32MB NOR flash device:
+
+(1) A typical layout of various images (including Linux and other firmware images)
+   is shown below considering a 32MB NOR flash device present on most
+   pre-silicon platforms (simulator and emulator):
 
 	-------------------------
-	|	linux		|
+	| 	FIT Image	|
+	| (linux + DTB + RFS)	|
 	------------------------- ----> 0x0120_0000
-	|	Debug Server 	|
+	| 	Debug Server FW |
 	------------------------- ----> 0x00C0_0000
-	|	AIOP SW 	|
+	|	AIOP FW 	|
 	------------------------- ----> 0x0070_0000
 	|	MC FW 		|
 	------------------------- ----> 0x006C_0000
-	| MC Data Path Layout 	|
+	| 	MC DPL Blob 	|
 	------------------------- ----> 0x0020_0000
-	|	BootLoader 	|
+	| 	BootLoader + Env|
 	------------------------- ----> 0x0000_1000
 	|	PBI 		|
 	------------------------- ----> 0x0000_0080
 	|	RCW 		|
 	------------------------- ----> 0x0000_0000
 
-	32-MB NOR flash layout
+	32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
+
+(2) A typical layout of various images (including Linux and other firmware images)
+    is shown below considering a 128MB NOR flash device present on QDS
+    boards:
+	----------------------------------------- ----> 0x5_8800_0000 ---
+	|	.. Unused .. (7M)		|			|
+	----------------------------------------- ----> 0x5_8790_0000	|
+	| FIT Image (linux + DTB + RFS)	(40M)	|			|
+	----------------------------------------- ----> 0x5_8510_0000	|
+	|	PHY firmware (2M)	 	|			|
+	----------------------------------------- ----> 0x5_84F0_0000	| 64K
+	|	Debug Server FW (2M)		|			| Alt
+	----------------------------------------- ----> 0x5_84D0_0000	| Bank
+	|	AIOP FW (4M)			|			|
+	----------------------------------------- ----> 0x5_8490_0000 (vbank4)
+	|	MC DPC Blob (1M) 		|			|
+	----------------------------------------- ----> 0x5_8480_0000	|
+	|	MC DPL Blob (1M)		|			|
+	----------------------------------------- ----> 0x5_8470_0000	|
+	| 	MC FW (4M)			|			|
+	----------------------------------------- ----> 0x5_8430_0000	|
+	|	BootLoader Environment (1M) 	|			|
+	----------------------------------------- ----> 0x5_8420_0000	|
+	|	BootLoader (1M)			|			|
+	----------------------------------------- ----> 0x5_8410_0000	|
+	|	RCW and PBI (1M) 		|			|
+	----------------------------------------- ----> 0x5_8400_0000 ---
+	|	.. Unused .. (7M)		|			|
+	----------------------------------------- ----> 0x5_8390_0000	|
+	| FIT Image (linux + DTB + RFS)	(40M)	|			|
+	----------------------------------------- ----> 0x5_8110_0000	|
+	|	PHY firmware (2M)	 	|			|
+	----------------------------------------- ----> 0x5_80F0_0000	| 64K
+	|	Debug Server FW (2M)		|			| Bank
+	----------------------------------------- ----> 0x5_80D0_0000	|
+	|	AIOP FW (4M)			|			|
+	----------------------------------------- ----> 0x5_8090_0000 (vbank0)
+	|	MC DPC Blob (1M) 		|			|
+	----------------------------------------- ----> 0x5_8080_0000	|
+	|	MC DPL Blob (1M)		|			|
+	----------------------------------------- ----> 0x5_8070_0000	|
+	| 	MC FW (4M)			|			|
+	----------------------------------------- ----> 0x5_8030_0000	|
+	|	BootLoader Environment (1M) 	|			|
+	----------------------------------------- ----> 0x5_8020_0000	|
+	|	BootLoader (1M)			|			|
+	----------------------------------------- ----> 0x5_8010_0000	|
+	|	RCW and PBI (1M) 		|			|
+	----------------------------------------- ----> 0x5_8000_0000 ---
+
+	128-MB NOR flash layout for QDS board
 
 Environment Variables
 =====================
diff --git a/board/freescale/ls2085aqds/Kconfig b/board/freescale/ls2085aqds/Kconfig
new file mode 100644
index 0000000..deb640d
--- /dev/null
+++ b/board/freescale/ls2085aqds/Kconfig
@@ -0,0 +1,16 @@
+
+if TARGET_LS2085AQDS
+
+config SYS_BOARD
+	default "ls2085aqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-lsch3"
+
+config SYS_CONFIG_NAME
+	default "ls2085aqds"
+
+endif
diff --git a/board/freescale/ls2085aqds/MAINTAINERS b/board/freescale/ls2085aqds/MAINTAINERS
new file mode 100644
index 0000000..74b3721
--- /dev/null
+++ b/board/freescale/ls2085aqds/MAINTAINERS
@@ -0,0 +1,7 @@
+LS2085A BOARD
+M:	Prabhakar Kushwaha <prabhakar@freescale.com>
+S:	Maintained
+F:	board/freescale/ls2085aqds/
+F:	board/freescale/ls2085a/ls2085aqds.c
+F:	include/configs/ls2085aqds.h
+F:	configs/ls2085aqds_defconfig
diff --git a/board/freescale/ls2085aqds/Makefile b/board/freescale/ls2085aqds/Makefile
new file mode 100644
index 0000000..f174f33
--- /dev/null
+++ b/board/freescale/ls2085aqds/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ls2085aqds.o
+obj-y += ddr.o
diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085aqds/README
new file mode 100644
index 0000000..fb3938e
--- /dev/null
+++ b/board/freescale/ls2085aqds/README
@@ -0,0 +1,129 @@
+Overview
+--------
+The LS2085A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2085A
+Layerscape Architecture processor. The LS2085AQDS provides validation and
+SW development platform for the Freescale LS2085A processor series, with
+a complete debugging environment.
+
+LS2085A SoC Overview
+------------------
+The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2085A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A57 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+  the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+   - Packet parsing, classification, and distribution (WRIOP)
+   - Queue and Hardware buffer management for scheduling, packet sequencing, and
+     congestion management, buffer allocation and de-allocation (QBMan)
+   - Cryptography acceleration (SEC) at up to 10 Gbps
+   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+   - Decompression/compression acceleration (DCE) at up to 20 Gbps
+   - Accelerated I/O processing (AIOP) at up to 20 Gbps
+   - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+   - Up to eight 10 Gbps Ethernet MACs
+   - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+   - Two serial ATA (SATA 3.0) controllers
+   - Two high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Serial peripheral interface (SPI) controller
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+  capabilities
+
+ LS2085AQDS board Overview
+ -----------------------
+ - SERDES Connections, 16 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - QSGMII
+      - SATA 3.0
+      - XAUI
+      - XFI
+ - DDR Controller
+     - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
+       chip-selects and two DIMM connectors. Support is up to 2133MT/s.
+     - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
+       and two DIMM connectors. Support is up to 1600MT/s.
+ -IFC/Local Bus
+    - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
+    - One in-socket 128 MB NOR flash 16-bit data bus
+    - One 512 MB NAND flash with ECC support
+    - IFC Test Port
+    - PromJet Port
+    - FPGA connection
+ - USB 3.0
+    - Two high speed USB 3.0 ports
+    - First USB 3.0 port configured as Host with Type-A connector
+    - Second USB 3.0 port configured as OTG with micro-AB connector
+ - SDHC: PCIe x1 Right Angle connector for supporting following cards
+    - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only
+    - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only
+    - 4-bit eMMC Card Rev 4.4 (1.8V only)
+    - 8-bit eMMC Card Rev 4.5 (1.8V only)
+    - SD Card Rev 2.0 and Rev 3.0
+ - DSPI: 3 high-speed flash Memory for storage
+    - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
+    - 8 MB high-speed flash Memory (up to 104 MHz)
+    - 512 MB low-speed flash Memory (up to 40 MHz)
+ - QSPI: via NAND/QSPI Card
+ - 4 I2C controllers
+ - Two SATA onboard connectors
+ - UART
+   - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
+   - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
+0x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
+0x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
+0x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
+0x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
+0x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
+0x80_8000_0000 .. 0xFF_FFFF_FFFF	DDR region #2
+
+Other addresses are either reserved, or not used directly by u-boot.
+This list should be updated when more addresses are used.
+
+IFC region map from core's view
+-------------------------------
+During boot i.e. IFC Region #1:-
+  0x30000000 - 0x37ffffff : 128MB : NOR flash
+  0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
+  0x3C000000 - 0x40000000 : 64MB  : FPGA etc
+
+After relocate to DDR i.e. IFC Region #2:-
+  0x5_1000_0000..0x5_1fff_ffff	Memory Hole
+  0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
+  0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
+  0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
+  0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
+
+Booting Options
+---------------
+a) Promjet Boot
+b) NOR boot
+c) NAND boot
+d) SD boot
+e) QSPI boot
diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2085aqds/ddr.c
new file mode 100644
index 0000000..6cd5e8b
--- /dev/null
+++ b/board/freescale/ls2085aqds/ddr.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+	int slot;
+
+	if (ctrl_num > 2) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+
+	for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
+		if (pdimm[slot].n_ranks)
+			break;
+	}
+
+	if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
+		return;
+
+	/*
+	 * we use identical timing for all slots. If needed, change the code
+	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+	 */
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[ctrl_num];
+	else
+		pbsp = udimms[ctrl_num];
+
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm[slot].n_ranks &&
+		    (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for data rate %lu MT/s\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
+		/* force DDR bus width to 32 bits */
+		popts->data_bus_width = 1;
+		popts->otf_burst_chop_en = 0;
+		popts->burst_length = DDR_BL8;
+		popts->bstopre = 0;	/* enable auto precharge */
+		/*
+		 * Layout optimization results byte mapping
+		 * Byte 0 -> Byte ECC
+		 * Byte 1 -> Byte 3
+		 * Byte 2 -> Byte 2
+		 * Byte 3 -> Byte 1
+		 * Byte ECC -> Byte 0
+		 */
+		dq_mapping_0 = pdimm[slot].dq_mapping[0];
+		dq_mapping_2 = pdimm[slot].dq_mapping[2];
+		dq_mapping_3 = pdimm[slot].dq_mapping[3];
+		pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
+		pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
+		pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
+		pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
+		pdimm[slot].dq_mapping[6] = dq_mapping_2;
+		pdimm[slot].dq_mapping[7] = dq_mapping_3;
+		pdimm[slot].dq_mapping[8] = dq_mapping_0;
+		pdimm[slot].dq_mapping[9] = 0;
+		pdimm[slot].dq_mapping[10] = 0;
+		pdimm[slot].dq_mapping[11] = 0;
+		pdimm[slot].dq_mapping[12] = 0;
+		pdimm[slot].dq_mapping[13] = 0;
+		pdimm[slot].dq_mapping[14] = 0;
+		pdimm[slot].dq_mapping[15] = 0;
+		pdimm[slot].dq_mapping[16] = 0;
+		pdimm[slot].dq_mapping[17] = 0;
+	}
+	/* To work at higher than 1333MT/s */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0x0;	/* 32 clocks */
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	if (ddr_freq < 2350) {
+		popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+				  DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+		popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+				  DDR_CDR2_VREF_RANGE_2;
+	} else {
+		popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+				  DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
+		popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
+				  DDR_CDR2_VREF_RANGE_2;
+	}
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing DDR....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+	phys_size_t dp_ddr_size;
+#endif
+
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
+		gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+		gd->bd->bi_dram[1].size = gd->ram_size -
+					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+	} else {
+		gd->bd->bi_dram[0].size = gd->ram_size;
+	}
+
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+	/* initialize DP-DDR here */
+	puts("DP-DDR:  ");
+	/*
+	 * DDR controller use 0 as the base address for binding.
+	 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+	 */
+	dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+					  CONFIG_DP_DDR_CTRL,
+					  CONFIG_DP_DDR_NUM_CTRLS,
+					  CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
+					  NULL, NULL, NULL);
+	if (dp_ddr_size) {
+		gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+		gd->bd->bi_dram[2].size = dp_ddr_size;
+	} else {
+		puts("Not detected");
+	}
+#endif
+}
diff --git a/board/freescale/ls2085aqds/ddr.h b/board/freescale/ls2085aqds/ddr.h
new file mode 100644
index 0000000..b76ea61
--- /dev/null
+++ b/board/freescale/ls2085aqds/ddr.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2300, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters udimm2[] = {
+	/*
+	 * memory controller 2
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1666, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1900, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  2200, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters rdimm2[] = {
+	/*
+	 * memory controller 2
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 4,     7, 0x0B0A090C, 0x0D0F100B,},
+	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+	udimm0,
+	udimm2,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+	rdimm0,
+	rdimm2,
+};
+
+
+#endif
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c
new file mode 100644
index 0000000..f7ed5b9
--- /dev/null
+++ b/board/freescale/ls2085aqds/ls2085aqds.c
@@ -0,0 +1,287 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <fsl_debug_server.h>
+#include <fsl-mc/fsl_mc.h>
+#include <environment.h>
+#include <i2c.h>
+#include <asm/arch-fsl-lsch3/soc.h>
+
+#include "../common/qixis.h"
+#include "ls2085aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long long get_qixis_addr(void)
+{
+	unsigned long long addr;
+
+	if (gd->flags & GD_FLG_RELOC)
+		addr = QIXIS_BASE_PHYS;
+	else
+		addr = QIXIS_BASE_PHYS_EARLY;
+
+	/*
+	 * IFC address under 256MB is mapped to 0x30000000, any address above
+	 * is mapped to 0x5_10000000 up to 4GB.
+	 */
+	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
+
+	return addr;
+}
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+	static const char *const freq[] = {"100", "125", "156.25",
+					    "100 separate SSCG"};
+	int clock;
+
+	sw = QIXIS_READ(arch);
+	printf("Board: %s, ", CONFIG_IDENT_STRING);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("PromJet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else if (sw == 0x15)
+		printf("IFCCard\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+	printf("FPGA: v%d (%s), build %d",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+	/* the timestamp string contains "\n"@the end */
+	printf(" on %s", qixis_read_time(buf));
+
+	/*
+	 * Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES1 Reference : ");
+	sw = QIXIS_READ(brdcfg[2]);
+	clock = (sw >> 6) & 3;
+	printf("Clock1 = %sMHz ", freq[clock]);
+	clock = (sw >> 4) & 3;
+	printf("Clock2 = %sMHz", freq[clock]);
+
+	puts("\nSERDES2 Reference : ");
+	clock = (sw >> 2) & 3;
+	printf("Clock1 = %sMHz ", freq[clock]);
+	clock = (sw >> 0) & 3;
+	printf("Clock2 = %sMHz\n", freq[clock]);
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	init_final_memctl_regs();
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch3_early_init_f();
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_ddr_info(0);
+	if (gd->bd->bi_dram[2].size) {
+		puts("\nDP-DDR ");
+		print_size(gd->bd->bi_dram[2].size, "");
+		print_ddr_info(CONFIG_DP_DDR_CTRL);
+	}
+}
+
+int dram_init(void)
+{
+	gd->ram_size = initdram(0);
+
+	return 0;
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+#ifdef CONFIG_FSL_DEBUG_SERVER
+	debug_server_init();
+#endif
+
+	return 0;
+}
+#endif
+
+unsigned long get_dram_size_to_hide(void)
+{
+	unsigned long dram_to_hide = 0;
+
+/* Carve the Debug Server private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_DEBUG_SERVER
+	dram_to_hide += debug_server_get_dram_block_size();
+#endif
+
+/* Carve the MC private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_MC_ENET
+	dram_to_hide += mc_get_dram_block_size();
+#endif
+
+	return dram_to_hide;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int error = 0;
+
+#ifdef CONFIG_FSL_MC_ENET
+	error = cpu_eth_init(bis);
+#endif
+
+	error = pci_eth_init(bis);
+
+	return error;
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *fdt)
+{
+	int offset;
+
+	offset = fdt_path_offset(fdt, "/fsl-mc");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/fsl,dprc at 0");
+
+	if (offset < 0) {
+		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
+		       __func__, offset);
+		return;
+	}
+
+	if (get_mc_boot_status() == 0)
+		fdt_status_okay(fdt, offset);
+	else
+		fdt_status_fail(fdt, offset);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	/* limit the memory size to bank 1 until Linux can handle 40-bit PA */
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_FSL_MC_ENET
+	fdt_fixup_board_enet(blob);
+	fsl_mc_ldpaa_exit(bd);
+#endif
+
+	return 0;
+}
+#endif
+
+void qixis_dump_switch(void)
+{
+	int i, nr_of_cfgsw;
+
+	QIXIS_WRITE(cms[0], 0x00);
+	nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+	puts("DIP switch settings dump:\n");
+	for (i = 1; i <= nr_of_cfgsw; i++) {
+		QIXIS_WRITE(cms[0], i);
+		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+	}
+}
diff --git a/board/freescale/ls2085aqds/ls2085aqds_qixis.h b/board/freescale/ls2085aqds/ls2085aqds_qixis.h
new file mode 100644
index 0000000..bb43e65
--- /dev/null
+++ b/board/freescale/ls2085aqds/ls2085aqds_qixis.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS2_QDS_QIXIS_H__
+#define __LS2_QDS_QIXIS_H__
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+#endif /*__LS2_QDS_QIXIS_H__*/
diff --git a/configs/ls2085aqds_defconfig b/configs/ls2085aqds_defconfig
new file mode 100644
index 0000000..e3a17a3
--- /dev/null
+++ b/configs/ls2085aqds_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS2085AQDS=y
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 4b68106..29a86f6 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -94,7 +94,7 @@
 #define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */
 
 /* Serial Port */
-#define CONFIG_CONS_INDEX       2
+#define CONFIG_CONS_INDEX       1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE     1
@@ -107,18 +107,35 @@
 #define CONFIG_FSL_IFC
 
 /*
- * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
- * address 0. But this region is limited to 256MB. To accommodate bigger NOR
- * flash and other devices, we will map CS0 to 0x580000000 after relocation.
+ * During booting, IFC is mapped at the region of 0x30000000.
+ * But this region is limited to 256MB. To accommodate NOR, promjet
+ * and FPGA. This region is divided as below:
+ * 0x30000000 - 0x37ffffff : 128MB : NOR flash
+ * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
+ * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
+ *
+ * To accommodate bigger NOR flash and other devices, we will map IFC
+ * chip selects to as below:
+ * 0x5_1000_0000..0x5_1fff_ffff	Memory Hole
+ * 0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
+ * 0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
+ * 0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
+ * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
+ *
+ * For e.g. NOR flash@CS0 will be mapped to 0x580000000 after relocation.
  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
  */
+
 #define CONFIG_SYS_FLASH_BASE			0x580000000ULL
 #define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
 
+#define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
+#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
+
 #ifndef CONFIG_SYS_NO_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
@@ -126,8 +143,15 @@
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #endif
 
-#define CONFIG_SYS_NAND_BASE		0x520000000
-#define CONFIG_SYS_NAND_BASE_PHYS	0x20000000
+#ifndef __ASSEMBLY__
+unsigned long long get_qixis_addr(void);
+#endif
+#define QIXIS_BASE				get_qixis_addr()
+#define QIXIS_BASE_PHYS				0x20000000
+#define QIXIS_BASE_PHYS_EARLY			0xC000000
+
+#define CONFIG_SYS_NAND_BASE			0x530000000ULL
+#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
 
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
@@ -225,7 +249,7 @@
 				"hugepages=16"
 #define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
 					"$kernel_size && bootm $kernel_load"
-#define CONFIG_BOOTDELAY		1
+#define CONFIG_BOOTDELAY		10
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
new file mode 100644
index 0000000..b1d2d48
--- /dev/null
+++ b/include/configs/ls2085aqds.h
@@ -0,0 +1,283 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS2_QDS_H
+#define __LS2_QDS_H
+
+#include "ls2085a_common.h"
+#include <config_cmd_default.h>
+
+#define CONFIG_IDENT_STRING		" LS2085A-QDS"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-QDS"
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x53
+#define SPD_EEPROM_ADDRESS4	0x54
+#define SPD_EEPROM_ADDRESS5	0x55
+#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR		2
+#define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
+
+/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
+
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1a) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
+					 CONFIG_SYS_FLASH_BASE + 0x40000000}
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_LBMAP_SWITCH		0x06
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define	QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_CSPR3_EXT	(0x0)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+					FTIM2_GPCM_TCH(0xf) | \
+					FTIM2_GPCM_TWP(0x3E))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_FW_IN_NOR
+#define CONFIG_SYS_LS_MC_FW_ADDR	0x580300000ULL
+
+#define CONFIG_SYS_LS_MC_DPL_IN_NOR
+#define CONFIG_SYS_LS_MC_DPL_ADDR	0x580700000ULL
+
+#define CONFIG_SYS_LS_MC_DPC_IN_NOR
+#define CONFIG_SYS_LS_MC_DPC_ADDR	0x580800000ULL
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/*
+ * I2C
+ */
+#define I2C_MUX_PCA_ADDR		0x77
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+
+#define CONFIG_FSL_MEMAC
+#define CONFIG_PCI		/* Enable PCIE */
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+
+
+/* Initial environment variables */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x581100000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x1000000\0"
+
+#endif /* __LS2_QDS_H */
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 6358b6f..e5b6e03 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -167,6 +167,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
 #define DDR_CDR2_VREF_OVRD(x)	(0x00008080 | ((((x) - 37) & 0x3F) << 8))
 #define DDR_CDR2_VREF_TRAIN_EN	0x00000080
+#define DDR_CDR2_VREF_RANGE_2	0x00000040
 
 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
 	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
-- 
1.7.9.5

[U-Boot] [PATCH v5 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform

[York Sun]

The LS2085ARDB is a evaluation platform that supports LS2085A
family SoCs. This patch add sbasic support for the platform.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

---

Changes in v5:
  Fix Kconfig help for inconsistent SoC name
  s/LS2080/LS2085/g

Changes in v4:
  Fix board README for inconsistent SoC name
  Fix comments in board header file

Changes in v3: None
Changes in v2: None

 arch/arm/Kconfig                              |   11 +
 arch/arm/cpu/armv8/fsl-lsch3/README           |    4 +-
 board/freescale/ls2085ardb/Kconfig            |   16 ++
 board/freescale/ls2085ardb/MAINTAINERS        |    7 +
 board/freescale/ls2085ardb/Makefile           |    8 +
 board/freescale/ls2085ardb/README             |  109 ++++++++++
 board/freescale/ls2085ardb/ddr.c              |  192 ++++++++++++++++++
 board/freescale/ls2085ardb/ddr.h              |   92 +++++++++
 board/freescale/ls2085ardb/ls2085ardb.c       |  249 +++++++++++++++++++++++
 board/freescale/ls2085ardb/ls2085ardb_qixis.h |   20 ++
 configs/ls2085ardb_defconfig                  |    3 +
 include/configs/ls2085ardb.h                  |  266 +++++++++++++++++++++++++
 12 files changed, 975 insertions(+), 2 deletions(-)
 create mode 100644 board/freescale/ls2085ardb/Kconfig
 create mode 100644 board/freescale/ls2085ardb/MAINTAINERS
 create mode 100644 board/freescale/ls2085ardb/Makefile
 create mode 100644 board/freescale/ls2085ardb/README
 create mode 100644 board/freescale/ls2085ardb/ddr.c
 create mode 100644 board/freescale/ls2085ardb/ddr.h
 create mode 100644 board/freescale/ls2085ardb/ls2085ardb.c
 create mode 100644 board/freescale/ls2085ardb/ls2085ardb_qixis.h
 create mode 100644 configs/ls2085ardb_defconfig
 create mode 100644 include/configs/ls2085ardb.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f4a7851..6ba4b8d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -658,6 +658,16 @@ config TARGET_LS2085AQDS
 	  development platform that supports the QorIQ LS2085A
 	  Layerscape Architecture processor.
 
+config TARGET_LS2085ARDB
+	bool "Support ls2085ardb"
+	select ARM64
+	select ARMV8_MULTIENTRY
+	help
+	  Support for Freescale LS2085ARDB platform.
+	  The LS2085A Reference design board (RDB) is a high-performance
+	  development platform that supports the QorIQ LS2085A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
@@ -804,6 +814,7 @@ source "board/embest/mx6boards/Kconfig"
 source "board/esg/ima3-mx53/Kconfig"
 source "board/freescale/ls2085a/Kconfig"
 source "board/freescale/ls2085aqds/Kconfig"
+source "board/freescale/ls2085ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README
index 817ea1b..4f36e2a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -38,7 +38,7 @@ Flash Layout
 	32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
 
 (2) A typical layout of various images (including Linux and other firmware images)
-    is shown below considering a 128MB NOR flash device present on QDS
+    is shown below considering a 128MB NOR flash device present on QDS and RDB
     boards:
 	----------------------------------------- ----> 0x5_8800_0000 ---
 	|	.. Unused .. (7M)		|			|
@@ -86,7 +86,7 @@ Flash Layout
 	|	RCW and PBI (1M) 		|			|
 	----------------------------------------- ----> 0x5_8000_0000 ---
 
-	128-MB NOR flash layout for QDS board
+	128-MB NOR flash layout for QDS and RDB boards
 
 Environment Variables
 =====================
diff --git a/board/freescale/ls2085ardb/Kconfig b/board/freescale/ls2085ardb/Kconfig
new file mode 100644
index 0000000..85a3dcd
--- /dev/null
+++ b/board/freescale/ls2085ardb/Kconfig
@@ -0,0 +1,16 @@
+
+if TARGET_LS2085ARDB
+
+config SYS_BOARD
+	default "ls2085ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-lsch3"
+
+config SYS_CONFIG_NAME
+	default "ls2085ardb"
+
+endif
diff --git a/board/freescale/ls2085ardb/MAINTAINERS b/board/freescale/ls2085ardb/MAINTAINERS
new file mode 100644
index 0000000..436039f
--- /dev/null
+++ b/board/freescale/ls2085ardb/MAINTAINERS
@@ -0,0 +1,7 @@
+LS2085A BOARD
+M:	Prabhakar Kushwaha <prabhakar@freescale.com>
+S:	Maintained
+F:	board/freescale/ls2085ardb/
+F:	board/freescale/ls2085a/ls2085ardb.c
+F:	include/configs/ls2085ardb.h
+F:	configs/ls2085ardb_defconfig
diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2085ardb/Makefile
new file mode 100644
index 0000000..0bfe21c
--- /dev/null
+++ b/board/freescale/ls2085ardb/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ls2085ardb.o
+obj-y += ddr.o
diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2085ardb/README
new file mode 100644
index 0000000..cfd5185
--- /dev/null
+++ b/board/freescale/ls2085ardb/README
@@ -0,0 +1,109 @@
+Overview
+--------
+The LS2085A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2085A
+Layerscape Architecture processor.
+
+LS2085A SoC Overview
+------------------
+The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2085A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A57 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+  the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+   - Packet parsing, classification, and distribution (WRIOP)
+   - Queue and Hardware buffer management for scheduling, packet sequencing, and
+     congestion management, buffer allocation and de-allocation (QBMan)
+   - Cryptography acceleration (SEC) at up to 10 Gbps
+   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+   - Decompression/compression acceleration (DCE) at up to 20 Gbps
+   - Accelerated I/O processing (AIOP) at up to 20 Gbps
+   - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+   - Up to eight 10 Gbps Ethernet MACs
+   - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+   - Two serial ATA (SATA 3.0) controllers
+   - Two high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Serial peripheral interface (SPI) controller
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+  capabilities
+
+ LS2085ARDB board Overview
+ -----------------------
+ - SERDES Connections, 16 lanes supporting:
+      - PCI Express - 3.0
+      - SATA 3.0
+      - XFI
+ - DDR Controller
+     - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
+       chip-selects and two DIMM connectors. Support is up to 2133MT/s.
+     - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
+       and two DIMM connectors. Support is up to 1600MT/s.
+ -IFC/Local Bus
+    - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
+    - 128 MB NOR flash 16-bit data bus
+    - One 2 GB NAND flash with ECC support
+    - CPLD connection
+ - USB 3.0
+    - Two high speed USB 3.0 ports
+    - First USB 3.0 port configured as Host with Type-A connector
+    - Second USB 3.0 port configured as OTG with micro-AB connector
+ - SDHC adapter
+    - SD Card Rev 2.0 and Rev 3.0
+ - DSPI
+    - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz)
+ - 4 I2C controllers
+ - Two SATA onboard connectors
+ - UART
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
+0x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
+0x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
+0x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
+0x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
+0x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
+0x80_8000_0000 .. 0xFF_FFFF_FFFF	DDR region #2
+
+Other addresses are either reserved, or not used directly by u-boot.
+This list should be updated when more addresses are used.
+
+IFC region map from core's view
+-------------------------------
+During boot i.e. IFC Region #1:-
+  0x30000000 - 0x37ffffff : 128MB : NOR flash
+  0x3C000000 - 0x40000000 : 64MB  : CPLD
+
+After relocate to DDR i.e. IFC Region #2:-
+  0x5_1000_0000..0x5_1fff_ffff	Memory Hole
+  0x5_2000_0000..0x5_3fff_ffff	IFC CSx (CPLD, NAND and others 512MB)
+  0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
+  0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
+  0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
+
+Booting Options
+---------------
+a) NOR boot
+b) NAND boot
diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2085ardb/ddr.c
new file mode 100644
index 0000000..6cd5e8b
--- /dev/null
+++ b/board/freescale/ls2085ardb/ddr.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+	int slot;
+
+	if (ctrl_num > 2) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+
+	for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
+		if (pdimm[slot].n_ranks)
+			break;
+	}
+
+	if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
+		return;
+
+	/*
+	 * we use identical timing for all slots. If needed, change the code
+	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+	 */
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[ctrl_num];
+	else
+		pbsp = udimms[ctrl_num];
+
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm[slot].n_ranks &&
+		    (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for data rate %lu MT/s\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
+		/* force DDR bus width to 32 bits */
+		popts->data_bus_width = 1;
+		popts->otf_burst_chop_en = 0;
+		popts->burst_length = DDR_BL8;
+		popts->bstopre = 0;	/* enable auto precharge */
+		/*
+		 * Layout optimization results byte mapping
+		 * Byte 0 -> Byte ECC
+		 * Byte 1 -> Byte 3
+		 * Byte 2 -> Byte 2
+		 * Byte 3 -> Byte 1
+		 * Byte ECC -> Byte 0
+		 */
+		dq_mapping_0 = pdimm[slot].dq_mapping[0];
+		dq_mapping_2 = pdimm[slot].dq_mapping[2];
+		dq_mapping_3 = pdimm[slot].dq_mapping[3];
+		pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
+		pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
+		pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
+		pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
+		pdimm[slot].dq_mapping[6] = dq_mapping_2;
+		pdimm[slot].dq_mapping[7] = dq_mapping_3;
+		pdimm[slot].dq_mapping[8] = dq_mapping_0;
+		pdimm[slot].dq_mapping[9] = 0;
+		pdimm[slot].dq_mapping[10] = 0;
+		pdimm[slot].dq_mapping[11] = 0;
+		pdimm[slot].dq_mapping[12] = 0;
+		pdimm[slot].dq_mapping[13] = 0;
+		pdimm[slot].dq_mapping[14] = 0;
+		pdimm[slot].dq_mapping[15] = 0;
+		pdimm[slot].dq_mapping[16] = 0;
+		pdimm[slot].dq_mapping[17] = 0;
+	}
+	/* To work at higher than 1333MT/s */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0x0;	/* 32 clocks */
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	if (ddr_freq < 2350) {
+		popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+				  DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+		popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+				  DDR_CDR2_VREF_RANGE_2;
+	} else {
+		popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+				  DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
+		popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
+				  DDR_CDR2_VREF_RANGE_2;
+	}
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing DDR....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+	phys_size_t dp_ddr_size;
+#endif
+
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
+		gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+		gd->bd->bi_dram[1].size = gd->ram_size -
+					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+	} else {
+		gd->bd->bi_dram[0].size = gd->ram_size;
+	}
+
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+	/* initialize DP-DDR here */
+	puts("DP-DDR:  ");
+	/*
+	 * DDR controller use 0 as the base address for binding.
+	 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+	 */
+	dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+					  CONFIG_DP_DDR_CTRL,
+					  CONFIG_DP_DDR_NUM_CTRLS,
+					  CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
+					  NULL, NULL, NULL);
+	if (dp_ddr_size) {
+		gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+		gd->bd->bi_dram[2].size = dp_ddr_size;
+	} else {
+		puts("Not detected");
+	}
+#endif
+}
diff --git a/board/freescale/ls2085ardb/ddr.h b/board/freescale/ls2085ardb/ddr.h
new file mode 100644
index 0000000..bda9d4a
--- /dev/null
+++ b/board/freescale/ls2085ardb/ddr.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 4,     8, 0x08090B0D, 0x0E10100C,},
+	{2,  1900, 0, 4,     8, 0x090A0C0E, 0x1012120D,},
+	{2,  2300, 0, 4,     9, 0x0A0B0C10, 0x1114140E,},
+	{}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters udimm2[] = {
+	/*
+	 * memory controller 2
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1666, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1900, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  2200, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters rdimm2[] = {
+	/*
+	 * memory controller 2
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 4,     7, 0x0B0A090C, 0x0D0F100B,},
+	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+	udimm0,
+	udimm2,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+	rdimm0,
+	rdimm2,
+};
+
+
+#endif
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
new file mode 100644
index 0000000..d05f2bc
--- /dev/null
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <fsl_debug_server.h>
+#include <fsl-mc/fsl_mc.h>
+#include <environment.h>
+#include <i2c.h>
+#include <asm/arch-fsl-lsch3/soc.h>
+
+#include "../common/qixis.h"
+#include "ls2085ardb_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long long get_qixis_addr(void)
+{
+	unsigned long long addr;
+
+	if (gd->flags & GD_FLG_RELOC)
+		addr = QIXIS_BASE_PHYS;
+	else
+		addr = QIXIS_BASE_PHYS_EARLY;
+
+	/*
+	 * IFC address under 256MB is mapped to 0x30000000, any address above
+	 * is mapped to 0x5_10000000 up to 4GB.
+	 */
+	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
+
+	return addr;
+}
+
+int checkboard(void)
+{
+	u8 sw;
+
+	sw = QIXIS_READ(arch);
+	printf("Board: %s, ", CONFIG_IDENT_STRING);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
+
+	puts("SERDES1 Reference : ");
+	printf("Clock1 = 156.25MHz ");
+	printf("Clock2 = 156.25MHz");
+
+	puts("\nSERDES2 Reference : ");
+	printf("Clock1 = 100MHz ");
+	printf("Clock2 = 100MHz\n");
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	init_final_memctl_regs();
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch3_early_init_f();
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_ddr_info(0);
+	if (gd->bd->bi_dram[2].size) {
+		puts("\nDP-DDR ");
+		print_size(gd->bd->bi_dram[2].size, "");
+		print_ddr_info(CONFIG_DP_DDR_CTRL);
+	}
+}
+
+int dram_init(void)
+{
+	gd->ram_size = initdram(0);
+
+	return 0;
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+#ifdef CONFIG_FSL_DEBUG_SERVER
+	debug_server_init();
+#endif
+
+	return 0;
+}
+#endif
+
+unsigned long get_dram_size_to_hide(void)
+{
+	unsigned long dram_to_hide = 0;
+
+/* Carve the Debug Server private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_DEBUG_SERVER
+	dram_to_hide += debug_server_get_dram_block_size();
+#endif
+
+/* Carve the MC private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_MC_ENET
+	dram_to_hide += mc_get_dram_block_size();
+#endif
+
+	return dram_to_hide;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int error = 0;
+
+#ifdef CONFIG_FSL_MC_ENET
+	error = cpu_eth_init(bis);
+#endif
+
+	error = pci_eth_init(bis);
+
+	return error;
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *fdt)
+{
+	int offset;
+
+	offset = fdt_path_offset(fdt, "/fsl-mc");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+
+	if (offset < 0) {
+		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
+		       __func__, offset);
+		return;
+	}
+
+	if (get_mc_boot_status() == 0)
+		fdt_status_okay(fdt, offset);
+	else
+		fdt_status_fail(fdt, offset);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	/* limit the memory size to bank 1 until Linux can handle 40-bit PA */
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_FSL_MC_ENET
+	fdt_fixup_board_enet(blob);
+	fsl_mc_ldpaa_exit(bd);
+#endif
+
+	return 0;
+}
+#endif
+
+void qixis_dump_switch(void)
+{
+	int i, nr_of_cfgsw;
+
+	QIXIS_WRITE(cms[0], 0x00);
+	nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+	puts("DIP switch settings dump:\n");
+	for (i = 1; i <= nr_of_cfgsw; i++) {
+		QIXIS_WRITE(cms[0], i);
+		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+	}
+}
diff --git a/board/freescale/ls2085ardb/ls2085ardb_qixis.h b/board/freescale/ls2085ardb/ls2085ardb_qixis.h
new file mode 100644
index 0000000..cb60c00
--- /dev/null
+++ b/board/freescale/ls2085ardb/ls2085ardb_qixis.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS2_RDB_QIXIS_H__
+#define __LS2_RDB_QIXIS_H__
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+
+#endif /*__LS2_RDB_QIXIS_H__*/
diff --git a/configs/ls2085ardb_defconfig b/configs/ls2085ardb_defconfig
new file mode 100644
index 0000000..6b64f71
--- /dev/null
+++ b/configs/ls2085ardb_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS2085ARDB=y
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
new file mode 100644
index 0000000..9c6f3ed
--- /dev/null
+++ b/include/configs/ls2085ardb.h
@@ -0,0 +1,266 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS2_RDB_H
+#define __LS2_RDB_H
+
+#include "ls2085a_common.h"
+#include <config_cmd_default.h>
+
+#define CONFIG_IDENT_STRING		" LS2085A-RDB"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-RDB"
+
+#undef CONFIG_CONS_INDEX
+#define CONFIG_CONS_INDEX       2
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		133333333
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x54
+#define SPD_EEPROM_ADDRESS4	0x53	/* Board error */
+#define SPD_EEPROM_ADDRESS5	0x55
+#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR		2
+#define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
+
+/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
+
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1a) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
+					 CONFIG_SYS_FLASH_BASE + 0x40000000}
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
+				| CSOR_NAND_PB(128))	/* Pages Per Block 128*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
+					FTIM0_NAND_TWP(0x30)   | \
+					FTIM0_NAND_TWCHT(0x0e) | \
+					FTIM0_NAND_TWH(0x14))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
+					FTIM1_NAND_TWBE(0xab)  | \
+					FTIM1_NAND_TRR(0x1c)   | \
+					FTIM1_NAND_TRP(0x30))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
+					FTIM2_NAND_TREH(0x14) | \
+					FTIM2_NAND_TWHRE(0x3c))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_LBMAP_SWITCH		0x06
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RST_CTL_RESET_EN		0x30
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define	QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_CSPR3_EXT	(0x0)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+					FTIM2_GPCM_TCH(0xf) | \
+					FTIM2_GPCM_TWP(0x3E))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_FW_IN_NOR
+#define CONFIG_SYS_LS_MC_FW_ADDR	0x580300000ULL
+
+#define CONFIG_SYS_LS_MC_DPL_IN_NOR
+#define CONFIG_SYS_LS_MC_DPL_ADDR	0x580700000ULL
+
+#define CONFIG_SYS_LS_MC_DPC_IN_NOR
+#define CONFIG_SYS_LS_MC_DPC_ADDR	0x580800000ULL
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/*
+ * I2C
+ */
+#define I2C_MUX_PCA_ADDR		0x77
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+
+#define CONFIG_FSL_MEMAC
+#define CONFIG_PCI		/* Enable PCIE */
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+
+
+/* Initial environment variables */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x581100000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x1000000\0"
+
+#endif /* __LS2_RDB_H */
-- 
1.7.9.5

[U-Boot] [PATCH v5 21/28] drivers/fsl-mc: Autoload AOIP image from NOR flash

[York Sun]

From: "J. German Rivera" <German.Rivera@freescale.com>

Load AIOP image from NOR flash into DDR so that the MC firmware
the MC fw can start it at boot time.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
[York Sun: This is a debug commit. Will drop once AIOP is loaded by Linux]
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/fsl-mc/mc.c          |   24 ++++++++++++++++++++++++
 include/configs/ls2085a_common.h |    2 ++
 include/configs/ls2085aqds.h     |    3 +++
 include/configs/ls2085ardb.h     |    3 +++
 4 files changed, 32 insertions(+)

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index c5c44bc..e6f6d55 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -298,6 +298,24 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size)
 	return 0;
 }
 
+#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+static int load_mc_aiop_img(u64 mc_ram_addr, size_t mc_ram_size)
+{
+	void *aiop_img;
+
+	/*
+	 * Load the MC AIOP image in the MC private DRAM block:
+	 */
+
+	aiop_img = (void *)CONFIG_SYS_LS_MC_AIOP_IMG_ADDR;
+	mc_copy_image("MC AIOP image",
+		      (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
+		      mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+
+	return 0;
+}
+#endif
+
 /**
  * Return the MC boot timeout value in milliseconds
  */
@@ -454,6 +472,12 @@ int mc_init(void)
 	if (error != 0)
 		goto out;
 
+#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+	error = load_mc_aiop_img(mc_ram_addr, mc_ram_size);
+	if (error != 0)
+		goto out;
+#endif
+
 	debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
 	dump_mc_ccsr_regs(mc_ccsr_regs);
 
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 29a86f6..44c6845 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -166,6 +166,8 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
+#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
+#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x1f800000
 
 /* Carve out a DDR region which will not be used by u-boot/Linux */
 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index b1d2d48..a807640 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -218,6 +218,9 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_LS_MC_DPC_IN_NOR
 #define CONFIG_SYS_LS_MC_DPC_ADDR	0x580800000ULL
 
+#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR	0x580900000ULL
+
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 /*
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 9c6f3ed..0a5873b 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -201,6 +201,9 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_LS_MC_DPC_IN_NOR
 #define CONFIG_SYS_LS_MC_DPC_ADDR	0x580800000ULL
 
+#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR	0x580900000ULL
+
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 /*
-- 
1.7.9.5

[U-Boot] [PATCH v5 22/28] board/ls2085qds: Add support ethernet

[York Sun]

From: Prabhakar Kushwaha <prabhakar@freescale.com>

Add support of ethernet:
 - eth.c: mapping lane to slot for (0x2A, 0x07)
 - ls2085a.c: To enable/disable dpmac and get link type

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/freescale/ls2085aqds/Makefile           |    1 +
 board/freescale/ls2085aqds/eth.c              |  380 +++++++++++++++++++++++++
 board/freescale/ls2085aqds/ls2085aqds.c       |   13 -
 board/freescale/ls2085aqds/ls2085aqds_qixis.h |    4 +
 drivers/net/ldpaa_eth/Makefile                |    1 +
 drivers/net/ldpaa_eth/ls2085a.c               |   83 ++++++
 include/configs/ls2085aqds.h                  |   19 ++
 7 files changed, 488 insertions(+), 13 deletions(-)
 create mode 100644 board/freescale/ls2085aqds/eth.c
 create mode 100644 drivers/net/ldpaa_eth/ls2085a.c

diff --git a/board/freescale/ls2085aqds/Makefile b/board/freescale/ls2085aqds/Makefile
index f174f33..da69a7d 100644
--- a/board/freescale/ls2085aqds/Makefile
+++ b/board/freescale/ls2085aqds/Makefile
@@ -6,3 +6,4 @@
 
 obj-y += ls2085aqds.o
 obj-y += ddr.o
+obj-y += eth.o
diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c
new file mode 100644
index 0000000..5ba4770
--- /dev/null
+++ b/board/freescale/ls2085aqds/eth.c
@@ -0,0 +1,380 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+#include "../common/qixis.h"
+
+#include "ls2085aqds_qixis.h"
+
+
+#ifdef CONFIG_FSL_MC_ENET
+ /* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks.
+ *   Bank 1 -> Lanes A, B, C, D, E, F, G, H
+ *   Bank 2 -> Lanes A,B, C, D, E, F, G, H
+ */
+
+ /* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here
+  * means that the mapping must be determined dynamically, or that the lane
+  * maps to something other than a board slot.
+  */
+
+static u8 lane_to_slot_fsm2[] = {
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
+ * housed.
+ */
+static int riser_phy_addr[] = {
+	SGMII_CARD_PORT1_PHY_ADDR,
+	SGMII_CARD_PORT2_PHY_ADDR,
+	SGMII_CARD_PORT3_PHY_ADDR,
+	SGMII_CARD_PORT4_PHY_ADDR,
+};
+
+/* Slot2 does not have EMI connections */
+#define EMI_NONE	0xFFFFFFFF
+#define EMI1_SLOT1	0
+#define EMI1_SLOT2	1
+#define EMI1_SLOT3	2
+#define EMI1_SLOT4	3
+#define EMI1_SLOT5	4
+#define EMI1_SLOT6	5
+#define EMI2		6
+#define SFP_TX		1
+
+static const char * const mdio_names[] = {
+	"LS2085A_QDS_MDIO0",
+	"LS2085A_QDS_MDIO1",
+	"LS2085A_QDS_MDIO2",
+	"LS2085A_QDS_MDIO3",
+	"LS2085A_QDS_MDIO4",
+	"LS2085A_QDS_MDIO5",
+	DEFAULT_WRIOP_MDIO2_NAME,
+};
+
+struct ls2085a_qds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+	struct mii_dev *bus;
+	const char *name = ls2085a_qds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+static void ls2085a_qds_enable_SFP_TX(u8 muxval)
+{
+	u8 brdcfg9;
+
+	brdcfg9 = QIXIS_READ(brdcfg[9]);
+	brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
+	brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
+	QIXIS_WRITE(brdcfg[9], brdcfg9);
+}
+
+static void ls2085a_qds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+
+	if (muxval <= 5) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr,
+				 int devad, int regnum)
+{
+	struct ls2085a_qds_mdio *priv = bus->priv;
+
+	ls2085a_qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				  int regnum, u16 value)
+{
+	struct ls2085a_qds_mdio *priv = bus->priv;
+
+	ls2085a_qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls2085a_qds_mdio_reset(struct mii_dev *bus)
+{
+	struct ls2085a_qds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int ls2085a_qds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct ls2085a_qds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate ls2085a_qds MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate ls2085a_qds private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = ls2085a_qds_mdio_read;
+	bus->write = ls2085a_qds_mdio_write;
+	bus->reset = ls2085a_qds_mdio_reset;
+	sprintf(bus->name, ls2085a_qds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+
+	return mdio_register(bus);
+}
+
+/*
+ * Initialize the dpmac_info array.
+ *
+ */
+static void initialize_dpmac_to_slot(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+	int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+
+	switch (serdes1_prtcl) {
+	case 0x2A:
+		printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		break;
+	default:
+		printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		break;
+	}
+
+	switch (serdes2_prtcl) {
+	case 0x07:
+	case 0x08:
+		printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n",
+		       serdes2_prtcl);
+		lane_to_slot_fsm2[0] = EMI1_SLOT4;
+		lane_to_slot_fsm2[1] = EMI1_SLOT4;
+		lane_to_slot_fsm2[2] = EMI1_SLOT4;
+		lane_to_slot_fsm2[3] = EMI1_SLOT4;
+		/* No MDIO physical connection */
+		lane_to_slot_fsm2[4] = EMI1_SLOT6;
+		lane_to_slot_fsm2[5] = EMI1_SLOT6;
+		lane_to_slot_fsm2[6] = EMI1_SLOT6;
+		lane_to_slot_fsm2[7] = EMI1_SLOT6;
+		break;
+	default:
+		printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+		       serdes2_prtcl);
+		break;
+	}
+}
+
+void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
+{
+	int lane, slot;
+	struct mii_dev *bus;
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+	int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+	switch (serdes1_prtcl) {
+	}
+
+	switch (serdes2_prtcl) {
+	case 0x07:
+	case 0x08:
+		lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
+							(dpmac_id - 9));
+		slot = lane_to_slot_fsm2[lane];
+
+		switch (++slot) {
+		case 1:
+			break;
+		case 3:
+			break;
+		case 4:
+			/* Slot housing a SGMII riser card? */
+			wriop_set_phy_address(dpmac_id,
+					      riser_phy_addr[dpmac_id - 9]);
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
+			bus = mii_dev_for_muxval(EMI1_SLOT4);
+			wriop_set_mdio(dpmac_id, bus);
+			dpmac_info[dpmac_id].phydev = phy_connect(
+						dpmac_info[dpmac_id].bus,
+						dpmac_info[dpmac_id].phy_addr,
+						NULL,
+						dpmac_info[dpmac_id].enet_if);
+			phy_config(dpmac_info[dpmac_id].phydev);
+		break;
+		case 5:
+		break;
+		case 6:
+			/* Slot housing a SGMII riser card? */
+			wriop_set_phy_address(dpmac_id,
+					      riser_phy_addr[dpmac_id - 13]);
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
+			bus = mii_dev_for_muxval(EMI1_SLOT6);
+			wriop_set_mdio(dpmac_id, bus);
+		break;
+	}
+	break;
+	default:
+		printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+		       serdes2_prtcl);
+	break;
+	}
+}
+void ls2085a_handle_phy_interface_xsgmii(int i)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	switch (serdes1_prtcl) {
+	case 0x2A:
+		/*
+		 * XFI does not need a PHY to work, but to avoid U-boot use
+		 * default PHY address which is zero to a MAC when it found
+		 * a MAC has no PHY address, we give a PHY address to XFI
+		 * MAC, and should not use a real XAUI PHY address, since
+		 * MDIO can access it successfully, and then MDIO thinks
+		 * the XAUI card is used for the XFI MAC, which will cause
+		 * error.
+		 */
+		wriop_set_phy_address(i, i + 4);
+		ls2085a_qds_enable_SFP_TX(SFP_TX);
+
+		break;
+	default:
+		printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		break;
+	}
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int error;
+#ifdef CONFIG_FSL_MC_ENET
+	struct memac_mdio_info *memac_mdio0_info;
+	struct memac_mdio_info *memac_mdio1_info;
+	unsigned int i;
+
+	initialize_dpmac_to_slot();
+
+	memac_mdio0_info = (struct memac_mdio_info *)malloc(
+					sizeof(struct memac_mdio_info));
+	memac_mdio0_info->regs =
+		(struct memac_mdio_controller *)
+					CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
+
+	/* Register the real MDIO1 bus */
+	fm_memac_mdio_init(bis, memac_mdio0_info);
+
+	memac_mdio1_info = (struct memac_mdio_info *)malloc(
+					sizeof(struct memac_mdio_info));
+	memac_mdio1_info->regs =
+		(struct memac_mdio_controller *)
+					CONFIG_SYS_FSL_WRIOP1_MDIO2;
+	memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
+
+	/* Register the real MDIO2 bus */
+	fm_memac_mdio_init(bis, memac_mdio1_info);
+
+	/* Register the muxing front-ends to the MDIO buses */
+	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
+	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
+	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
+	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
+	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
+	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
+
+	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
+
+	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+		switch (wriop_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_QSGMII:
+			break;
+		case PHY_INTERFACE_MODE_SGMII:
+			ls2085a_handle_phy_interface_sgmii(i);
+			break;
+		case PHY_INTERFACE_MODE_XGMII:
+			ls2085a_handle_phy_interface_xsgmii(i);
+			break;
+		default:
+			break;
+		}
+	}
+
+	error = cpu_eth_init(bis);
+#endif
+	error = pci_eth_init(bis);
+	return error;
+}
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c
index f7ed5b9..6a22122 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2085aqds/ls2085aqds.c
@@ -214,19 +214,6 @@ unsigned long get_dram_size_to_hide(void)
 	return dram_to_hide;
 }
 
-int board_eth_init(bd_t *bis)
-{
-	int error = 0;
-
-#ifdef CONFIG_FSL_MC_ENET
-	error = cpu_eth_init(bis);
-#endif
-
-	error = pci_eth_init(bis);
-
-	return error;
-}
-
 #ifdef CONFIG_FSL_MC_ENET
 void fdt_fixup_board_enet(void *fdt)
 {
diff --git a/board/freescale/ls2085aqds/ls2085aqds_qixis.h b/board/freescale/ls2085aqds/ls2085aqds_qixis.h
index bb43e65..e281e5f 100644
--- a/board/freescale/ls2085aqds/ls2085aqds_qixis.h
+++ b/board/freescale/ls2085aqds/ls2085aqds_qixis.h
@@ -23,4 +23,8 @@
 #define QIXIS_DDRCLK_125		0x2
 #define QIXIS_DDRCLK_133		0x3
 
+#define BRDCFG4_EMISEL_MASK		0xE0
+#define BRDCFG4_EMISEL_SHIFT		5
+#define BRDCFG9_SFPTX_MASK		0x10
+#define BRDCFG9_SFPTX_SHIFT		4
 #endif /*__LS2_QDS_QIXIS_H__*/
diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile
index d32d67e..c37633f 100644
--- a/drivers/net/ldpaa_eth/Makefile
+++ b/drivers/net/ldpaa_eth/Makefile
@@ -6,3 +6,4 @@
 
 obj-y += ldpaa_wriop.o
 obj-y += ldpaa_eth.o
+obj-$(CONFIG_LS2085A) += ls2085a.o
diff --git a/drivers/net/ldpaa_eth/ls2085a.c b/drivers/net/ldpaa_eth/ls2085a.c
new file mode 100644
index 0000000..6b7960a
--- /dev/null
+++ b/drivers/net/ldpaa_eth/ls2085a.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <phy.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include <asm/io.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+u32 dpmac_to_devdisr[] = {
+	[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
+	[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
+	[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
+	[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
+	[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
+	[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
+	[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
+	[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
+	[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
+	[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
+	[WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
+	[WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
+	[WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
+	[WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
+	[WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
+	[WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
+	[WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
+	[WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
+	[WRIOP1_DPMAC19] = FSL_CHASSIS3_DEVDISR2_DPMAC19,
+	[WRIOP1_DPMAC20] = FSL_CHASSIS3_DEVDISR2_DPMAC20,
+	[WRIOP1_DPMAC21] = FSL_CHASSIS3_DEVDISR2_DPMAC21,
+	[WRIOP1_DPMAC22] = FSL_CHASSIS3_DEVDISR2_DPMAC22,
+	[WRIOP1_DPMAC23] = FSL_CHASSIS3_DEVDISR2_DPMAC23,
+	[WRIOP1_DPMAC24] = FSL_CHASSIS3_DEVDISR2_DPMAC24,
+};
+
+static int is_device_disabled(int dpmac_id)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 devdisr2 = in_le32(&gur->devdisr2);
+
+	return dpmac_to_devdisr[dpmac_id] & devdisr2;
+}
+
+void wriop_dpmac_disable(int dpmac_id)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+	setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
+}
+
+void wriop_dpmac_enable(int dpmac_id)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+	clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
+}
+
+phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
+{
+	enum srds_prtcl;
+
+	if (is_device_disabled(dpmac_id + 1))
+		return PHY_INTERFACE_MODE_NONE;
+
+	if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16)
+		return PHY_INTERFACE_MODE_SGMII;
+
+	if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
+		return PHY_INTERFACE_MODE_XGMII;
+
+	if (lane_prtcl >= XAUI1 && lane_prtcl <= XAUI2)
+		return PHY_INTERFACE_MODE_XGMII;
+
+	if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D)
+		return PHY_INTERFACE_MODE_QSGMII;
+
+	return PHY_INTERFACE_MODE_NONE;
+}
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index a807640..d54c731 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -283,4 +283,23 @@ unsigned long get_board_ddr_clk(void);
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x1000000\0"
 
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_FSL_MEMAC
+#define	CONFIG_PHYLIB
+#define CONFIG_PHYLIB_10G
+#define	CONFIG_CMD_MII
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"DPNI1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+#endif
+
 #endif /* __LS2_QDS_H */
-- 
1.7.9.5

[U-Boot] [PATCH v5 23/28] driver/ifc: Add 64KB page support

[York Sun]

From: Jaiprakash Singh <b44839@freescale.com>

IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.

FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv7/ls102xa/clock.c        |    4 +-
 arch/arm/cpu/armv8/fsl-lsch3/speed.c      |    4 +-
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |    8 +--
 arch/powerpc/cpu/mpc85xx/speed.c          |    4 +-
 board/freescale/bsc9132qds/bsc9132qds.c   |    4 +-
 board/freescale/c29xpcie/c29xpcie.c       |    4 +-
 board/freescale/p1010rdb/p1010rdb.c       |    5 +-
 board/freescale/p1010rdb/spl.c            |    4 +-
 drivers/mtd/nand/fsl_ifc_nand.c           |   53 ++++++++++--------
 drivers/mtd/nand/fsl_ifc_spl.c            |   23 ++++++--
 include/fsl_ifc.h                         |   84 +++++++++++++++++++----------
 11 files changed, 126 insertions(+), 71 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c
index 8f80c61..7a337e1 100644
--- a/arch/arm/cpu/armv7/ls102xa/clock.c
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -20,7 +20,7 @@ void get_sys_info(struct sys_info *sys_info)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 #ifdef CONFIG_FSL_IFC
-	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
@@ -74,7 +74,7 @@ void get_sys_info(struct sys_info *sys_info)
 	}
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = in_be32(&ifc_regs->ifc_ccr);
+	ccr = in_be32(&ifc_regs.gregs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 
 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
index 2b140cd..cac4f92 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
@@ -26,7 +26,7 @@ void get_sys_info(struct sys_info *sys_info)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 #ifdef CONFIG_FSL_IFC
-	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
 	struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
@@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info)
 	}
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = in_le32(&ifc_regs->ifc_ccr);
+	ccr = in_le32(&ifc_regs.gregs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 
 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 5ca9bf5..235a635 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_A003399_NOR_WORKAROUND
 void setup_ifc(void)
 {
-	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
 	phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
 
@@ -70,9 +70,9 @@ void setup_ifc(void)
 #endif
 
 	/* Change flash's physical address */
-	ifc_out32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
-	ifc_out32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
-	ifc_out32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
+	ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
+	ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
+	ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
 
 	return ;
 }
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e24b857..321ade2 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -28,7 +28,7 @@ void get_sys_info(sys_info_t *sys_info)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_FSL_IFC
-	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
 #ifdef CONFIG_FSL_CORENET
@@ -597,7 +597,7 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = ifc_in32(&ifc_regs->ifc_ccr);
+	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 
 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index 36a68db..586dacc 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -36,9 +36,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_early_init_f(void)
 {
-	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 
-	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
 
 	return 0;
 }
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index d757709..f42d373 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -38,10 +38,10 @@ int checkboard(void)
 
 int board_early_init_f(void)
 {
-	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 
 	/* Clock configuration to access CPLD using IFC(GPCM) */
-	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
 
 	return 0;
 }
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 1cf0ab7..ebffe9a 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -77,10 +77,9 @@ struct cpld_data {
 int board_early_init_f(void)
 {
 	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
-
+	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	/* Clock configuration to access CPLD using IFC(GPCM) */
-	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
 	/*
 	* Reset PCIe slots via GPIO4
 	*/
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index 11bd9cf..ee873b0 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -23,12 +23,12 @@ void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 
 	console_init_f();
 
 	/* Clock configuration to access CPLD using IFC(GPCM) */
-	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
 
 #ifdef CONFIG_P1010RDB_PB
 	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 16266fa..e8269c8 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -46,7 +46,7 @@ struct fsl_ifc_ctrl {
 	struct fsl_ifc_mtd *chips[MAX_BANKS];
 
 	/* device info */
-	struct fsl_ifc *regs;
+	struct fsl_ifc regs;
 	uint8_t __iomem *addr;   /* Address of assigned IFC buffer        */
 	unsigned int cs_nand;    /* On which chipsel NAND is connected	  */
 	unsigned int page;       /* Last page written to / read from      */
@@ -225,7 +225,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_ifc_mtd *priv = chip->priv;
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
-	struct fsl_ifc *ifc = ctrl->regs;
+	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 	int buf_num;
 
 	ctrl->page = page_addr;
@@ -289,7 +289,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_ifc_mtd *priv = chip->priv;
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
-	struct fsl_ifc *ifc = ctrl->regs;
+	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 	u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
 	u32 time_start;
 	u32 eccstat[8] = {0};
@@ -369,7 +369,7 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
 {
 	struct fsl_ifc_mtd *priv = chip->priv;
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
-	struct fsl_ifc *ifc = ctrl->regs;
+	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 
 	/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 	if (mtd->writesize > 512) {
@@ -407,7 +407,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_ifc_mtd *priv = chip->priv;
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
-	struct fsl_ifc *ifc = ctrl->regs;
+	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 
 	/* clear the read buffer */
 	ctrl->read_bytes = 0;
@@ -732,7 +732,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
 	struct fsl_ifc_mtd *priv = chip->priv;
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
-	struct fsl_ifc *ifc = ctrl->regs;
+	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 	u32 nand_fsr;
 
 	if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
@@ -789,24 +789,33 @@ static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 
 static void fsl_ifc_ctrl_init(void)
 {
+	uint32_t ver = 0;
 	ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
 	if (!ifc_ctrl)
 		return;
 
-	ifc_ctrl->regs = IFC_BASE_ADDR;
+	ifc_ctrl->regs.gregs = IFC_FCM_BASE_ADDR;
+
+	ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
+	if (ver >= FSL_IFC_V2_0_0)
+		ifc_ctrl->regs.rregs =
+			(void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
+	else
+		ifc_ctrl->regs.rregs =
+			(void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
 
 	/* clear event registers */
-	ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
-	ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
+	ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
+	ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
 
 	/* Enable error and event for any detected errors */
-	ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
+	ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_en,
 		  IFC_NAND_EVTER_EN_OPC_EN |
 		  IFC_NAND_EVTER_EN_PGRDCMPL_EN |
 		  IFC_NAND_EVTER_EN_FTOER_EN |
 		  IFC_NAND_EVTER_EN_WPER_EN);
 
-	ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
+	ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.ncfgr, 0x0);
 }
 
 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
@@ -815,7 +824,7 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 
 static int fsl_ifc_sram_init(uint32_t ver)
 {
-	struct fsl_ifc *ifc = ifc_ctrl->regs;
+	struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
 	uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
 	uint32_t ncfgr = 0;
 	u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
@@ -841,13 +850,13 @@ static int fsl_ifc_sram_init(uint32_t ver)
 	cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
 
 	/* Save CSOR and CSOR_ext */
-	csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor);
-	csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
+	csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
+	csor_ext = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext);
 
 	/* chage PageSize 8K and SpareSize 1K*/
 	csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
-	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
-	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
+	ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor_8k);
+	ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, 0x0000400);
 
 	/* READID */
 	ifc_out32(&ifc->ifc_nand.nand_fir0,
@@ -887,8 +896,8 @@ static int fsl_ifc_sram_init(uint32_t ver)
 	ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
 
 	/* Restore CSOR and CSOR_ext */
-	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
-	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
+	ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor);
+	ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, csor_ext);
 
 	return 0;
 }
@@ -899,6 +908,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	struct nand_chip *nand;
 	struct fsl_ifc_mtd *priv;
 	struct nand_ecclayout *layout;
+	struct fsl_ifc_fcm *gregs = NULL;
 	uint32_t cspr = 0, csor = 0, ver = 0;
 	int ret = 0;
 
@@ -914,14 +924,15 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 
 	priv->ctrl = ifc_ctrl;
 	priv->vbase = addr;
+	gregs = ifc_ctrl->regs.gregs;
 
 	/* Find which chip select it is connected to.
 	 */
 	for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 		phys_addr_t phys_addr = virt_to_phys(addr);
 
-		cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
-		csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
+		cspr = ifc_in32(&gregs->cspr_cs[priv->bank].cspr);
+		csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);
 
 		if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
 		    (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
@@ -1043,7 +1054,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 		nand->ecc.mode = NAND_ECC_SOFT;
 	}
 
-	ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
+	ver = ifc_in32(&gregs->ifc_rev);
 	if (ver >= FSL_IFC_V1_1_0)
 		ret = fsl_ifc_sram_init(ver);
 	if (ret)
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index fb827c5..2fb9fb1 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -48,9 +48,23 @@ static inline int check_read_ecc(uchar *buf, u32 *eccstat,
 	return 0;
 }
 
+static inline struct fsl_ifc_runtime *runtime_regs_address(void)
+{
+	struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL};
+	int ver = 0;
+
+	ver = ifc_in32(&regs.gregs->ifc_rev);
+	if (ver >= FSL_IFC_V2_0_0)
+		regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
+	else
+		regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
+
+	return regs.rregs;
+}
+
 static inline void nand_wait(uchar *buf, int bufnum, int page_size)
 {
-	struct fsl_ifc *ifc = IFC_BASE_ADDR;
+	struct fsl_ifc_runtime *ifc = runtime_regs_address();
 	u32 status;
 	u32 eccstat[4];
 	int bufperpage = page_size / 512;
@@ -90,7 +104,8 @@ static inline int bad_block(uchar *marker, int port_size)
 
 int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
 {
-	struct fsl_ifc *ifc = IFC_BASE_ADDR;
+	struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc_runtime *ifc = NULL;
 	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
 	int page_size;
 	int port_size;
@@ -107,6 +122,8 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
 	int pg_no;
 	uchar *dst = vdst;
 
+	ifc = runtime_regs_address();
+
 	/* Get NAND Flash configuration */
 	csor = CONFIG_SYS_NAND_CSOR;
 	cspr = CONFIG_SYS_NAND_CSPR;
@@ -130,7 +147,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
 			bad_marker = 5;
 	}
 
-	ver = ifc_in32(&ifc->ifc_rev);
+	ver = ifc_in32(&gregs->ifc_rev);
 	if (ver >= FSL_IFC_V2_0_0)
 		bufnum_mask = (bufnum_mask * 2) + 1;
 
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
index 11474b7..a7ddd5f 100644
--- a/include/fsl_ifc.h
+++ b/include/fsl_ifc.h
@@ -790,24 +790,36 @@ extern void print_ifc_regs(void);
 extern void init_early_memctl_regs(void);
 void init_final_memctl_regs(void);
 
-#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
-
-#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
-#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
-#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
-#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
-#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
-#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
-
-#define set_ifc_cspr_ext(i, v) \
-			(ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
-#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
-#define set_ifc_csor_ext(i, v) \
-			(ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
-#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
-#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
-#define set_ifc_ftim(i, j, v) \
-			(ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
+#define IFC_RREGS_4KOFFSET	(4*1024)
+#define IFC_RREGS_64KOFFSET	(64*1024)
+
+#define IFC_FCM_BASE_ADDR \
+	((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR)
+
+#define get_ifc_cspr_ext(i)	\
+		(ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext))
+#define get_ifc_cspr(i)		\
+		(ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr))
+#define get_ifc_csor_ext(i)	\
+		(ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext))
+#define get_ifc_csor(i)		\
+		(ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor))
+#define get_ifc_amask(i)	\
+		(ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask))
+#define get_ifc_ftim(i, j)	\
+		(ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j]))
+#define set_ifc_cspr_ext(i, v)	\
+		(ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
+#define set_ifc_cspr(i, v)	\
+		(ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v))
+#define set_ifc_csor_ext(i, v)	\
+		(ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v))
+#define set_ifc_csor(i, v)	\
+		(ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v))
+#define set_ifc_amask(i, v)	\
+		(ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v))
+#define set_ifc_ftim(i, j, v)	\
+		(ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v))
 
 enum ifc_chip_sel {
 	IFC_CS0,
@@ -869,20 +881,26 @@ struct fsl_ifc_nand {
 	u32 nand_evter_en;
 	u32 res17[0x2];
 	u32 nand_evter_intr_en;
-	u32 res18[0x2];
+	u32 nand_vol_addr_stat;
+	u32 res18;
 	u32 nand_erattr0;
 	u32 nand_erattr1;
 	u32 res19[0x10];
 	u32 nand_fsr;
-	u32 res20;
-	u32 nand_eccstat[4];
-	u32 res21[0x20];
+	u32 res20[0x3];
+	u32 nand_eccstat[6];
+	u32 res21[0x1c];
 	u32 nanndcr;
 	u32 res22[0x2];
 	u32 nand_autoboot_trgr;
 	u32 res23;
 	u32 nand_mdr;
-	u32 res24[0x5C];
+	u32 res24[0x1c];
+	u32 nand_dll_lowcfg0;
+	u32 nand_dll_lowcfg1;
+	u32 res25;
+	u32 nand_dll_lowstat;
+	u32 res26[0x3C];
 };
 
 /*
@@ -917,7 +935,6 @@ struct fsl_ifc_gpcm {
 	u32 gpcm_erattr1;
 	u32 gpcm_erattr2;
 	u32 gpcm_stat;
-	u32 res4[0x1F3];
 };
 
 #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
@@ -965,9 +982,11 @@ struct fsl_ifc_ftim {
 };
 
 /*
- * IFC Controller Registers
+ * IFC Controller Global Registers
+ * FCM - Flash control machine
  */
-struct fsl_ifc {
+
+struct fsl_ifc_fcm {
 	u32 ifc_rev;
 	u32 res1[0x2];
 	struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
@@ -979,7 +998,8 @@ struct fsl_ifc {
 	struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
 	u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
 	u32 rb_stat;
-	u32 res6[0x2];
+	u32 rb_map;
+	u32 wp_map;
 	u32 ifc_gcr;
 	u32 res7[0x2];
 	u32 cm_evter_stat;
@@ -993,12 +1013,20 @@ struct fsl_ifc {
 	u32 res11[0x2];
 	u32 ifc_ccr;
 	u32 ifc_csr;
-	u32 res12[0x2EB];
+	u32 ddr_ccr_low;
+};
+
+struct fsl_ifc_runtime {
 	struct fsl_ifc_nand ifc_nand;
 	struct fsl_ifc_nor ifc_nor;
 	struct fsl_ifc_gpcm ifc_gpcm;
 };
 
+struct fsl_ifc {
+	struct fsl_ifc_fcm *gregs;
+	struct fsl_ifc_runtime *rregs;
+};
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 #undef CSPR_MSEL_NOR
 #define CSPR_MSEL_NOR	CSPR_MSEL_GPCM
-- 
1.7.9.5

[U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support

[York Sun]

From: Scott Wood <scottwood@freescale.com>

This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>

---

Changes in v5:
  Update LS2085AQDS README to include instructions to form NAND image

Changes in v4:
  Update MAINTAINERS file

Changes in v3: None
Changes in v2: None

 arch/arm/Kconfig                             |    1 +
 arch/arm/cpu/armv8/fsl-lsch3/soc.c           |   48 ++++++++++++++++
 arch/arm/cpu/armv8/u-boot-spl.lds            |   77 ++++++++++++++++++++++++++
 arch/arm/include/asm/arch-fsl-lsch3/config.h |    9 +++
 arch/arm/lib/crt0_64.S                       |    7 +++
 board/freescale/ls2085aqds/MAINTAINERS       |    1 +
 board/freescale/ls2085aqds/README            |   19 +++++++
 board/freescale/ls2085aqds/ddr.c             |    4 ++
 common/spl/spl.c                             |    2 +-
 common/spl/spl_nand.c                        |    2 +-
 configs/ls2085aqds_nand_defconfig            |    4 ++
 drivers/misc/fsl_ifc.c                       |   12 ++++
 drivers/mtd/nand/fsl_ifc_spl.c               |    2 +-
 include/configs/ls2085a_common.h             |   29 ++++++++++
 include/configs/ls2085aqds.h                 |   50 +++++++++++++++--
 15 files changed, 259 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/u-boot-spl.lds
 create mode 100644 configs/ls2085aqds_nand_defconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6ba4b8d..f73541c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -652,6 +652,7 @@ config TARGET_LS2085AQDS
 	bool "Support ls2085aqds"
 	select ARM64
 	select ARMV8_MULTIENTRY
+	select SUPPORT_SPL
 	help
 	  Support for Freescale LS2085AQDS platform
 	  The LS2085A Development System (QDS) is a high-performance
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index 17700ef..ca00108 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -6,8 +6,13 @@
 
 #include <common.h>
 #include <fsl_ifc.h>
+#include <nand.h>
+#include <spl.h>
 #include <asm/arch-fsl-lsch3/soc.h>
 #include <asm/io.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 static void erratum_a008751(void)
 {
@@ -18,8 +23,51 @@ static void erratum_a008751(void)
 #endif
 }
 
+static void erratum_rcw_src(void)
+{
+#if defined(CONFIG_SPL)
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
+	u32 val;
+
+	val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+	val &= ~DCFG_PORSR1_RCW_SRC;
+	val |= DCFG_PORSR1_RCW_SRC_NOR;
+	out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
+#endif
+}
+
 void fsl_lsch3_early_init_f(void)
 {
 	erratum_a008751();
+	erratum_rcw_src();
 	init_early_memctl_regs();	/* tighten IFC timing */
 }
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+	board_early_init_f();
+	timer_init();
+	env_init();
+	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
+
+	serial_init();
+	console_init_f();
+	dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NAND;
+}
+#endif
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds
new file mode 100644
index 0000000..4df339c
--- /dev/null
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+	.text : {
+		. = ALIGN(8);
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	} >.sram
+
+	.rodata : {
+		. = ALIGN(8);
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} >.sram
+
+	.data : {
+		. = ALIGN(8);
+		*(.data*)
+	} >.sram
+
+	.u_boot_list : {
+		. = ALIGN(8);
+		KEEP(*(SORT(.u_boot_list*)));
+	} >.sram
+
+	.image_copy_end : {
+		. = ALIGN(8);
+		*(.__image_copy_end)
+	} >.sram
+
+	.end : {
+		. = ALIGN(8);
+		*(.__end)
+	} >.sram
+
+	.bss_start : {
+		. = ALIGN(8);
+		KEEP(*(.__bss_start));
+	} >.sdram
+
+	.bss : {
+		*(.bss*)
+		 . = ALIGN(8);
+	} >.sdram
+
+	.bss_end : {
+		KEEP(*(.__bss_end));
+	} >.sdram
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 403b2ef..77c20ab 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -130,6 +130,15 @@
 #define CCI_MN_DVM_DOMAIN_CTL		0x200
 #define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
 
+/* Device Configuration */
+#define DCFG_BASE		0x01e00000
+#define DCFG_PORSR1			0x000
+#define DCFG_PORSR1_RCW_SRC		0xff800000
+#define DCFG_PORSR1_RCW_SRC_NOR		0x12f00000
+
+#define DCFG_DCSR_BASE		0X700100000ULL
+#define DCFG_DCSR_PORCR1		0x000
+
 /* Supplemental Configuration */
 #define SCFG_BASE		0x01fc0000
 #define SCFG_USB3PRM1CR			0x000
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index 7756396..bf4ca99 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -61,13 +61,18 @@ ENTRY(_main)
 /*
  * Set up initial C runtime environment and call board_init_f(0).
  */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+	ldr	x0, =(CONFIG_SPL_STACK)
+#else
 	ldr	x0, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
 	sub	x0, x0, #GD_SIZE	/* allocate one GD above SP */
 	bic	sp, x0, #0xf	/* 16-byte alignment for ABI compliance */
 	mov	x18, sp			/* GD is above SP */
 	mov	x0, #0
 	bl	board_init_f
 
+#if !defined(CONFIG_SPL_BUILD)
 /*
  * Set up intermediate environment (new sp and gd) and call
  * relocate_code(addr_moni). Trick here is that we'll return
@@ -110,4 +115,6 @@ clear_loop:
 
 	/* NOTREACHED - board_init_r() does not return */
 
+#endif /* !CONFIG_SPL_BUILD */
+
 ENDPROC(_main)
diff --git a/board/freescale/ls2085aqds/MAINTAINERS b/board/freescale/ls2085aqds/MAINTAINERS
index 74b3721..fbed672 100644
--- a/board/freescale/ls2085aqds/MAINTAINERS
+++ b/board/freescale/ls2085aqds/MAINTAINERS
@@ -5,3 +5,4 @@ F:	board/freescale/ls2085aqds/
 F:	board/freescale/ls2085a/ls2085aqds.c
 F:	include/configs/ls2085aqds.h
 F:	configs/ls2085aqds_defconfig
+F:	configs/ls2085aqds_nand_defconfig
diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085aqds/README
index fb3938e..90d9c8f 100644
--- a/board/freescale/ls2085aqds/README
+++ b/board/freescale/ls2085aqds/README
@@ -127,3 +127,22 @@ b) NOR boot
 c) NAND boot
 d) SD boot
 e) QSPI boot
+
+Generage NAND image
+-------------------
+To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig.
+Append u-boot-with-spl.bin after RCW image. The RCW image should
+have these PBI commands
+
+1) CCSR 4-byte write to 0x00e00404, data=0x00000000
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+3) Block Copy: SRC=0x0104, SRC_ADDR=0x000000c0, DEST_ADDR=0x1800a000,
+BLOCK_SIZE=0x00014000
+
+These PBI commands set the bootloc registers to OCRAM address 0x1800a000
+and the SPL image is copied from the combined image into OCRAM.
+
+The SRC_ADDR should match the size of RCW image, i.e. it is the offset
+of u-boot-with-spl.bin in the NAND image. If putting RCW in a separated
+block is desired, the offset needs adjustment. Padding between the end
+of RCW and the start of u-boot image may be required.
diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2085aqds/ddr.c
index 6cd5e8b..8d71ae1 100644
--- a/board/freescale/ls2085aqds/ddr.c
+++ b/board/freescale/ls2085aqds/ddr.c
@@ -147,9 +147,13 @@ phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size;
 
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	return fsl_ddr_sdram_size();
+#else
 	puts("Initializing DDR....using SPD\n");
 
 	dram_size = fsl_ddr_sdram();
+#endif
 
 	return dram_size;
 }
diff --git a/common/spl/spl.c b/common/spl/spl.c
index cd75bbc..6d5cb0e 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -113,7 +113,7 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	typedef void __noreturn (*image_entry_noargs_t)(void);
 
 	image_entry_noargs_t image_entry =
-			(image_entry_noargs_t) spl_image->entry_point;
+		(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
 
 	debug("image entry point: 0x%X\n", spl_image->entry_point);
 	image_entry();
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index b7801cb..b8c369d 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -91,7 +91,7 @@ void spl_nand_load_image(void)
 		sizeof(*header), (void *)header);
 	spl_parse_image_header(header);
 	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-		spl_image.size, (void *)spl_image.load_addr);
+		spl_image.size, (void *)(unsigned long)spl_image.load_addr);
 	nand_deselect();
 }
 #endif
diff --git a/configs/ls2085aqds_nand_defconfig b/configs/ls2085aqds_nand_defconfig
new file mode 100644
index 0000000..446206a
--- /dev/null
+++ b/configs/ls2085aqds_nand_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS2085AQDS=y
diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c
index 45d299c..a33efdb 100644
--- a/drivers/misc/fsl_ifc.c
+++ b/drivers/misc/fsl_ifc.c
@@ -168,13 +168,25 @@ void init_final_memctl_regs(void)
 #ifdef CONFIG_SYS_CSPR0_FINAL
 	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
 #endif
+#ifdef CONFIG_SYS_AMASK0_FINAL
+	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+#endif
 #ifdef CONFIG_SYS_CSPR1_FINAL
 	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
 #endif
 #ifdef CONFIG_SYS_AMASK1_FINAL
 	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
 #endif
+#ifdef CONFIG_SYS_CSPR2_FINAL
+	set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL);
+#endif
+#ifdef CONFIG_SYS_AMASK2_FINAL
+	set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
+#endif
 #ifdef CONFIG_SYS_CSPR3_FINAL
 	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
 #endif
+#ifdef CONFIG_SYS_AMASK3_FINAL
+	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
+#endif
 }
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 2fb9fb1..fccbfb5 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -66,7 +66,7 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size)
 {
 	struct fsl_ifc_runtime *ifc = runtime_regs_address();
 	u32 status;
-	u32 eccstat[4];
+	u32 eccstat[8];
 	int bufperpage = page_size / 512;
 	int bufnum_end, i;
 
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 44c6845..9bc3869 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -28,7 +28,11 @@
 #define CONFIG_ARCH_MISC_INIT
 
 /* Link Definitions */
+#ifdef CONFIG_SPL
+#define CONFIG_SYS_TEXT_BASE		0x80400000
+#else
 #define CONFIG_SYS_TEXT_BASE		0x30100000
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
@@ -47,7 +51,9 @@
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
 
+#ifndef CONFIG_SPL
 #define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
+#endif
 #ifndef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
 #define CONFIG_SYS_DDR_RAW_TIMING
@@ -272,4 +278,27 @@ unsigned long get_dram_size_to_hide(void);
 
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MAX_SIZE		0x16000
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_STACK		(CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_TEXT_BASE		0x1800a000
+
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x80400000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
 #endif /* __LS2_COMMON_H */
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index d54c731..7307a59 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -147,10 +147,12 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_LBMAP_NAND		0x09
 #define QIXIS_RST_CTL_RESET		0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_RCW_SRC_NAND		0x107
 #define	QIXIS_RST_FORCE_MEM		0x01
 
 #define CONFIG_SYS_CSPR3_EXT	(0x0)
@@ -176,6 +178,43 @@ unsigned long get_board_ddr_clk(void);
 					FTIM2_GPCM_TWP(0x3E))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK2_FINAL		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(896 * 1024)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SPL_PAD_TO		0x1ff40
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
+#else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
 #define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
@@ -204,6 +243,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#endif
+
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL
@@ -249,11 +294,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
-#define CONFIG_ENV_SECT_SIZE		0x20000
-#define CONFIG_ENV_SIZE			0x2000
-
 #define CONFIG_FSL_MEMAC
 #define CONFIG_PCI		/* Enable PCIE */
 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
-- 
1.7.9.5

[U-Boot] [PATCH v5 25/28] freescale/qixis: Add support for booting from NAND

[York Sun]

From: Scott Wood <scottwood@freescale.com>

Use "qixis_reset nand" to reset the board to boot from NAND.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/freescale/common/qixis.c |   31 +++++++++++++++++++++----------
 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index a49e300..9f6b0e7 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -138,24 +138,23 @@ void qixis_bank_reset(void)
 	QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 }
 
-/* Set the boot bank to the power-on default bank */
-void clear_altbank(void)
+static void __maybe_unused set_lbmap(int lbmap)
 {
 	u8 reg;
 
 	reg = QIXIS_READ(brdcfg[0]);
-	reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK;
+	reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
 	QIXIS_WRITE(brdcfg[0], reg);
 }
 
-/* Set the boot bank to the alternate bank */
-void set_altbank(void)
+static void __maybe_unused set_rcw_src(int rcw_src)
 {
 	u8 reg;
 
-	reg = QIXIS_READ(brdcfg[0]);
-	reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK;
-	QIXIS_WRITE(brdcfg[0], reg);
+	reg = QIXIS_READ(dutcfg[1]);
+	reg = (reg & ~1) | (rcw_src & 1);
+	QIXIS_WRITE(dutcfg[1], reg);
+	QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
 }
 
 static void qixis_dump_regs(void)
@@ -201,11 +200,22 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	int i;
 
 	if (argc <= 1) {
-		clear_altbank();
+		set_lbmap(QIXIS_LBMAP_DFLTBANK);
 		qixis_reset();
 	} else if (strcmp(argv[1], "altbank") == 0) {
-		set_altbank();
+		set_lbmap(QIXIS_LBMAP_ALTBANK);
 		qixis_bank_reset();
+	} else if (strcmp(argv[1], "nand") == 0) {
+#ifdef QIXIS_LBMAP_NAND
+		QIXIS_WRITE(rst_ctl, 0x30);
+		QIXIS_WRITE(rcfg_ctl, 0);
+		set_lbmap(QIXIS_LBMAP_NAND);
+		set_rcw_src(QIXIS_RCW_SRC_NAND);
+		QIXIS_WRITE(rcfg_ctl, 0x20);
+		QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+		printf("Not implemented\n");
+#endif
 	} else if (strcmp(argv[1], "watchdog") == 0) {
 		static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
 					  "1min", "2min", "4min", "8min"};
@@ -244,6 +254,7 @@ U_BOOT_CMD(
 	"Reset the board using the FPGA sequencer",
 	"- hard reset to default bank\n"
 	"qixis_reset altbank - reset to alternate bank\n"
+	"qixis_reset nand - reset to nand\n"
 	"qixis watchdog <watchdog_period> - set the watchdog period\n"
 	"	period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
 	"qixis_reset dump - display the QIXIS registers\n"
-- 
1.7.9.5

[U-Boot] [PATCH v5 26/28] armv8/ls2085ardb: Enable NAND SPL support

[York Sun]

From: Scott Wood <scottwood@freescale.com>

Enable NAND boot support using SPL framework. To boot from
NAND, either use DIP switches on board, or "qixis_reset nand"
command. Details of forming NAND image can be found in README.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>

---

Changes in v5:
  Fix signed-off-by signature
  Update LS2085ARDB README to include instructions to form NAND image

Changes in v4:
  Update MAINTAINERS file

Changes in v3: None
Changes in v2: None

 arch/arm/Kconfig                       |    1 +
 board/freescale/ls2085ardb/MAINTAINERS |    1 +
 board/freescale/ls2085ardb/README      |   19 +++++++++++++++
 board/freescale/ls2085ardb/ddr.c       |    4 ++++
 configs/ls2085ardb_nand_defconfig      |    4 ++++
 include/configs/ls2085ardb.h           |   40 ++++++++++++++++++++++++++++----
 6 files changed, 64 insertions(+), 5 deletions(-)
 create mode 100644 configs/ls2085ardb_nand_defconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f73541c..cf291c8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -663,6 +663,7 @@ config TARGET_LS2085ARDB
 	bool "Support ls2085ardb"
 	select ARM64
 	select ARMV8_MULTIENTRY
+	select SUPPORT_SPL
 	help
 	  Support for Freescale LS2085ARDB platform.
 	  The LS2085A Reference design board (RDB) is a high-performance
diff --git a/board/freescale/ls2085ardb/MAINTAINERS b/board/freescale/ls2085ardb/MAINTAINERS
index 436039f..d5cce40 100644
--- a/board/freescale/ls2085ardb/MAINTAINERS
+++ b/board/freescale/ls2085ardb/MAINTAINERS
@@ -5,3 +5,4 @@ F:	board/freescale/ls2085ardb/
 F:	board/freescale/ls2085a/ls2085ardb.c
 F:	include/configs/ls2085ardb.h
 F:	configs/ls2085ardb_defconfig
+F:	configs/ls2085ardb_nand_defconfig
diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2085ardb/README
index cfd5185..5a5171c 100644
--- a/board/freescale/ls2085ardb/README
+++ b/board/freescale/ls2085ardb/README
@@ -107,3 +107,22 @@ Booting Options
 ---------------
 a) NOR boot
 b) NAND boot
+
+Generage NAND image
+-------------------
+To form the NAND image, build u-boot with LS2085ARDB_NAND_defconfig.
+Append u-boot-with-spl.bin after RCW image. The RCW image should
+have these PBI commands
+
+1) CCSR 4-byte write to 0x00e00404, data=0x00000000
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+3) Block Copy: SRC=0x0104, SRC_ADDR=0x000000c0, DEST_ADDR=0x1800a000,
+BLOCK_SIZE=0x00014000
+
+These PBI commands set the bootloc registers to OCRAM address 0x1800a000
+and the SPL image is copied from the combined image into OCRAM.
+
+The SRC_ADDR should match the size of RCW image, i.e. it is the offset
+of u-boot-with-spl.bin in the NAND image. If putting RCW in a separated
+block is desired, the offset needs adjustment. Padding between the end
+of RCW and the start of u-boot image may be required.
diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2085ardb/ddr.c
index 6cd5e8b..8d71ae1 100644
--- a/board/freescale/ls2085ardb/ddr.c
+++ b/board/freescale/ls2085ardb/ddr.c
@@ -147,9 +147,13 @@ phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size;
 
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	return fsl_ddr_sdram_size();
+#else
 	puts("Initializing DDR....using SPD\n");
 
 	dram_size = fsl_ddr_sdram();
+#endif
 
 	return dram_size;
 }
diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig
new file mode 100644
index 0000000..39ba8c5
--- /dev/null
+++ b/configs/ls2085ardb_nand_defconfig
@@ -0,0 +1,4 @@
++S:CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
++S:CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS2085ARDB=y
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 0a5873b..e97f054 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -139,11 +139,13 @@ unsigned long get_board_sys_clk(void);
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_LBMAP_NAND		0x09
 #define QIXIS_RST_CTL_RESET		0x31
 #define QIXIS_RST_CTL_RESET_EN		0x30
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_RCW_SRC_NAND		0x119
 #define	QIXIS_RST_FORCE_MEM		0x01
 
 #define CONFIG_SYS_CSPR3_EXT	(0x0)
@@ -169,6 +171,33 @@ unsigned long get_board_sys_clk(void);
 					FTIM2_GPCM_TWP(0x3E))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(1536 * 1024)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SPL_PAD_TO		0x7ff40
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
+#else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
 #define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
@@ -187,6 +216,12 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#endif
+
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL
@@ -232,11 +267,6 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
-#define CONFIG_ENV_SECT_SIZE		0x20000
-#define CONFIG_ENV_SIZE			0x2000
-
 #define CONFIG_FSL_MEMAC
 #define CONFIG_PCI		/* Enable PCIE */
 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
-- 
1.7.9.5

[U-Boot] [PATCH v5 27/28] ls2085a: esdhc: Add esdhc support for ls2085a

[York Sun]

From: Yangbo Lu <yangbo.lu@freescale.com>

This patch adds esdhc support for ls2085a.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv8/fsl-lsch3/cpu.c           |   10 +++++++
 arch/arm/cpu/armv8/fsl-lsch3/fdt.c           |    7 +++++
 arch/arm/include/asm/arch-fsl-lsch3/config.h |    2 ++
 drivers/mmc/fsl_esdhc.c                      |   36 ++++++++++++++++++++++++--
 include/configs/ls2085a_common.h             |    5 ++--
 include/configs/ls2085aqds.h                 |   19 +++++++++++++-
 include/configs/ls2085ardb.h                 |   11 +++++++-
 include/fsl_esdhc.h                          |    4 +++
 8 files changed, 88 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 22b5fb2..e738c49 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -13,6 +13,9 @@
 #include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
 #include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
 #include "cpu.h"
 #include "mp.h"
 #include "speed.h"
@@ -416,6 +419,13 @@ int print_cpuinfo(void)
 }
 #endif
 
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+	return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
 int cpu_eth_init(bd_t *bis)
 {
 	int error = 0;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
index 42c5b58..d370023 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
@@ -7,6 +7,9 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
 #include "mp.h"
 
 #ifdef CONFIG_MP
@@ -65,4 +68,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	do_fixup_by_compat_u32(blob, "fsl,ns16550",
 			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
+
+#if defined(CONFIG_FSL_ESDHC)
+	fdt_fixup_esdhc(blob, bd);
+#endif
 }
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 77c20ab..ca8d38c 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -31,6 +31,7 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
@@ -110,6 +111,7 @@
 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
 
+#define CONFIG_SYS_FSL_ESDHC_LE
 /* IFC */
 #define CONFIG_SYS_FSL_IFC_LE
 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c5e270d..7528b9d 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -105,7 +105,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 	else if (cmd->resp_type & MMC_RSP_PRESENT)
 		xfertyp |= XFERTYP_RSPTYP_48;
 
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102XA)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
+	defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 		xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
@@ -183,7 +184,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 	int timeout;
 	struct fsl_esdhc_cfg *cfg = mmc->priv;
 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-
+#ifdef CONFIG_LS2085A
+	dma_addr_t addr;
+#endif
 	uint wml_value;
 
 	wml_value = data->blocksize/4;
@@ -194,8 +197,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 
 		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifdef CONFIG_LS2085A
+		addr = virt_to_phys((void *)(data->dest));
+		if (upper_32_bits(addr))
+			printf("Error found for upper 32 bits\n");
+		else
+			esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
+#else
 		esdhc_write32(&regs->dsaddr, (u32)data->dest);
 #endif
+#endif
 	} else {
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 		flush_dcache_range((ulong)data->src,
@@ -212,8 +223,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 					wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifdef CONFIG_LS2085A
+		addr = virt_to_phys((void *)(data->src));
+		if (upper_32_bits(addr))
+			printf("Error found for upper 32 bits\n");
+		else
+			esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
+#else
 		esdhc_write32(&regs->dsaddr, (u32)data->src);
 #endif
+#endif
 	}
 
 	esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
@@ -259,10 +278,23 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 static void check_and_invalidate_dcache_range
 	(struct mmc_cmd *cmd,
 	 struct mmc_data *data) {
+#ifdef CONFIG_LS2085A
+	unsigned start = 0;
+#else
 	unsigned start = (unsigned)data->dest ;
+#endif
 	unsigned size = roundup(ARCH_DMA_MINALIGN,
 				data->blocks*data->blocksize);
 	unsigned end = start+size ;
+#ifdef CONFIG_LS2085A
+	dma_addr_t addr;
+
+	addr = virt_to_phys((void *)(data->dest));
+	if (upper_32_bits(addr))
+		printf("Error found for upper 32 bits\n");
+	else
+		start = lower_32_bits(addr);
+#endif
 	invalidate_dcache_range(start, end);
 }
 #endif
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 9bc3869..54c4e5c 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -155,6 +155,9 @@ unsigned long long get_qixis_addr(void);
 #define QIXIS_BASE				get_qixis_addr()
 #define QIXIS_BASE_PHYS				0x20000000
 #define QIXIS_BASE_PHYS_EARLY			0xC000000
+#define QIXIS_STAT_PRES1			0xb
+#define QIXIS_SDID_MASK				0x07
+#define QIXIS_ESDHC_NO_ADAPTER			0x7
 
 #define CONFIG_SYS_NAND_BASE			0x530000000ULL
 #define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
@@ -219,8 +222,6 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_CMD_BOOTD
 #define CONFIG_CMD_ECHO
 #define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index 7307a59..1de387a 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -278,6 +278,14 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT      0x8
 
 /*
+ * MMC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
+	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
+#endif
+
+/*
  * RTC configuration
  */
 #define RTC
@@ -307,7 +315,16 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_NET
 #endif
 
-
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
 
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index e97f054..d87532a 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -280,7 +280,16 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_CMD_NET
 #endif
 
-
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
 
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 57295b4..41bf05b 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -158,7 +158,11 @@
 #define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
 
 struct fsl_esdhc_cfg {
+#ifdef CONFIG_LS2085A
+	u64	esdhc_base;
+#else
 	u32	esdhc_base;
+#endif
 	u32	sdhc_clk;
 	u8	max_bus_width;
 	struct mmc_config cfg;
-- 
1.7.9.5

[U-Boot] [PATCH v5 28/28] armv8/fsl-lsch3: Implement workaround for I2C issue

[York Sun]

This erratum requires setting GLITCH_EN bit in debug register.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Heiko Schocher <hs@denx.de>

---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
  Add comment to I2C workaround

 arch/arm/cpu/armv8/fsl-lsch3/soc.c |   34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index ca00108..7cbf43c 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -37,11 +37,45 @@ static void erratum_rcw_src(void)
 #endif
 }
 
+#define I2C_DEBUG_REG 0x6
+#define I2C_GLITCH_EN 0x8
+/*
+ * This erratum indicates setting glitch_en bit enables
+ * digital glitch filter for improved stability.
+ */
+static void erratum_i2c(void)
+{
+	u8 __iomem *ptr;
+#ifdef CONFIG_SYS_I2C
+#ifdef I2C1_BASE_ADDR
+	ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
+
+	writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C2_BASE_ADDR
+	ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
+
+	writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C3_BASE_ADDR
+	ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
+
+	writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C4_BASE_ADDR
+	ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
+
+	writeb(I2C_GLITCH_EN, ptr);
+#endif
+#endif
+}
+
 void fsl_lsch3_early_init_f(void)
 {
 	erratum_a008751();
 	erratum_rcw_src();
 	init_early_memctl_regs();	/* tighten IFC timing */
+	erratum_i2c();
 }
 
 #ifdef CONFIG_SPL_BUILD
-- 
1.7.9.5

[U-Boot] [PATCH v5 17/28] armv8/fsl-lsch3: Enable system error aborts

[York Sun]

On 03/20/2015 07:28 PM, York Sun wrote:
> From: Scott Wood <scottwood@freescale.com>
> 
> This lets us see the problems (close to) when they happen,
> rather than Linux hanging when it enables them prior to having a
> working console.
> 
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> 
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  arch/arm/cpu/armv8/fsl-lsch3/cpu.c |    4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
> index 07064a3..22b5fb2 100644
> --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
> @@ -263,6 +263,10 @@ int arch_cpu_init(void)
>  	__asm_invalidate_tlb_all();
>  	early_mmu_setup();
>  	set_sctlr(get_sctlr() | CR_C);
> +
> +	/* Enable system error aborts */
> +	asm volatile("msr daifclr, #4" : : : "memory");
> +

I should have dropped this patch according to Scott's comment.

York

[U-Boot] [PATCH v5 14/28] drivers/fsl-mc: Changed MC firmware loading for new boot architecture

[Kim Phillips]

On Fri, 20 Mar 2015 19:28:18 -0700
York Sun <yorksun@freescale.com> wrote:

> From: "J. German Rivera" <German.Rivera@freescale.com>
> 
> Changed MC firmware loading to comply with the new MC boot architecture.
> Flush D-cache hierarchy after loading MC images. Add environment
> variables "mcboottimeout" for MC boot timeout in milliseconds,
> "mcmemsize" for MC DRAM block size. Check MC boot status before calling
> flib functions.
> 
> Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> 
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None

Hi, I made comments to v1 of this patch - why is it being
resubmitted without them being addressed?

Thanks,

Kim

[U-Boot] [PATCH v5 14/28] drivers/fsl-mc: Changed MC firmware loading for new boot architecture

[York Sun]

On 03/23/2015 11:02 AM, Kim Phillips wrote:
> On Fri, 20 Mar 2015 19:28:18 -0700
> York Sun <yorksun@freescale.com> wrote:
> 
>> From: "J. German Rivera" <German.Rivera@freescale.com>
>>
>> Changed MC firmware loading to comply with the new MC boot architecture.
>> Flush D-cache hierarchy after loading MC images. Add environment
>> variables "mcboottimeout" for MC boot timeout in milliseconds,
>> "mcmemsize" for MC DRAM block size. Check MC boot status before calling
>> flib functions.
>>
>> Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
>> Signed-off-by: York Sun <yorksun@freescale.com>
>> ---
>>
>> Changes in v5: None
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
> 
> Hi, I made comments to v1 of this patch - why is it being
> resubmitted without them being addressed?
> 

Kim,

Your comment was not addressed. I am hoping German can respond.
I upreved the patch set due to many of them have been updated. The change log
shows what has been changed.

York

[U-Boot] [PATCH v5 26/28] armv8/ls2085ardb: Enable NAND SPL support

[Scott Wood]

On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote:
> diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2085ardb/README
> index cfd5185..5a5171c 100644
> --- a/board/freescale/ls2085ardb/README
> +++ b/board/freescale/ls2085ardb/README
> @@ -107,3 +107,22 @@ Booting Options
>  ---------------
>  a) NOR boot
>  b) NAND boot
> +
> +Generage NAND image

Generate

> +-------------------
> +To form the NAND image, build u-boot with LS2085ARDB_NAND_defconfig.
> +Append u-boot-with-spl.bin after RCW image.

I thought we were going to put the SPL image in a separate erase block,
rather than concatenate it to the PBI.

>  The RCW image should
> +have these PBI commands
> +
> +1) CCSR 4-byte write to 0x00e00404, data=0x00000000
> +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
> +3) Block Copy: SRC=0x0104, SRC_ADDR=0x000000c0, DEST_ADDR=0x1800a000,
> +BLOCK_SIZE=0x00014000

0xc0 assumes that's the size of the PBI.  This is one reason I don't
like the concatenated approach.

> +These PBI commands set the bootloc registers to OCRAM address 0x1800a000
> +and the SPL image is copied from the combined image into OCRAM.
> +
> +The SRC_ADDR should match the size of RCW image, i.e. it is the offset
> +of u-boot-with-spl.bin in the NAND image. If putting RCW in a separated
> +block is desired, the offset needs adjustment. Padding between the end
> +of RCW and the start of u-boot image may be required.

The padding between SPL and main U-Boot and other constants would also
need to change.  I don't think we want to make this a user knob.

-Scott

[U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support

[Scott Wood]

On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote:
> +Generage NAND image
> +-------------------
> +To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig.
> +Append u-boot-with-spl.bin after RCW image. The RCW image should
> +have these PBI commands
> +
> +1) CCSR 4-byte write to 0x00e00404, data=0x00000000
> +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
> +3) Block Copy: SRC=0x0104, SRC_ADDR=0x000000c0, DEST_ADDR=0x1800a000,
> +BLOCK_SIZE=0x00014000

The RCW source should probably be 0x107, not 0x104.  Bit 0x002 requests
first/last bad block markers rather than first/second, and bit 0x001
enables ECC.  Also, this documentation is LS2085A-specific (most of it
will probably apply to all chips with this chassis), not RDB or QDS
specific, with the exception of the RCW source ID which depends on the
specific NAND chip.  It would be better to put it in one place rather
than duplicate it, with a table of RCW source IDs for each board.

Also, you have RDB as having SRC=0x104, but that (as well as 0x107) is
for a 2K-page NAND chip.  RDB has a 4K-page NAND, so I think you want
RCW source to be 0x111.

-Scott

[U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support

[York Sun]

On 03/23/2015 06:34 PM, Scott Wood wrote:
> On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote:
>> +Generage NAND image
>> +-------------------
>> +To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig.
>> +Append u-boot-with-spl.bin after RCW image. The RCW image should
>> +have these PBI commands
>> +
>> +1) CCSR 4-byte write to 0x00e00404, data=0x00000000
>> +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
>> +3) Block Copy: SRC=0x0104, SRC_ADDR=0x000000c0, DEST_ADDR=0x1800a000,
>> +BLOCK_SIZE=0x00014000
> 
> The RCW source should probably be 0x107, not 0x104.  Bit 0x002 requests
> first/last bad block markers rather than first/second, and bit 0x001
> enables ECC.  Also, this documentation is LS2085A-specific (most of it
> will probably apply to all chips with this chassis), not RDB or QDS
> specific, with the exception of the RCW source ID which depends on the
> specific NAND chip.  It would be better to put it in one place rather
> than duplicate it, with a table of RCW source IDs for each board.
> 
> Also, you have RDB as having SRC=0x104, but that (as well as 0x107) is
> for a 2K-page NAND chip.  RDB has a 4K-page NAND, so I think you want
> RCW source to be 0x111.
> 

I will try your suggestion. I use the value from the original RCW we created
during bring-up. Oddly it still works if it is wrong.

York

[U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support

[prabhakar at freescale.com]

> -----Original Message-----
> From: Sun York-R58495
> Sent: Tuesday, March 24, 2015 9:15 PM
> To: Wood Scott-B07421
> Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579
> Subject: Re: [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support
> 
> 
> 
> On 03/23/2015 06:34 PM, Scott Wood wrote:
> > On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote:
> >> +Generage NAND image
> >> +-------------------
> >> +To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig.
> >> +Append u-boot-with-spl.bin after RCW image. The RCW image should
> >> +have these PBI commands
> >> +
> >> +1) CCSR 4-byte write to 0x00e00404, data=0x00000000
> >> +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
> >> +3) Block Copy: SRC=0x0104, SRC_ADDR=0x000000c0,
> >> +DEST_ADDR=0x1800a000,
> >> +BLOCK_SIZE=0x00014000
> >
> > The RCW source should probably be 0x107, not 0x104.  Bit 0x002
> > requests first/last bad block markers rather than first/second, and
> > bit 0x001 enables ECC.  Also, this documentation is LS2085A-specific
> > (most of it will probably apply to all chips with this chassis), not
> > RDB or QDS specific, with the exception of the RCW source ID which
> > depends on the specific NAND chip.  It would be better to put it in
> > one place rather than duplicate it, with a table of RCW source IDs for each
> board.
> >
> > Also, you have RDB as having SRC=0x104, but that (as well as 0x107) is
> > for a 2K-page NAND chip.  RDB has a 4K-page NAND, so I think you want
> > RCW source to be 0x111.
> >
> 
for RDB. I think RCW source should be 0x119. 
bad block at first/last page(ONFI requirement) and 4bit ECC

-prabhakar

[U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support

[York Sun]

On 03/24/2015 09:34 AM, Kushwaha Prabhakar-B32579 wrote:
> 
>> -----Original Message-----
>> From: Sun York-R58495
>> Sent: Tuesday, March 24, 2015 9:15 PM
>> To: Wood Scott-B07421
>> Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579
>> Subject: Re: [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support
>>
>>
>>
>> On 03/23/2015 06:34 PM, Scott Wood wrote:
>>> On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote:
>>>> +Generage NAND image
>>>> +-------------------
>>>> +To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig.
>>>> +Append u-boot-with-spl.bin after RCW image. The RCW image should
>>>> +have these PBI commands
>>>> +
>>>> +1) CCSR 4-byte write to 0x00e00404, data=0x00000000
>>>> +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
>>>> +3) Block Copy: SRC=0x0104, SRC_ADDR=0x000000c0,
>>>> +DEST_ADDR=0x1800a000,
>>>> +BLOCK_SIZE=0x00014000
>>>
>>> The RCW source should probably be 0x107, not 0x104.  Bit 0x002
>>> requests first/last bad block markers rather than first/second, and
>>> bit 0x001 enables ECC.  Also, this documentation is LS2085A-specific
>>> (most of it will probably apply to all chips with this chassis), not
>>> RDB or QDS specific, with the exception of the RCW source ID which
>>> depends on the specific NAND chip.  It would be better to put it in
>>> one place rather than duplicate it, with a table of RCW source IDs for each
>> board.
>>>
>>> Also, you have RDB as having SRC=0x104, but that (as well as 0x107) is
>>> for a 2K-page NAND chip.  RDB has a 4K-page NAND, so I think you want
>>> RCW source to be 0x111.
>>>
>>
> for RDB. I think RCW source should be 0x119. 
> bad block at first/last page(ONFI requirement) and 4bit ECC
> 

I think 0x119 is correct. It is the same value I read back from rcw_src. I just
verified it boots OK. I have been using 0x104 as the source id incorrectly but
it also boots.

York

[U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support

[Scott Wood]

On Tue, 2015-03-24 at 11:34 -0500, Kushwaha Prabhakar-B32579 wrote:
> 
> > -----Original Message-----
> > From: Sun York-R58495
> > Sent: Tuesday, March 24, 2015 9:15 PM
> > To: Wood Scott-B07421
> > Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579
> > Subject: Re: [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support
> > 
> > 
> > 
> > On 03/23/2015 06:34 PM, Scott Wood wrote:
> > > On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote:
> > >> +Generage NAND image
> > >> +-------------------
> > >> +To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig.
> > >> +Append u-boot-with-spl.bin after RCW image. The RCW image should
> > >> +have these PBI commands
> > >> +
> > >> +1) CCSR 4-byte write to 0x00e00404, data=0x00000000
> > >> +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
> > >> +3) Block Copy: SRC=0x0104, SRC_ADDR=0x000000c0,
> > >> +DEST_ADDR=0x1800a000,
> > >> +BLOCK_SIZE=0x00014000
> > >
> > > The RCW source should probably be 0x107, not 0x104.  Bit 0x002
> > > requests first/last bad block markers rather than first/second, and
> > > bit 0x001 enables ECC.  Also, this documentation is LS2085A-specific
> > > (most of it will probably apply to all chips with this chassis), not
> > > RDB or QDS specific, with the exception of the RCW source ID which
> > > depends on the specific NAND chip.  It would be better to put it in
> > > one place rather than duplicate it, with a table of RCW source IDs for each
> > board.
> > >
> > > Also, you have RDB as having SRC=0x104, but that (as well as 0x107) is
> > > for a 2K-page NAND chip.  RDB has a 4K-page NAND, so I think you want
> > > RCW source to be 0x111.
> > >
> > 
> for RDB. I think RCW source should be 0x119. 
> bad block at first/last page(ONFI requirement) and 4bit ECC

Yes, sorry.

-Scott

[U-Boot] [PATCH v5 0/28] Adding LS2085AQDS and RDB

[York Sun]

On 03/20/2015 07:28 PM, York Sun wrote:
> This set adds necessary support in common ls2085a support and board
> support for QDS and RDB.
> 
> Changes in v5:
>   Re-generate patches using patman default flags
>   s/LayerScape/Layerscape/g
>   Fix board README for inconsistent SoC name
>   Fix comment in board header file
>   s/LS2080/LS2085/g
>   Fix Kconfig help for inconsistent SoC name
>   Update LS2085AQDS README to include instructions to form NAND image
>   Update LS2085ARDB README to include instructions to form NAND image
> 
> Changes in v4:
>   Remove temporary variable cntfrq.
>   Fix board README for inconsistent SoC name
>   Fix comments in board header file
>   Update MAINTAINERS file
>   Update MAINTAINERS file
> 
> Changes in v3:
>   Move secondary core fix to mp.c.
>   Replace hard-coded value with COUNTER_FREQUENCY.
> 
> Changes in v2:
>   Rebase after adding macros CONFIG_SYS_I2C_MXC_I2C3 in another patch set
>   Fix CNTFRQ for secondary cores when COUNTER_FREQUENCY_REAL is defined.
>   Add comment to I2C workaround
> 
> Bhupesh Sharma (1):
>   armv8/fsl-ch3: Add support to print RCW configuration
> 
> J. German Rivera (2):
>   drivers/fsl-mc: Changed MC firmware loading for new boot architecture
>   drivers/fsl-mc: Autoload AOIP image from NOR flash
> 
> Jaiprakash Singh (1):
>   driver/ifc: Add 64KB page support
> 
> Minghuan Lian (1):
>   armv8: Add SerDes framework for Layerscape Architecture
> 
> Prabhakar Kushwaha (4):
>   armv8/ls2085a: Update common header file
>   driver/ldpaa_eth: Update ldpaa ethernet driver
>   driver/ldpaa: Add support of WRIOP static data structure
>   board/ls2085qds: Add support ethernet
> 
> Scott Wood (8):
>   armv8/fsl-lsch3: Set nodes in DVM domain
>   fsl-lsch3: Introduce place for common early SoC init
>   armv8/ls2085a: Add workaround for USB erratum A-008751
>   armv8/fsl-lsch3: Use correct compatible for serial clock fixup
>   armv8/fsl-lsch3: Enable system error aborts
>   armv8/ls2085aqds: NAND boot support
>   freescale/qixis: Add support for booting from NAND
>   armv8/ls2085ardb: Enable NAND SPL support
> 
> Shaohui Xie (1):
>   net/memac_phy: reuse driver for little endian SoCs
> 
> Yangbo Lu (1):
>   ls2085a: esdhc: Add esdhc support for ls2085a
> 
> York Sun (7):
>   armv8/fsl-lsch3: Implement workaround for erratum A008585
>   armv8/fsl-lsch3: Fix platform clock calculation
>   armv8/ls2085a: Fix generic timer clock source
>   armv8/fsl-lsch3: Update early MMU table
>   armv8/ls2085aqds: Add support of LS2085AQDS platform
>   armv8/ls2085ardb: Add support of LS2085ARDB platform
>   armv8/fsl-lsch3: Implement workaround for I2C issue
> 
> pankaj chauhan (2):
>   armv8/ls2085a: Add support for reset request
>   net/phy/cortina: Fix compilation warning
> 

This set (except 17/28 and 21/28) is applied to fsl-qoriq master, awaiting upstream.

[U-Boot,v5,01/28] armv8/fsl-lsch3: Implement workaround for erratum A008585
[U-Boot,v5,02/28] armv8/ls2085a: Update common header file
[U-Boot,v5,03/28] armv8/fsl-lsch3: Fix platform clock calculation
[U-Boot,v5,04/28] armv8/ls2085a: Fix generic timer clock source
[U-Boot,v5,05/28] armv8/ls2085a: Add support for reset request
[U-Boot,v5,06/28] armv8/fsl-lsch3: Set nodes in DVM domain
[U-Boot,v5,07/28] armv8/fsl-lsch3: Update early MMU table
[U-Boot,v5,08/28] fsl-lsch3: Introduce place for common early SoC init
[U-Boot,v5,09/28] armv8/ls2085a: Add workaround for USB erratum A-008751
[U-Boot,v5,10/28] armv8/fsl-lsch3: Use correct compatible for serial clock fixup
[U-Boot,v5,11/28] driver/ldpaa_eth: Update ldpaa ethernet driver
[U-Boot,v5,12/28] armv8: Add SerDes framework for Layerscape Architecture
[U-Boot,v5,13/28] net/phy/cortina: Fix compilation warning
[U-Boot,v5,14/28] drivers/fsl-mc: Changed MC firmware loading for new boot
architecture
[U-Boot,v5,15/28] net/memac_phy: reuse driver for little endian SoCs
[U-Boot,v5,16/28] armv8/fsl-ch3: Add support to print RCW configuration
[U-Boot,v5,18/28] driver/ldpaa: Add support of WRIOP static data structure
[U-Boot,v5,19/28] armv8/ls2085aqds: Add support of LS2085AQDS platform
[U-Boot,v5,20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
[U-Boot,v5,22/28] board/ls2085qds: Add support ethernet
[U-Boot,v5,23/28] driver/ifc: Add 64KB page support
[U-Boot,v9,24/28] armv8/ls2085aqds: NAND boot support
[U-Boot,v5,25/28] freescale/qixis: Add support for booting from NAND
[U-Boot,v9,26/28] armv8/ls2085ardb: Enable NAND SPL support
[U-Boot,v5,27/28] ls2085a: esdhc: Add esdhc support for ls2085a
[U-Boot,v6,28/28] armv8/fsl-lsch3: Implement workaround for I2C erratum A009203

York