[PATCH 0/2] BMIPS: trivial fixes

[PATCH 0/2] BMIPS: trivial fixes

[Florian Fainelli]

Hi Ralf,

First patch is a respin of http://patchwork.linux-mips.org/patch/8848/ to fix
the build on MIPS64 platforms that you reported.

Second patch prevents a "choice" to be leaking to other MIPS platforms.

This is against upstream-sfr.git/mips-for-linux-next.

Thanks!

Florian Fainelli (1):
  MIPS: BMIPS: restrict DTB selection to BMIPS_GENERIC

Kevin Cernekee (1):
  MIPS: BMIPS: Flush the readahead cache after DMA

 arch/mips/bmips/Kconfig       |  4 ++++
 arch/mips/include/asm/bmips.h |  2 +-
 arch/mips/mm/dma-default.c    | 15 +++++++++++++++
 3 files changed, 20 insertions(+), 1 deletion(-)

-- 
2.1.0

[PATCH 1/2] MIPS: BMIPS: Flush the readahead cache after DMA

[Florian Fainelli]

From: Kevin Cernekee <cernekee@gmail.com>

BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
the L1/L2.  During a DMA operation, accesses adjacent to a DMA buffer
may cause parts of the DMA buffer to be prefetched into the RAC.  To
avoid possible coherency problems, flush the RAC upon DMA completion.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/mips/include/asm/bmips.h |  2 +-
 arch/mips/mm/dma-default.c    | 15 +++++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 30939b02e3ff..866cdbecebbf 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -40,7 +40,7 @@
 #define BMIPS_NMI_RESET_VEC		0x80000000
 #define BMIPS_WARM_RESTART_VEC		0x80000380
 
-#define ZSCM_REG_BASE			0x97000000
+#define ZSCM_REG_BASE			0x97000000UL
 
 #if !defined(__ASSEMBLY__)
 
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index af5f046e627e..38ee47acf06b 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -18,6 +18,7 @@
 #include <linux/highmem.h>
 #include <linux/dma-contiguous.h>
 
+#include <asm/bmips.h>
 #include <asm/cache.h>
 #include <asm/cpu-type.h>
 #include <asm/io.h>
@@ -69,6 +70,20 @@ static inline struct page *dma_addr_to_page(struct device *dev,
  */
 static inline int cpu_needs_post_dma_flush(struct device *dev)
 {
+	if (boot_cpu_type() == CPU_BMIPS3300 ||
+	    boot_cpu_type() == CPU_BMIPS4350 ||
+	    boot_cpu_type() == CPU_BMIPS4380) {
+		void __iomem *cbr = BMIPS_GET_CBR();
+		u32 cfg;
+
+		/* Flush stale data out of the readahead cache */
+		cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
+		__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
+		__raw_readl(cbr + BMIPS_RAC_CONFIG);
+
+		return 0;
+	}
+
 	return !plat_device_is_coherent(dev) &&
 	       (boot_cpu_type() == CPU_R10000 ||
 		boot_cpu_type() == CPU_R12000 ||
-- 
2.1.0

[PATCH 2/2] MIPS: BMIPS: restrict DTB selection to BMIPS_GENERIC

[Florian Fainelli]

Since we are always sourcing arch/mips/bmips/Kconfig and there is no
dependency on BMIPS_GENERIC, we will offer building BMIPS-related DTBs
while this is not relevant for the other MIPS platforms.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/mips/bmips/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/mips/bmips/Kconfig b/arch/mips/bmips/Kconfig
index 6ffc42cbb846..f35c84c019df 100644
--- a/arch/mips/bmips/Kconfig
+++ b/arch/mips/bmips/Kconfig
@@ -1,3 +1,5 @@
+if BMIPS_GENERIC
+
 choice
 	prompt "Built-in device tree"
 	help
@@ -56,3 +58,5 @@ config DT_BCM97425SVMB
 	select BUILTIN_DTB
 
 endchoice
+
+endif
-- 
2.1.0

Re: [PATCH 1/2] MIPS: BMIPS: Flush the readahead cache after DMA

[Ralf Baechle]

On Wed, Mar 25, 2015 at 09:55:14PM -0700, Florian Fainelli wrote:

> From: Kevin Cernekee <cernekee@gmail.com>
> 
> BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
> the L1/L2.  During a DMA operation, accesses adjacent to a DMA buffer
> may cause parts of the DMA buffer to be prefetched into the RAC.  To
> avoid possible coherency problems, flush the RAC upon DMA completion.
> 
> Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  arch/mips/include/asm/bmips.h |  2 +-
>  arch/mips/mm/dma-default.c    | 15 +++++++++++++++
>  2 files changed, 16 insertions(+), 1 deletion(-)

I'm not keen on including platform-specific files that may blow up on
another platform.  So what I suggest instead is something like rewriting
cpu_needs_post_dma_flush() to invoke a platform-specific hook function
plat_post_dma_flush() which would be defined in <asm/dma-coherence.h>
rsp. <mach/dma-coherence.h>.

I'm going to whip up something.

  Ralf

Re: [PATCH 1/2] MIPS: BMIPS: Flush the readahead cache after DMA

[Kevin Cernekee]

On Fri, Mar 27, 2015 at 5:04 AM, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Wed, Mar 25, 2015 at 09:55:14PM -0700, Florian Fainelli wrote:
>
>> From: Kevin Cernekee <cernekee@gmail.com>
>>
>> BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
>> the L1/L2.  During a DMA operation, accesses adjacent to a DMA buffer
>> may cause parts of the DMA buffer to be prefetched into the RAC.  To
>> avoid possible coherency problems, flush the RAC upon DMA completion.
>>
>> Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
>> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>>  arch/mips/include/asm/bmips.h |  2 +-
>>  arch/mips/mm/dma-default.c    | 15 +++++++++++++++
>>  2 files changed, 16 insertions(+), 1 deletion(-)
>
> I'm not keen on including platform-specific files that may blow up on
> another platform.  So what I suggest instead is something like rewriting
> cpu_needs_post_dma_flush() to invoke a platform-specific hook function
> plat_post_dma_flush() which would be defined in <asm/dma-coherence.h>
> rsp. <mach/dma-coherence.h>.
>
> I'm going to whip up something.

Hi Ralf,

Regarding this patch:
http://git.linux-mips.org/cgit/ralf/upstream-sfr.git/commit/?id=47df84c7341a4816b69b784b01fce304a15777a2

The same change is also needed for mach-bcm63xx (in-tree) and
mach-brcmstb (out-of-tree).  Somewhat confusingly, mach-bmips is a
"Generic BMIPS kernel" but it isn't the only platform which uses BMIPS
processors that have readahead caches.

I am hoping that someday mach-bmips will have support for all
mach-bcm63xx and mach-brcmstb platforms/peripherals, but we aren't
quite there yet.