From: Rajendra Nayak <rnayak@codeaurora.org> To: sboyd@codeaurora.org, mturquette@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, georgi.djakov@linaro.org, svarbanov@mm-sol.com, srinivas.kandagatla@linaro.org, sviau@codeaurora.org, Rajendra Nayak <rnayak@codeaurora.org> Subject: [PATCH v4 6/8] clk: qcom: gdsc: Add GDSCs in apq8084 GCC Date: Thu, 26 Mar 2015 14:50:17 +0530 [thread overview] Message-ID: <1427361619-20360-7-git-send-email-rnayak@codeaurora.org> (raw) In-Reply-To: <1427361619-20360-1-git-send-email-rnayak@codeaurora.org> Add the GDSC instances that exist as part of apq8084 GCC block Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> --- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-apq8084.c | 38 ++++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-apq8084.h | 6 +++++ 3 files changed, 45 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 104ec0c..c246417 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -6,6 +6,7 @@ config COMMON_CLK_QCOM config APQ_GCC_8084 tristate "APQ8084 Global Clock Controller" + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the global clock controller on apq8084 devices. diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c index f75b505..6fafc2a 100644 --- a/drivers/clk/qcom/gcc-apq8084.c +++ b/drivers/clk/qcom/gcc-apq8084.c @@ -31,6 +31,7 @@ #include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum { P_XO, @@ -3259,6 +3260,34 @@ static struct clk_branch gcc_usb_hsic_system_clk = { }, }; +static struct gdsc usb_hs_hsic_gdsc = { + .gdscr = 0x404, + .pd = { + .name = "usb_hs_hsic", + }, +}; + +static struct gdsc pcie0_gdsc = { + .gdscr = 0x1ac4, + .pd = { + .name = "pcie0", + }, +}; + +static struct gdsc pcie1_gdsc = { + .gdscr = 0x1b44, + .pd = { + .name = "pcie1", + }, +}; + +static struct gdsc usb30_gdsc = { + .gdscr = 0x1e84, + .pd = { + .name = "usb30", + }, +}; + static struct clk_regmap *gcc_apq8084_clocks[] = { [GPLL0] = &gpll0.clkr, [GPLL0_VOTE] = &gpll0_vote, @@ -3452,6 +3481,13 @@ static struct clk_regmap *gcc_apq8084_clocks[] = { [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, }; +static struct gdsc *gcc_apq8084_gdscs[] = { + [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, + [PCIE0_GDSC] = &pcie0_gdsc, + [PCIE1_GDSC] = &pcie1_gdsc, + [USB30_GDSC] = &usb30_gdsc, +}; + static const struct qcom_reset_map gcc_apq8084_resets[] = { [GCC_SYSTEM_NOC_BCR] = { 0x0100 }, [GCC_CONFIG_NOC_BCR] = { 0x0140 }, @@ -3560,6 +3596,8 @@ static const struct qcom_cc_desc gcc_apq8084_desc = { .num_clks = ARRAY_SIZE(gcc_apq8084_clocks), .resets = gcc_apq8084_resets, .num_resets = ARRAY_SIZE(gcc_apq8084_resets), + .gdscs = gcc_apq8084_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs), }; static const struct of_device_id gcc_apq8084_match_table[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-apq8084.h b/include/dt-bindings/clock/qcom,gcc-apq8084.h index 2c0da56..5aa7ebe 100644 --- a/include/dt-bindings/clock/qcom,gcc-apq8084.h +++ b/include/dt-bindings/clock/qcom,gcc-apq8084.h @@ -348,4 +348,10 @@ #define GCC_PCIE_1_PIPE_CLK 331 #define GCC_PCIE_1_SLV_AXI_CLK 332 +/* gdscs */ +#define USB_HS_HSIC_GDSC 0 +#define PCIE0_GDSC 1 +#define PCIE1_GDSC 2 +#define USB30_GDSC 3 + #endif -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: rnayak@codeaurora.org (Rajendra Nayak) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 6/8] clk: qcom: gdsc: Add GDSCs in apq8084 GCC Date: Thu, 26 Mar 2015 14:50:17 +0530 [thread overview] Message-ID: <1427361619-20360-7-git-send-email-rnayak@codeaurora.org> (raw) In-Reply-To: <1427361619-20360-1-git-send-email-rnayak@codeaurora.org> Add the GDSC instances that exist as part of apq8084 GCC block Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> --- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-apq8084.c | 38 ++++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-apq8084.h | 6 +++++ 3 files changed, 45 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 104ec0c..c246417 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -6,6 +6,7 @@ config COMMON_CLK_QCOM config APQ_GCC_8084 tristate "APQ8084 Global Clock Controller" + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the global clock controller on apq8084 devices. diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c index f75b505..6fafc2a 100644 --- a/drivers/clk/qcom/gcc-apq8084.c +++ b/drivers/clk/qcom/gcc-apq8084.c @@ -31,6 +31,7 @@ #include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum { P_XO, @@ -3259,6 +3260,34 @@ static struct clk_branch gcc_usb_hsic_system_clk = { }, }; +static struct gdsc usb_hs_hsic_gdsc = { + .gdscr = 0x404, + .pd = { + .name = "usb_hs_hsic", + }, +}; + +static struct gdsc pcie0_gdsc = { + .gdscr = 0x1ac4, + .pd = { + .name = "pcie0", + }, +}; + +static struct gdsc pcie1_gdsc = { + .gdscr = 0x1b44, + .pd = { + .name = "pcie1", + }, +}; + +static struct gdsc usb30_gdsc = { + .gdscr = 0x1e84, + .pd = { + .name = "usb30", + }, +}; + static struct clk_regmap *gcc_apq8084_clocks[] = { [GPLL0] = &gpll0.clkr, [GPLL0_VOTE] = &gpll0_vote, @@ -3452,6 +3481,13 @@ static struct clk_regmap *gcc_apq8084_clocks[] = { [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, }; +static struct gdsc *gcc_apq8084_gdscs[] = { + [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, + [PCIE0_GDSC] = &pcie0_gdsc, + [PCIE1_GDSC] = &pcie1_gdsc, + [USB30_GDSC] = &usb30_gdsc, +}; + static const struct qcom_reset_map gcc_apq8084_resets[] = { [GCC_SYSTEM_NOC_BCR] = { 0x0100 }, [GCC_CONFIG_NOC_BCR] = { 0x0140 }, @@ -3560,6 +3596,8 @@ static const struct qcom_cc_desc gcc_apq8084_desc = { .num_clks = ARRAY_SIZE(gcc_apq8084_clocks), .resets = gcc_apq8084_resets, .num_resets = ARRAY_SIZE(gcc_apq8084_resets), + .gdscs = gcc_apq8084_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs), }; static const struct of_device_id gcc_apq8084_match_table[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-apq8084.h b/include/dt-bindings/clock/qcom,gcc-apq8084.h index 2c0da56..5aa7ebe 100644 --- a/include/dt-bindings/clock/qcom,gcc-apq8084.h +++ b/include/dt-bindings/clock/qcom,gcc-apq8084.h @@ -348,4 +348,10 @@ #define GCC_PCIE_1_PIPE_CLK 331 #define GCC_PCIE_1_SLV_AXI_CLK 332 +/* gdscs */ +#define USB_HS_HSIC_GDSC 0 +#define PCIE0_GDSC 1 +#define PCIE1_GDSC 2 +#define USB30_GDSC 3 + #endif -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2015-03-26 9:20 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-03-26 9:20 [PATCH v4 0/8] Add support for QCOM GDSCs Rajendra Nayak 2015-03-26 9:20 ` Rajendra Nayak 2015-03-26 9:20 ` [PATCH v4 1/8] clk: qcom: Add support for GDSCs Rajendra Nayak 2015-03-26 9:20 ` Rajendra Nayak 2015-03-26 9:20 ` [PATCH v4 2/8] clk: qcom: gdsc: Prepare common clk probe to register gdscs Rajendra Nayak 2015-03-26 9:20 ` Rajendra Nayak 2015-03-26 9:20 ` [PATCH v4 3/8] clk: qcom: gdsc: Add GDSCs in msm8916 GCC Rajendra Nayak 2015-03-26 9:20 ` Rajendra Nayak 2015-03-26 9:20 ` [PATCH v4 4/8] clk: qcom: gdsc: Add GDSCs in msm8974 GCC Rajendra Nayak 2015-03-26 9:20 ` Rajendra Nayak 2015-03-26 9:20 ` [PATCH v4 5/8] clk: qcom: gdsc: Add GDSCs in msm8974 MMCC Rajendra Nayak 2015-03-26 9:20 ` Rajendra Nayak 2015-03-26 9:20 ` Rajendra Nayak [this message] 2015-03-26 9:20 ` [PATCH v4 6/8] clk: qcom: gdsc: Add GDSCs in apq8084 GCC Rajendra Nayak 2015-03-26 9:20 ` [PATCH v4 7/8] clk: qcom: gdsc: Add GDSCs in apq8084 MMCC Rajendra Nayak 2015-03-26 9:20 ` Rajendra Nayak 2015-03-26 9:20 ` [PATCH v4 8/8] arm: dts: qcom: Add #power-domain-cells property Rajendra Nayak 2015-03-26 9:20 ` Rajendra Nayak
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1427361619-20360-7-git-send-email-rnayak@codeaurora.org \ --to=rnayak@codeaurora.org \ --cc=georgi.djakov@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-arm-msm@vger.kernel.org \ --cc=mturquette@linaro.org \ --cc=sboyd@codeaurora.org \ --cc=srinivas.kandagatla@linaro.org \ --cc=svarbanov@mm-sol.com \ --cc=sviau@codeaurora.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.