* [PATCH 1/8] tools/intel_bios_reader: fix SSC freq for VLV/CHV
2015-03-31 17:32 [PATCH 0/8] igt: add basic Broxton support Imre Deak
@ 2015-03-31 17:32 ` Imre Deak
2015-03-31 17:32 ` [PATCH 2/8] lib/intel_chipset: fix HAS_PCH_SPLIT on CHV Imre Deak
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Imre Deak @ 2015-03-31 17:32 UTC (permalink / raw)
To: intel-gfx
VLV/CHV has a fixed 100MHz SSC reference frequency.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
tools/intel_bios_reader.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tools/intel_bios_reader.c b/tools/intel_bios_reader.c
index 4fa47a9..8704cdf 100644
--- a/tools/intel_bios_reader.c
+++ b/tools/intel_bios_reader.c
@@ -153,7 +153,9 @@ static void dump_general_features(const struct bdb_block *block)
printf("\tExternal VBT: %s\n", YESNO(features->download_ext_vbt));
printf("\tEnable SSC: %s\n", YESNO(features->enable_ssc));
if (features->enable_ssc) {
- if (HAS_PCH_SPLIT(devid))
+ if (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid))
+ printf("\tSSC frequency: 100 MHz\n");
+ else if (HAS_PCH_SPLIT(devid))
printf("\tSSC frequency: %s\n", features->ssc_freq ?
"100 MHz" : "120 MHz");
else
--
2.1.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/8] lib/intel_chipset: fix HAS_PCH_SPLIT on CHV
2015-03-31 17:32 [PATCH 0/8] igt: add basic Broxton support Imre Deak
2015-03-31 17:32 ` [PATCH 1/8] tools/intel_bios_reader: fix SSC freq for VLV/CHV Imre Deak
@ 2015-03-31 17:32 ` Imre Deak
2015-03-31 17:32 ` [PATCH 3/8] lib/intel_chipset: fix HAS_PCH_SPLIT on GEN9 Imre Deak
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Imre Deak @ 2015-03-31 17:32 UTC (permalink / raw)
To: intel-gfx
CherryView is GEN8 but doesn't have PCH so fix the macro accordingly.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
lib/intel_chipset.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index bd1b9ed..bccbb8e 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -419,7 +419,7 @@ void intel_check_pch(void);
#define HAS_PCH_SPLIT(devid) (IS_GEN5(devid) || \
IS_GEN6(devid) || \
IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
- IS_GEN8(devid) || \
+ IS_BROADWELL(devid) || \
IS_GEN9(devid))
#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \
--
2.1.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/8] lib/intel_chipset: fix HAS_PCH_SPLIT on GEN9
2015-03-31 17:32 [PATCH 0/8] igt: add basic Broxton support Imre Deak
2015-03-31 17:32 ` [PATCH 1/8] tools/intel_bios_reader: fix SSC freq for VLV/CHV Imre Deak
2015-03-31 17:32 ` [PATCH 2/8] lib/intel_chipset: fix HAS_PCH_SPLIT on CHV Imre Deak
@ 2015-03-31 17:32 ` Imre Deak
2015-03-31 17:32 ` [PATCH 4/8] lib/bxt: Add Broxton PCI ids Imre Deak
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Imre Deak @ 2015-03-31 17:32 UTC (permalink / raw)
To: intel-gfx
In the next patch we'll add support for BXT which is GEN9, but doesn't
have PCH, so fix the macro accordingly.
No functional change.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
lib/intel_chipset.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index bccbb8e..3c66744 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -420,7 +420,7 @@ void intel_check_pch(void);
IS_GEN6(devid) || \
IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
IS_BROADWELL(devid) || \
- IS_GEN9(devid))
+ IS_SKYLAKE(devid))
#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \
IS_GEN7(devid) || \
--
2.1.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/8] lib/bxt: Add Broxton PCI ids
2015-03-31 17:32 [PATCH 0/8] igt: add basic Broxton support Imre Deak
` (2 preceding siblings ...)
2015-03-31 17:32 ` [PATCH 3/8] lib/intel_chipset: fix HAS_PCH_SPLIT on GEN9 Imre Deak
@ 2015-03-31 17:32 ` Imre Deak
2015-03-31 17:32 ` [PATCH 5/8] list-workarounds/bxt: Add Broxton to the list of valid platorms Imre Deak
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Imre Deak @ 2015-03-31 17:32 UTC (permalink / raw)
To: intel-gfx
From: Damien Lespiau <damien.lespiau@intel.com>
v2: Rebase on top of the SKL upstreaming
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
lib/intel_chipset.h | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 3c66744..37554e6 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -206,6 +206,11 @@ void intel_check_pch(void);
#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A
#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
+#define PCI_CHIP_BROXTON_0 0x0A84
+#define PCI_CHIP_BROXTON_1 0x0A85
+#define PCI_CHIP_BROXTON_2 0x0A86
+#define PCI_CHIP_BROXTON_3 0x0A87
+
#endif /* __GTK_DOC_IGNORE__ */
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
@@ -390,7 +395,12 @@ void intel_check_pch(void);
IS_SKL_GT2(devid) || \
IS_SKL_GT3(devid))
-#define IS_GEN9(devid) IS_SKYLAKE(devid)
+#define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \
+ (devid) == PCI_CHIP_BROXTON_1 || \
+ (devid) == PCI_CHIP_BROXTON_2 || \
+ (devid) == PCI_CHIP_BROXTON_3)
+
+#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid))
#define IS_965(devid) (IS_GEN4(devid) || \
IS_GEN5(devid) || \
--
2.1.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/8] list-workarounds/bxt: Add Broxton to the list of valid platorms
2015-03-31 17:32 [PATCH 0/8] igt: add basic Broxton support Imre Deak
` (3 preceding siblings ...)
2015-03-31 17:32 ` [PATCH 4/8] lib/bxt: Add Broxton PCI ids Imre Deak
@ 2015-03-31 17:32 ` Imre Deak
2015-03-31 17:32 ` [PATCH 6/8] tools/intel_bios_read: fix SSC freq for BXT Imre Deak
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Imre Deak @ 2015-03-31 17:32 UTC (permalink / raw)
To: intel-gfx
From: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
scripts/list-workarounds | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/list-workarounds b/scripts/list-workarounds
index 620d02f..42af6a3 100755
--- a/scripts/list-workarounds
+++ b/scripts/list-workarounds
@@ -18,7 +18,7 @@ def find_nth(haystack, needle, n):
return start
valid_platforms = ('ctg', 'elk', 'ilk', 'snb', 'ivb', 'vlv', 'hsw', 'bdw',
- 'chv', 'skl')
+ 'chv', 'skl', 'bxt')
def parse_platforms(p):
l = p.split(',')
for p in l:
--
2.1.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 6/8] tools/intel_bios_read: fix SSC freq for BXT
2015-03-31 17:32 [PATCH 0/8] igt: add basic Broxton support Imre Deak
` (4 preceding siblings ...)
2015-03-31 17:32 ` [PATCH 5/8] list-workarounds/bxt: Add Broxton to the list of valid platorms Imre Deak
@ 2015-03-31 17:32 ` Imre Deak
2015-03-31 17:32 ` [PATCH 7/8] tools/intel_reg_dumper: fix DSPCNTR decode " Imre Deak
2015-03-31 17:32 ` [PATCH 8/8] tools/intel_reg_dumper: fix PIPECONF decode Imre Deak
7 siblings, 0 replies; 9+ messages in thread
From: Imre Deak @ 2015-03-31 17:32 UTC (permalink / raw)
To: intel-gfx
On BXT the SSC reference frequency is fixed 100MHz.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
tools/intel_bios_reader.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/intel_bios_reader.c b/tools/intel_bios_reader.c
index 8704cdf..0239095 100644
--- a/tools/intel_bios_reader.c
+++ b/tools/intel_bios_reader.c
@@ -153,7 +153,8 @@ static void dump_general_features(const struct bdb_block *block)
printf("\tExternal VBT: %s\n", YESNO(features->download_ext_vbt));
printf("\tEnable SSC: %s\n", YESNO(features->enable_ssc));
if (features->enable_ssc) {
- if (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid))
+ if (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid) ||
+ IS_BROXTON(devid))
printf("\tSSC frequency: 100 MHz\n");
else if (HAS_PCH_SPLIT(devid))
printf("\tSSC frequency: %s\n", features->ssc_freq ?
--
2.1.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 7/8] tools/intel_reg_dumper: fix DSPCNTR decode for BXT
2015-03-31 17:32 [PATCH 0/8] igt: add basic Broxton support Imre Deak
` (5 preceding siblings ...)
2015-03-31 17:32 ` [PATCH 6/8] tools/intel_bios_read: fix SSC freq for BXT Imre Deak
@ 2015-03-31 17:32 ` Imre Deak
2015-03-31 17:32 ` [PATCH 8/8] tools/intel_reg_dumper: fix PIPECONF decode Imre Deak
7 siblings, 0 replies; 9+ messages in thread
From: Imre Deak @ 2015-03-31 17:32 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
tools/intel_reg_dumper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index 0b6d887..d539f96 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -138,7 +138,7 @@ DEBUGSTRING(i830_debug_dspcntr)
{
const char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled";
char plane = val & DISPPLANE_SEL_PIPE_B ? 'B' : 'A';
- if (HAS_PCH_SPLIT(devid))
+ if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid))
snprintf(result, len, "%s", enabled);
else
snprintf(result, len, "%s, pipe %c", enabled, plane);
--
2.1.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 8/8] tools/intel_reg_dumper: fix PIPECONF decode
2015-03-31 17:32 [PATCH 0/8] igt: add basic Broxton support Imre Deak
` (6 preceding siblings ...)
2015-03-31 17:32 ` [PATCH 7/8] tools/intel_reg_dumper: fix DSPCNTR decode " Imre Deak
@ 2015-03-31 17:32 ` Imre Deak
7 siblings, 0 replies; 9+ messages in thread
From: Imre Deak @ 2015-03-31 17:32 UTC (permalink / raw)
To: intel-gfx
Decode the register for BXT too and don't decode rotation and bpc on
platforms where these fields are not defined.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
tools/intel_reg_dumper.c | 82 +++++++++++++++++++++++++++++-------------------
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index d539f96..f03ab35 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -155,10 +155,17 @@ DEBUGSTRING(i830_debug_pipeconf)
bit30 =
val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide";
- if (HAS_PCH_SPLIT(devid)) {
+ if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid)) {
const char *bpc, *rotation;
+ int interlace_mode;
- switch ((val >> 21) & 7) {
+ if ((IS_IVYBRIDGE(devid) || IS_HASWELL(devid) ||
+ IS_BROADWELL(devid) || IS_GEN9(devid)))
+ interlace_mode = (val >> 21) & 3;
+ else
+ interlace_mode = (val >> 21) & 7;
+
+ switch (interlace_mode) {
case 0:
interlace = "pf-pd";
break;
@@ -179,40 +186,49 @@ DEBUGSTRING(i830_debug_pipeconf)
break;
}
- switch ((val >> 14) & 3) {
- case 0:
- rotation = "rotate 0";
- break;
- case 1:
- rotation = "rotate 90";
- break;
- case 2:
- rotation = "rotate 180";
- break;
- case 3:
- rotation = "rotate 270";
- break;
+ rotation = "";
+ if (IS_HASWELL(devid) || IS_IVYBRIDGE(devid) ||
+ IS_GEN6(devid) || IS_GEN5(devid)) {
+ switch ((val >> 14) & 3) {
+ case 0:
+ rotation = "rotate 0";
+ break;
+ case 1:
+ rotation = "rotate 90";
+ break;
+ case 2:
+ rotation = "rotate 180";
+ break;
+ case 3:
+ rotation = "rotate 270";
+ break;
+ }
}
- switch (val & (7 << 5)) {
- case PIPECONF_8BPP:
- bpc = "8bpc";
- break;
- case PIPECONF_10BPP:
- bpc = "10bpc";
- break;
- case PIPECONF_6BPP:
- bpc = "6bpc";
- break;
- case PIPECONF_12BPP:
- bpc = "12bpc";
- break;
- default:
- bpc = "invalid bpc";
- break;
+ bpc = "";
+ if (IS_IVYBRIDGE(devid) || IS_GEN6(devid) || IS_GEN5(devid)) {
+ switch (val & (7 << 5)) {
+ case PIPECONF_8BPP:
+ bpc = "8bpc";
+ break;
+ case PIPECONF_10BPP:
+ bpc = "10bpc";
+ break;
+ case PIPECONF_6BPP:
+ bpc = "6bpc";
+ break;
+ case PIPECONF_12BPP:
+ bpc = "12bpc";
+ break;
+ default:
+ bpc = "invalid bpc";
+ break;
+ }
}
- snprintf(result, len, "%s, %s, %s, %s, %s", enabled, bit30,
- interlace, rotation, bpc);
+ snprintf(result, len, "%s, %s, %s, %s%s%s", enabled, bit30,
+ interlace,
+ rotation, rotation[0] ? ", " : "",
+ bpc);
} else if (IS_GEN4(devid)) {
switch ((val >> 21) & 7) {
case 0:
--
2.1.0
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