* [U-Boot] [PATCH v2 1/4] ARM: atmel: arm926ejs: fix clock configuration
2015-03-27 6:23 [U-Boot] [PATCH v2 0/4] ARM: atmel: boards: enable SPL support Bo Shen
@ 2015-03-27 6:23 ` Bo Shen
2015-03-31 23:06 ` [U-Boot] [U-Boot,v2,1/4] " Andreas Bießmann
2015-03-27 6:23 ` [U-Boot] [PATCH v2 2/4] ARM: atmel: at91sam9m10g45ek: enable spl support Bo Shen
` (2 subsequent siblings)
3 siblings, 1 reply; 15+ messages in thread
From: Bo Shen @ 2015-03-27 6:23 UTC (permalink / raw)
To: u-boot
Config MCKR according to the datasheet sequence, or else it
will cause the MCKR configuration failed.
Remove timeout checking for clock configuration, if configure
the clock failed, let the system hang while not run in wrong
clock configuration.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
---
Changes in v2: None
arch/arm/mach-at91/arm926ejs/clock.c | 54 +++++++++++++++++++-----------------
1 file changed, 28 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
index f363982..8d6934e 100644
--- a/arch/arm/mach-at91/arm926ejs/clock.c
+++ b/arch/arm/mach-at91/arm926ejs/clock.c
@@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock)
void at91_plla_init(u32 pllar)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- int timeout = AT91_PLL_LOCK_TIMEOUT;
writel(pllar, &pmc->pllar);
- while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
- timeout--;
- if (timeout == 0)
- break;
- }
+ while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
+ ;
}
void at91_pllb_init(u32 pllbr)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- int timeout = AT91_PLL_LOCK_TIMEOUT;
writel(pllbr, &pmc->pllbr);
- while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
- timeout--;
- if (timeout == 0)
- break;
- }
+ while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
+ ;
}
void at91_mck_init(u32 mckr)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- int timeout = AT91_PLL_LOCK_TIMEOUT;
u32 tmp;
tmp = readl(&pmc->mckr);
- tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
- AT91_PMC_MCKR_MDIV_MASK |
- AT91_PMC_MCKR_PLLADIV_MASK |
- AT91_PMC_MCKR_CSS_MASK);
- tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
- AT91_PMC_MCKR_MDIV_MASK |
- AT91_PMC_MCKR_PLLADIV_MASK |
- AT91_PMC_MCKR_CSS_MASK);
+ tmp &= ~AT91_PMC_MCKR_PRES_MASK;
+ tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
writel(tmp, &pmc->mckr);
+ while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+ ;
- while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
- timeout--;
- if (timeout == 0)
- break;
- }
+ tmp = readl(&pmc->mckr);
+ tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
+ tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
+ writel(tmp, &pmc->mckr);
+ while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+ ;
+
+ tmp = readl(&pmc->mckr);
+ tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
+ tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
+ writel(tmp, &pmc->mckr);
+ while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+ ;
+
+ tmp = readl(&pmc->mckr);
+ tmp &= ~AT91_PMC_MCKR_CSS_MASK;
+ tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
+ writel(tmp, &pmc->mckr);
+ while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+ ;
}
void at91_periph_clk_enable(int id)
--
2.3.3.220.g9ab698f
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [U-Boot,v2,1/4] ARM: atmel: arm926ejs: fix clock configuration
2015-03-27 6:23 ` [U-Boot] [PATCH v2 1/4] ARM: atmel: arm926ejs: fix clock configuration Bo Shen
@ 2015-03-31 23:06 ` Andreas Bießmann
0 siblings, 0 replies; 15+ messages in thread
From: Andreas Bießmann @ 2015-03-31 23:06 UTC (permalink / raw)
To: u-boot
Dear Bo Shen,
Bo Shen <voice.shen@atmel.com> writes:
>Config MCKR according to the datasheet sequence, or else it
>will cause the MCKR configuration failed.
>
>Remove timeout checking for clock configuration, if configure
>the clock failed, let the system hang while not run in wrong
>clock configuration.
>
>Signed-off-by: Bo Shen <voice.shen@atmel.com>
>Tested-by: Heiko Schocher <hs@denx.de>
>---
>
>Changes in v2: None
>
> arch/arm/mach-at91/arm926ejs/clock.c | 54 +++++++++++++++++++-----------------
> 1 file changed, 28 insertions(+), 26 deletions(-)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v2 2/4] ARM: atmel: at91sam9m10g45ek: enable spl support
2015-03-27 6:23 [U-Boot] [PATCH v2 0/4] ARM: atmel: boards: enable SPL support Bo Shen
2015-03-27 6:23 ` [U-Boot] [PATCH v2 1/4] ARM: atmel: arm926ejs: fix clock configuration Bo Shen
@ 2015-03-27 6:23 ` Bo Shen
2015-03-31 23:06 ` [U-Boot] [U-Boot,v2,2/4] " Andreas Bießmann
2015-03-27 6:23 ` [U-Boot] [PATCH v2 3/4] ARM: atmel: at91sam9x5ek: " Bo Shen
2015-03-27 6:23 ` [U-Boot] [PATCH v2 4/4] ARM: atmel: at91sam9n12ek: " Bo Shen
3 siblings, 1 reply; 15+ messages in thread
From: Bo Shen @ 2015-03-27 6:23 UTC (permalink / raw)
To: u-boot
Supports boot up from NAND flash with software ECC eanbled.
And supports boot up from SD/MMC card with FAT file system.
As the boot from SD/MMC card with FAT file system, the BSS
segment is too big to fit into SRAM, so, use the lds to put
it into SDRAM.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
---
Changes in v2:
- Remove the meaningless prefix "+S:" in configuration file.
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 48 +++++++++++++++
arch/arm/mach-at91/spl_at91.c | 6 +-
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 80 +++++++++++++++++++++++++
configs/at91sam9m10g45ek_mmc_defconfig | 1 +
configs/at91sam9m10g45ek_nandflash_defconfig | 1 +
include/configs/at91sam9m10g45ek.h | 58 ++++++++++++++++++
7 files changed, 194 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 30945c1..25da926 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -66,6 +66,7 @@ config TARGET_STAMP9G20
config TARGET_AT91SAM9M10G45EK
bool "Atmel AT91SAM9M10G45-EK board"
select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_PM9G45
bool "Ronetix pm9g45 board"
diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
new file mode 100644
index 0000000..acadd1d
--- /dev/null
+++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ *(.vectors)
+ arch/arm/cpu/arm926ejs/start.o (.text*)
+ *(.text*)
+ } >.sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+
+ .end :
+ {
+ *(.__end)
+ } >.sram
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } >.sdram
+}
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index 89f588b..af6fc0d 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -71,7 +71,11 @@ void __weak at91_spl_board_init(void)
{
}
-void spl_board_init(void)
+void __weak spl_board_init(void)
+{
+}
+
+void board_init_f(ulong dummy)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index b807ef9..4289179 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/clk.h>
#include <asm/arch/at91sam9g45_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
@@ -15,6 +16,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
+#include <linux/mtd/nand.h>
#include <atmel_lcdc.h>
#include <atmel_mci.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -71,6 +73,84 @@ void at91sam9m10g45ek_nand_hw_init(void)
}
#endif
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+ /*
+ * On the at91sam9m10g45ek board, the chip wm9711 stays in the
+ * test mode, so it needs do some action to exit test mode.
+ */
+ at91_periph_clk_enable(ATMEL_ID_PIODE);
+ at91_set_gpio_output(AT91_PIN_PD7, 0);
+ at91_set_gpio_output(AT91_PIN_PD8, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
+
+#ifdef CONFIG_SYS_USE_MMC
+ at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+ at91sam9m10g45ek_nand_hw_init();
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_14 |
+ ATMEL_MPDDRC_CR_DQMS_SHARED |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+
+ ddr2->rtr = 0x24b;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+ 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+ 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct atmel_mpddr ddr2;
+ unsigned long csa;
+
+ ddr2_conf(&ddr2);
+
+ /* enable DDR2 clock */
+ writel(0x4, &pmc->scer);
+
+ /* Chip select 1 is for DDR2/SDRAM */
+ csa = readl(&mat->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+ csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
+ writel(csa, &mat->ebicsa);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_CS6, &ddr2);
+}
+#endif
+
#ifdef CONFIG_CMD_USB
static void at91sam9m10g45ek_usb_hw_init(void)
{
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index 6949d3a..f3e1ebe 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index 30967e3..5e0b16e 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index db5d5ea..e4c49f4 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -203,4 +203,62 @@
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x300000
+#define CONFIG_SPL_MAX_SIZE 0x010000
+#define CONFIG_SPL_STACK 0x310000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+
+#ifdef CONFIG_SYS_USE_MMC
+
+#define CONFIG_SPL_BSS_START_ADDR 0x70000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
+#define CONFIG_SYS_SPL_MALLOC_START 0x70080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
+
+#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE 256
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+ 48, 49, 50, 51, 52, 53, 54, 55, \
+ 56, 57, 58, 59, 60, 61, 62, 63, }
+#endif
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CONFIG_SYS_AT91_PLLA 0x20c73f03
+#define CONFIG_SYS_MCKR 0x1301
+#define CONFIG_SYS_MCKR_CSS 0x1302
+
+#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
#endif
--
2.3.3.220.g9ab698f
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [U-Boot,v2,2/4] ARM: atmel: at91sam9m10g45ek: enable spl support
2015-03-27 6:23 ` [U-Boot] [PATCH v2 2/4] ARM: atmel: at91sam9m10g45ek: enable spl support Bo Shen
@ 2015-03-31 23:06 ` Andreas Bießmann
0 siblings, 0 replies; 15+ messages in thread
From: Andreas Bießmann @ 2015-03-31 23:06 UTC (permalink / raw)
To: u-boot
Dear Bo Shen,
Bo Shen <voice.shen@atmel.com> writes:
>Supports boot up from NAND flash with software ECC eanbled.
>And supports boot up from SD/MMC card with FAT file system.
>
>As the boot from SD/MMC card with FAT file system, the BSS
>segment is too big to fit into SRAM, so, use the lds to put
>it into SDRAM.
>
>Signed-off-by: Bo Shen <voice.shen@atmel.com>
>---
>
>Changes in v2:
> - Remove the meaningless prefix "+S:" in configuration file.
>
> arch/arm/mach-at91/Kconfig | 1 +
> arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 48 +++++++++++++++
> arch/arm/mach-at91/spl_at91.c | 6 +-
> board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 80 +++++++++++++++++++++++++
> configs/at91sam9m10g45ek_mmc_defconfig | 1 +
> configs/at91sam9m10g45ek_nandflash_defconfig | 1 +
> include/configs/at91sam9m10g45ek.h | 58 ++++++++++++++++++
> 7 files changed, 194 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v2 3/4] ARM: atmel: at91sam9x5ek: enable spl support
2015-03-27 6:23 [U-Boot] [PATCH v2 0/4] ARM: atmel: boards: enable SPL support Bo Shen
2015-03-27 6:23 ` [U-Boot] [PATCH v2 1/4] ARM: atmel: arm926ejs: fix clock configuration Bo Shen
2015-03-27 6:23 ` [U-Boot] [PATCH v2 2/4] ARM: atmel: at91sam9m10g45ek: enable spl support Bo Shen
@ 2015-03-27 6:23 ` Bo Shen
2015-03-31 23:06 ` [U-Boot] [U-Boot,v2,3/4] " Andreas Bießmann
2019-02-19 13:27 ` [U-Boot] [PATCH v2 3/4] " Stefan Roese
2015-03-27 6:23 ` [U-Boot] [PATCH v2 4/4] ARM: atmel: at91sam9n12ek: " Bo Shen
3 siblings, 2 replies; 15+ messages in thread
From: Bo Shen @ 2015-03-27 6:23 UTC (permalink / raw)
To: u-boot
Enable SPL support for at91sam9x5ek board. Now, it supports
boot up from NAND flash and SPI flash.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
---
Changes in v2:
- Remove the meaningless prefix "+S:" in configuration file.
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/include/mach/at91_pmc.h | 6 ++-
arch/arm/mach-at91/include/mach/at91sam9x5.h | 10 ++++
arch/arm/mach-at91/mpddrc.c | 3 +-
arch/arm/mach-at91/spl.c | 2 +-
arch/arm/mach-at91/spl_at91.c | 5 ++
board/atmel/at91sam9x5ek/at91sam9x5ek.c | 74 ++++++++++++++++++++++++++++
configs/at91sam9x5ek_nandflash_defconfig | 1 +
configs/at91sam9x5ek_spiflash_defconfig | 1 +
include/configs/at91sam9x5ek.h | 57 +++++++++++++++++++++
11 files changed, 157 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 25da926..bdf87f9 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -83,6 +83,7 @@ config TARGET_AT91SAM9RLEK
config TARGET_AT91SAM9X5EK
bool "Atmel AT91SAM9X5-EK board"
select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_SAMA5D3_XPLAINED
bool "SAMA5D3 Xplained board"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index e596ba6..ba83616 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
ifneq ($(CONFIG_SPL_BUILD),)
obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
+obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
obj-y += spl.o
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 65691ab..c903260 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -97,7 +97,8 @@ typedef struct at91_pmc {
#define AT91_PMC_MCKR_CSS_PLLB 0x00000003
#define AT91_PMC_MCKR_CSS_MASK 0x00000003
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+ defined(CONFIG_AT91SAM9X5)
#define AT91_PMC_MCKR_PRES_1 0x00000000
#define AT91_PMC_MCKR_PRES_2 0x00000010
#define AT91_PMC_MCKR_PRES_4 0x00000020
@@ -126,7 +127,8 @@ typedef struct at91_pmc {
#else
#define AT91_PMC_MCKR_MDIV_1 0x00000000
#define AT91_PMC_MCKR_MDIV_2 0x00000100
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+ defined(CONFIG_AT91SAM9X5)
#define AT91_PMC_MCKR_MDIV_3 0x00000300
#endif
#define AT91_PMC_MCKR_MDIV_4 0x00000200
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 36a5cdf..d18c936 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -124,6 +124,16 @@
#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
#endif
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x10000000
+#define ATMEL_BASE_CS1 0x20000000
+#define ATMEL_BASE_CS2 0x30000000
+#define ATMEL_BASE_CS3 0x40000000
+#define ATMEL_BASE_CS4 0x50000000
+#define ATMEL_BASE_CS5 0x60000000
+
/* 9x5 series chip id definitions */
#define ARCH_ID_AT91SAM9X5 0x819a05a0
#define ARCH_ID_VERSION_MASK 0x1f
diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
index beec13d..24d5fcd 100644
--- a/arch/arm/mach-at91/mpddrc.c
+++ b/arch/arm/mach-at91/mpddrc.c
@@ -19,7 +19,8 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
static int ddr2_decodtype_is_seq(u32 cr)
{
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+ defined(CONFIG_AT91SAM9X5)
if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
return 0;
#endif
diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
index aaa5eec..27a405a 100644
--- a/arch/arm/mach-at91/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -29,7 +29,7 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_MMC1;
#elif CONFIG_SYS_USE_NANDFLASH
return BOOT_DEVICE_NAND;
-#elif CONFIG_SYS_USE_SERIALFLASH
+#elif CONFIG_SYS_USE_SERIALFLASH || CONFIG_SYS_USE_SPIFLASH
return BOOT_DEVICE_SPI;
#endif
return BOOT_DEVICE_NONE;
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index af6fc0d..e28e568 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -115,9 +115,14 @@ void board_init_f(ulong dummy)
timer_init();
/* enable clocks for all PIOs */
+#ifdef CONFIG_AT91SAM9X5
+ at91_periph_clk_enable(ATMEL_ID_PIOAB);
+ at91_periph_clk_enable(ATMEL_ID_PIOCD);
+#else
at91_periph_clk_enable(ATMEL_ID_PIOA);
at91_periph_clk_enable(ATMEL_ID_PIOB);
at91_periph_clk_enable(ATMEL_ID_PIOC);
+#endif
/* init console */
at91_seriald_hw_init();
preloader_console_init();
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 17a2a40..114ac5c 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -293,3 +293,77 @@ int dram_init(void)
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+ at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+ at91sam9x5ek_nand_hw_init();
+#elif CONFIG_SYS_USE_SPIFLASH
+ at91_spi0_hw_init(1 << 4);
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct atmel_mpddr ddr2;
+ unsigned long csa;
+
+ ddr2_conf(&ddr2);
+
+ /* enable DDR2 clock */
+ writel(0x4, &pmc->scer);
+
+ /* Chip select 1 is for DDR2/SDRAM */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+ csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+ csa |= AT91_MATRIX_EBI_DBPD_OFF;
+ csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+ writel(csa, &matrix->ebicsa);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_CS1, &ddr2);
+}
+#endif
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index c2ebb00..6eea1af 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index 76f68a6..7ef1534 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 6d8b71d..1a481b3 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -243,4 +243,61 @@
*/
#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x300000
+#define CONFIG_SPL_MAX_SIZE 0x6000
+#define CONFIG_SPL_STACK 0x308000
+
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CONFIG_SYS_AT91_PLLA 0x20c73f03
+#define CONFIG_SYS_MCKR 0x1301
+#define CONFIG_SYS_MCKR_CSS 0x1302
+
+#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+
+#elif CONFIG_SYS_USE_SPIFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
+
+#endif
+
#endif
--
2.3.3.220.g9ab698f
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [U-Boot,v2,3/4] ARM: atmel: at91sam9x5ek: enable spl support
2015-03-27 6:23 ` [U-Boot] [PATCH v2 3/4] ARM: atmel: at91sam9x5ek: " Bo Shen
@ 2015-03-31 23:06 ` Andreas Bießmann
2019-02-19 13:27 ` [U-Boot] [PATCH v2 3/4] " Stefan Roese
1 sibling, 0 replies; 15+ messages in thread
From: Andreas Bießmann @ 2015-03-31 23:06 UTC (permalink / raw)
To: u-boot
Dear Bo Shen,
Bo Shen <voice.shen@atmel.com> writes:
>Enable SPL support for at91sam9x5ek board. Now, it supports
>boot up from NAND flash and SPI flash.
>
>Signed-off-by: Bo Shen <voice.shen@atmel.com>
>---
>
>Changes in v2:
> - Remove the meaningless prefix "+S:" in configuration file.
>
> arch/arm/mach-at91/Kconfig | 1 +
> arch/arm/mach-at91/Makefile | 1 +
> arch/arm/mach-at91/include/mach/at91_pmc.h | 6 ++-
> arch/arm/mach-at91/include/mach/at91sam9x5.h | 10 ++++
> arch/arm/mach-at91/mpddrc.c | 3 +-
> arch/arm/mach-at91/spl.c | 2 +-
> arch/arm/mach-at91/spl_at91.c | 5 ++
> board/atmel/at91sam9x5ek/at91sam9x5ek.c | 74 ++++++++++++++++++++++++++++
> configs/at91sam9x5ek_nandflash_defconfig | 1 +
> configs/at91sam9x5ek_spiflash_defconfig | 1 +
> include/configs/at91sam9x5ek.h | 57 +++++++++++++++++++++
> 11 files changed, 157 insertions(+), 4 deletions(-)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v2 3/4] ARM: atmel: at91sam9x5ek: enable spl support
2015-03-27 6:23 ` [U-Boot] [PATCH v2 3/4] ARM: atmel: at91sam9x5ek: " Bo Shen
2015-03-31 23:06 ` [U-Boot] [U-Boot,v2,3/4] " Andreas Bießmann
@ 2019-02-19 13:27 ` Stefan Roese
2019-02-19 14:12 ` Eugen.Hristev at microchip.com
1 sibling, 1 reply; 15+ messages in thread
From: Stefan Roese @ 2019-02-19 13:27 UTC (permalink / raw)
To: u-boot
Hi Eugene,
Hi Bo,
On 27.03.15 07:23, Bo Shen wrote:
> Enable SPL support for at91sam9x5ek board. Now, it supports
> boot up from NAND flash and SPI flash.
>
> Signed-off-by: Bo Shen <voice.shen@atmel.com>
Sorry to hijack this thread, but I do have a few questions here.
I'm currently working on a mainline port for a custom board
based on the CORE9G25 SoM [1] and would like to use U-Boot SPL
instead of AT91Bootstrap. In this email, you "enable spl support"
as stated in the commit subject, but CONFIG_SPL is not enabled
for this board at any time. So only the code is present to e.g.
init the DDR2 but its actually not executed. Or am I missing
something here.
Could you please let me know, what the status of this SPL
support for the AT91SAM9X5 is? Has this been tested without
AT91Bootstrap lately?
Thanks,
Stefan
[1] www.armdevs.com/CORE9G25.html
> ---
>
> Changes in v2:
> - Remove the meaningless prefix "+S:" in configuration file.
>
> arch/arm/mach-at91/Kconfig | 1 +
> arch/arm/mach-at91/Makefile | 1 +
> arch/arm/mach-at91/include/mach/at91_pmc.h | 6 ++-
> arch/arm/mach-at91/include/mach/at91sam9x5.h | 10 ++++
> arch/arm/mach-at91/mpddrc.c | 3 +-
> arch/arm/mach-at91/spl.c | 2 +-
> arch/arm/mach-at91/spl_at91.c | 5 ++
> board/atmel/at91sam9x5ek/at91sam9x5ek.c | 74 ++++++++++++++++++++++++++++
> configs/at91sam9x5ek_nandflash_defconfig | 1 +
> configs/at91sam9x5ek_spiflash_defconfig | 1 +
> include/configs/at91sam9x5ek.h | 57 +++++++++++++++++++++
> 11 files changed, 157 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index 25da926..bdf87f9 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -83,6 +83,7 @@ config TARGET_AT91SAM9RLEK
> config TARGET_AT91SAM9X5EK
> bool "Atmel AT91SAM9X5-EK board"
> select CPU_ARM926EJS
> + select SUPPORT_SPL
>
> config TARGET_SAMA5D3_XPLAINED
> bool "SAMA5D3 Xplained board"
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index e596ba6..ba83616 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -2,6 +2,7 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
> ifneq ($(CONFIG_SPL_BUILD),)
> obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
> obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
> +obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
> obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
> obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
> obj-y += spl.o
> diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
> index 65691ab..c903260 100644
> --- a/arch/arm/mach-at91/include/mach/at91_pmc.h
> +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
> @@ -97,7 +97,8 @@ typedef struct at91_pmc {
> #define AT91_PMC_MCKR_CSS_PLLB 0x00000003
> #define AT91_PMC_MCKR_CSS_MASK 0x00000003
>
> -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
> +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
> + defined(CONFIG_AT91SAM9X5)
> #define AT91_PMC_MCKR_PRES_1 0x00000000
> #define AT91_PMC_MCKR_PRES_2 0x00000010
> #define AT91_PMC_MCKR_PRES_4 0x00000020
> @@ -126,7 +127,8 @@ typedef struct at91_pmc {
> #else
> #define AT91_PMC_MCKR_MDIV_1 0x00000000
> #define AT91_PMC_MCKR_MDIV_2 0x00000100
> -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
> +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
> + defined(CONFIG_AT91SAM9X5)
> #define AT91_PMC_MCKR_MDIV_3 0x00000300
> #endif
> #define AT91_PMC_MCKR_MDIV_4 0x00000200
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> index 36a5cdf..d18c936 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> @@ -124,6 +124,16 @@
> #define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
> #endif
>
> +/*
> + * External memory
> + */
> +#define ATMEL_BASE_CS0 0x10000000
> +#define ATMEL_BASE_CS1 0x20000000
> +#define ATMEL_BASE_CS2 0x30000000
> +#define ATMEL_BASE_CS3 0x40000000
> +#define ATMEL_BASE_CS4 0x50000000
> +#define ATMEL_BASE_CS5 0x60000000
> +
> /* 9x5 series chip id definitions */
> #define ARCH_ID_AT91SAM9X5 0x819a05a0
> #define ARCH_ID_VERSION_MASK 0x1f
> diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
> index beec13d..24d5fcd 100644
> --- a/arch/arm/mach-at91/mpddrc.c
> +++ b/arch/arm/mach-at91/mpddrc.c
> @@ -19,7 +19,8 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
>
> static int ddr2_decodtype_is_seq(u32 cr)
> {
> -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
> +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
> + defined(CONFIG_AT91SAM9X5)
> if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
> return 0;
> #endif
> diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
> index aaa5eec..27a405a 100644
> --- a/arch/arm/mach-at91/spl.c
> +++ b/arch/arm/mach-at91/spl.c
> @@ -29,7 +29,7 @@ u32 spl_boot_device(void)
> return BOOT_DEVICE_MMC1;
> #elif CONFIG_SYS_USE_NANDFLASH
> return BOOT_DEVICE_NAND;
> -#elif CONFIG_SYS_USE_SERIALFLASH
> +#elif CONFIG_SYS_USE_SERIALFLASH || CONFIG_SYS_USE_SPIFLASH
> return BOOT_DEVICE_SPI;
> #endif
> return BOOT_DEVICE_NONE;
> diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
> index af6fc0d..e28e568 100644
> --- a/arch/arm/mach-at91/spl_at91.c
> +++ b/arch/arm/mach-at91/spl_at91.c
> @@ -115,9 +115,14 @@ void board_init_f(ulong dummy)
> timer_init();
>
> /* enable clocks for all PIOs */
> +#ifdef CONFIG_AT91SAM9X5
> + at91_periph_clk_enable(ATMEL_ID_PIOAB);
> + at91_periph_clk_enable(ATMEL_ID_PIOCD);
> +#else
> at91_periph_clk_enable(ATMEL_ID_PIOA);
> at91_periph_clk_enable(ATMEL_ID_PIOB);
> at91_periph_clk_enable(ATMEL_ID_PIOC);
> +#endif
> /* init console */
> at91_seriald_hw_init();
> preloader_console_init();
> diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
> index 17a2a40..114ac5c 100644
> --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
> +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
> @@ -293,3 +293,77 @@ int dram_init(void)
> CONFIG_SYS_SDRAM_SIZE);
> return 0;
> }
> +
> +#if defined(CONFIG_SPL_BUILD)
> +#include <spl.h>
> +#include <nand.h>
> +
> +void at91_spl_board_init(void)
> +{
> +#ifdef CONFIG_SYS_USE_MMC
> + at91_mci_hw_init();
> +#elif CONFIG_SYS_USE_NANDFLASH
> + at91sam9x5ek_nand_hw_init();
> +#elif CONFIG_SYS_USE_SPIFLASH
> + at91_spi0_hw_init(1 << 4);
> +#endif
> +}
> +
> +#include <asm/arch/atmel_mpddrc.h>
> +static void ddr2_conf(struct atmel_mpddr *ddr2)
> +{
> + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
> +
> + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
> + ATMEL_MPDDRC_CR_NR_ROW_13 |
> + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
> + ATMEL_MPDDRC_CR_NB_8BANKS |
> + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
> +
> + ddr2->rtr = 0x411;
> +
> + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
> + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
> +
> + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
> + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
> + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
> + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
> +
> + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
> + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
> + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
> +}
> +
> +void mem_init(void)
> +{
> + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
> + struct atmel_mpddr ddr2;
> + unsigned long csa;
> +
> + ddr2_conf(&ddr2);
> +
> + /* enable DDR2 clock */
> + writel(0x4, &pmc->scer);
> +
> + /* Chip select 1 is for DDR2/SDRAM */
> + csa = readl(&matrix->ebicsa);
> + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
> + csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
> + csa |= AT91_MATRIX_EBI_DBPD_OFF;
> + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
> + writel(csa, &matrix->ebicsa);
> +
> + /* DDRAM2 Controller initialize */
> + ddr2_init(ATMEL_BASE_CS1, &ddr2);
> +}
> +#endif
> diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
> index c2ebb00..6eea1af 100644
> --- a/configs/at91sam9x5ek_nandflash_defconfig
> +++ b/configs/at91sam9x5ek_nandflash_defconfig
> @@ -1,3 +1,4 @@
> +CONFIG_SPL=y
> CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
> CONFIG_ARM=y
> CONFIG_ARCH_AT91=y
> diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
> index 76f68a6..7ef1534 100644
> --- a/configs/at91sam9x5ek_spiflash_defconfig
> +++ b/configs/at91sam9x5ek_spiflash_defconfig
> @@ -1,3 +1,4 @@
> +CONFIG_SPL=y
> CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
> CONFIG_ARM=y
> CONFIG_ARCH_AT91=y
> diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
> index 6d8b71d..1a481b3 100644
> --- a/include/configs/at91sam9x5ek.h
> +++ b/include/configs/at91sam9x5ek.h
> @@ -243,4 +243,61 @@
> */
> #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
>
> +/* SPL */
> +#define CONFIG_SPL_FRAMEWORK
> +#define CONFIG_SPL_TEXT_BASE 0x300000
> +#define CONFIG_SPL_MAX_SIZE 0x6000
> +#define CONFIG_SPL_STACK 0x308000
> +
> +#define CONFIG_SPL_BSS_START_ADDR 0x20000000
> +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
> +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
> +
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_GPIO_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +
> +#define CONFIG_SPL_BOARD_INIT
> +#define CONFIG_SYS_MONITOR_LEN (512 << 10)
> +
> +#define CONFIG_SYS_MASTER_CLOCK 132096000
> +#define CONFIG_SYS_AT91_PLLA 0x20c73f03
> +#define CONFIG_SYS_MCKR 0x1301
> +#define CONFIG_SYS_MCKR_CSS 0x1302
> +
> +#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
> +
> +#ifdef CONFIG_SYS_USE_MMC
> +#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
> +#define CONFIG_SPL_MMC_SUPPORT
> +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
> +#define CONFIG_SPL_FAT_SUPPORT
> +#define CONFIG_SPL_LIBDISK_SUPPORT
> +
> +#elif CONFIG_SYS_USE_NANDFLASH
> +#define CONFIG_SPL_NAND_SUPPORT
> +#define CONFIG_SPL_NAND_DRIVERS
> +#define CONFIG_SPL_NAND_BASE
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
> +#define CONFIG_SYS_NAND_PAGE_COUNT 64
> +#define CONFIG_SYS_NAND_OOBSIZE 64
> +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
> +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
> +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
> +
> +#elif CONFIG_SYS_USE_SPIFLASH
> +#define CONFIG_SPL_SPI_SUPPORT
> +#define CONFIG_SPL_SPI_FLASH_SUPPORT
> +#define CONFIG_SPL_SPI_LOAD
> +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
> +
> +#endif
> +
> #endif
>
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
^ permalink raw reply [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 3/4] ARM: atmel: at91sam9x5ek: enable spl support
2019-02-19 13:27 ` [U-Boot] [PATCH v2 3/4] " Stefan Roese
@ 2019-02-19 14:12 ` Eugen.Hristev at microchip.com
2019-02-19 14:56 ` Stefan Roese
0 siblings, 1 reply; 15+ messages in thread
From: Eugen.Hristev at microchip.com @ 2019-02-19 14:12 UTC (permalink / raw)
To: u-boot
On 19.02.2019 15:27, Stefan Roese wrote:
> Hi Eugene,
> Hi Bo,
>
> On 27.03.15 07:23, Bo Shen wrote:
>> Enable SPL support for at91sam9x5ek board. Now, it supports
>> boot up from NAND flash and SPI flash.
>>
>> Signed-off-by: Bo Shen <voice.shen@atmel.com>
>
> Sorry to hijack this thread, but I do have a few questions here.
>
> I'm currently working on a mainline port for a custom board
> based on the CORE9G25 SoM [1] and would like to use U-Boot SPL
> instead of AT91Bootstrap. In this email, you "enable spl support"
> as stated in the commit subject, but CONFIG_SPL is not enabled
> for this board at any time. So only the code is present to e.g.
> init the DDR2 but its actually not executed. Or am I missing
> something here.
>
> Could you please let me know, what the status of this SPL
> support for the AT91SAM9X5 is? Has this been tested without
> AT91Bootstrap lately?
Hi,
I did not test myself the SPL for any 9x5 board. The DDR2 init code
should be executed inside the SPL. Once you build your board with a
CONFIG_SPL enabled, you should get the spl binary built, then you can
add both SPL + U-boot proper on the boot media and have SPL boot
(execute DDR init code and load U-boot proper). I would suggest to try
on Sd-card first because it's easier (filesystem), but the commit says
only SPI and NAND tested.
You can also look at the U-boot version which first included this patch,
some things may have changed since...
Let me know of your findings. I will let you know if I have the chance
to test this myself.
Eugen
>
> Thanks,
> Stefan
>
> [1] www.armdevs.com/CORE9G25.html
>
>> ---
[...]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v2 3/4] ARM: atmel: at91sam9x5ek: enable spl support
2019-02-19 14:12 ` Eugen.Hristev at microchip.com
@ 2019-02-19 14:56 ` Stefan Roese
2019-02-21 17:00 ` Stefan Roese
0 siblings, 1 reply; 15+ messages in thread
From: Stefan Roese @ 2019-02-19 14:56 UTC (permalink / raw)
To: u-boot
Hi Eugene,
On 19.02.19 15:12, Eugen.Hristev at microchip.com wrote:
> On 19.02.2019 15:27, Stefan Roese wrote:
>> Hi Eugene,
>> Hi Bo,
>>
>> On 27.03.15 07:23, Bo Shen wrote:
>>> Enable SPL support for at91sam9x5ek board. Now, it supports
>>> boot up from NAND flash and SPI flash.
>>>
>>> Signed-off-by: Bo Shen <voice.shen@atmel.com>
>>
>> Sorry to hijack this thread, but I do have a few questions here.
>>
>> I'm currently working on a mainline port for a custom board
>> based on the CORE9G25 SoM [1] and would like to use U-Boot SPL
>> instead of AT91Bootstrap. In this email, you "enable spl support"
>> as stated in the commit subject, but CONFIG_SPL is not enabled
>> for this board at any time. So only the code is present to e.g.
>> init the DDR2 but its actually not executed. Or am I missing
>> something here.
>>
>> Could you please let me know, what the status of this SPL
>> support for the AT91SAM9X5 is? Has this been tested without
>> AT91Bootstrap lately?
>
>
> Hi,
>
> I did not test myself the SPL for any 9x5 board. The DDR2 init code
> should be executed inside the SPL. Once you build your board with a
> CONFIG_SPL enabled, you should get the spl binary built, then you can
> add both SPL + U-boot proper on the boot media and have SPL boot
> (execute DDR init code and load U-boot proper). I would suggest to try
> on Sd-card first because it's easier (filesystem), but the commit says
> only SPI and NAND tested.
On this board I only have NAND, so there is no option to first test
some other boot device unfortunately.
> You can also look at the U-boot version which first included this patch,
> some things may have changed since...
Sure, I can and will check this. But I first wanted to check with
you guys about the status, since you implemented and most likely
also tested this stuff.
> Let me know of your findings. I will let you know if I have the chance
> to test this myself.
Okay. I'll try to test this stuff (even though I don't have JTAG on
this board) and will get back to you with findings and most likely
also some further questions.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v2 3/4] ARM: atmel: at91sam9x5ek: enable spl support
2019-02-19 14:56 ` Stefan Roese
@ 2019-02-21 17:00 ` Stefan Roese
2019-02-22 15:57 ` Eugen.Hristev at microchip.com
0 siblings, 1 reply; 15+ messages in thread
From: Stefan Roese @ 2019-02-21 17:00 UTC (permalink / raw)
To: u-boot
Hi Eugene,
On 19.02.19 15:56, Stefan Roese wrote:
<snip>
>> I did not test myself the SPL for any 9x5 board. The DDR2 init code
>> should be executed inside the SPL. Once you build your board with a
>> CONFIG_SPL enabled, you should get the spl binary built, then you can
>> add both SPL + U-boot proper on the boot media and have SPL boot
>> (execute DDR init code and load U-boot proper). I would suggest to try
>> on Sd-card first because it's easier (filesystem), but the commit says
>> only SPI and NAND tested.
>
> On this board I only have NAND, so there is no option to first test
> some other boot device unfortunately.
>
>> You can also look at the U-boot version which first included this patch,
>> some things may have changed since...
>
> Sure, I can and will check this. But I first wanted to check with
> you guys about the status, since you implemented and most likely
> also tested this stuff.
>
>> Let me know of your findings. I will let you know if I have the chance
>> to test this myself.
>
> Okay. I'll try to test this stuff (even though I don't have JTAG on
> this board) and will get back to you with findings and most likely
> also some further questions.
So I did make some progress here but building and testing the SPL
version by loading it to 0x30.0000 and starting it there via the
"go" command. I'm not brave enough to flash it right now, since
de-bricking might be tricky here, as I don't have JTAG. With the
loaded version I'm able to fully load the main U-Boot image from
NAND and run it from there to the prompt.
But then I looked at the latest AT91Bootstrap code and noticed the
many changes in the lowlevel boot code (clocking, DDR2, etc). I'm
a bit hesitant to port all this code to mainline U-Boot SPL here.
One reason being that you at Microchip / Atmel will most likely
continue to work on the AT91Bootstrap code and not on the
potentially ported SPL code version. So what's you opinion here on
this? Why do you not integrate all this code into U-Boot SPL and
drop this bootstrap version completely? What is your suggestion for
me on how to handle this? Stay with AT91Bootstrap or move to SPL?
Thanks,
Stefan
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v2 3/4] ARM: atmel: at91sam9x5ek: enable spl support
2019-02-21 17:00 ` Stefan Roese
@ 2019-02-22 15:57 ` Eugen.Hristev at microchip.com
2019-02-22 16:36 ` Stefan Roese
0 siblings, 1 reply; 15+ messages in thread
From: Eugen.Hristev at microchip.com @ 2019-02-22 15:57 UTC (permalink / raw)
To: u-boot
On 21.02.2019 19:00, Stefan Roese wrote:
> Hi Eugene,
>
> On 19.02.19 15:56, Stefan Roese wrote:
>
> <snip>
>
>>> I did not test myself the SPL for any 9x5 board. The DDR2 init code
>>> should be executed inside the SPL. Once you build your board with a
>>> CONFIG_SPL enabled, you should get the spl binary built, then you can
>>> add both SPL + U-boot proper on the boot media and have SPL boot
>>> (execute DDR init code and load U-boot proper). I would suggest to try
>>> on Sd-card first because it's easier (filesystem), but the commit says
>>> only SPI and NAND tested.
>>
>> On this board I only have NAND, so there is no option to first test
>> some other boot device unfortunately.
>>
>>> You can also look at the U-boot version which first included this patch,
>>> some things may have changed since...
>>
>> Sure, I can and will check this. But I first wanted to check with
>> you guys about the status, since you implemented and most likely
>> also tested this stuff.
>>> Let me know of your findings. I will let you know if I have the chance
>>> to test this myself.
>>
>> Okay. I'll try to test this stuff (even though I don't have JTAG on
>> this board) and will get back to you with findings and most likely
>> also some further questions.
>
> So I did make some progress here but building and testing the SPL
> version by loading it to 0x30.0000 and starting it there via the
> "go" command. I'm not brave enough to flash it right now, since
> de-bricking might be tricky here, as I don't have JTAG. With the
> loaded version I'm able to fully load the main U-Boot image from
> NAND and run it from there to the prompt.
Hi Stefan,
Send me a patch and I can apply and test, but I cannot promise to have
it very fast :) (or your git tree from where I can pull...)
Have to make it for 9x5-ek board, as I do not have anything else at my
disposal
>
> But then I looked at the latest AT91Bootstrap code and noticed the
> many changes in the lowlevel boot code (clocking, DDR2, etc). I'm
> a bit hesitant to port all this code to mainline U-Boot SPL here.
> One reason being that you at Microchip / Atmel will most likely
> continue to work on the AT91Bootstrap code and not on the
> potentially ported SPL code version. So what's you opinion here on
> this? Why do you not integrate all this code into U-Boot SPL and
> drop this bootstrap version completely? What is your suggestion for
> me on how to handle this? Stay with AT91Bootstrap or move to SPL?
At91boostrap is always recommended as we have the latest implementation
and it's used by most of the people using at91 boards and more tested.
We always try to keep SPL in sync , but it's only on best-effort at this
moment
I will review/take patches for SPL of course. There are people who use
it so we try to have it working at all times.
Eugen
>
> Thanks,
> Stefan
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v2 3/4] ARM: atmel: at91sam9x5ek: enable spl support
2019-02-22 15:57 ` Eugen.Hristev at microchip.com
@ 2019-02-22 16:36 ` Stefan Roese
0 siblings, 0 replies; 15+ messages in thread
From: Stefan Roese @ 2019-02-22 16:36 UTC (permalink / raw)
To: u-boot
Hi Eugene,
On 22.02.19 16:57, Eugen.Hristev at microchip.com wrote:
>
>
> On 21.02.2019 19:00, Stefan Roese wrote:
>> Hi Eugene,
>>
>> On 19.02.19 15:56, Stefan Roese wrote:
>>
>> <snip>
>>
>>>> I did not test myself the SPL for any 9x5 board. The DDR2 init code
>>>> should be executed inside the SPL. Once you build your board with a
>>>> CONFIG_SPL enabled, you should get the spl binary built, then you can
>>>> add both SPL + U-boot proper on the boot media and have SPL boot
>>>> (execute DDR init code and load U-boot proper). I would suggest to try
>>>> on Sd-card first because it's easier (filesystem), but the commit says
>>>> only SPI and NAND tested.
>>>
>>> On this board I only have NAND, so there is no option to first test
>>> some other boot device unfortunately.
>>>
>>>> You can also look at the U-boot version which first included this patch,
>>>> some things may have changed since...
>>>
>>> Sure, I can and will check this. But I first wanted to check with
>>> you guys about the status, since you implemented and most likely
>>> also tested this stuff.
>>>> Let me know of your findings. I will let you know if I have the chance
>>>> to test this myself.
>>>
>>> Okay. I'll try to test this stuff (even though I don't have JTAG on
>>> this board) and will get back to you with findings and most likely
>>> also some further questions.
>>
>> So I did make some progress here but building and testing the SPL
>> version by loading it to 0x30.0000 and starting it there via the
>> "go" command. I'm not brave enough to flash it right now, since
>> de-bricking might be tricky here, as I don't have JTAG. With the
>> loaded version I'm able to fully load the main U-Boot image from
>> NAND and run it from there to the prompt.
>
> Hi Stefan,
>
> Send me a patch and I can apply and test, but I cannot promise to have
> it very fast :) (or your git tree from where I can pull...)
> Have to make it for 9x5-ek board, as I do not have anything else at my
> disposal
I might come back to your offer, thanks!
>
>>
>> But then I looked at the latest AT91Bootstrap code and noticed the
>> many changes in the lowlevel boot code (clocking, DDR2, etc). I'm
>> a bit hesitant to port all this code to mainline U-Boot SPL here.
>> One reason being that you at Microchip / Atmel will most likely
>> continue to work on the AT91Bootstrap code and not on the
>> potentially ported SPL code version. So what's you opinion here on
>> this? Why do you not integrate all this code into U-Boot SPL and
>> drop this bootstrap version completely? What is your suggestion for
>> me on how to handle this? Stay with AT91Bootstrap or move to SPL?
>
> At91boostrap is always recommended as we have the latest implementation
> and it's used by most of the people using at91 boards and more tested.
I see. The decision to completely move to SPL should have probably been
made some years ago then (as other SoC vendors have done). Nothing to be
done about this now.
Still, what I really like in this SPL approach vs the vendor pre U-Boot
loader is, that all is encapsulated in one source code repository and
one image usually is generated, simplifying the bootloader building
and programming quite a bit.
> We always try to keep SPL in sync , but it's only on best-effort at this
> moment
> I will review/take patches for SPL of course. There are people who use
> it so we try to have it working at all times.
Okay, good to know.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v2 4/4] ARM: atmel: at91sam9n12ek: enable spl support
2015-03-27 6:23 [U-Boot] [PATCH v2 0/4] ARM: atmel: boards: enable SPL support Bo Shen
` (2 preceding siblings ...)
2015-03-27 6:23 ` [U-Boot] [PATCH v2 3/4] ARM: atmel: at91sam9x5ek: " Bo Shen
@ 2015-03-27 6:23 ` Bo Shen
2015-03-31 23:06 ` [U-Boot] [U-Boot,v2,4/4] " Andreas Bießmann
3 siblings, 1 reply; 15+ messages in thread
From: Bo Shen @ 2015-03-27 6:23 UTC (permalink / raw)
To: u-boot
Enable SPL support for at91sam9n12ek boards, now it supports
boot up from NAND flash, serial flash.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
---
Changes in v2:
- Remove the meaningless prefix "+S:" in configuration file.
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/include/mach/at91_pmc.h | 4 +-
arch/arm/mach-at91/mpddrc.c | 2 +-
arch/arm/mach-at91/spl_at91.c | 2 +-
board/atmel/at91sam9n12ek/at91sam9n12ek.c | 73 ++++++++++++++++++++++++++++++
configs/at91sam9n12ek_nandflash_defconfig | 1 +
configs/at91sam9n12ek_spiflash_defconfig | 1 +
include/configs/at91sam9n12ek.h | 58 +++++++++++++++++++++++-
9 files changed, 138 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index bdf87f9..30c4e17 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -75,6 +75,7 @@ config TARGET_PM9G45
config TARGET_AT91SAM9N12EK
bool "Atmel AT91SAM9N12-EK board"
select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_AT91SAM9RLEK
bool "Atmel at91sam9rl reference board"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index ba83616..0d3ee48 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
ifneq ($(CONFIG_SPL_BUILD),)
obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
+obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index c903260..ebb7dec 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -98,7 +98,7 @@ typedef struct at91_pmc {
#define AT91_PMC_MCKR_CSS_MASK 0x00000003
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
- defined(CONFIG_AT91SAM9X5)
+ defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
#define AT91_PMC_MCKR_PRES_1 0x00000000
#define AT91_PMC_MCKR_PRES_2 0x00000010
#define AT91_PMC_MCKR_PRES_4 0x00000020
@@ -128,7 +128,7 @@ typedef struct at91_pmc {
#define AT91_PMC_MCKR_MDIV_1 0x00000000
#define AT91_PMC_MCKR_MDIV_2 0x00000100
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
- defined(CONFIG_AT91SAM9X5)
+ defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
#define AT91_PMC_MCKR_MDIV_3 0x00000300
#endif
#define AT91_PMC_MCKR_MDIV_4 0x00000200
diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
index 24d5fcd..e2b6a49 100644
--- a/arch/arm/mach-at91/mpddrc.c
+++ b/arch/arm/mach-at91/mpddrc.c
@@ -20,7 +20,7 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
static int ddr2_decodtype_is_seq(u32 cr)
{
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
- defined(CONFIG_AT91SAM9X5)
+ defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
return 0;
#endif
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index e28e568..a79a9dc 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -115,7 +115,7 @@ void board_init_f(ulong dummy)
timer_init();
/* enable clocks for all PIOs */
-#ifdef CONFIG_AT91SAM9X5
+#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
at91_periph_clk_enable(ATMEL_ID_PIOAB);
at91_periph_clk_enable(ATMEL_ID_PIOCD);
#else
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index 9adc992..4f46a03 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -257,3 +257,76 @@ int dram_init(void)
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+ at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+ at91sam9n12ek_nand_hw_init();
+#elif CONFIG_SYS_USE_SPIFLASH
+ at91_spi0_hw_init(1 << 4);
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct atmel_mpddr ddr2;
+ unsigned long csa;
+
+ ddr2_conf(&ddr2);
+
+ /* enable DDR2 clock */
+ writel(0x4, &pmc->scer);
+
+ /* Chip select 1 is for DDR2/SDRAM */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+ csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+ csa |= AT91_MATRIX_EBI_DBPD_OFF;
+ csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+ writel(csa, &matrix->ebicsa);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_CS1, &ddr2);
+}
+#endif
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index f908246..11b42d4 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index d106b5a..5426bcd 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index f02fce9..aeec8b8 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -228,6 +228,62 @@
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x300000
+#define CONFIG_SPL_MAX_SIZE 0x6000
+#define CONFIG_SPL_STACK 0x308000
+
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CONFIG_SYS_AT91_PLLA 0x20953f03
+#define CONFIG_SYS_MCKR 0x1301
+#define CONFIG_SYS_MCKR_CSS 0x1302
+
+#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+
+#elif CONFIG_SYS_USE_SPIFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
+
+#endif
#endif
--
2.3.3.220.g9ab698f
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [U-Boot,v2,4/4] ARM: atmel: at91sam9n12ek: enable spl support
2015-03-27 6:23 ` [U-Boot] [PATCH v2 4/4] ARM: atmel: at91sam9n12ek: " Bo Shen
@ 2015-03-31 23:06 ` Andreas Bießmann
0 siblings, 0 replies; 15+ messages in thread
From: Andreas Bießmann @ 2015-03-31 23:06 UTC (permalink / raw)
To: u-boot
Dear Bo Shen,
Bo Shen <voice.shen@atmel.com> writes:
>Enable SPL support for at91sam9n12ek boards, now it supports
>boot up from NAND flash, serial flash.
>
>Signed-off-by: Bo Shen <voice.shen@atmel.com>
>---
>
>Changes in v2:
> - Remove the meaningless prefix "+S:" in configuration file.
>
> arch/arm/mach-at91/Kconfig | 1 +
> arch/arm/mach-at91/Makefile | 1 +
> arch/arm/mach-at91/include/mach/at91_pmc.h | 4 +-
> arch/arm/mach-at91/mpddrc.c | 2 +-
> arch/arm/mach-at91/spl_at91.c | 2 +-
> board/atmel/at91sam9n12ek/at91sam9n12ek.c | 73 ++++++++++++++++++++++++++++++
> configs/at91sam9n12ek_nandflash_defconfig | 1 +
> configs/at91sam9n12ek_spiflash_defconfig | 1 +
> include/configs/at91sam9n12ek.h | 58 +++++++++++++++++++++++-
> 9 files changed, 138 insertions(+), 5 deletions(-)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 15+ messages in thread