[PATCH 0/8] ARM64: Update support for FSL's LS2085A SoC

[PATCH 0/8] ARM64: Update support for FSL's LS2085A SoC

[Bhupesh Sharma]

This patchset updates the support for FSL's LS2085A SoC which is based on
ARMv8 architecture:

  - Updates the support of various peripherals (PMU, Watchdog, SMMU,
    SPI, etc.) present on FSL LS2085a SoC in the SoC DTSI.

  - Updates the DTS LS2085a simulator platform to reflect the new
    peripherals added in the DTSI.

  - Adds new DTS files for LS2085a based QDS and RDB boards.

Rebased against arm-soc git tree, branch: next/dt

Further details of the LS2085a based platforms can be seen here:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=LS2085A

Note:
-----
I get a checkpatch warning for the amba-bus compatible string
being missing from Documentation/devicetree/bindings/ . I am not aware
if some patch is already being worked on, to solve the same:
	compatible = "arm,amba-bus";

If not, I can try to send a patch, with the re-spin of this patchset.

Bhupesh Sharma (7):
  Documentation: DT: Add entry for FSL LS2085A QDS and RDB boards
  doc/bindings: Update PCIe devicetree binding documentation for
    LS2085A
  doc/bindings: Update clk-qoriq bindings for FSL's chassis-3.0 SoCs
  dts/ls2085a: Update DTSI to add support of various peripherals
  dts/ls2085a: Update Simulator DTS to add support of various
    peripherals
  dts/ls2085a: Add DTS support for LS2085a QDS & RDB boards
  dts/Makefile: Add build support for LS2085a QDS & RDB board DTS

Wang Dongsheng (1):
  layerscape/ftm: Add compatible string for FTM0 be used as alarm
    timer.

 Documentation/devicetree/bindings/arm/fsl.txt      |    8 +
 .../devicetree/bindings/clock/qoriq-clock.txt      |   14 +-
 .../devicetree/bindings/pci/layerscape-pci.txt     |    3 +-
 .../devicetree/bindings/timer/fsl,ftm-timer.txt    |   46 +-
 arch/arm64/boot/dts/freescale/Makefile             |    2 +-
 .../{fsl-ls2085a-simu.dts => fsl-ls2085a-qds.dts}  |  140 +++++-
 .../{fsl-ls2085a-simu.dts => fsl-ls2085a-rdb.dts}  |   76 ++-
 arch/arm64/boot/dts/freescale/fsl-ls2085a-simu.dts |   40 ++
 arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi     |  523 +++++++++++++++++++-
 9 files changed, 812 insertions(+), 40 deletions(-)
 copy arch/arm64/boot/dts/freescale/{fsl-ls2085a-simu.dts => fsl-ls2085a-qds.dts} (51%)
 copy arch/arm64/boot/dts/freescale/{fsl-ls2085a-simu.dts => fsl-ls2085a-rdb.dts} (69%)

-- 
1.7.9.5

[PATCH 1/8] Documentation: DT: Add entry for FSL LS2085A QDS and RDB boards

[Bhupesh Sharma]

This patch adds a devicetree binding documentation for FSL's
LS2085A QDS and RDB boards.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 Documentation/devicetree/bindings/arm/fsl.txt |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index a5462b6..29b53a7 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -132,3 +132,11 @@ LS2085A ARMv8 based Simulator model
 Required root node properties:
     - compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
 
+LS2085A ARMv8 based QDS Board
+Required root node properties:
+    - compatible = "fsl,ls2085a-qds", "fsl,ls2085a";
+
+LS2085A ARMv8 based RDB Board
+Required root node properties:
+    - compatible = "fsl,ls2085a-rdb", "fsl,ls2085a";
+
-- 
1.7.9.5

[PATCH 2/8] doc/bindings: Update PCIe devicetree binding documentation for LS2085A

[Bhupesh Sharma]

Add the documentation for compatible string "fsl,ls2085a-pcie"
for LS2085A platform.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Change-Id: I0d51607e86544be8906c996c08a2b2b558243bd4
Reviewed-on: http://git.am.freescale.net:8181/28740
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Tested-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 .../devicetree/bindings/pci/layerscape-pci.txt     |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 6286f04..0654809 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
+- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie",
+  "fsl,ls2085a-pcie".
 - reg: base addresses and lengths of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
-- 
1.7.9.5

[PATCH 3/8] doc/bindings: Update clk-qoriq bindings for FSL's chassis-3.0 SoCs

[Bhupesh Sharma]

This patch updates the 'clk-qoriq' device-tree bindings for
chassis-3.0 compliant SoCs from FSL, for e.g. LS2085A

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 .../devicetree/bindings/clock/qoriq-clock.txt      |   14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index df4a259..60d758e 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -14,6 +14,7 @@ Chassis Version		Example Chips
 ---------------		-------------
 1.0			p4080, p5020, p5040
 2.0			t4240, b4860, t1040
+3.0			ls2085a
 
 1. Clock Block Binding
 
@@ -30,9 +31,11 @@ Required properties:
 	* "fsl,b4420-clockgen"
 	* "fsl,b4860-clockgen"
 	* "fsl,ls1021a-clockgen"
+	* "fsl,ls2085a-clockgen"
 	Chassis clock strings include:
 	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
 	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
+	* "fsl,qoriq-clockgen-3.0": for chassis 3.0 clocks
 - reg: Describes the address of the device's resources within the
 	address space defined by its parent bus, and resource zero
 	represents the clock register set
@@ -57,18 +60,23 @@ Required properties:
 - compatible : Should include one of the following:
 	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
 	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
+	* "fsl,qoriq-core-pll-3.0" for core PLL clocks (v3.0)
 	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
 	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
+	* "fsl,qoriq-core-mux-3.0" for core mux clocks (v3.0)
 	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
 		It takes parent's clock-frequency as its clock.
 	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
 		It takes parent's clock-frequency as its clock.
+	* "fsl,qoriq-sysclk-3.0": for input system clock (v3.0).
+		It takes parent's clock-frequency as its clock.
 	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
 	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
+	* "fsl,qoriq-platform-pll-3.0" for the platform PLL clock (v3.0)
 - #clock-cells: From common clock binding. The number of cells in a
-	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
-	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
-	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
+	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2,3].0"
+	clocks, or <1> for "fsl,qoriq-core-pll-[1,2,3].0" clocks.
+	For "fsl,qoriq-core-pll-[1,2,3].0" clocks, the single
 	clock-specifier cell may take the following values:
 	* 0 - equal to the PLL frequency
 	* 1 - equal to the PLL frequency divided by 2
-- 
1.7.9.5

[PATCH 4/8] layerscape/ftm: Add compatible string for FTM0 be used as alarm timer.

[Bhupesh Sharma]

From: Wang Dongsheng <dongsheng.wang@freescale.com>

Only FTM0 can be used as an alarm timer, so add a "fsl,ftm-alarm"
compatible string to describe FTM0 alarm mode.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: Ie9a6c1c01a362ee6f0b6c995f9a104a3afff9165
Reviewed-on: http://git.am.freescale.net:8181/30167
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Tested-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 .../devicetree/bindings/timer/fsl,ftm-timer.txt    |   46 ++++++++++++++------
 1 file changed, 32 insertions(+), 14 deletions(-)

diff --git a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
index aa8c402..a372ed7 100644
--- a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
+++ b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
@@ -2,12 +2,18 @@ Freescale FlexTimer Module (FTM) Timer
 
 Required properties:
 
-- compatible : should be "fsl,ftm-timer"
+- compatible : should be "fsl,ftm-timer" & "fsl,ftm-alarm".
+  (a) "fsl,ftm-timer", for FlexTimer compatible as normal timer.
+  (b) "fsl,ftm-alarm", for FlexTimer compatible when FTM0 as an ALARM timer.
+
 - reg : Specifies base physical address and size of the register sets for the
   clock event device and clock source device.
+
 - interrupts : Should be the clock event device interrupt.
+
 - clocks : The clocks provided by the SoC to drive the timer, must contain an
   entry for each entry in clock-names.
+
 - clock-names : Must include the following entries:
   o "ftm-evt"
   o "ftm-src"
@@ -16,16 +22,28 @@ Required properties:
 - big-endian: One boolean property, the big endian mode will be in use if it is
   present, or the little endian mode will be in use for all the device registers.
 
-Example:
-ftm: ftm at 400b8000 {
-	compatible = "fsl,ftm-timer";
-	reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
-	interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
-	clock-names = "ftm-evt", "ftm-src",
-		"ftm-evt-counter-en", "ftm-src-counter-en";
-	clocks = <&clks VF610_CLK_FTM2>,
-		<&clks VF610_CLK_FTM3>,
-		<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
-		<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
-	big-endian;
-};
+Example 1: In this example, The FlexTimer module (FTM) is a two-to-eight,
+	   channel timer that supports input capture, output compare, and
+	   the generation of PWM signals to control electric motor and power
+	   management applications.
+
+	ftm: ftm at 400b8000 {
+		compatible = "fsl,ftm-timer";
+		reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
+		interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "ftm-evt", "ftm-src",
+			"ftm-evt-counter-en", "ftm-src-counter-en";
+		clocks = <&clks VF610_CLK_FTM2>,
+			<&clks VF610_CLK_FTM3>,
+			<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
+			<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
+		big-endian;
+	};
+
+Example 2: In this example, FTM0 only be used as an alarm timer.
+
+	ftm0: ftm0 at 2800000 {
+		compatible = "fsl,ftm-alarm";
+		reg = <0x0 0x2800000 0x0 0x10000>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+	};
-- 
1.7.9.5

[PATCH 2/8] doc/bindings: Update PCIe devicetree binding documentation for LS2085A

[Mark Rutland]

Hi,

On Wed, Apr 01, 2015 at 12:40:56PM +0100, Bhupesh Sharma wrote:
> Add the documentation for compatible string "fsl,ls2085a-pcie"
> for LS2085A platform.
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>

[...]

> Change-Id: I0d51607e86544be8906c996c08a2b2b558243bd4
> Reviewed-on: http://git.am.freescale.net:8181/28740
> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>

These three are meaningless here. Please drop them.

> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> Tested-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> ---
>  .../devicetree/bindings/pci/layerscape-pci.txt     |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 6286f04..0654809 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
>  and thus inherits all the common properties defined in designware-pcie.txt.
>  
>  Required properties:
> -- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
> +- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie",
> +  "fsl,ls2085a-pcie".

Please format this as a list, e.g.

- compatible: schould contain one of:
  * "fsl,ls1021a-pcie"
  * "fsl,ls2085a-pcie"

Is the ls2085a PCIe controller significantly different from that of
ls1021a? Is "fsl,ls1021a-pcie" valid as a fallback entry?

Mark.

>  - reg: base addresses and lengths of the PCIe controller
>  - interrupts: A list of interrupt outputs of the controller. Must contain an
>    entry for each entry in the interrupt-names property.
> -- 
> 1.7.9.5
> 
> 

[PATCH 2/8] doc/bindings: Update PCIe devicetree binding documentation for LS2085A

[bhupesh.sharma at freescale.com]

Hi Mark,

> From: Mark Rutland [mailto:mark.rutland at arm.com]
> 
> Hi,
> 
> On Wed, Apr 01, 2015 at 12:40:56PM +0100, Bhupesh Sharma wrote:
> > Add the documentation for compatible string "fsl,ls2085a-pcie"
> > for LS2085A platform.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> 
> [...]
> 
> > Change-Id: I0d51607e86544be8906c996c08a2b2b558243bd4
> > Reviewed-on: http://git.am.freescale.net:8181/28740
> > Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
> 
> These three are meaningless here. Please drop them.

Sorry. I just sent out a RESEND version. I pushed the send button too quickly :)

> 
> > Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> > Tested-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> > ---
> >  .../devicetree/bindings/pci/layerscape-pci.txt     |    3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index 6286f04..0654809 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis
> > Designware PCIe IP  and thus inherits all the common properties defined
> in designware-pcie.txt.
> >
> >  Required properties:
> > -- compatible: should contain the platform identifier such as
> "fsl,ls1021a-pcie"
> > +- compatible: should contain the platform identifier such as
> > +"fsl,ls1021a-pcie",
> > +  "fsl,ls2085a-pcie".
> 
> Please format this as a list, e.g.
> 
> - compatible: schould contain one of:
>   * "fsl,ls1021a-pcie"
>   * "fsl,ls2085a-pcie"
> 
> Is the ls2085a PCIe controller significantly different from that of
> ls1021a? Is "fsl,ls1021a-pcie" valid as a fallback entry?
> 

Minghuan, can you please share your views on Mark's comments above. 

Regards,
Bhupesh
 
> >  - reg: base addresses and lengths of the PCIe controller
> >  - interrupts: A list of interrupt outputs of the controller. Must
> contain an
> >    entry for each entry in the interrupt-names property.
> > --
> > 1.7.9.5
> >
> >

[PATCH 2/8] doc/bindings: Update PCIe devicetree binding documentation for LS2085A

[Minghuan.Lian at freescale.com]

Hi Mark and Bhupesh,

I am sorry for the long silence.
Please see my comments inline.

> -----Original Message-----
> From: Sharma Bhupesh-B45370
> Sent: Wednesday, April 01, 2015 7:52 PM
> To: Mark Rutland; Lian Minghuan-B31939
> Cc: arnd at arndb.de; linux-arm-kernel at lists.infradead.org; Marc Zyngier;
> bhupesh.linux at gmail.com; Catalin Marinas; Yoder Stuart-B08248;
> olof at lixom.net; Will Deacon
> Subject: RE: [PATCH 2/8] doc/bindings: Update PCIe devicetree binding
> documentation for LS2085A
> 
> Hi Mark,
> 
> > From: Mark Rutland [mailto:mark.rutland at arm.com]
> >
> > Hi,
> >
> > On Wed, Apr 01, 2015 at 12:40:56PM +0100, Bhupesh Sharma wrote:
> > > Add the documentation for compatible string "fsl,ls2085a-pcie"
> > > for LS2085A platform.
> > >
> > > Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> >
> > [...]
> >
> > > Change-Id: I0d51607e86544be8906c996c08a2b2b558243bd4
> > > Reviewed-on: http://git.am.freescale.net:8181/28740
> > > Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
> >
> > These three are meaningless here. Please drop them.
> 
> Sorry. I just sent out a RESEND version. I pushed the send button too quickly :)
> 
> >
> > > Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> > > Tested-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> > > ---
> > >  .../devicetree/bindings/pci/layerscape-pci.txt     |    3 ++-
> > >  1 file changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > > index 6286f04..0654809 100644
> > > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > > @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis
> > > Designware PCIe IP  and thus inherits all the common properties
> > > defined
> > in designware-pcie.txt.
> > >
> > >  Required properties:
> > > -- compatible: should contain the platform identifier such as
> > "fsl,ls1021a-pcie"
> > > +- compatible: should contain the platform identifier such as
> > > +"fsl,ls1021a-pcie",
> > > +  "fsl,ls2085a-pcie".
> >
> > Please format this as a list, e.g.
> >
> > - compatible: schould contain one of:
> >   * "fsl,ls1021a-pcie"
> >   * "fsl,ls2085a-pcie"
> >
> > Is the ls2085a PCIe controller significantly different from that of
> > ls1021a? Is "fsl,ls1021a-pcie" valid as a fallback entry?
> >
> 
[Minghuan] ls2085a uses different arm core and different PCIe IP version from ls1021a.
Between them, there are different way to check linkup status, different MSI implementation, and different hardware Errata.
Besides, there is different dts property.
The driver need to call different initialization function according to compatible string.

> Minghuan, can you please share your views on Mark's comments above.
> 
> Regards,
> Bhupesh
> 
> > >  - reg: base addresses and lengths of the PCIe controller
> > >  - interrupts: A list of interrupt outputs of the controller. Must
> > contain an
> > >    entry for each entry in the interrupt-names property.
> > > --
> > > 1.7.9.5
> > >
> > >